Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / sdma_v4_0.c
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
29
30 #include "sdma0/sdma0_4_2_offset.h"
31 #include "sdma0/sdma0_4_2_sh_mask.h"
32 #include "sdma1/sdma1_4_2_offset.h"
33 #include "sdma1/sdma1_4_2_sh_mask.h"
34 #include "hdp/hdp_4_0_offset.h"
35 #include "sdma0/sdma0_4_1_default.h"
36
37 #include "soc15_common.h"
38 #include "soc15.h"
39 #include "vega10_sdma_pkt_open.h"
40
41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
43
44 #include "amdgpu_ras.h"
45
46 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
47 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
48 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
50 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
51 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
52 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
54 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
55
56 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
57 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
58
59 #define WREG32_SDMA(instance, offset, value) \
60         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
61 #define RREG32_SDMA(instance, offset) \
62         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
63
64 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
65 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
66 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
67 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
68
69 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
70         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
71         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
72         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
73         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
75         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
76         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
77         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
78         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
79         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
80         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
81         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
82         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
83         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
84         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
85         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
86         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
87         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
88         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
89         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
90         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
91         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
92         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
93         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
94         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
95 };
96
97 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
100         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
101         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
102         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
103 };
104
105 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
106         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
107         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
108         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
109         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
110         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
111 };
112
113 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
114         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
115         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
116         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
117         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
118         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
119         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
120         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
121         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
122         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
123         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
124         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
125 };
126
127 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
128         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
129 };
130
131 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
132 {
133         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
134         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
135         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
136         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
137         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
143         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
144         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
145         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
147         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
149         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
151         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
152         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
153         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
154         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
155         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
157         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
159         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),
160 };
161
162 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
163         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
164         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
165         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
166         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
167         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
168         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
169         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
170         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
171         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
172         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
174         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
183         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
184         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
185         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
186         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
187         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
188         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
189         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),
190 };
191
192 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
193 {
194         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
195         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
196 };
197
198 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
199 {
200         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
201         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
202 };
203
204 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
205                 u32 instance, u32 offset)
206 {
207         return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
208                         (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
209 }
210
211 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
212 {
213         switch (adev->asic_type) {
214         case CHIP_VEGA10:
215                 soc15_program_register_sequence(adev,
216                                                  golden_settings_sdma_4,
217                                                  ARRAY_SIZE(golden_settings_sdma_4));
218                 soc15_program_register_sequence(adev,
219                                                  golden_settings_sdma_vg10,
220                                                  ARRAY_SIZE(golden_settings_sdma_vg10));
221                 break;
222         case CHIP_VEGA12:
223                 soc15_program_register_sequence(adev,
224                                                 golden_settings_sdma_4,
225                                                 ARRAY_SIZE(golden_settings_sdma_4));
226                 soc15_program_register_sequence(adev,
227                                                 golden_settings_sdma_vg12,
228                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
229                 break;
230         case CHIP_VEGA20:
231                 soc15_program_register_sequence(adev,
232                                                 golden_settings_sdma0_4_2_init,
233                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
234                 soc15_program_register_sequence(adev,
235                                                 golden_settings_sdma0_4_2,
236                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
237                 soc15_program_register_sequence(adev,
238                                                 golden_settings_sdma1_4_2,
239                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
240                 break;
241         case CHIP_RAVEN:
242                 soc15_program_register_sequence(adev,
243                                                 golden_settings_sdma_4_1,
244                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
245                 if (adev->rev_id >= 8)
246                         soc15_program_register_sequence(adev,
247                                                         golden_settings_sdma_rv2,
248                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
249                 else
250                         soc15_program_register_sequence(adev,
251                                                         golden_settings_sdma_rv1,
252                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
253                 break;
254         default:
255                 break;
256         }
257 }
258
259 /**
260  * sdma_v4_0_init_microcode - load ucode images from disk
261  *
262  * @adev: amdgpu_device pointer
263  *
264  * Use the firmware interface to load the ucode images into
265  * the driver (not loaded into hw).
266  * Returns 0 on success, error on failure.
267  */
268
269 // emulation only, won't work on real chip
270 // vega10 real chip need to use PSP to load firmware
271 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
272 {
273         const char *chip_name;
274         char fw_name[30];
275         int err = 0, i;
276         struct amdgpu_firmware_info *info = NULL;
277         const struct common_firmware_header *header = NULL;
278         const struct sdma_firmware_header_v1_0 *hdr;
279
280         DRM_DEBUG("\n");
281
282         switch (adev->asic_type) {
283         case CHIP_VEGA10:
284                 chip_name = "vega10";
285                 break;
286         case CHIP_VEGA12:
287                 chip_name = "vega12";
288                 break;
289         case CHIP_VEGA20:
290                 chip_name = "vega20";
291                 break;
292         case CHIP_RAVEN:
293                 if (adev->rev_id >= 8)
294                         chip_name = "raven2";
295                 else if (adev->pdev->device == 0x15d8)
296                         chip_name = "picasso";
297                 else
298                         chip_name = "raven";
299                 break;
300         default:
301                 BUG();
302         }
303
304         for (i = 0; i < adev->sdma.num_instances; i++) {
305                 if (i == 0)
306                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
307                 else
308                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
309                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
310                 if (err)
311                         goto out;
312                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
313                 if (err)
314                         goto out;
315                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
316                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
317                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
318                 if (adev->sdma.instance[i].feature_version >= 20)
319                         adev->sdma.instance[i].burst_nop = true;
320                 DRM_DEBUG("psp_load == '%s'\n",
321                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
322
323                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
324                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
325                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
326                         info->fw = adev->sdma.instance[i].fw;
327                         header = (const struct common_firmware_header *)info->fw->data;
328                         adev->firmware.fw_size +=
329                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
330                 }
331         }
332 out:
333         if (err) {
334                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
335                 for (i = 0; i < adev->sdma.num_instances; i++) {
336                         release_firmware(adev->sdma.instance[i].fw);
337                         adev->sdma.instance[i].fw = NULL;
338                 }
339         }
340         return err;
341 }
342
343 /**
344  * sdma_v4_0_ring_get_rptr - get the current read pointer
345  *
346  * @ring: amdgpu ring pointer
347  *
348  * Get the current rptr from the hardware (VEGA10+).
349  */
350 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
351 {
352         u64 *rptr;
353
354         /* XXX check if swapping is necessary on BE */
355         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
356
357         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
358         return ((*rptr) >> 2);
359 }
360
361 /**
362  * sdma_v4_0_ring_get_wptr - get the current write pointer
363  *
364  * @ring: amdgpu ring pointer
365  *
366  * Get the current wptr from the hardware (VEGA10+).
367  */
368 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
369 {
370         struct amdgpu_device *adev = ring->adev;
371         u64 wptr;
372
373         if (ring->use_doorbell) {
374                 /* XXX check if swapping is necessary on BE */
375                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
376                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
377         } else {
378                 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
379                 wptr = wptr << 32;
380                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
381                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
382                                 ring->me, wptr);
383         }
384
385         return wptr >> 2;
386 }
387
388 /**
389  * sdma_v4_0_ring_set_wptr - commit the write pointer
390  *
391  * @ring: amdgpu ring pointer
392  *
393  * Write the wptr back to the hardware (VEGA10+).
394  */
395 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
396 {
397         struct amdgpu_device *adev = ring->adev;
398
399         DRM_DEBUG("Setting write pointer\n");
400         if (ring->use_doorbell) {
401                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
402
403                 DRM_DEBUG("Using doorbell -- "
404                                 "wptr_offs == 0x%08x "
405                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
406                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
407                                 ring->wptr_offs,
408                                 lower_32_bits(ring->wptr << 2),
409                                 upper_32_bits(ring->wptr << 2));
410                 /* XXX check if swapping is necessary on BE */
411                 WRITE_ONCE(*wb, (ring->wptr << 2));
412                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
413                                 ring->doorbell_index, ring->wptr << 2);
414                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
415         } else {
416                 DRM_DEBUG("Not using doorbell -- "
417                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
418                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
419                                 ring->me,
420                                 lower_32_bits(ring->wptr << 2),
421                                 ring->me,
422                                 upper_32_bits(ring->wptr << 2));
423                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
424                             lower_32_bits(ring->wptr << 2));
425                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
426                             upper_32_bits(ring->wptr << 2));
427         }
428 }
429
430 /**
431  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
432  *
433  * @ring: amdgpu ring pointer
434  *
435  * Get the current wptr from the hardware (VEGA10+).
436  */
437 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
438 {
439         struct amdgpu_device *adev = ring->adev;
440         u64 wptr;
441
442         if (ring->use_doorbell) {
443                 /* XXX check if swapping is necessary on BE */
444                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
445         } else {
446                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
447                 wptr = wptr << 32;
448                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
449         }
450
451         return wptr >> 2;
452 }
453
454 /**
455  * sdma_v4_0_ring_set_wptr - commit the write pointer
456  *
457  * @ring: amdgpu ring pointer
458  *
459  * Write the wptr back to the hardware (VEGA10+).
460  */
461 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
462 {
463         struct amdgpu_device *adev = ring->adev;
464
465         if (ring->use_doorbell) {
466                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
467
468                 /* XXX check if swapping is necessary on BE */
469                 WRITE_ONCE(*wb, (ring->wptr << 2));
470                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
471         } else {
472                 uint64_t wptr = ring->wptr << 2;
473
474                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
475                             lower_32_bits(wptr));
476                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
477                             upper_32_bits(wptr));
478         }
479 }
480
481 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
482 {
483         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
484         int i;
485
486         for (i = 0; i < count; i++)
487                 if (sdma && sdma->burst_nop && (i == 0))
488                         amdgpu_ring_write(ring, ring->funcs->nop |
489                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
490                 else
491                         amdgpu_ring_write(ring, ring->funcs->nop);
492 }
493
494 /**
495  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
496  *
497  * @ring: amdgpu ring pointer
498  * @ib: IB object to schedule
499  *
500  * Schedule an IB in the DMA ring (VEGA10).
501  */
502 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
503                                    struct amdgpu_job *job,
504                                    struct amdgpu_ib *ib,
505                                    uint32_t flags)
506 {
507         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
508
509         /* IB packet must end on a 8 DW boundary */
510         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
511
512         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
513                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
514         /* base must be 32 byte aligned */
515         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
516         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
517         amdgpu_ring_write(ring, ib->length_dw);
518         amdgpu_ring_write(ring, 0);
519         amdgpu_ring_write(ring, 0);
520
521 }
522
523 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
524                                    int mem_space, int hdp,
525                                    uint32_t addr0, uint32_t addr1,
526                                    uint32_t ref, uint32_t mask,
527                                    uint32_t inv)
528 {
529         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
530                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
531                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
532                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
533         if (mem_space) {
534                 /* memory */
535                 amdgpu_ring_write(ring, addr0);
536                 amdgpu_ring_write(ring, addr1);
537         } else {
538                 /* registers */
539                 amdgpu_ring_write(ring, addr0 << 2);
540                 amdgpu_ring_write(ring, addr1 << 2);
541         }
542         amdgpu_ring_write(ring, ref); /* reference */
543         amdgpu_ring_write(ring, mask); /* mask */
544         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
545                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
546 }
547
548 /**
549  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
550  *
551  * @ring: amdgpu ring pointer
552  *
553  * Emit an hdp flush packet on the requested DMA ring.
554  */
555 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
556 {
557         struct amdgpu_device *adev = ring->adev;
558         u32 ref_and_mask = 0;
559         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
560
561         if (ring->me == 0)
562                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
563         else
564                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
565
566         sdma_v4_0_wait_reg_mem(ring, 0, 1,
567                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
568                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
569                                ref_and_mask, ref_and_mask, 10);
570 }
571
572 /**
573  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
574  *
575  * @ring: amdgpu ring pointer
576  * @fence: amdgpu fence object
577  *
578  * Add a DMA fence packet to the ring to write
579  * the fence seq number and DMA trap packet to generate
580  * an interrupt if needed (VEGA10).
581  */
582 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
583                                       unsigned flags)
584 {
585         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
586         /* write the fence */
587         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
588         /* zero in first two bits */
589         BUG_ON(addr & 0x3);
590         amdgpu_ring_write(ring, lower_32_bits(addr));
591         amdgpu_ring_write(ring, upper_32_bits(addr));
592         amdgpu_ring_write(ring, lower_32_bits(seq));
593
594         /* optionally write high bits as well */
595         if (write64bit) {
596                 addr += 4;
597                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
598                 /* zero in first two bits */
599                 BUG_ON(addr & 0x3);
600                 amdgpu_ring_write(ring, lower_32_bits(addr));
601                 amdgpu_ring_write(ring, upper_32_bits(addr));
602                 amdgpu_ring_write(ring, upper_32_bits(seq));
603         }
604
605         /* generate an interrupt */
606         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
607         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
608 }
609
610
611 /**
612  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
613  *
614  * @adev: amdgpu_device pointer
615  *
616  * Stop the gfx async dma ring buffers (VEGA10).
617  */
618 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
619 {
620         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
621         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
622         u32 rb_cntl, ib_cntl;
623         int i;
624
625         if ((adev->mman.buffer_funcs_ring == sdma0) ||
626             (adev->mman.buffer_funcs_ring == sdma1))
627                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
628
629         for (i = 0; i < adev->sdma.num_instances; i++) {
630                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
631                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
632                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
633                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
634                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
635                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
636         }
637
638         sdma0->sched.ready = false;
639         sdma1->sched.ready = false;
640 }
641
642 /**
643  * sdma_v4_0_rlc_stop - stop the compute async dma engines
644  *
645  * @adev: amdgpu_device pointer
646  *
647  * Stop the compute async dma queues (VEGA10).
648  */
649 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
650 {
651         /* XXX todo */
652 }
653
654 /**
655  * sdma_v4_0_page_stop - stop the page async dma engines
656  *
657  * @adev: amdgpu_device pointer
658  *
659  * Stop the page async dma ring buffers (VEGA10).
660  */
661 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
662 {
663         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page;
664         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page;
665         u32 rb_cntl, ib_cntl;
666         int i;
667
668         if ((adev->mman.buffer_funcs_ring == sdma0) ||
669             (adev->mman.buffer_funcs_ring == sdma1))
670                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
671
672         for (i = 0; i < adev->sdma.num_instances; i++) {
673                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
674                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
675                                         RB_ENABLE, 0);
676                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
677                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
678                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
679                                         IB_ENABLE, 0);
680                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
681         }
682
683         sdma0->sched.ready = false;
684         sdma1->sched.ready = false;
685 }
686
687 /**
688  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
689  *
690  * @adev: amdgpu_device pointer
691  * @enable: enable/disable the DMA MEs context switch.
692  *
693  * Halt or unhalt the async dma engines context switch (VEGA10).
694  */
695 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
696 {
697         u32 f32_cntl, phase_quantum = 0;
698         int i;
699
700         if (amdgpu_sdma_phase_quantum) {
701                 unsigned value = amdgpu_sdma_phase_quantum;
702                 unsigned unit = 0;
703
704                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
705                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
706                         value = (value + 1) >> 1;
707                         unit++;
708                 }
709                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
710                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
711                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
712                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
713                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
714                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
715                         WARN_ONCE(1,
716                         "clamping sdma_phase_quantum to %uK clock cycles\n",
717                                   value << unit);
718                 }
719                 phase_quantum =
720                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
721                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
722         }
723
724         for (i = 0; i < adev->sdma.num_instances; i++) {
725                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
726                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
727                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
728                 if (enable && amdgpu_sdma_phase_quantum) {
729                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
730                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
731                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
732                 }
733                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
734         }
735
736 }
737
738 /**
739  * sdma_v4_0_enable - stop the async dma engines
740  *
741  * @adev: amdgpu_device pointer
742  * @enable: enable/disable the DMA MEs.
743  *
744  * Halt or unhalt the async dma engines (VEGA10).
745  */
746 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
747 {
748         u32 f32_cntl;
749         int i;
750
751         if (enable == false) {
752                 sdma_v4_0_gfx_stop(adev);
753                 sdma_v4_0_rlc_stop(adev);
754                 if (adev->sdma.has_page_queue)
755                         sdma_v4_0_page_stop(adev);
756         }
757
758         for (i = 0; i < adev->sdma.num_instances; i++) {
759                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
760                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
761                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
762         }
763 }
764
765 /**
766  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
767  */
768 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
769 {
770         /* Set ring buffer size in dwords */
771         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
772
773         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
774 #ifdef __BIG_ENDIAN
775         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
776         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
777                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
778 #endif
779         return rb_cntl;
780 }
781
782 /**
783  * sdma_v4_0_gfx_resume - setup and start the async dma engines
784  *
785  * @adev: amdgpu_device pointer
786  * @i: instance to resume
787  *
788  * Set up the gfx DMA ring buffers and enable them (VEGA10).
789  * Returns 0 for success, error for failure.
790  */
791 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
792 {
793         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
794         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
795         u32 wb_offset;
796         u32 doorbell;
797         u32 doorbell_offset;
798         u64 wptr_gpu_addr;
799
800         wb_offset = (ring->rptr_offs * 4);
801
802         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
803         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
804         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
805
806         /* Initialize the ring buffer's read and write pointers */
807         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
808         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
809         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
810         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
811
812         /* set the wb address whether it's enabled or not */
813         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
814                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
815         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
816                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
817
818         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
819                                 RPTR_WRITEBACK_ENABLE, 1);
820
821         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
822         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
823
824         ring->wptr = 0;
825
826         /* before programing wptr to a less value, need set minor_ptr_update first */
827         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
828
829         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
830         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
831
832         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
833                                  ring->use_doorbell);
834         doorbell_offset = REG_SET_FIELD(doorbell_offset,
835                                         SDMA0_GFX_DOORBELL_OFFSET,
836                                         OFFSET, ring->doorbell_index);
837         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
838         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
839
840         sdma_v4_0_ring_set_wptr(ring);
841
842         /* set minor_ptr_update to 0 after wptr programed */
843         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
844
845         /* setup the wptr shadow polling */
846         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
847         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
848                     lower_32_bits(wptr_gpu_addr));
849         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
850                     upper_32_bits(wptr_gpu_addr));
851         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
852         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
853                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
854                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
855         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
856
857         /* enable DMA RB */
858         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
859         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
860
861         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
862         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
863 #ifdef __BIG_ENDIAN
864         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
865 #endif
866         /* enable DMA IBs */
867         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
868
869         ring->sched.ready = true;
870 }
871
872 /**
873  * sdma_v4_0_page_resume - setup and start the async dma engines
874  *
875  * @adev: amdgpu_device pointer
876  * @i: instance to resume
877  *
878  * Set up the page DMA ring buffers and enable them (VEGA10).
879  * Returns 0 for success, error for failure.
880  */
881 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
882 {
883         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
884         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
885         u32 wb_offset;
886         u32 doorbell;
887         u32 doorbell_offset;
888         u64 wptr_gpu_addr;
889
890         wb_offset = (ring->rptr_offs * 4);
891
892         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
893         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
894         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
895
896         /* Initialize the ring buffer's read and write pointers */
897         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
898         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
899         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
900         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
901
902         /* set the wb address whether it's enabled or not */
903         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
904                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
905         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
906                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
907
908         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
909                                 RPTR_WRITEBACK_ENABLE, 1);
910
911         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
912         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
913
914         ring->wptr = 0;
915
916         /* before programing wptr to a less value, need set minor_ptr_update first */
917         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
918
919         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
920         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
921
922         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
923                                  ring->use_doorbell);
924         doorbell_offset = REG_SET_FIELD(doorbell_offset,
925                                         SDMA0_PAGE_DOORBELL_OFFSET,
926                                         OFFSET, ring->doorbell_index);
927         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
928         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
929
930         /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
931         sdma_v4_0_page_ring_set_wptr(ring);
932
933         /* set minor_ptr_update to 0 after wptr programed */
934         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
935
936         /* setup the wptr shadow polling */
937         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
938         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
939                     lower_32_bits(wptr_gpu_addr));
940         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
941                     upper_32_bits(wptr_gpu_addr));
942         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
943         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
944                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
945                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
946         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
947
948         /* enable DMA RB */
949         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
950         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
951
952         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
953         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
954 #ifdef __BIG_ENDIAN
955         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
956 #endif
957         /* enable DMA IBs */
958         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
959
960         ring->sched.ready = true;
961 }
962
963 static void
964 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
965 {
966         uint32_t def, data;
967
968         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
969                 /* enable idle interrupt */
970                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
971                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
972
973                 if (data != def)
974                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
975         } else {
976                 /* disable idle interrupt */
977                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
978                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
979                 if (data != def)
980                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
981         }
982 }
983
984 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
985 {
986         uint32_t def, data;
987
988         /* Enable HW based PG. */
989         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
990         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
991         if (data != def)
992                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
993
994         /* enable interrupt */
995         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
996         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
997         if (data != def)
998                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
999
1000         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1001         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1002         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1003         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1004         /* Configure switch time for hysteresis purpose. Use default right now */
1005         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1006         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1007         if(data != def)
1008                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1009 }
1010
1011 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1012 {
1013         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1014                 return;
1015
1016         switch (adev->asic_type) {
1017         case CHIP_RAVEN:
1018                 sdma_v4_1_init_power_gating(adev);
1019                 sdma_v4_1_update_power_gating(adev, true);
1020                 break;
1021         default:
1022                 break;
1023         }
1024 }
1025
1026 /**
1027  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1028  *
1029  * @adev: amdgpu_device pointer
1030  *
1031  * Set up the compute DMA queues and enable them (VEGA10).
1032  * Returns 0 for success, error for failure.
1033  */
1034 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1035 {
1036         sdma_v4_0_init_pg(adev);
1037
1038         return 0;
1039 }
1040
1041 /**
1042  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1043  *
1044  * @adev: amdgpu_device pointer
1045  *
1046  * Loads the sDMA0/1 ucode.
1047  * Returns 0 for success, -EINVAL if the ucode is not available.
1048  */
1049 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1050 {
1051         const struct sdma_firmware_header_v1_0 *hdr;
1052         const __le32 *fw_data;
1053         u32 fw_size;
1054         int i, j;
1055
1056         /* halt the MEs */
1057         sdma_v4_0_enable(adev, false);
1058
1059         for (i = 0; i < adev->sdma.num_instances; i++) {
1060                 if (!adev->sdma.instance[i].fw)
1061                         return -EINVAL;
1062
1063                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1064                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1065                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1066
1067                 fw_data = (const __le32 *)
1068                         (adev->sdma.instance[i].fw->data +
1069                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1070
1071                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1072
1073                 for (j = 0; j < fw_size; j++)
1074                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1075                                     le32_to_cpup(fw_data++));
1076
1077                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1078                             adev->sdma.instance[i].fw_version);
1079         }
1080
1081         return 0;
1082 }
1083
1084 /**
1085  * sdma_v4_0_start - setup and start the async dma engines
1086  *
1087  * @adev: amdgpu_device pointer
1088  *
1089  * Set up the DMA engines and enable them (VEGA10).
1090  * Returns 0 for success, error for failure.
1091  */
1092 static int sdma_v4_0_start(struct amdgpu_device *adev)
1093 {
1094         struct amdgpu_ring *ring;
1095         int i, r;
1096
1097         if (amdgpu_sriov_vf(adev)) {
1098                 sdma_v4_0_ctx_switch_enable(adev, false);
1099                 sdma_v4_0_enable(adev, false);
1100         } else {
1101
1102                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1103                         r = sdma_v4_0_load_microcode(adev);
1104                         if (r)
1105                                 return r;
1106                 }
1107
1108                 /* unhalt the MEs */
1109                 sdma_v4_0_enable(adev, true);
1110                 /* enable sdma ring preemption */
1111                 sdma_v4_0_ctx_switch_enable(adev, true);
1112         }
1113
1114         /* start the gfx rings and rlc compute queues */
1115         for (i = 0; i < adev->sdma.num_instances; i++) {
1116                 uint32_t temp;
1117
1118                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1119                 sdma_v4_0_gfx_resume(adev, i);
1120                 if (adev->sdma.has_page_queue)
1121                         sdma_v4_0_page_resume(adev, i);
1122
1123                 /* set utc l1 enable flag always to 1 */
1124                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1125                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1126                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1127
1128                 if (!amdgpu_sriov_vf(adev)) {
1129                         /* unhalt engine */
1130                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1131                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1132                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1133                 }
1134         }
1135
1136         if (amdgpu_sriov_vf(adev)) {
1137                 sdma_v4_0_ctx_switch_enable(adev, true);
1138                 sdma_v4_0_enable(adev, true);
1139         } else {
1140                 r = sdma_v4_0_rlc_resume(adev);
1141                 if (r)
1142                         return r;
1143         }
1144
1145         for (i = 0; i < adev->sdma.num_instances; i++) {
1146                 ring = &adev->sdma.instance[i].ring;
1147
1148                 r = amdgpu_ring_test_helper(ring);
1149                 if (r)
1150                         return r;
1151
1152                 if (adev->sdma.has_page_queue) {
1153                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1154
1155                         r = amdgpu_ring_test_helper(page);
1156                         if (r)
1157                                 return r;
1158
1159                         if (adev->mman.buffer_funcs_ring == page)
1160                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1161                 }
1162
1163                 if (adev->mman.buffer_funcs_ring == ring)
1164                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
1165         }
1166
1167         return r;
1168 }
1169
1170 /**
1171  * sdma_v4_0_ring_test_ring - simple async dma engine test
1172  *
1173  * @ring: amdgpu_ring structure holding ring information
1174  *
1175  * Test the DMA engine by writing using it to write an
1176  * value to memory. (VEGA10).
1177  * Returns 0 for success, error for failure.
1178  */
1179 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1180 {
1181         struct amdgpu_device *adev = ring->adev;
1182         unsigned i;
1183         unsigned index;
1184         int r;
1185         u32 tmp;
1186         u64 gpu_addr;
1187
1188         r = amdgpu_device_wb_get(adev, &index);
1189         if (r)
1190                 return r;
1191
1192         gpu_addr = adev->wb.gpu_addr + (index * 4);
1193         tmp = 0xCAFEDEAD;
1194         adev->wb.wb[index] = cpu_to_le32(tmp);
1195
1196         r = amdgpu_ring_alloc(ring, 5);
1197         if (r)
1198                 goto error_free_wb;
1199
1200         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1201                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1202         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1203         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1204         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1205         amdgpu_ring_write(ring, 0xDEADBEEF);
1206         amdgpu_ring_commit(ring);
1207
1208         for (i = 0; i < adev->usec_timeout; i++) {
1209                 tmp = le32_to_cpu(adev->wb.wb[index]);
1210                 if (tmp == 0xDEADBEEF)
1211                         break;
1212                 DRM_UDELAY(1);
1213         }
1214
1215         if (i >= adev->usec_timeout)
1216                 r = -ETIMEDOUT;
1217
1218 error_free_wb:
1219         amdgpu_device_wb_free(adev, index);
1220         return r;
1221 }
1222
1223 /**
1224  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1225  *
1226  * @ring: amdgpu_ring structure holding ring information
1227  *
1228  * Test a simple IB in the DMA ring (VEGA10).
1229  * Returns 0 on success, error on failure.
1230  */
1231 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1232 {
1233         struct amdgpu_device *adev = ring->adev;
1234         struct amdgpu_ib ib;
1235         struct dma_fence *f = NULL;
1236         unsigned index;
1237         long r;
1238         u32 tmp = 0;
1239         u64 gpu_addr;
1240
1241         r = amdgpu_device_wb_get(adev, &index);
1242         if (r)
1243                 return r;
1244
1245         gpu_addr = adev->wb.gpu_addr + (index * 4);
1246         tmp = 0xCAFEDEAD;
1247         adev->wb.wb[index] = cpu_to_le32(tmp);
1248         memset(&ib, 0, sizeof(ib));
1249         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1250         if (r)
1251                 goto err0;
1252
1253         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1254                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1255         ib.ptr[1] = lower_32_bits(gpu_addr);
1256         ib.ptr[2] = upper_32_bits(gpu_addr);
1257         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1258         ib.ptr[4] = 0xDEADBEEF;
1259         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1260         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1261         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1262         ib.length_dw = 8;
1263
1264         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1265         if (r)
1266                 goto err1;
1267
1268         r = dma_fence_wait_timeout(f, false, timeout);
1269         if (r == 0) {
1270                 r = -ETIMEDOUT;
1271                 goto err1;
1272         } else if (r < 0) {
1273                 goto err1;
1274         }
1275         tmp = le32_to_cpu(adev->wb.wb[index]);
1276         if (tmp == 0xDEADBEEF)
1277                 r = 0;
1278         else
1279                 r = -EINVAL;
1280
1281 err1:
1282         amdgpu_ib_free(adev, &ib, NULL);
1283         dma_fence_put(f);
1284 err0:
1285         amdgpu_device_wb_free(adev, index);
1286         return r;
1287 }
1288
1289
1290 /**
1291  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1292  *
1293  * @ib: indirect buffer to fill with commands
1294  * @pe: addr of the page entry
1295  * @src: src addr to copy from
1296  * @count: number of page entries to update
1297  *
1298  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1299  */
1300 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1301                                   uint64_t pe, uint64_t src,
1302                                   unsigned count)
1303 {
1304         unsigned bytes = count * 8;
1305
1306         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1307                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1308         ib->ptr[ib->length_dw++] = bytes - 1;
1309         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1310         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1311         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1312         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1313         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1314
1315 }
1316
1317 /**
1318  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1319  *
1320  * @ib: indirect buffer to fill with commands
1321  * @pe: addr of the page entry
1322  * @addr: dst addr to write into pe
1323  * @count: number of page entries to update
1324  * @incr: increase next addr by incr bytes
1325  * @flags: access flags
1326  *
1327  * Update PTEs by writing them manually using sDMA (VEGA10).
1328  */
1329 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1330                                    uint64_t value, unsigned count,
1331                                    uint32_t incr)
1332 {
1333         unsigned ndw = count * 2;
1334
1335         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1336                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1337         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1338         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1339         ib->ptr[ib->length_dw++] = ndw - 1;
1340         for (; ndw > 0; ndw -= 2) {
1341                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1342                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1343                 value += incr;
1344         }
1345 }
1346
1347 /**
1348  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1349  *
1350  * @ib: indirect buffer to fill with commands
1351  * @pe: addr of the page entry
1352  * @addr: dst addr to write into pe
1353  * @count: number of page entries to update
1354  * @incr: increase next addr by incr bytes
1355  * @flags: access flags
1356  *
1357  * Update the page tables using sDMA (VEGA10).
1358  */
1359 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1360                                      uint64_t pe,
1361                                      uint64_t addr, unsigned count,
1362                                      uint32_t incr, uint64_t flags)
1363 {
1364         /* for physically contiguous pages (vram) */
1365         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1366         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1367         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1368         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1369         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1370         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1371         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1372         ib->ptr[ib->length_dw++] = incr; /* increment size */
1373         ib->ptr[ib->length_dw++] = 0;
1374         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1375 }
1376
1377 /**
1378  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1379  *
1380  * @ib: indirect buffer to fill with padding
1381  *
1382  */
1383 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1384 {
1385         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1386         u32 pad_count;
1387         int i;
1388
1389         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1390         for (i = 0; i < pad_count; i++)
1391                 if (sdma && sdma->burst_nop && (i == 0))
1392                         ib->ptr[ib->length_dw++] =
1393                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1394                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1395                 else
1396                         ib->ptr[ib->length_dw++] =
1397                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1398 }
1399
1400
1401 /**
1402  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1403  *
1404  * @ring: amdgpu_ring pointer
1405  *
1406  * Make sure all previous operations are completed (CIK).
1407  */
1408 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1409 {
1410         uint32_t seq = ring->fence_drv.sync_seq;
1411         uint64_t addr = ring->fence_drv.gpu_addr;
1412
1413         /* wait for idle */
1414         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1415                                addr & 0xfffffffc,
1416                                upper_32_bits(addr) & 0xffffffff,
1417                                seq, 0xffffffff, 4);
1418 }
1419
1420
1421 /**
1422  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1423  *
1424  * @ring: amdgpu_ring pointer
1425  * @vm: amdgpu_vm pointer
1426  *
1427  * Update the page table base and flush the VM TLB
1428  * using sDMA (VEGA10).
1429  */
1430 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1431                                          unsigned vmid, uint64_t pd_addr)
1432 {
1433         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1434 }
1435
1436 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1437                                      uint32_t reg, uint32_t val)
1438 {
1439         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1440                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1441         amdgpu_ring_write(ring, reg);
1442         amdgpu_ring_write(ring, val);
1443 }
1444
1445 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1446                                          uint32_t val, uint32_t mask)
1447 {
1448         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1449 }
1450
1451 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1452 {
1453         uint fw_version = adev->sdma.instance[0].fw_version;
1454
1455         switch (adev->asic_type) {
1456         case CHIP_VEGA10:
1457                 return fw_version >= 430;
1458         case CHIP_VEGA12:
1459                 /*return fw_version >= 31;*/
1460                 return false;
1461         case CHIP_VEGA20:
1462                 return fw_version >= 123;
1463         default:
1464                 return false;
1465         }
1466 }
1467
1468 static int sdma_v4_0_early_init(void *handle)
1469 {
1470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471         int r;
1472
1473         if (adev->asic_type == CHIP_RAVEN)
1474                 adev->sdma.num_instances = 1;
1475         else
1476                 adev->sdma.num_instances = 2;
1477
1478         r = sdma_v4_0_init_microcode(adev);
1479         if (r) {
1480                 DRM_ERROR("Failed to load sdma firmware!\n");
1481                 return r;
1482         }
1483
1484         /* TODO: Page queue breaks driver reload under SRIOV */
1485         if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1486                 adev->sdma.has_page_queue = false;
1487         else if (sdma_v4_0_fw_support_paging_queue(adev))
1488                 adev->sdma.has_page_queue = true;
1489
1490         sdma_v4_0_set_ring_funcs(adev);
1491         sdma_v4_0_set_buffer_funcs(adev);
1492         sdma_v4_0_set_vm_pte_funcs(adev);
1493         sdma_v4_0_set_irq_funcs(adev);
1494
1495         return 0;
1496 }
1497
1498 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1499                 struct amdgpu_iv_entry *entry);
1500
1501 static int sdma_v4_0_late_init(void *handle)
1502 {
1503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1504         struct ras_common_if **ras_if = &adev->sdma.ras_if;
1505         struct ras_ih_if ih_info = {
1506                 .cb = sdma_v4_0_process_ras_data_cb,
1507         };
1508         struct ras_fs_if fs_info = {
1509                 .sysfs_name = "sdma_err_count",
1510                 .debugfs_name = "sdma_err_inject",
1511         };
1512         struct ras_common_if ras_block = {
1513                 .block = AMDGPU_RAS_BLOCK__SDMA,
1514                 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1515                 .sub_block_index = 0,
1516                 .name = "sdma",
1517         };
1518         int r;
1519
1520         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1521                 amdgpu_ras_feature_enable(adev, &ras_block, 0);
1522                 return 0;
1523         }
1524
1525         /* handle resume path. */
1526         if (*ras_if)
1527                 goto resume;
1528
1529         *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
1530         if (!*ras_if)
1531                 return -ENOMEM;
1532
1533         **ras_if = ras_block;
1534
1535         r = amdgpu_ras_feature_enable(adev, *ras_if, 1);
1536         if (r)
1537                 goto feature;
1538
1539         ih_info.head = **ras_if;
1540         fs_info.head = **ras_if;
1541
1542         r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
1543         if (r)
1544                 goto interrupt;
1545
1546         r = amdgpu_ras_debugfs_create(adev, &fs_info);
1547         if (r)
1548                 goto debugfs;
1549
1550         r = amdgpu_ras_sysfs_create(adev, &fs_info);
1551         if (r)
1552                 goto sysfs;
1553 resume:
1554         r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
1555         if (r)
1556                 goto irq;
1557
1558         r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC1);
1559         if (r) {
1560                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
1561                 goto irq;
1562         }
1563
1564         return 0;
1565 irq:
1566         amdgpu_ras_sysfs_remove(adev, *ras_if);
1567 sysfs:
1568         amdgpu_ras_debugfs_remove(adev, *ras_if);
1569 debugfs:
1570         amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1571 interrupt:
1572         amdgpu_ras_feature_enable(adev, *ras_if, 0);
1573 feature:
1574         kfree(*ras_if);
1575         *ras_if = NULL;
1576         return -EINVAL;
1577 }
1578
1579 static int sdma_v4_0_sw_init(void *handle)
1580 {
1581         struct amdgpu_ring *ring;
1582         int r, i;
1583         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1584
1585         /* SDMA trap event */
1586         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
1587                               &adev->sdma.trap_irq);
1588         if (r)
1589                 return r;
1590
1591         /* SDMA trap event */
1592         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
1593                               &adev->sdma.trap_irq);
1594         if (r)
1595                 return r;
1596
1597         /* SDMA SRAM ECC event */
1598         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1599                         &adev->sdma.ecc_irq);
1600         if (r)
1601                 return r;
1602
1603         /* SDMA SRAM ECC event */
1604         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_SRAM_ECC,
1605                         &adev->sdma.ecc_irq);
1606         if (r)
1607                 return r;
1608
1609         for (i = 0; i < adev->sdma.num_instances; i++) {
1610                 ring = &adev->sdma.instance[i].ring;
1611                 ring->ring_obj = NULL;
1612                 ring->use_doorbell = true;
1613
1614                 DRM_INFO("use_doorbell being set to: [%s]\n",
1615                                 ring->use_doorbell?"true":"false");
1616
1617                 /* doorbell size is 2 dwords, get DWORD offset */
1618                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1619
1620                 sprintf(ring->name, "sdma%d", i);
1621                 r = amdgpu_ring_init(adev, ring, 1024,
1622                                      &adev->sdma.trap_irq,
1623                                      (i == 0) ?
1624                                      AMDGPU_SDMA_IRQ_TRAP0 :
1625                                      AMDGPU_SDMA_IRQ_TRAP1);
1626                 if (r)
1627                         return r;
1628
1629                 if (adev->sdma.has_page_queue) {
1630                         ring = &adev->sdma.instance[i].page;
1631                         ring->ring_obj = NULL;
1632                         ring->use_doorbell = true;
1633
1634                         /* paging queue use same doorbell index/routing as gfx queue
1635                          * with 0x400 (4096 dwords) offset on second doorbell page
1636                          */
1637                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1638                         ring->doorbell_index += 0x400;
1639
1640                         sprintf(ring->name, "page%d", i);
1641                         r = amdgpu_ring_init(adev, ring, 1024,
1642                                              &adev->sdma.trap_irq,
1643                                              (i == 0) ?
1644                                              AMDGPU_SDMA_IRQ_TRAP0 :
1645                                              AMDGPU_SDMA_IRQ_TRAP1);
1646                         if (r)
1647                                 return r;
1648                 }
1649         }
1650
1651         return r;
1652 }
1653
1654 static int sdma_v4_0_sw_fini(void *handle)
1655 {
1656         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1657         int i;
1658
1659         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
1660                         adev->sdma.ras_if) {
1661                 struct ras_common_if *ras_if = adev->sdma.ras_if;
1662                 struct ras_ih_if ih_info = {
1663                         .head = *ras_if,
1664                 };
1665
1666                 /*remove fs first*/
1667                 amdgpu_ras_debugfs_remove(adev, ras_if);
1668                 amdgpu_ras_sysfs_remove(adev, ras_if);
1669                 /*remove the IH*/
1670                 amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
1671                 amdgpu_ras_feature_enable(adev, ras_if, 0);
1672                 kfree(ras_if);
1673         }
1674
1675         for (i = 0; i < adev->sdma.num_instances; i++) {
1676                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1677                 if (adev->sdma.has_page_queue)
1678                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1679         }
1680
1681         for (i = 0; i < adev->sdma.num_instances; i++) {
1682                 release_firmware(adev->sdma.instance[i].fw);
1683                 adev->sdma.instance[i].fw = NULL;
1684         }
1685
1686         return 0;
1687 }
1688
1689 static int sdma_v4_0_hw_init(void *handle)
1690 {
1691         int r;
1692         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1693
1694         if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1695                         adev->powerplay.pp_funcs->set_powergating_by_smu)
1696                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1697
1698         sdma_v4_0_init_golden_registers(adev);
1699
1700         r = sdma_v4_0_start(adev);
1701
1702         return r;
1703 }
1704
1705 static int sdma_v4_0_hw_fini(void *handle)
1706 {
1707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1708
1709         if (amdgpu_sriov_vf(adev))
1710                 return 0;
1711
1712         amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC0);
1713         amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_ECC1);
1714
1715         sdma_v4_0_ctx_switch_enable(adev, false);
1716         sdma_v4_0_enable(adev, false);
1717
1718         if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1719                         && adev->powerplay.pp_funcs->set_powergating_by_smu)
1720                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1721
1722         return 0;
1723 }
1724
1725 static int sdma_v4_0_suspend(void *handle)
1726 {
1727         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1728
1729         return sdma_v4_0_hw_fini(adev);
1730 }
1731
1732 static int sdma_v4_0_resume(void *handle)
1733 {
1734         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1735
1736         return sdma_v4_0_hw_init(adev);
1737 }
1738
1739 static bool sdma_v4_0_is_idle(void *handle)
1740 {
1741         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1742         u32 i;
1743
1744         for (i = 0; i < adev->sdma.num_instances; i++) {
1745                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1746
1747                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1748                         return false;
1749         }
1750
1751         return true;
1752 }
1753
1754 static int sdma_v4_0_wait_for_idle(void *handle)
1755 {
1756         unsigned i;
1757         u32 sdma0, sdma1;
1758         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1759
1760         for (i = 0; i < adev->usec_timeout; i++) {
1761                 sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG);
1762                 sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG);
1763
1764                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1765                         return 0;
1766                 udelay(1);
1767         }
1768         return -ETIMEDOUT;
1769 }
1770
1771 static int sdma_v4_0_soft_reset(void *handle)
1772 {
1773         /* todo */
1774
1775         return 0;
1776 }
1777
1778 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1779                                         struct amdgpu_irq_src *source,
1780                                         unsigned type,
1781                                         enum amdgpu_interrupt_state state)
1782 {
1783         unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1;
1784         u32 sdma_cntl;
1785
1786         sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL);
1787         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1788                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1789         WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl);
1790
1791         return 0;
1792 }
1793
1794 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1795                                       struct amdgpu_irq_src *source,
1796                                       struct amdgpu_iv_entry *entry)
1797 {
1798         uint32_t instance;
1799
1800         DRM_DEBUG("IH: SDMA trap\n");
1801         switch (entry->client_id) {
1802         case SOC15_IH_CLIENTID_SDMA0:
1803                 instance = 0;
1804                 break;
1805         case SOC15_IH_CLIENTID_SDMA1:
1806                 instance = 1;
1807                 break;
1808         default:
1809                 return 0;
1810         }
1811
1812         switch (entry->ring_id) {
1813         case 0:
1814                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
1815                 break;
1816         case 1:
1817                 if (adev->asic_type == CHIP_VEGA20)
1818                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
1819                 break;
1820         case 2:
1821                 /* XXX compute */
1822                 break;
1823         case 3:
1824                 if (adev->asic_type != CHIP_VEGA20)
1825                         amdgpu_fence_process(&adev->sdma.instance[instance].page);
1826                 break;
1827         }
1828         return 0;
1829 }
1830
1831 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1832                 struct amdgpu_iv_entry *entry)
1833 {
1834         uint32_t instance, err_source;
1835
1836         switch (entry->client_id) {
1837         case SOC15_IH_CLIENTID_SDMA0:
1838                 instance = 0;
1839                 break;
1840         case SOC15_IH_CLIENTID_SDMA1:
1841                 instance = 1;
1842                 break;
1843         default:
1844                 return 0;
1845         }
1846
1847         switch (entry->src_id) {
1848         case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
1849                 err_source = 0;
1850                 break;
1851         case SDMA0_4_0__SRCID__SDMA_ECC:
1852                 err_source = 1;
1853                 break;
1854         default:
1855                 return 0;
1856         }
1857
1858         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
1859
1860         amdgpu_ras_reset_gpu(adev, 0);
1861
1862         return AMDGPU_RAS_UE;
1863 }
1864
1865 static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
1866                                       struct amdgpu_irq_src *source,
1867                                       struct amdgpu_iv_entry *entry)
1868 {
1869         struct ras_dispatch_if ih_data = {
1870                 .head = *adev->sdma.ras_if,
1871                 .entry = entry,
1872         };
1873         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1874         return 0;
1875 }
1876
1877 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1878                                               struct amdgpu_irq_src *source,
1879                                               struct amdgpu_iv_entry *entry)
1880 {
1881         int instance;
1882
1883         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1884
1885         switch (entry->client_id) {
1886         case SOC15_IH_CLIENTID_SDMA0:
1887                 instance = 0;
1888                 break;
1889         case SOC15_IH_CLIENTID_SDMA1:
1890                 instance = 1;
1891                 break;
1892         default:
1893                 return 0;
1894         }
1895
1896         switch (entry->ring_id) {
1897         case 0:
1898                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1899                 break;
1900         }
1901         return 0;
1902 }
1903
1904 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
1905                                         struct amdgpu_irq_src *source,
1906                                         unsigned type,
1907                                         enum amdgpu_interrupt_state state)
1908 {
1909         u32 sdma_edc_config;
1910
1911         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_ECC0) ?
1912                 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) :
1913                 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG);
1914
1915         sdma_edc_config = RREG32(reg_offset);
1916         sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
1917                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1918         WREG32(reg_offset, sdma_edc_config);
1919
1920         return 0;
1921 }
1922
1923 static void sdma_v4_0_update_medium_grain_clock_gating(
1924                 struct amdgpu_device *adev,
1925                 bool enable)
1926 {
1927         uint32_t data, def;
1928
1929         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1930                 /* enable sdma0 clock gating */
1931                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1932                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1933                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1934                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1935                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1936                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1937                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1938                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1939                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1940                 if (def != data)
1941                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1942
1943                 if (adev->sdma.num_instances > 1) {
1944                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1945                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1946                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1947                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1948                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1949                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1950                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1951                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1952                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1953                         if (def != data)
1954                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1955                 }
1956         } else {
1957                 /* disable sdma0 clock gating */
1958                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1959                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1960                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1961                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1962                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1963                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1964                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1965                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1966                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1967
1968                 if (def != data)
1969                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1970
1971                 if (adev->sdma.num_instances > 1) {
1972                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1973                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1974                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1975                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1976                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1977                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1978                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1979                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1980                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1981                         if (def != data)
1982                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1983                 }
1984         }
1985 }
1986
1987
1988 static void sdma_v4_0_update_medium_grain_light_sleep(
1989                 struct amdgpu_device *adev,
1990                 bool enable)
1991 {
1992         uint32_t data, def;
1993
1994         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1995                 /* 1-not override: enable sdma0 mem light sleep */
1996                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1997                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1998                 if (def != data)
1999                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
2000
2001                 /* 1-not override: enable sdma1 mem light sleep */
2002                 if (adev->sdma.num_instances > 1) {
2003                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
2004                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2005                         if (def != data)
2006                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
2007                 }
2008         } else {
2009                 /* 0-override:disable sdma0 mem light sleep */
2010                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2011                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2012                 if (def != data)
2013                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
2014
2015                 /* 0-override:disable sdma1 mem light sleep */
2016                 if (adev->sdma.num_instances > 1) {
2017                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
2018                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2019                         if (def != data)
2020                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
2021                 }
2022         }
2023 }
2024
2025 static int sdma_v4_0_set_clockgating_state(void *handle,
2026                                           enum amd_clockgating_state state)
2027 {
2028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2029
2030         if (amdgpu_sriov_vf(adev))
2031                 return 0;
2032
2033         switch (adev->asic_type) {
2034         case CHIP_VEGA10:
2035         case CHIP_VEGA12:
2036         case CHIP_VEGA20:
2037         case CHIP_RAVEN:
2038                 sdma_v4_0_update_medium_grain_clock_gating(adev,
2039                                 state == AMD_CG_STATE_GATE ? true : false);
2040                 sdma_v4_0_update_medium_grain_light_sleep(adev,
2041                                 state == AMD_CG_STATE_GATE ? true : false);
2042                 break;
2043         default:
2044                 break;
2045         }
2046         return 0;
2047 }
2048
2049 static int sdma_v4_0_set_powergating_state(void *handle,
2050                                           enum amd_powergating_state state)
2051 {
2052         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2053
2054         switch (adev->asic_type) {
2055         case CHIP_RAVEN:
2056                 sdma_v4_1_update_power_gating(adev,
2057                                 state == AMD_PG_STATE_GATE ? true : false);
2058                 break;
2059         default:
2060                 break;
2061         }
2062
2063         return 0;
2064 }
2065
2066 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2067 {
2068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2069         int data;
2070
2071         if (amdgpu_sriov_vf(adev))
2072                 *flags = 0;
2073
2074         /* AMD_CG_SUPPORT_SDMA_MGCG */
2075         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2076         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2077                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2078
2079         /* AMD_CG_SUPPORT_SDMA_LS */
2080         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2081         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2082                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2083 }
2084
2085 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2086         .name = "sdma_v4_0",
2087         .early_init = sdma_v4_0_early_init,
2088         .late_init = sdma_v4_0_late_init,
2089         .sw_init = sdma_v4_0_sw_init,
2090         .sw_fini = sdma_v4_0_sw_fini,
2091         .hw_init = sdma_v4_0_hw_init,
2092         .hw_fini = sdma_v4_0_hw_fini,
2093         .suspend = sdma_v4_0_suspend,
2094         .resume = sdma_v4_0_resume,
2095         .is_idle = sdma_v4_0_is_idle,
2096         .wait_for_idle = sdma_v4_0_wait_for_idle,
2097         .soft_reset = sdma_v4_0_soft_reset,
2098         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2099         .set_powergating_state = sdma_v4_0_set_powergating_state,
2100         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2101 };
2102
2103 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2104         .type = AMDGPU_RING_TYPE_SDMA,
2105         .align_mask = 0xf,
2106         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2107         .support_64bit_ptrs = true,
2108         .vmhub = AMDGPU_MMHUB,
2109         .get_rptr = sdma_v4_0_ring_get_rptr,
2110         .get_wptr = sdma_v4_0_ring_get_wptr,
2111         .set_wptr = sdma_v4_0_ring_set_wptr,
2112         .emit_frame_size =
2113                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2114                 3 + /* hdp invalidate */
2115                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2116                 /* sdma_v4_0_ring_emit_vm_flush */
2117                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2118                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2119                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2120         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2121         .emit_ib = sdma_v4_0_ring_emit_ib,
2122         .emit_fence = sdma_v4_0_ring_emit_fence,
2123         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2124         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2125         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2126         .test_ring = sdma_v4_0_ring_test_ring,
2127         .test_ib = sdma_v4_0_ring_test_ib,
2128         .insert_nop = sdma_v4_0_ring_insert_nop,
2129         .pad_ib = sdma_v4_0_ring_pad_ib,
2130         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2131         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2132         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2133 };
2134
2135 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2136         .type = AMDGPU_RING_TYPE_SDMA,
2137         .align_mask = 0xf,
2138         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2139         .support_64bit_ptrs = true,
2140         .vmhub = AMDGPU_MMHUB,
2141         .get_rptr = sdma_v4_0_ring_get_rptr,
2142         .get_wptr = sdma_v4_0_page_ring_get_wptr,
2143         .set_wptr = sdma_v4_0_page_ring_set_wptr,
2144         .emit_frame_size =
2145                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2146                 3 + /* hdp invalidate */
2147                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2148                 /* sdma_v4_0_ring_emit_vm_flush */
2149                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2150                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2151                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2152         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2153         .emit_ib = sdma_v4_0_ring_emit_ib,
2154         .emit_fence = sdma_v4_0_ring_emit_fence,
2155         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2156         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2157         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2158         .test_ring = sdma_v4_0_ring_test_ring,
2159         .test_ib = sdma_v4_0_ring_test_ib,
2160         .insert_nop = sdma_v4_0_ring_insert_nop,
2161         .pad_ib = sdma_v4_0_ring_pad_ib,
2162         .emit_wreg = sdma_v4_0_ring_emit_wreg,
2163         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2164         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2165 };
2166
2167 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2168 {
2169         int i;
2170
2171         for (i = 0; i < adev->sdma.num_instances; i++) {
2172                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
2173                 adev->sdma.instance[i].ring.me = i;
2174                 if (adev->sdma.has_page_queue) {
2175                         adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs;
2176                         adev->sdma.instance[i].page.me = i;
2177                 }
2178         }
2179 }
2180
2181 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2182         .set = sdma_v4_0_set_trap_irq_state,
2183         .process = sdma_v4_0_process_trap_irq,
2184 };
2185
2186 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2187         .process = sdma_v4_0_process_illegal_inst_irq,
2188 };
2189
2190 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2191         .set = sdma_v4_0_set_ecc_irq_state,
2192         .process = sdma_v4_0_process_ecc_irq,
2193 };
2194
2195
2196
2197 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2198 {
2199         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2200         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2201         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2202         adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2203         adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2204 }
2205
2206 /**
2207  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2208  *
2209  * @ring: amdgpu_ring structure holding ring information
2210  * @src_offset: src GPU address
2211  * @dst_offset: dst GPU address
2212  * @byte_count: number of bytes to xfer
2213  *
2214  * Copy GPU buffers using the DMA engine (VEGA10/12).
2215  * Used by the amdgpu ttm implementation to move pages if
2216  * registered as the asic copy callback.
2217  */
2218 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2219                                        uint64_t src_offset,
2220                                        uint64_t dst_offset,
2221                                        uint32_t byte_count)
2222 {
2223         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2224                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2225         ib->ptr[ib->length_dw++] = byte_count - 1;
2226         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2227         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2228         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2229         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2230         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2231 }
2232
2233 /**
2234  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2235  *
2236  * @ring: amdgpu_ring structure holding ring information
2237  * @src_data: value to write to buffer
2238  * @dst_offset: dst GPU address
2239  * @byte_count: number of bytes to xfer
2240  *
2241  * Fill GPU buffers using the DMA engine (VEGA10/12).
2242  */
2243 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2244                                        uint32_t src_data,
2245                                        uint64_t dst_offset,
2246                                        uint32_t byte_count)
2247 {
2248         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2249         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2250         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2251         ib->ptr[ib->length_dw++] = src_data;
2252         ib->ptr[ib->length_dw++] = byte_count - 1;
2253 }
2254
2255 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2256         .copy_max_bytes = 0x400000,
2257         .copy_num_dw = 7,
2258         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2259
2260         .fill_max_bytes = 0x400000,
2261         .fill_num_dw = 5,
2262         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2263 };
2264
2265 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2266 {
2267         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2268         if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1)
2269                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page;
2270         else
2271                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2272 }
2273
2274 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2275         .copy_pte_num_dw = 7,
2276         .copy_pte = sdma_v4_0_vm_copy_pte,
2277
2278         .write_pte = sdma_v4_0_vm_write_pte,
2279         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2280 };
2281
2282 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2283 {
2284         struct drm_gpu_scheduler *sched;
2285         unsigned i;
2286
2287         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2288         if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) {
2289                 for (i = 1; i < adev->sdma.num_instances; i++) {
2290                         sched = &adev->sdma.instance[i].page.sched;
2291                         adev->vm_manager.vm_pte_rqs[i - 1] =
2292                                 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2293                 }
2294                 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1;
2295         } else {
2296                 for (i = 0; i < adev->sdma.num_instances; i++) {
2297                         sched = &adev->sdma.instance[i].ring.sched;
2298                         adev->vm_manager.vm_pte_rqs[i] =
2299                                 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2300                 }
2301                 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
2302         }
2303 }
2304
2305 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2306         .type = AMD_IP_BLOCK_TYPE_SDMA,
2307         .major = 4,
2308         .minor = 0,
2309         .rev = 0,
2310         .funcs = &sdma_v4_0_ip_funcs,
2311 };