drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "vega10/soc15ip.h"
  31 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  32 #include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
  33 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  34 #include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
  35 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  37 #include "vega10/HDP/hdp_4_0_offset.h"
  38 #include "raven1/SDMA0/sdma0_4_1_default.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "vega10_sdma_pkt_open.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  46 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  47
  48 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  49 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  50
  51 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  52 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  53 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  54 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  55
  56 static const u32 golden_settings_sdma_4[] = {
  57         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
  58         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
  59         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  60         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  61         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  62         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  63         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
  64         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  65         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  66         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  67         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  68         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
  69         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  70         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
  71         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  72         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  73         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  74         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  75         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
  76         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  77         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  78         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  79         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  80         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
  81 };
  82
  83 static const u32 golden_settings_sdma_vg10[] = {
  84         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  85         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
  86         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  87         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
  88 };
  89
  90 static const u32 golden_settings_sdma_4_1[] =
  91 {
  92         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831d07,
  93         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
  94         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
  95         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  96         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
  97         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
  98         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  99         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
 100         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
 101         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
 102 };
 103
 104 static const u32 golden_settings_sdma_rv1[] =
 105 {
 106         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002,
 107         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
 108 };
 109
 110 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
 111 {
 112         u32 base = 0;
 113
 114         switch (instance) {
 115         case 0:
 116                 base = SDMA0_BASE.instance[0].segment[0];
 117                 break;
 118         case 1:
 119                 base = SDMA1_BASE.instance[0].segment[0];
 120                 break;
 121         default:
 122                 BUG();
 123                 break;
 124         }
 125
 126         return base + internal_offset;
 127 }
 128
 129 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 130 {
 131         switch (adev->asic_type) {
 132         case CHIP_VEGA10:
 133                 amdgpu_program_register_sequence(adev,
 134                                                  golden_settings_sdma_4,
 135                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4));
 136                 amdgpu_program_register_sequence(adev,
 137                                                  golden_settings_sdma_vg10,
 138                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
 139                 break;
 140         case CHIP_RAVEN:
 141                 amdgpu_program_register_sequence(adev,
 142                                                  golden_settings_sdma_4_1,
 143                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
 144                 amdgpu_program_register_sequence(adev,
 145                                                  golden_settings_sdma_rv1,
 146                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
 147                 break;
 148         default:
 149                 break;
 150         }
 151 }
 152
 153 /**
 154  * sdma_v4_0_init_microcode - load ucode images from disk
 155  *
 156  * @adev: amdgpu_device pointer
 157  *
 158  * Use the firmware interface to load the ucode images into
 159  * the driver (not loaded into hw).
 160  * Returns 0 on success, error on failure.
 161  */
 162
 163 // emulation only, won't work on real chip
 164 // vega10 real chip need to use PSP to load firmware
 165 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 166 {
 167         const char *chip_name;
 168         char fw_name[30];
 169         int err = 0, i;
 170         struct amdgpu_firmware_info *info = NULL;
 171         const struct common_firmware_header *header = NULL;
 172         const struct sdma_firmware_header_v1_0 *hdr;
 173
 174         DRM_DEBUG("\n");
 175
 176         switch (adev->asic_type) {
 177         case CHIP_VEGA10:
 178                 chip_name = "vega10";
 179                 break;
 180         case CHIP_RAVEN:
 181                 chip_name = "raven";
 182                 break;
 183         default:
 184                 BUG();
 185         }
 186
 187         for (i = 0; i < adev->sdma.num_instances; i++) {
 188                 if (i == 0)
 189                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 190                 else
 191                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 192                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 193                 if (err)
 194                         goto out;
 195                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 196                 if (err)
 197                         goto out;
 198                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 199                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 200                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 201                 if (adev->sdma.instance[i].feature_version >= 20)
 202                         adev->sdma.instance[i].burst_nop = true;
 203                 DRM_DEBUG("psp_load == '%s'\n",
 204                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 205
 206                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 207                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 208                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 209                         info->fw = adev->sdma.instance[i].fw;
 210                         header = (const struct common_firmware_header *)info->fw->data;
 211                         adev->firmware.fw_size +=
 212                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 213                 }
 214         }
 215 out:
 216         if (err) {
 217                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 218                 for (i = 0; i < adev->sdma.num_instances; i++) {
 219                         release_firmware(adev->sdma.instance[i].fw);
 220                         adev->sdma.instance[i].fw = NULL;
 221                 }
 222         }
 223         return err;
 224 }
 225
 226 /**
 227  * sdma_v4_0_ring_get_rptr - get the current read pointer
 228  *
 229  * @ring: amdgpu ring pointer
 230  *
 231  * Get the current rptr from the hardware (VEGA10+).
 232  */
 233 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 234 {
 235         u64 *rptr;
 236
 237         /* XXX check if swapping is necessary on BE */
 238         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 239
 240         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 241         return ((*rptr) >> 2);
 242 }
 243
 244 /**
 245  * sdma_v4_0_ring_get_wptr - get the current write pointer
 246  *
 247  * @ring: amdgpu ring pointer
 248  *
 249  * Get the current wptr from the hardware (VEGA10+).
 250  */
 251 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 252 {
 253         struct amdgpu_device *adev = ring->adev;
 254         u64 *wptr = NULL;
 255         uint64_t local_wptr = 0;
 256
 257         if (ring->use_doorbell) {
 258                 /* XXX check if swapping is necessary on BE */
 259                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 260                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 261                 *wptr = (*wptr) >> 2;
 262                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 263         } else {
 264                 u32 lowbit, highbit;
 265                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 266
 267                 wptr = &local_wptr;
 268                 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 269                 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 270
 271                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 272                                 me, highbit, lowbit);
 273                 *wptr = highbit;
 274                 *wptr = (*wptr) << 32;
 275                 *wptr |= lowbit;
 276         }
 277
 278         return *wptr;
 279 }
 280
 281 /**
 282  * sdma_v4_0_ring_set_wptr - commit the write pointer
 283  *
 284  * @ring: amdgpu ring pointer
 285  *
 286  * Write the wptr back to the hardware (VEGA10+).
 287  */
 288 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 289 {
 290         struct amdgpu_device *adev = ring->adev;
 291
 292         DRM_DEBUG("Setting write pointer\n");
 293         if (ring->use_doorbell) {
 294                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 295
 296                 DRM_DEBUG("Using doorbell -- "
 297                                 "wptr_offs == 0x%08x "
 298                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 299                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 300                                 ring->wptr_offs,
 301                                 lower_32_bits(ring->wptr << 2),
 302                                 upper_32_bits(ring->wptr << 2));
 303                 /* XXX check if swapping is necessary on BE */
 304                 WRITE_ONCE(*wb, (ring->wptr << 2));
 305                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 306                                 ring->doorbell_index, ring->wptr << 2);
 307                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 308         } else {
 309                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 310
 311                 DRM_DEBUG("Not using doorbell -- "
 312                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 313                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 314                                 me,
 315                                 lower_32_bits(ring->wptr << 2),
 316                                 me,
 317                                 upper_32_bits(ring->wptr << 2));
 318                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 319                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 320         }
 321 }
 322
 323 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 324 {
 325         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 326         int i;
 327
 328         for (i = 0; i < count; i++)
 329                 if (sdma && sdma->burst_nop && (i == 0))
 330                         amdgpu_ring_write(ring, ring->funcs->nop |
 331                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 332                 else
 333                         amdgpu_ring_write(ring, ring->funcs->nop);
 334 }
 335
 336 /**
 337  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 338  *
 339  * @ring: amdgpu ring pointer
 340  * @ib: IB object to schedule
 341  *
 342  * Schedule an IB in the DMA ring (VEGA10).
 343  */
 344 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 345                                         struct amdgpu_ib *ib,
 346                                         unsigned vm_id, bool ctx_switch)
 347 {
 348         u32 vmid = vm_id & 0xf;
 349
 350         /* IB packet must end on a 8 DW boundary */
 351         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 352
 353         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 354                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 355         /* base must be 32 byte aligned */
 356         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 357         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 358         amdgpu_ring_write(ring, ib->length_dw);
 359         amdgpu_ring_write(ring, 0);
 360         amdgpu_ring_write(ring, 0);
 361
 362 }
 363
 364 /**
 365  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 366  *
 367  * @ring: amdgpu ring pointer
 368  *
 369  * Emit an hdp flush packet on the requested DMA ring.
 370  */
 371 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 372 {
 373         u32 ref_and_mask = 0;
 374         const struct nbio_hdp_flush_reg *nbio_hf_reg;
 375
 376         if (ring->adev->flags & AMD_IS_APU)
 377                 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
 378         else
 379                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
 380
 381         if (ring == &ring->adev->sdma.instance[0].ring)
 382                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 383         else
 384                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 385
 386         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 387                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 388                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 389         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2);
 390         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2);
 391         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 392         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 393         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 394                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 395 }
 396
 397 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 398 {
 399         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 400                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 401         amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
 402         amdgpu_ring_write(ring, 1);
 403 }
 404
 405 /**
 406  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 407  *
 408  * @ring: amdgpu ring pointer
 409  * @fence: amdgpu fence object
 410  *
 411  * Add a DMA fence packet to the ring to write
 412  * the fence seq number and DMA trap packet to generate
 413  * an interrupt if needed (VEGA10).
 414  */
 415 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 416                                       unsigned flags)
 417 {
 418         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 419         /* write the fence */
 420         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 421         /* zero in first two bits */
 422         BUG_ON(addr & 0x3);
 423         amdgpu_ring_write(ring, lower_32_bits(addr));
 424         amdgpu_ring_write(ring, upper_32_bits(addr));
 425         amdgpu_ring_write(ring, lower_32_bits(seq));
 426
 427         /* optionally write high bits as well */
 428         if (write64bit) {
 429                 addr += 4;
 430                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 431                 /* zero in first two bits */
 432                 BUG_ON(addr & 0x3);
 433                 amdgpu_ring_write(ring, lower_32_bits(addr));
 434                 amdgpu_ring_write(ring, upper_32_bits(addr));
 435                 amdgpu_ring_write(ring, upper_32_bits(seq));
 436         }
 437
 438         /* generate an interrupt */
 439         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 440         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 441 }
 442
 443
 444 /**
 445  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 446  *
 447  * @adev: amdgpu_device pointer
 448  *
 449  * Stop the gfx async dma ring buffers (VEGA10).
 450  */
 451 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 452 {
 453         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 454         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 455         u32 rb_cntl, ib_cntl;
 456         int i;
 457
 458         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 459             (adev->mman.buffer_funcs_ring == sdma1))
 460                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 461
 462         for (i = 0; i < adev->sdma.num_instances; i++) {
 463                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 464                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 465                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 466                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 467                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 468                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 469         }
 470
 471         sdma0->ready = false;
 472         sdma1->ready = false;
 473 }
 474
 475 /**
 476  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 477  *
 478  * @adev: amdgpu_device pointer
 479  *
 480  * Stop the compute async dma queues (VEGA10).
 481  */
 482 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 483 {
 484         /* XXX todo */
 485 }
 486
 487 /**
 488  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 489  *
 490  * @adev: amdgpu_device pointer
 491  * @enable: enable/disable the DMA MEs context switch.
 492  *
 493  * Halt or unhalt the async dma engines context switch (VEGA10).
 494  */
 495 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 496 {
 497         u32 f32_cntl, phase_quantum = 0;
 498         int i;
 499
 500         if (amdgpu_sdma_phase_quantum) {
 501                 unsigned value = amdgpu_sdma_phase_quantum;
 502                 unsigned unit = 0;
 503
 504                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 505                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 506                         value = (value + 1) >> 1;
 507                         unit++;
 508                 }
 509                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 510                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 511                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 512                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 513                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 514                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 515                         WARN_ONCE(1,
 516                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 517                                   value << unit);
 518                 }
 519                 phase_quantum =
 520                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 521                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 522         }
 523
 524         for (i = 0; i < adev->sdma.num_instances; i++) {
 525                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 526                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 527                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 528                 if (enable && amdgpu_sdma_phase_quantum) {
 529                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE0_QUANTUM),
 530                                phase_quantum);
 531                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE1_QUANTUM),
 532                                phase_quantum);
 533                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE2_QUANTUM),
 534                                phase_quantum);
 535                 }
 536                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl);
 537         }
 538
 539 }
 540
 541 /**
 542  * sdma_v4_0_enable - stop the async dma engines
 543  *
 544  * @adev: amdgpu_device pointer
 545  * @enable: enable/disable the DMA MEs.
 546  *
 547  * Halt or unhalt the async dma engines (VEGA10).
 548  */
 549 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 550 {
 551         u32 f32_cntl;
 552         int i;
 553
 554         if (enable == false) {
 555                 sdma_v4_0_gfx_stop(adev);
 556                 sdma_v4_0_rlc_stop(adev);
 557         }
 558
 559         for (i = 0; i < adev->sdma.num_instances; i++) {
 560                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 561                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 562                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl);
 563         }
 564 }
 565
 566 /**
 567  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 568  *
 569  * @adev: amdgpu_device pointer
 570  *
 571  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 572  * Returns 0 for success, error for failure.
 573  */
 574 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 575 {
 576         struct amdgpu_ring *ring;
 577         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 578         u32 rb_bufsz;
 579         u32 wb_offset;
 580         u32 doorbell;
 581         u32 doorbell_offset;
 582         u32 temp;
 583         u64 wptr_gpu_addr;
 584         int i, r;
 585
 586         for (i = 0; i < adev->sdma.num_instances; i++) {
 587                 ring = &adev->sdma.instance[i].ring;
 588                 wb_offset = (ring->rptr_offs * 4);
 589
 590                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 591
 592                 /* Set ring buffer size in dwords */
 593                 rb_bufsz = order_base_2(ring->ring_size / 4);
 594                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 595                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 596 #ifdef __BIG_ENDIAN
 597                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 598                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 599                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 600 #endif
 601                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 602
 603                 /* Initialize the ring buffer's read and write pointers */
 604                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0);
 605                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 606                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0);
 607                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 608
 609                 /* set the wb address whether it's enabled or not */
 610                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 611                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 612                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 613                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 614
 615                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 616
 617                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 618                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 619
 620                 ring->wptr = 0;
 621
 622                 /* before programing wptr to a less value, need set minor_ptr_update first */
 623                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 624
 625                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 626                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 627                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 628                 }
 629
 630                 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL));
 631                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET));
 632
 633                 if (ring->use_doorbell) {
 634                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 635                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 636                                         OFFSET, ring->doorbell_index);
 637                 } else {
 638                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 639                 }
 640                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
 641                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 642                 if (adev->flags & AMD_IS_APU)
 643                         nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 644                 else
 645                         nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 646
 647                 if (amdgpu_sriov_vf(adev))
 648                         sdma_v4_0_ring_set_wptr(ring);
 649
 650                 /* set minor_ptr_update to 0 after wptr programed */
 651                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 652
 653                 /* set utc l1 enable flag always to 1 */
 654                 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 655                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 656                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
 657
 658                 if (!amdgpu_sriov_vf(adev)) {
 659                         /* unhalt engine */
 660                         temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 661                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 662                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
 663                 }
 664
 665                 /* setup the wptr shadow polling */
 666                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 667                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 668                        lower_32_bits(wptr_gpu_addr));
 669                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 670                        upper_32_bits(wptr_gpu_addr));
 671                 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 672                 if (amdgpu_sriov_vf(adev))
 673                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 674                 else
 675                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 676                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 677
 678                 /* enable DMA RB */
 679                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 680                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 681
 682                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 683                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 684 #ifdef __BIG_ENDIAN
 685                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 686 #endif
 687                 /* enable DMA IBs */
 688                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 689
 690                 ring->ready = true;
 691
 692                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 693                         sdma_v4_0_ctx_switch_enable(adev, true);
 694                         sdma_v4_0_enable(adev, true);
 695                 }
 696
 697                 r = amdgpu_ring_test_ring(ring);
 698                 if (r) {
 699                         ring->ready = false;
 700                         return r;
 701                 }
 702
 703                 if (adev->mman.buffer_funcs_ring == ring)
 704                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 705
 706         }
 707
 708         return 0;
 709 }
 710
 711 static void
 712 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 713 {
 714         uint32_t def, data;
 715
 716         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 717                 /* disable idle interrupt */
 718                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 719                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 720
 721                 if (data != def)
 722                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 723         } else {
 724                 /* disable idle interrupt */
 725                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 726                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 727                 if (data != def)
 728                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 729         }
 730 }
 731
 732 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 733 {
 734         uint32_t def, data;
 735
 736         /* Enable HW based PG. */
 737         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 738         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 739         if (data != def)
 740                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 741
 742         /* enable interrupt */
 743         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 744         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 745         if (data != def)
 746                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 747
 748         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 749         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 750         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 751         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 752         /* Configure switch time for hysteresis purpose. Use default right now */
 753         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 754         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 755         if(data != def)
 756                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 757 }
 758
 759 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 760 {
 761         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 762                 return;
 763
 764         switch (adev->asic_type) {
 765         case CHIP_RAVEN:
 766                 sdma_v4_1_init_power_gating(adev);
 767                 sdma_v4_1_update_power_gating(adev, true);
 768                 break;
 769         default:
 770                 break;
 771         }
 772 }
 773
 774 /**
 775  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 776  *
 777  * @adev: amdgpu_device pointer
 778  *
 779  * Set up the compute DMA queues and enable them (VEGA10).
 780  * Returns 0 for success, error for failure.
 781  */
 782 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 783 {
 784         sdma_v4_0_init_pg(adev);
 785
 786         return 0;
 787 }
 788
 789 /**
 790  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 791  *
 792  * @adev: amdgpu_device pointer
 793  *
 794  * Loads the sDMA0/1 ucode.
 795  * Returns 0 for success, -EINVAL if the ucode is not available.
 796  */
 797 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 798 {
 799         const struct sdma_firmware_header_v1_0 *hdr;
 800         const __le32 *fw_data;
 801         u32 fw_size;
 802         int i, j;
 803
 804         /* halt the MEs */
 805         sdma_v4_0_enable(adev, false);
 806
 807         for (i = 0; i < adev->sdma.num_instances; i++) {
 808                 if (!adev->sdma.instance[i].fw)
 809                         return -EINVAL;
 810
 811                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 812                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 813                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 814
 815                 fw_data = (const __le32 *)
 816                         (adev->sdma.instance[i].fw->data +
 817                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 818
 819                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0);
 820
 821                 for (j = 0; j < fw_size; j++)
 822                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 823
 824                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 825         }
 826
 827         return 0;
 828 }
 829
 830 /**
 831  * sdma_v4_0_start - setup and start the async dma engines
 832  *
 833  * @adev: amdgpu_device pointer
 834  *
 835  * Set up the DMA engines and enable them (VEGA10).
 836  * Returns 0 for success, error for failure.
 837  */
 838 static int sdma_v4_0_start(struct amdgpu_device *adev)
 839 {
 840         int r = 0;
 841
 842         if (amdgpu_sriov_vf(adev)) {
 843                 sdma_v4_0_ctx_switch_enable(adev, false);
 844                 sdma_v4_0_enable(adev, false);
 845
 846                 /* set RB registers */
 847                 r = sdma_v4_0_gfx_resume(adev);
 848                 return r;
 849         }
 850
 851         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 852                 r = sdma_v4_0_load_microcode(adev);
 853                 if (r)
 854                         return r;
 855         }
 856
 857         /* unhalt the MEs */
 858         sdma_v4_0_enable(adev, true);
 859         /* enable sdma ring preemption */
 860         sdma_v4_0_ctx_switch_enable(adev, true);
 861
 862         /* start the gfx rings and rlc compute queues */
 863         r = sdma_v4_0_gfx_resume(adev);
 864         if (r)
 865                 return r;
 866         r = sdma_v4_0_rlc_resume(adev);
 867
 868         return r;
 869 }
 870
 871 /**
 872  * sdma_v4_0_ring_test_ring - simple async dma engine test
 873  *
 874  * @ring: amdgpu_ring structure holding ring information
 875  *
 876  * Test the DMA engine by writing using it to write an
 877  * value to memory. (VEGA10).
 878  * Returns 0 for success, error for failure.
 879  */
 880 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 881 {
 882         struct amdgpu_device *adev = ring->adev;
 883         unsigned i;
 884         unsigned index;
 885         int r;
 886         u32 tmp;
 887         u64 gpu_addr;
 888
 889         r = amdgpu_wb_get(adev, &index);
 890         if (r) {
 891                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 892                 return r;
 893         }
 894
 895         gpu_addr = adev->wb.gpu_addr + (index * 4);
 896         tmp = 0xCAFEDEAD;
 897         adev->wb.wb[index] = cpu_to_le32(tmp);
 898
 899         r = amdgpu_ring_alloc(ring, 5);
 900         if (r) {
 901                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 902                 amdgpu_wb_free(adev, index);
 903                 return r;
 904         }
 905
 906         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 907                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 908         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 909         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 910         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 911         amdgpu_ring_write(ring, 0xDEADBEEF);
 912         amdgpu_ring_commit(ring);
 913
 914         for (i = 0; i < adev->usec_timeout; i++) {
 915                 tmp = le32_to_cpu(adev->wb.wb[index]);
 916                 if (tmp == 0xDEADBEEF)
 917                         break;
 918                 DRM_UDELAY(1);
 919         }
 920
 921         if (i < adev->usec_timeout) {
 922                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 923         } else {
 924                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 925                           ring->idx, tmp);
 926                 r = -EINVAL;
 927         }
 928         amdgpu_wb_free(adev, index);
 929
 930         return r;
 931 }
 932
 933 /**
 934  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 935  *
 936  * @ring: amdgpu_ring structure holding ring information
 937  *
 938  * Test a simple IB in the DMA ring (VEGA10).
 939  * Returns 0 on success, error on failure.
 940  */
 941 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 942 {
 943         struct amdgpu_device *adev = ring->adev;
 944         struct amdgpu_ib ib;
 945         struct dma_fence *f = NULL;
 946         unsigned index;
 947         long r;
 948         u32 tmp = 0;
 949         u64 gpu_addr;
 950
 951         r = amdgpu_wb_get(adev, &index);
 952         if (r) {
 953                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 954                 return r;
 955         }
 956
 957         gpu_addr = adev->wb.gpu_addr + (index * 4);
 958         tmp = 0xCAFEDEAD;
 959         adev->wb.wb[index] = cpu_to_le32(tmp);
 960         memset(&ib, 0, sizeof(ib));
 961         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 962         if (r) {
 963                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 964                 goto err0;
 965         }
 966
 967         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 968                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 969         ib.ptr[1] = lower_32_bits(gpu_addr);
 970         ib.ptr[2] = upper_32_bits(gpu_addr);
 971         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 972         ib.ptr[4] = 0xDEADBEEF;
 973         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 974         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 975         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 976         ib.length_dw = 8;
 977
 978         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 979         if (r)
 980                 goto err1;
 981
 982         r = dma_fence_wait_timeout(f, false, timeout);
 983         if (r == 0) {
 984                 DRM_ERROR("amdgpu: IB test timed out\n");
 985                 r = -ETIMEDOUT;
 986                 goto err1;
 987         } else if (r < 0) {
 988                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 989                 goto err1;
 990         }
 991         tmp = le32_to_cpu(adev->wb.wb[index]);
 992         if (tmp == 0xDEADBEEF) {
 993                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 994                 r = 0;
 995         } else {
 996                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 997                 r = -EINVAL;
 998         }
 999 err1:
1000         amdgpu_ib_free(adev, &ib, NULL);
1001         dma_fence_put(f);
1002 err0:
1003         amdgpu_wb_free(adev, index);
1004         return r;
1005 }
1006
1007
1008 /**
1009  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1010  *
1011  * @ib: indirect buffer to fill with commands
1012  * @pe: addr of the page entry
1013  * @src: src addr to copy from
1014  * @count: number of page entries to update
1015  *
1016  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1017  */
1018 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1019                                   uint64_t pe, uint64_t src,
1020                                   unsigned count)
1021 {
1022         unsigned bytes = count * 8;
1023
1024         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1025                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1026         ib->ptr[ib->length_dw++] = bytes - 1;
1027         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1028         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1029         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1030         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1031         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1032
1033 }
1034
1035 /**
1036  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1037  *
1038  * @ib: indirect buffer to fill with commands
1039  * @pe: addr of the page entry
1040  * @addr: dst addr to write into pe
1041  * @count: number of page entries to update
1042  * @incr: increase next addr by incr bytes
1043  * @flags: access flags
1044  *
1045  * Update PTEs by writing them manually using sDMA (VEGA10).
1046  */
1047 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1048                                    uint64_t value, unsigned count,
1049                                    uint32_t incr)
1050 {
1051         unsigned ndw = count * 2;
1052
1053         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1054                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1055         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1056         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1057         ib->ptr[ib->length_dw++] = ndw - 1;
1058         for (; ndw > 0; ndw -= 2) {
1059                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1060                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1061                 value += incr;
1062         }
1063 }
1064
1065 /**
1066  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1067  *
1068  * @ib: indirect buffer to fill with commands
1069  * @pe: addr of the page entry
1070  * @addr: dst addr to write into pe
1071  * @count: number of page entries to update
1072  * @incr: increase next addr by incr bytes
1073  * @flags: access flags
1074  *
1075  * Update the page tables using sDMA (VEGA10).
1076  */
1077 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1078                                      uint64_t pe,
1079                                      uint64_t addr, unsigned count,
1080                                      uint32_t incr, uint64_t flags)
1081 {
1082         /* for physically contiguous pages (vram) */
1083         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1084         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1085         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1086         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1087         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1088         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1089         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1090         ib->ptr[ib->length_dw++] = incr; /* increment size */
1091         ib->ptr[ib->length_dw++] = 0;
1092         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1093 }
1094
1095 /**
1096  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1097  *
1098  * @ib: indirect buffer to fill with padding
1099  *
1100  */
1101 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1102 {
1103         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1104         u32 pad_count;
1105         int i;
1106
1107         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1108         for (i = 0; i < pad_count; i++)
1109                 if (sdma && sdma->burst_nop && (i == 0))
1110                         ib->ptr[ib->length_dw++] =
1111                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1112                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1113                 else
1114                         ib->ptr[ib->length_dw++] =
1115                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1116 }
1117
1118
1119 /**
1120  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1121  *
1122  * @ring: amdgpu_ring pointer
1123  *
1124  * Make sure all previous operations are completed (CIK).
1125  */
1126 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1127 {
1128         uint32_t seq = ring->fence_drv.sync_seq;
1129         uint64_t addr = ring->fence_drv.gpu_addr;
1130
1131         /* wait for idle */
1132         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1133                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1134                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1135                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1136         amdgpu_ring_write(ring, addr & 0xfffffffc);
1137         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1138         amdgpu_ring_write(ring, seq); /* reference */
1139         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1140         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1141                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1142 }
1143
1144
1145 /**
1146  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1147  *
1148  * @ring: amdgpu_ring pointer
1149  * @vm: amdgpu_vm pointer
1150  *
1151  * Update the page table base and flush the VM TLB
1152  * using sDMA (VEGA10).
1153  */
1154 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1155                                          unsigned vm_id, uint64_t pd_addr)
1156 {
1157         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1158         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1159         unsigned eng = ring->vm_inv_eng;
1160
1161         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1162         pd_addr |= AMDGPU_PTE_VALID;
1163
1164         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1165                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1166         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
1167         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1168
1169         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1170                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1171         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
1172         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1173
1174         /* flush TLB */
1175         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1176                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1177         amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
1178         amdgpu_ring_write(ring, req);
1179
1180         /* wait for flush */
1181         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1182                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1183                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1184         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1185         amdgpu_ring_write(ring, 0);
1186         amdgpu_ring_write(ring, 1 << vm_id); /* reference */
1187         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
1188         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1189                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1190 }
1191
1192 static int sdma_v4_0_early_init(void *handle)
1193 {
1194         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1195
1196         if (adev->asic_type == CHIP_RAVEN)
1197                 adev->sdma.num_instances = 1;
1198         else
1199                 adev->sdma.num_instances = 2;
1200
1201         sdma_v4_0_set_ring_funcs(adev);
1202         sdma_v4_0_set_buffer_funcs(adev);
1203         sdma_v4_0_set_vm_pte_funcs(adev);
1204         sdma_v4_0_set_irq_funcs(adev);
1205
1206         return 0;
1207 }
1208
1209
1210 static int sdma_v4_0_sw_init(void *handle)
1211 {
1212         struct amdgpu_ring *ring;
1213         int r, i;
1214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1215
1216         /* SDMA trap event */
1217         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
1218                               &adev->sdma.trap_irq);
1219         if (r)
1220                 return r;
1221
1222         /* SDMA trap event */
1223         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
1224                               &adev->sdma.trap_irq);
1225         if (r)
1226                 return r;
1227
1228         r = sdma_v4_0_init_microcode(adev);
1229         if (r) {
1230                 DRM_ERROR("Failed to load sdma firmware!\n");
1231                 return r;
1232         }
1233
1234         for (i = 0; i < adev->sdma.num_instances; i++) {
1235                 ring = &adev->sdma.instance[i].ring;
1236                 ring->ring_obj = NULL;
1237                 ring->use_doorbell = true;
1238
1239                 DRM_INFO("use_doorbell being set to: [%s]\n",
1240                                 ring->use_doorbell?"true":"false");
1241
1242                 ring->doorbell_index = (i == 0) ?
1243                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1244                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1245
1246                 sprintf(ring->name, "sdma%d", i);
1247                 r = amdgpu_ring_init(adev, ring, 1024,
1248                                      &adev->sdma.trap_irq,
1249                                      (i == 0) ?
1250                                      AMDGPU_SDMA_IRQ_TRAP0 :
1251                                      AMDGPU_SDMA_IRQ_TRAP1);
1252                 if (r)
1253                         return r;
1254         }
1255
1256         return r;
1257 }
1258
1259 static int sdma_v4_0_sw_fini(void *handle)
1260 {
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262         int i;
1263
1264         for (i = 0; i < adev->sdma.num_instances; i++)
1265                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1266
1267         for (i = 0; i < adev->sdma.num_instances; i++) {
1268                 release_firmware(adev->sdma.instance[i].fw);
1269                 adev->sdma.instance[i].fw = NULL;
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int sdma_v4_0_hw_init(void *handle)
1276 {
1277         int r;
1278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280         sdma_v4_0_init_golden_registers(adev);
1281
1282         r = sdma_v4_0_start(adev);
1283
1284         return r;
1285 }
1286
1287 static int sdma_v4_0_hw_fini(void *handle)
1288 {
1289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290
1291         if (amdgpu_sriov_vf(adev))
1292                 return 0;
1293
1294         sdma_v4_0_ctx_switch_enable(adev, false);
1295         sdma_v4_0_enable(adev, false);
1296
1297         return 0;
1298 }
1299
1300 static int sdma_v4_0_suspend(void *handle)
1301 {
1302         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303
1304         return sdma_v4_0_hw_fini(adev);
1305 }
1306
1307 static int sdma_v4_0_resume(void *handle)
1308 {
1309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310
1311         return sdma_v4_0_hw_init(adev);
1312 }
1313
1314 static bool sdma_v4_0_is_idle(void *handle)
1315 {
1316         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317         u32 i;
1318
1319         for (i = 0; i < adev->sdma.num_instances; i++) {
1320                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));
1321
1322                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1323                         return false;
1324         }
1325
1326         return true;
1327 }
1328
1329 static int sdma_v4_0_wait_for_idle(void *handle)
1330 {
1331         unsigned i;
1332         u32 sdma0, sdma1;
1333         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334
1335         for (i = 0; i < adev->usec_timeout; i++) {
1336                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));
1337                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
1338
1339                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1340                         return 0;
1341                 udelay(1);
1342         }
1343         return -ETIMEDOUT;
1344 }
1345
1346 static int sdma_v4_0_soft_reset(void *handle)
1347 {
1348         /* todo */
1349
1350         return 0;
1351 }
1352
1353 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1354                                         struct amdgpu_irq_src *source,
1355                                         unsigned type,
1356                                         enum amdgpu_interrupt_state state)
1357 {
1358         u32 sdma_cntl;
1359
1360         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1361                 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) :
1362                 sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL);
1363
1364         sdma_cntl = RREG32(reg_offset);
1365         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1366                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1367         WREG32(reg_offset, sdma_cntl);
1368
1369         return 0;
1370 }
1371
1372 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1373                                       struct amdgpu_irq_src *source,
1374                                       struct amdgpu_iv_entry *entry)
1375 {
1376         DRM_DEBUG("IH: SDMA trap\n");
1377         switch (entry->client_id) {
1378         case AMDGPU_IH_CLIENTID_SDMA0:
1379                 switch (entry->ring_id) {
1380                 case 0:
1381                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1382                         break;
1383                 case 1:
1384                         /* XXX compute */
1385                         break;
1386                 case 2:
1387                         /* XXX compute */
1388                         break;
1389                 case 3:
1390                         /* XXX page queue*/
1391                         break;
1392                 }
1393                 break;
1394         case AMDGPU_IH_CLIENTID_SDMA1:
1395                 switch (entry->ring_id) {
1396                 case 0:
1397                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1398                         break;
1399                 case 1:
1400                         /* XXX compute */
1401                         break;
1402                 case 2:
1403                         /* XXX compute */
1404                         break;
1405                 case 3:
1406                         /* XXX page queue*/
1407                         break;
1408                 }
1409                 break;
1410         }
1411         return 0;
1412 }
1413
1414 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1415                                               struct amdgpu_irq_src *source,
1416                                               struct amdgpu_iv_entry *entry)
1417 {
1418         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1419         schedule_work(&adev->reset_work);
1420         return 0;
1421 }
1422
1423
1424 static void sdma_v4_0_update_medium_grain_clock_gating(
1425                 struct amdgpu_device *adev,
1426                 bool enable)
1427 {
1428         uint32_t data, def;
1429
1430         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1431                 /* enable sdma0 clock gating */
1432                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1433                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1434                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1435                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1436                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1437                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1438                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1439                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1440                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1441                 if (def != data)
1442                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1443
1444                 if (adev->asic_type == CHIP_VEGA10) {
1445                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1446                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1447                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1448                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1449                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1450                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1451                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1452                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1453                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1454                         if (def != data)
1455                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1456                 }
1457         } else {
1458                 /* disable sdma0 clock gating */
1459                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1460                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1461                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1462                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1463                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1464                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1465                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1466                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1467                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1468
1469                 if (def != data)
1470                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1471
1472                 if (adev->asic_type == CHIP_VEGA10) {
1473                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1474                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1475                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1476                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1477                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1478                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1479                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1480                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1481                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1482                         if (def != data)
1483                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1484                 }
1485         }
1486 }
1487
1488
1489 static void sdma_v4_0_update_medium_grain_light_sleep(
1490                 struct amdgpu_device *adev,
1491                 bool enable)
1492 {
1493         uint32_t data, def;
1494
1495         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1496                 /* 1-not override: enable sdma0 mem light sleep */
1497                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1498                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1499                 if (def != data)
1500                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1501
1502                 /* 1-not override: enable sdma1 mem light sleep */
1503                 if (adev->asic_type == CHIP_VEGA10) {
1504                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1505                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1506                         if (def != data)
1507                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1508                 }
1509         } else {
1510                 /* 0-override:disable sdma0 mem light sleep */
1511                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1512                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1513                 if (def != data)
1514                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1515
1516                 /* 0-override:disable sdma1 mem light sleep */
1517                 if (adev->asic_type == CHIP_VEGA10) {
1518                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1519                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1520                         if (def != data)
1521                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1522                 }
1523         }
1524 }
1525
1526 static int sdma_v4_0_set_clockgating_state(void *handle,
1527                                           enum amd_clockgating_state state)
1528 {
1529         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1530
1531         if (amdgpu_sriov_vf(adev))
1532                 return 0;
1533
1534         switch (adev->asic_type) {
1535         case CHIP_VEGA10:
1536         case CHIP_RAVEN:
1537                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1538                                 state == AMD_CG_STATE_GATE ? true : false);
1539                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1540                                 state == AMD_CG_STATE_GATE ? true : false);
1541                 break;
1542         default:
1543                 break;
1544         }
1545         return 0;
1546 }
1547
1548 static int sdma_v4_0_set_powergating_state(void *handle,
1549                                           enum amd_powergating_state state)
1550 {
1551         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1552
1553         switch (adev->asic_type) {
1554         case CHIP_RAVEN:
1555                 sdma_v4_1_update_power_gating(adev,
1556                                 state == AMD_PG_STATE_GATE ? true : false);
1557                 break;
1558         default:
1559                 break;
1560         }
1561
1562         return 0;
1563 }
1564
1565 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1566 {
1567         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1568         int data;
1569
1570         if (amdgpu_sriov_vf(adev))
1571                 *flags = 0;
1572
1573         /* AMD_CG_SUPPORT_SDMA_MGCG */
1574         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1575         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1576                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1577
1578         /* AMD_CG_SUPPORT_SDMA_LS */
1579         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1580         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1581                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1582 }
1583
1584 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1585         .name = "sdma_v4_0",
1586         .early_init = sdma_v4_0_early_init,
1587         .late_init = NULL,
1588         .sw_init = sdma_v4_0_sw_init,
1589         .sw_fini = sdma_v4_0_sw_fini,
1590         .hw_init = sdma_v4_0_hw_init,
1591         .hw_fini = sdma_v4_0_hw_fini,
1592         .suspend = sdma_v4_0_suspend,
1593         .resume = sdma_v4_0_resume,
1594         .is_idle = sdma_v4_0_is_idle,
1595         .wait_for_idle = sdma_v4_0_wait_for_idle,
1596         .soft_reset = sdma_v4_0_soft_reset,
1597         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1598         .set_powergating_state = sdma_v4_0_set_powergating_state,
1599         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1600 };
1601
1602 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1603         .type = AMDGPU_RING_TYPE_SDMA,
1604         .align_mask = 0xf,
1605         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1606         .support_64bit_ptrs = true,
1607         .vmhub = AMDGPU_MMHUB,
1608         .get_rptr = sdma_v4_0_ring_get_rptr,
1609         .get_wptr = sdma_v4_0_ring_get_wptr,
1610         .set_wptr = sdma_v4_0_ring_set_wptr,
1611         .emit_frame_size =
1612                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1613                 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
1614                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1615                 18 + /* sdma_v4_0_ring_emit_vm_flush */
1616                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1617         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1618         .emit_ib = sdma_v4_0_ring_emit_ib,
1619         .emit_fence = sdma_v4_0_ring_emit_fence,
1620         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1621         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1622         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1623         .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
1624         .test_ring = sdma_v4_0_ring_test_ring,
1625         .test_ib = sdma_v4_0_ring_test_ib,
1626         .insert_nop = sdma_v4_0_ring_insert_nop,
1627         .pad_ib = sdma_v4_0_ring_pad_ib,
1628 };
1629
1630 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1631 {
1632         int i;
1633
1634         for (i = 0; i < adev->sdma.num_instances; i++)
1635                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1636 }
1637
1638 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1639         .set = sdma_v4_0_set_trap_irq_state,
1640         .process = sdma_v4_0_process_trap_irq,
1641 };
1642
1643 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1644         .process = sdma_v4_0_process_illegal_inst_irq,
1645 };
1646
1647 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1648 {
1649         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1650         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1651         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1652 }
1653
1654 /**
1655  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1656  *
1657  * @ring: amdgpu_ring structure holding ring information
1658  * @src_offset: src GPU address
1659  * @dst_offset: dst GPU address
1660  * @byte_count: number of bytes to xfer
1661  *
1662  * Copy GPU buffers using the DMA engine (VEGA10).
1663  * Used by the amdgpu ttm implementation to move pages if
1664  * registered as the asic copy callback.
1665  */
1666 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1667                                        uint64_t src_offset,
1668                                        uint64_t dst_offset,
1669                                        uint32_t byte_count)
1670 {
1671         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1672                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1673         ib->ptr[ib->length_dw++] = byte_count - 1;
1674         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1675         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1676         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1677         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1678         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1679 }
1680
1681 /**
1682  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1683  *
1684  * @ring: amdgpu_ring structure holding ring information
1685  * @src_data: value to write to buffer
1686  * @dst_offset: dst GPU address
1687  * @byte_count: number of bytes to xfer
1688  *
1689  * Fill GPU buffers using the DMA engine (VEGA10).
1690  */
1691 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1692                                        uint32_t src_data,
1693                                        uint64_t dst_offset,
1694                                        uint32_t byte_count)
1695 {
1696         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1697         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1698         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1699         ib->ptr[ib->length_dw++] = src_data;
1700         ib->ptr[ib->length_dw++] = byte_count - 1;
1701 }
1702
1703 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1704         .copy_max_bytes = 0x400000,
1705         .copy_num_dw = 7,
1706         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1707
1708         .fill_max_bytes = 0x400000,
1709         .fill_num_dw = 5,
1710         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1711 };
1712
1713 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1714 {
1715         if (adev->mman.buffer_funcs == NULL) {
1716                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1717                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1718         }
1719 }
1720
1721 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1722         .copy_pte_num_dw = 7,
1723         .copy_pte = sdma_v4_0_vm_copy_pte,
1724
1725         .write_pte = sdma_v4_0_vm_write_pte,
1726
1727         .set_max_nums_pte_pde = 0x400000 >> 3,
1728         .set_pte_pde_num_dw = 10,
1729         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1730 };
1731
1732 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1733 {
1734         unsigned i;
1735
1736         if (adev->vm_manager.vm_pte_funcs == NULL) {
1737                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1738                 for (i = 0; i < adev->sdma.num_instances; i++)
1739                         adev->vm_manager.vm_pte_rings[i] =
1740                                 &adev->sdma.instance[i].ring;
1741
1742                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1743         }
1744 }
1745
1746 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1747         .type = AMD_IP_BLOCK_TYPE_SDMA,
1748         .major = 4,
1749         .minor = 0,
1750         .rev = 0,
1751         .funcs = &sdma_v4_0_ip_funcs,
1752 };