drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  54 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  56 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  57 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  58 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  59 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  65
  66
  67 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  68 {
  69         SDMA0_REGISTER_OFFSET,
  70         SDMA1_REGISTER_OFFSET
  71 };
  72
  73 static const u32 golden_settings_tonga_a11[] =
  74 {
  75         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  76         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  77         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  78         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  79         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  80         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  81         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  82         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  83         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  84         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  85 };
  86
  87 static const u32 tonga_mgcg_cgcg_init[] =
  88 {
  89         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  90         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  91 };
  92
  93 static const u32 golden_settings_fiji_a10[] =
  94 {
  95         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  96         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  97         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  98         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  99         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 100         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 101         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 102         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 103 };
 104
 105 static const u32 fiji_mgcg_cgcg_init[] =
 106 {
 107         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 108         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 109 };
 110
 111 static const u32 golden_settings_polaris11_a11[] =
 112 {
 113         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 114         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 115         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 116         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 117         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 118         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 119         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 120         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 121         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 122         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 123 };
 124
 125 static const u32 golden_settings_polaris10_a11[] =
 126 {
 127         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 128         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 129         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 130         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 131         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 132         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 133         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 134         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 135         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 136         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 137 };
 138
 139 static const u32 cz_golden_settings_a11[] =
 140 {
 141         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 142         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 143         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 144         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 145         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 146         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 147         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 148         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 149         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 150         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 151         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 152         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 153 };
 154
 155 static const u32 cz_mgcg_cgcg_init[] =
 156 {
 157         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 158         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 159 };
 160
 161 static const u32 stoney_golden_settings_a11[] =
 162 {
 163         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 164         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 165         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 166         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 167 };
 168
 169 static const u32 stoney_mgcg_cgcg_init[] =
 170 {
 171         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 172 };
 173
 174 /*
 175  * sDMA - System DMA
 176  * Starting with CIK, the GPU has new asynchronous
 177  * DMA engines.  These engines are used for compute
 178  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 179  * and each one supports 1 ring buffer used for gfx
 180  * and 2 queues used for compute.
 181  *
 182  * The programming model is very similar to the CP
 183  * (ring buffer, IBs, etc.), but sDMA has it's own
 184  * packet format that is different from the PM4 format
 185  * used by the CP. sDMA supports copying data, writing
 186  * embedded data, solid fills, and a number of other
 187  * things.  It also has support for tiling/detiling of
 188  * buffers.
 189  */
 190
 191 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 192 {
 193         switch (adev->asic_type) {
 194         case CHIP_FIJI:
 195                 amdgpu_program_register_sequence(adev,
 196                                                  fiji_mgcg_cgcg_init,
 197                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 198                 amdgpu_program_register_sequence(adev,
 199                                                  golden_settings_fiji_a10,
 200                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 201                 break;
 202         case CHIP_TONGA:
 203                 amdgpu_program_register_sequence(adev,
 204                                                  tonga_mgcg_cgcg_init,
 205                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 206                 amdgpu_program_register_sequence(adev,
 207                                                  golden_settings_tonga_a11,
 208                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 209                 break;
 210         case CHIP_POLARIS11:
 211         case CHIP_POLARIS12:
 212                 amdgpu_program_register_sequence(adev,
 213                                                  golden_settings_polaris11_a11,
 214                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 215                 break;
 216         case CHIP_POLARIS10:
 217                 amdgpu_program_register_sequence(adev,
 218                                                  golden_settings_polaris10_a11,
 219                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 220                 break;
 221         case CHIP_CARRIZO:
 222                 amdgpu_program_register_sequence(adev,
 223                                                  cz_mgcg_cgcg_init,
 224                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 225                 amdgpu_program_register_sequence(adev,
 226                                                  cz_golden_settings_a11,
 227                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 228                 break;
 229         case CHIP_STONEY:
 230                 amdgpu_program_register_sequence(adev,
 231                                                  stoney_mgcg_cgcg_init,
 232                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 233                 amdgpu_program_register_sequence(adev,
 234                                                  stoney_golden_settings_a11,
 235                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 236                 break;
 237         default:
 238                 break;
 239         }
 240 }
 241
 242 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 243 {
 244         int i;
 245         for (i = 0; i < adev->sdma.num_instances; i++) {
 246                 release_firmware(adev->sdma.instance[i].fw);
 247                 adev->sdma.instance[i].fw = NULL;
 248         }
 249 }
 250
 251 /**
 252  * sdma_v3_0_init_microcode - load ucode images from disk
 253  *
 254  * @adev: amdgpu_device pointer
 255  *
 256  * Use the firmware interface to load the ucode images into
 257  * the driver (not loaded into hw).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 261 {
 262         const char *chip_name;
 263         char fw_name[30];
 264         int err = 0, i;
 265         struct amdgpu_firmware_info *info = NULL;
 266         const struct common_firmware_header *header = NULL;
 267         const struct sdma_firmware_header_v1_0 *hdr;
 268
 269         DRM_DEBUG("\n");
 270
 271         switch (adev->asic_type) {
 272         case CHIP_TONGA:
 273                 chip_name = "tonga";
 274                 break;
 275         case CHIP_FIJI:
 276                 chip_name = "fiji";
 277                 break;
 278         case CHIP_POLARIS11:
 279                 chip_name = "polaris11";
 280                 break;
 281         case CHIP_POLARIS10:
 282                 chip_name = "polaris10";
 283                 break;
 284         case CHIP_POLARIS12:
 285                 chip_name = "polaris12";
 286                 break;
 287         case CHIP_CARRIZO:
 288                 chip_name = "carrizo";
 289                 break;
 290         case CHIP_STONEY:
 291                 chip_name = "stoney";
 292                 break;
 293         default: BUG();
 294         }
 295
 296         for (i = 0; i < adev->sdma.num_instances; i++) {
 297                 if (i == 0)
 298                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 299                 else
 300                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 301                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 302                 if (err)
 303                         goto out;
 304                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 305                 if (err)
 306                         goto out;
 307                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 308                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 309                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 310                 if (adev->sdma.instance[i].feature_version >= 20)
 311                         adev->sdma.instance[i].burst_nop = true;
 312
 313                 if (adev->firmware.smu_load) {
 314                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 315                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 316                         info->fw = adev->sdma.instance[i].fw;
 317                         header = (const struct common_firmware_header *)info->fw->data;
 318                         adev->firmware.fw_size +=
 319                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 320                 }
 321         }
 322 out:
 323         if (err) {
 324                 printk(KERN_ERR
 325                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 326                        fw_name);
 327                 for (i = 0; i < adev->sdma.num_instances; i++) {
 328                         release_firmware(adev->sdma.instance[i].fw);
 329                         adev->sdma.instance[i].fw = NULL;
 330                 }
 331         }
 332         return err;
 333 }
 334
 335 /**
 336  * sdma_v3_0_ring_get_rptr - get the current read pointer
 337  *
 338  * @ring: amdgpu ring pointer
 339  *
 340  * Get the current rptr from the hardware (VI+).
 341  */
 342 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 343 {
 344         /* XXX check if swapping is necessary on BE */
 345         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 346 }
 347
 348 /**
 349  * sdma_v3_0_ring_get_wptr - get the current write pointer
 350  *
 351  * @ring: amdgpu ring pointer
 352  *
 353  * Get the current wptr from the hardware (VI+).
 354  */
 355 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 356 {
 357         struct amdgpu_device *adev = ring->adev;
 358         u32 wptr;
 359
 360         if (ring->use_doorbell) {
 361                 /* XXX check if swapping is necessary on BE */
 362                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 363         } else {
 364                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 365
 366                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 367         }
 368
 369         return wptr;
 370 }
 371
 372 /**
 373  * sdma_v3_0_ring_set_wptr - commit the write pointer
 374  *
 375  * @ring: amdgpu ring pointer
 376  *
 377  * Write the wptr back to the hardware (VI+).
 378  */
 379 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 380 {
 381         struct amdgpu_device *adev = ring->adev;
 382
 383         if (ring->use_doorbell) {
 384                 /* XXX check if swapping is necessary on BE */
 385                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 386                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 387         } else {
 388                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 389
 390                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 391         }
 392 }
 393
 394 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 395 {
 396         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 397         int i;
 398
 399         for (i = 0; i < count; i++)
 400                 if (sdma && sdma->burst_nop && (i == 0))
 401                         amdgpu_ring_write(ring, ring->funcs->nop |
 402                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 403                 else
 404                         amdgpu_ring_write(ring, ring->funcs->nop);
 405 }
 406
 407 /**
 408  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 409  *
 410  * @ring: amdgpu ring pointer
 411  * @ib: IB object to schedule
 412  *
 413  * Schedule an IB in the DMA ring (VI).
 414  */
 415 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 416                                    struct amdgpu_ib *ib,
 417                                    unsigned vm_id, bool ctx_switch)
 418 {
 419         u32 vmid = vm_id & 0xf;
 420
 421         /* IB packet must end on a 8 DW boundary */
 422         sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 423
 424         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 425                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 426         /* base must be 32 byte aligned */
 427         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 428         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 429         amdgpu_ring_write(ring, ib->length_dw);
 430         amdgpu_ring_write(ring, 0);
 431         amdgpu_ring_write(ring, 0);
 432
 433 }
 434
 435 /**
 436  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 437  *
 438  * @ring: amdgpu ring pointer
 439  *
 440  * Emit an hdp flush packet on the requested DMA ring.
 441  */
 442 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 443 {
 444         u32 ref_and_mask = 0;
 445
 446         if (ring == &ring->adev->sdma.instance[0].ring)
 447                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 448         else
 449                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 450
 451         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 452                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 453                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 454         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 455         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 456         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 457         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 458         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 459                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 460 }
 461
 462 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 463 {
 464         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 465                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 466         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 467         amdgpu_ring_write(ring, 1);
 468 }
 469
 470 /**
 471  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 472  *
 473  * @ring: amdgpu ring pointer
 474  * @fence: amdgpu fence object
 475  *
 476  * Add a DMA fence packet to the ring to write
 477  * the fence seq number and DMA trap packet to generate
 478  * an interrupt if needed (VI).
 479  */
 480 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 481                                       unsigned flags)
 482 {
 483         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 484         /* write the fence */
 485         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 486         amdgpu_ring_write(ring, lower_32_bits(addr));
 487         amdgpu_ring_write(ring, upper_32_bits(addr));
 488         amdgpu_ring_write(ring, lower_32_bits(seq));
 489
 490         /* optionally write high bits as well */
 491         if (write64bit) {
 492                 addr += 4;
 493                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 494                 amdgpu_ring_write(ring, lower_32_bits(addr));
 495                 amdgpu_ring_write(ring, upper_32_bits(addr));
 496                 amdgpu_ring_write(ring, upper_32_bits(seq));
 497         }
 498
 499         /* generate an interrupt */
 500         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 501         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 502 }
 503
 504 /**
 505  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 506  *
 507  * @adev: amdgpu_device pointer
 508  *
 509  * Stop the gfx async dma ring buffers (VI).
 510  */
 511 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 512 {
 513         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 514         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 515         u32 rb_cntl, ib_cntl;
 516         int i;
 517
 518         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 519             (adev->mman.buffer_funcs_ring == sdma1))
 520                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 521
 522         for (i = 0; i < adev->sdma.num_instances; i++) {
 523                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 524                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 525                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 526                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 527                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 528                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 529         }
 530         sdma0->ready = false;
 531         sdma1->ready = false;
 532 }
 533
 534 /**
 535  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 536  *
 537  * @adev: amdgpu_device pointer
 538  *
 539  * Stop the compute async dma queues (VI).
 540  */
 541 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 542 {
 543         /* XXX todo */
 544 }
 545
 546 /**
 547  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 548  *
 549  * @adev: amdgpu_device pointer
 550  * @enable: enable/disable the DMA MEs context switch.
 551  *
 552  * Halt or unhalt the async dma engines context switch (VI).
 553  */
 554 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 555 {
 556         u32 f32_cntl;
 557         int i;
 558
 559         for (i = 0; i < adev->sdma.num_instances; i++) {
 560                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 561                 if (enable)
 562                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 563                                         AUTO_CTXSW_ENABLE, 1);
 564                 else
 565                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 566                                         AUTO_CTXSW_ENABLE, 0);
 567                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 568         }
 569 }
 570
 571 /**
 572  * sdma_v3_0_enable - stop the async dma engines
 573  *
 574  * @adev: amdgpu_device pointer
 575  * @enable: enable/disable the DMA MEs.
 576  *
 577  * Halt or unhalt the async dma engines (VI).
 578  */
 579 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 580 {
 581         u32 f32_cntl;
 582         int i;
 583
 584         if (!enable) {
 585                 sdma_v3_0_gfx_stop(adev);
 586                 sdma_v3_0_rlc_stop(adev);
 587         }
 588
 589         for (i = 0; i < adev->sdma.num_instances; i++) {
 590                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 591                 if (enable)
 592                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 593                 else
 594                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 595                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 596         }
 597 }
 598
 599 /**
 600  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 601  *
 602  * @adev: amdgpu_device pointer
 603  *
 604  * Set up the gfx DMA ring buffers and enable them (VI).
 605  * Returns 0 for success, error for failure.
 606  */
 607 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 608 {
 609         struct amdgpu_ring *ring;
 610         u32 rb_cntl, ib_cntl;
 611         u32 rb_bufsz;
 612         u32 wb_offset;
 613         u32 doorbell;
 614         int i, j, r;
 615
 616         for (i = 0; i < adev->sdma.num_instances; i++) {
 617                 ring = &adev->sdma.instance[i].ring;
 618                 wb_offset = (ring->rptr_offs * 4);
 619
 620                 mutex_lock(&adev->srbm_mutex);
 621                 for (j = 0; j < 16; j++) {
 622                         vi_srbm_select(adev, 0, 0, 0, j);
 623                         /* SDMA GFX */
 624                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 625                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 626                 }
 627                 vi_srbm_select(adev, 0, 0, 0, 0);
 628                 mutex_unlock(&adev->srbm_mutex);
 629
 630                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 631                        adev->gfx.config.gb_addr_config & 0x70);
 632
 633                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 634
 635                 /* Set ring buffer size in dwords */
 636                 rb_bufsz = order_base_2(ring->ring_size / 4);
 637                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 638                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 639 #ifdef __BIG_ENDIAN
 640                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 641                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 642                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 643 #endif
 644                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 645
 646                 /* Initialize the ring buffer's read and write pointers */
 647                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 648                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 649                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 650                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 651
 652                 /* set the wb address whether it's enabled or not */
 653                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 654                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 655                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 656                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 657
 658                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 659
 660                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 661                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 662
 663                 ring->wptr = 0;
 664                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 665
 666                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 667
 668                 if (ring->use_doorbell) {
 669                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 670                                                  OFFSET, ring->doorbell_index);
 671                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 672                 } else {
 673                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 674                 }
 675                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 676
 677                 /* enable DMA RB */
 678                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 679                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 680
 681                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 682                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 683 #ifdef __BIG_ENDIAN
 684                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 685 #endif
 686                 /* enable DMA IBs */
 687                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 688
 689                 ring->ready = true;
 690         }
 691
 692         /* unhalt the MEs */
 693         sdma_v3_0_enable(adev, true);
 694         /* enable sdma ring preemption */
 695         sdma_v3_0_ctx_switch_enable(adev, true);
 696
 697         for (i = 0; i < adev->sdma.num_instances; i++) {
 698                 ring = &adev->sdma.instance[i].ring;
 699                 r = amdgpu_ring_test_ring(ring);
 700                 if (r) {
 701                         ring->ready = false;
 702                         return r;
 703                 }
 704
 705                 if (adev->mman.buffer_funcs_ring == ring)
 706                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 707         }
 708
 709         return 0;
 710 }
 711
 712 /**
 713  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 714  *
 715  * @adev: amdgpu_device pointer
 716  *
 717  * Set up the compute DMA queues and enable them (VI).
 718  * Returns 0 for success, error for failure.
 719  */
 720 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 721 {
 722         /* XXX todo */
 723         return 0;
 724 }
 725
 726 /**
 727  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 728  *
 729  * @adev: amdgpu_device pointer
 730  *
 731  * Loads the sDMA0/1 ucode.
 732  * Returns 0 for success, -EINVAL if the ucode is not available.
 733  */
 734 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 735 {
 736         const struct sdma_firmware_header_v1_0 *hdr;
 737         const __le32 *fw_data;
 738         u32 fw_size;
 739         int i, j;
 740
 741         /* halt the MEs */
 742         sdma_v3_0_enable(adev, false);
 743
 744         for (i = 0; i < adev->sdma.num_instances; i++) {
 745                 if (!adev->sdma.instance[i].fw)
 746                         return -EINVAL;
 747                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 748                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 749                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 750                 fw_data = (const __le32 *)
 751                         (adev->sdma.instance[i].fw->data +
 752                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 753                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 754                 for (j = 0; j < fw_size; j++)
 755                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 756                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 757         }
 758
 759         return 0;
 760 }
 761
 762 /**
 763  * sdma_v3_0_start - setup and start the async dma engines
 764  *
 765  * @adev: amdgpu_device pointer
 766  *
 767  * Set up the DMA engines and enable them (VI).
 768  * Returns 0 for success, error for failure.
 769  */
 770 static int sdma_v3_0_start(struct amdgpu_device *adev)
 771 {
 772         int r, i;
 773
 774         if (!adev->pp_enabled) {
 775                 if (!adev->firmware.smu_load) {
 776                         r = sdma_v3_0_load_microcode(adev);
 777                         if (r)
 778                                 return r;
 779                 } else {
 780                         for (i = 0; i < adev->sdma.num_instances; i++) {
 781                                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 782                                                                                  (i == 0) ?
 783                                                                                  AMDGPU_UCODE_ID_SDMA0 :
 784                                                                                  AMDGPU_UCODE_ID_SDMA1);
 785                                 if (r)
 786                                         return -EINVAL;
 787                         }
 788                 }
 789         }
 790
 791         /* disble sdma engine before programing it */
 792         sdma_v3_0_ctx_switch_enable(adev, false);
 793         sdma_v3_0_enable(adev, false);
 794
 795         /* start the gfx rings and rlc compute queues */
 796         r = sdma_v3_0_gfx_resume(adev);
 797         if (r)
 798                 return r;
 799         r = sdma_v3_0_rlc_resume(adev);
 800         if (r)
 801                 return r;
 802
 803         return 0;
 804 }
 805
 806 /**
 807  * sdma_v3_0_ring_test_ring - simple async dma engine test
 808  *
 809  * @ring: amdgpu_ring structure holding ring information
 810  *
 811  * Test the DMA engine by writing using it to write an
 812  * value to memory. (VI).
 813  * Returns 0 for success, error for failure.
 814  */
 815 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 816 {
 817         struct amdgpu_device *adev = ring->adev;
 818         unsigned i;
 819         unsigned index;
 820         int r;
 821         u32 tmp;
 822         u64 gpu_addr;
 823
 824         r = amdgpu_wb_get(adev, &index);
 825         if (r) {
 826                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 827                 return r;
 828         }
 829
 830         gpu_addr = adev->wb.gpu_addr + (index * 4);
 831         tmp = 0xCAFEDEAD;
 832         adev->wb.wb[index] = cpu_to_le32(tmp);
 833
 834         r = amdgpu_ring_alloc(ring, 5);
 835         if (r) {
 836                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 837                 amdgpu_wb_free(adev, index);
 838                 return r;
 839         }
 840
 841         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 842                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 843         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 844         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 845         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 846         amdgpu_ring_write(ring, 0xDEADBEEF);
 847         amdgpu_ring_commit(ring);
 848
 849         for (i = 0; i < adev->usec_timeout; i++) {
 850                 tmp = le32_to_cpu(adev->wb.wb[index]);
 851                 if (tmp == 0xDEADBEEF)
 852                         break;
 853                 DRM_UDELAY(1);
 854         }
 855
 856         if (i < adev->usec_timeout) {
 857                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 858         } else {
 859                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 860                           ring->idx, tmp);
 861                 r = -EINVAL;
 862         }
 863         amdgpu_wb_free(adev, index);
 864
 865         return r;
 866 }
 867
 868 /**
 869  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 870  *
 871  * @ring: amdgpu_ring structure holding ring information
 872  *
 873  * Test a simple IB in the DMA ring (VI).
 874  * Returns 0 on success, error on failure.
 875  */
 876 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 877 {
 878         struct amdgpu_device *adev = ring->adev;
 879         struct amdgpu_ib ib;
 880         struct dma_fence *f = NULL;
 881         unsigned index;
 882         u32 tmp = 0;
 883         u64 gpu_addr;
 884         long r;
 885
 886         r = amdgpu_wb_get(adev, &index);
 887         if (r) {
 888                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 889                 return r;
 890         }
 891
 892         gpu_addr = adev->wb.gpu_addr + (index * 4);
 893         tmp = 0xCAFEDEAD;
 894         adev->wb.wb[index] = cpu_to_le32(tmp);
 895         memset(&ib, 0, sizeof(ib));
 896         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 897         if (r) {
 898                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 899                 goto err0;
 900         }
 901
 902         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 903                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 904         ib.ptr[1] = lower_32_bits(gpu_addr);
 905         ib.ptr[2] = upper_32_bits(gpu_addr);
 906         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 907         ib.ptr[4] = 0xDEADBEEF;
 908         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 909         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 910         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 911         ib.length_dw = 8;
 912
 913         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 914         if (r)
 915                 goto err1;
 916
 917         r = dma_fence_wait_timeout(f, false, timeout);
 918         if (r == 0) {
 919                 DRM_ERROR("amdgpu: IB test timed out\n");
 920                 r = -ETIMEDOUT;
 921                 goto err1;
 922         } else if (r < 0) {
 923                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 924                 goto err1;
 925         }
 926         tmp = le32_to_cpu(adev->wb.wb[index]);
 927         if (tmp == 0xDEADBEEF) {
 928                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 929                 r = 0;
 930         } else {
 931                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 932                 r = -EINVAL;
 933         }
 934 err1:
 935         amdgpu_ib_free(adev, &ib, NULL);
 936         dma_fence_put(f);
 937 err0:
 938         amdgpu_wb_free(adev, index);
 939         return r;
 940 }
 941
 942 /**
 943  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 944  *
 945  * @ib: indirect buffer to fill with commands
 946  * @pe: addr of the page entry
 947  * @src: src addr to copy from
 948  * @count: number of page entries to update
 949  *
 950  * Update PTEs by copying them from the GART using sDMA (CIK).
 951  */
 952 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 953                                   uint64_t pe, uint64_t src,
 954                                   unsigned count)
 955 {
 956         unsigned bytes = count * 8;
 957
 958         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 959                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 960         ib->ptr[ib->length_dw++] = bytes;
 961         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 962         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 963         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 964         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 965         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 966 }
 967
 968 /**
 969  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 970  *
 971  * @ib: indirect buffer to fill with commands
 972  * @pe: addr of the page entry
 973  * @value: dst addr to write into pe
 974  * @count: number of page entries to update
 975  * @incr: increase next addr by incr bytes
 976  *
 977  * Update PTEs by writing them manually using sDMA (CIK).
 978  */
 979 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 980                                    uint64_t value, unsigned count,
 981                                    uint32_t incr)
 982 {
 983         unsigned ndw = count * 2;
 984
 985         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 986                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 987         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 988         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 989         ib->ptr[ib->length_dw++] = ndw;
 990         for (; ndw > 0; ndw -= 2) {
 991                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 992                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 993                 value += incr;
 994         }
 995 }
 996
 997 /**
 998  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 999  *
1000  * @ib: indirect buffer to fill with commands
1001  * @pe: addr of the page entry
1002  * @addr: dst addr to write into pe
1003  * @count: number of page entries to update
1004  * @incr: increase next addr by incr bytes
1005  * @flags: access flags
1006  *
1007  * Update the page tables using sDMA (CIK).
1008  */
1009 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1010                                      uint64_t addr, unsigned count,
1011                                      uint32_t incr, uint32_t flags)
1012 {
1013         /* for physically contiguous pages (vram) */
1014         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1015         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1016         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1017         ib->ptr[ib->length_dw++] = flags; /* mask */
1018         ib->ptr[ib->length_dw++] = 0;
1019         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1020         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1021         ib->ptr[ib->length_dw++] = incr; /* increment size */
1022         ib->ptr[ib->length_dw++] = 0;
1023         ib->ptr[ib->length_dw++] = count; /* number of entries */
1024 }
1025
1026 /**
1027  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1028  *
1029  * @ib: indirect buffer to fill with padding
1030  *
1031  */
1032 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1033 {
1034         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1035         u32 pad_count;
1036         int i;
1037
1038         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1039         for (i = 0; i < pad_count; i++)
1040                 if (sdma && sdma->burst_nop && (i == 0))
1041                         ib->ptr[ib->length_dw++] =
1042                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1043                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1044                 else
1045                         ib->ptr[ib->length_dw++] =
1046                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1047 }
1048
1049 /**
1050  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1051  *
1052  * @ring: amdgpu_ring pointer
1053  *
1054  * Make sure all previous operations are completed (CIK).
1055  */
1056 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1057 {
1058         uint32_t seq = ring->fence_drv.sync_seq;
1059         uint64_t addr = ring->fence_drv.gpu_addr;
1060
1061         /* wait for idle */
1062         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1063                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1064                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1065                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1066         amdgpu_ring_write(ring, addr & 0xfffffffc);
1067         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1068         amdgpu_ring_write(ring, seq); /* reference */
1069         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1070         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1071                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1072 }
1073
1074 /**
1075  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1076  *
1077  * @ring: amdgpu_ring pointer
1078  * @vm: amdgpu_vm pointer
1079  *
1080  * Update the page table base and flush the VM TLB
1081  * using sDMA (VI).
1082  */
1083 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1084                                          unsigned vm_id, uint64_t pd_addr)
1085 {
1086         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1087                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1088         if (vm_id < 8) {
1089                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1090         } else {
1091                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1092         }
1093         amdgpu_ring_write(ring, pd_addr >> 12);
1094
1095         /* flush TLB */
1096         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1097                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1098         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1099         amdgpu_ring_write(ring, 1 << vm_id);
1100
1101         /* wait for flush */
1102         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1103                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1104                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1105         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1106         amdgpu_ring_write(ring, 0);
1107         amdgpu_ring_write(ring, 0); /* reference */
1108         amdgpu_ring_write(ring, 0); /* mask */
1109         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1110                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1111 }
1112
1113 static int sdma_v3_0_early_init(void *handle)
1114 {
1115         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1116
1117         switch (adev->asic_type) {
1118         case CHIP_STONEY:
1119                 adev->sdma.num_instances = 1;
1120                 break;
1121         default:
1122                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1123                 break;
1124         }
1125
1126         sdma_v3_0_set_ring_funcs(adev);
1127         sdma_v3_0_set_buffer_funcs(adev);
1128         sdma_v3_0_set_vm_pte_funcs(adev);
1129         sdma_v3_0_set_irq_funcs(adev);
1130
1131         return 0;
1132 }
1133
1134 static int sdma_v3_0_sw_init(void *handle)
1135 {
1136         struct amdgpu_ring *ring;
1137         int r, i;
1138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
1140         /* SDMA trap event */
1141         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1142         if (r)
1143                 return r;
1144
1145         /* SDMA Privileged inst */
1146         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1147         if (r)
1148                 return r;
1149
1150         /* SDMA Privileged inst */
1151         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1152         if (r)
1153                 return r;
1154
1155         r = sdma_v3_0_init_microcode(adev);
1156         if (r) {
1157                 DRM_ERROR("Failed to load sdma firmware!\n");
1158                 return r;
1159         }
1160
1161         for (i = 0; i < adev->sdma.num_instances; i++) {
1162                 ring = &adev->sdma.instance[i].ring;
1163                 ring->ring_obj = NULL;
1164                 ring->use_doorbell = true;
1165                 ring->doorbell_index = (i == 0) ?
1166                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1167
1168                 sprintf(ring->name, "sdma%d", i);
1169                 r = amdgpu_ring_init(adev, ring, 1024,
1170                                      &adev->sdma.trap_irq,
1171                                      (i == 0) ?
1172                                      AMDGPU_SDMA_IRQ_TRAP0 :
1173                                      AMDGPU_SDMA_IRQ_TRAP1);
1174                 if (r)
1175                         return r;
1176         }
1177
1178         return r;
1179 }
1180
1181 static int sdma_v3_0_sw_fini(void *handle)
1182 {
1183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184         int i;
1185
1186         for (i = 0; i < adev->sdma.num_instances; i++)
1187                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1188
1189         sdma_v3_0_free_microcode(adev);
1190         return 0;
1191 }
1192
1193 static int sdma_v3_0_hw_init(void *handle)
1194 {
1195         int r;
1196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1197
1198         sdma_v3_0_init_golden_registers(adev);
1199
1200         r = sdma_v3_0_start(adev);
1201         if (r)
1202                 return r;
1203
1204         return r;
1205 }
1206
1207 static int sdma_v3_0_hw_fini(void *handle)
1208 {
1209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210
1211         sdma_v3_0_ctx_switch_enable(adev, false);
1212         sdma_v3_0_enable(adev, false);
1213
1214         return 0;
1215 }
1216
1217 static int sdma_v3_0_suspend(void *handle)
1218 {
1219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220
1221         return sdma_v3_0_hw_fini(adev);
1222 }
1223
1224 static int sdma_v3_0_resume(void *handle)
1225 {
1226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228         return sdma_v3_0_hw_init(adev);
1229 }
1230
1231 static bool sdma_v3_0_is_idle(void *handle)
1232 {
1233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234         u32 tmp = RREG32(mmSRBM_STATUS2);
1235
1236         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1237                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1238             return false;
1239
1240         return true;
1241 }
1242
1243 static int sdma_v3_0_wait_for_idle(void *handle)
1244 {
1245         unsigned i;
1246         u32 tmp;
1247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1248
1249         for (i = 0; i < adev->usec_timeout; i++) {
1250                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1251                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1252
1253                 if (!tmp)
1254                         return 0;
1255                 udelay(1);
1256         }
1257         return -ETIMEDOUT;
1258 }
1259
1260 static bool sdma_v3_0_check_soft_reset(void *handle)
1261 {
1262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263         u32 srbm_soft_reset = 0;
1264         u32 tmp = RREG32(mmSRBM_STATUS2);
1265
1266         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1267             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1268                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1269                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1270         }
1271
1272         if (srbm_soft_reset) {
1273                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1274                 return true;
1275         } else {
1276                 adev->sdma.srbm_soft_reset = 0;
1277                 return false;
1278         }
1279 }
1280
1281 static int sdma_v3_0_pre_soft_reset(void *handle)
1282 {
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284         u32 srbm_soft_reset = 0;
1285
1286         if (!adev->sdma.srbm_soft_reset)
1287                 return 0;
1288
1289         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1290
1291         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1292             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1293                 sdma_v3_0_ctx_switch_enable(adev, false);
1294                 sdma_v3_0_enable(adev, false);
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int sdma_v3_0_post_soft_reset(void *handle)
1301 {
1302         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303         u32 srbm_soft_reset = 0;
1304
1305         if (!adev->sdma.srbm_soft_reset)
1306                 return 0;
1307
1308         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1309
1310         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1311             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1312                 sdma_v3_0_gfx_resume(adev);
1313                 sdma_v3_0_rlc_resume(adev);
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int sdma_v3_0_soft_reset(void *handle)
1320 {
1321         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322         u32 srbm_soft_reset = 0;
1323         u32 tmp;
1324
1325         if (!adev->sdma.srbm_soft_reset)
1326                 return 0;
1327
1328         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1329
1330         if (srbm_soft_reset) {
1331                 tmp = RREG32(mmSRBM_SOFT_RESET);
1332                 tmp |= srbm_soft_reset;
1333                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1334                 WREG32(mmSRBM_SOFT_RESET, tmp);
1335                 tmp = RREG32(mmSRBM_SOFT_RESET);
1336
1337                 udelay(50);
1338
1339                 tmp &= ~srbm_soft_reset;
1340                 WREG32(mmSRBM_SOFT_RESET, tmp);
1341                 tmp = RREG32(mmSRBM_SOFT_RESET);
1342
1343                 /* Wait a little for things to settle down */
1344                 udelay(50);
1345         }
1346
1347         return 0;
1348 }
1349
1350 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1351                                         struct amdgpu_irq_src *source,
1352                                         unsigned type,
1353                                         enum amdgpu_interrupt_state state)
1354 {
1355         u32 sdma_cntl;
1356
1357         switch (type) {
1358         case AMDGPU_SDMA_IRQ_TRAP0:
1359                 switch (state) {
1360                 case AMDGPU_IRQ_STATE_DISABLE:
1361                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1362                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1363                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1364                         break;
1365                 case AMDGPU_IRQ_STATE_ENABLE:
1366                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1367                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1368                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1369                         break;
1370                 default:
1371                         break;
1372                 }
1373                 break;
1374         case AMDGPU_SDMA_IRQ_TRAP1:
1375                 switch (state) {
1376                 case AMDGPU_IRQ_STATE_DISABLE:
1377                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1378                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1379                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1380                         break;
1381                 case AMDGPU_IRQ_STATE_ENABLE:
1382                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1383                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1384                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1385                         break;
1386                 default:
1387                         break;
1388                 }
1389                 break;
1390         default:
1391                 break;
1392         }
1393         return 0;
1394 }
1395
1396 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1397                                       struct amdgpu_irq_src *source,
1398                                       struct amdgpu_iv_entry *entry)
1399 {
1400         u8 instance_id, queue_id;
1401
1402         instance_id = (entry->ring_id & 0x3) >> 0;
1403         queue_id = (entry->ring_id & 0xc) >> 2;
1404         DRM_DEBUG("IH: SDMA trap\n");
1405         switch (instance_id) {
1406         case 0:
1407                 switch (queue_id) {
1408                 case 0:
1409                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1410                         break;
1411                 case 1:
1412                         /* XXX compute */
1413                         break;
1414                 case 2:
1415                         /* XXX compute */
1416                         break;
1417                 }
1418                 break;
1419         case 1:
1420                 switch (queue_id) {
1421                 case 0:
1422                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1423                         break;
1424                 case 1:
1425                         /* XXX compute */
1426                         break;
1427                 case 2:
1428                         /* XXX compute */
1429                         break;
1430                 }
1431                 break;
1432         }
1433         return 0;
1434 }
1435
1436 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1437                                               struct amdgpu_irq_src *source,
1438                                               struct amdgpu_iv_entry *entry)
1439 {
1440         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1441         schedule_work(&adev->reset_work);
1442         return 0;
1443 }
1444
1445 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1446                 struct amdgpu_device *adev,
1447                 bool enable)
1448 {
1449         uint32_t temp, data;
1450         int i;
1451
1452         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1453                 for (i = 0; i < adev->sdma.num_instances; i++) {
1454                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1455                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1456                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1457                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1458                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1459                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1460                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1461                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1462                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1463                         if (data != temp)
1464                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1465                 }
1466         } else {
1467                 for (i = 0; i < adev->sdma.num_instances; i++) {
1468                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1469                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1470                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1471                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1472                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1473                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1474                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1475                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1476                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1477
1478                         if (data != temp)
1479                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1480                 }
1481         }
1482 }
1483
1484 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1485                 struct amdgpu_device *adev,
1486                 bool enable)
1487 {
1488         uint32_t temp, data;
1489         int i;
1490
1491         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1492                 for (i = 0; i < adev->sdma.num_instances; i++) {
1493                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1494                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1495
1496                         if (temp != data)
1497                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1498                 }
1499         } else {
1500                 for (i = 0; i < adev->sdma.num_instances; i++) {
1501                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1502                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1503
1504                         if (temp != data)
1505                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1506                 }
1507         }
1508 }
1509
1510 static int sdma_v3_0_set_clockgating_state(void *handle,
1511                                           enum amd_clockgating_state state)
1512 {
1513         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1514
1515         switch (adev->asic_type) {
1516         case CHIP_FIJI:
1517         case CHIP_CARRIZO:
1518         case CHIP_STONEY:
1519                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1520                                 state == AMD_CG_STATE_GATE ? true : false);
1521                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1522                                 state == AMD_CG_STATE_GATE ? true : false);
1523                 break;
1524         default:
1525                 break;
1526         }
1527         return 0;
1528 }
1529
1530 static int sdma_v3_0_set_powergating_state(void *handle,
1531                                           enum amd_powergating_state state)
1532 {
1533         return 0;
1534 }
1535
1536 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1537         .name = "sdma_v3_0",
1538         .early_init = sdma_v3_0_early_init,
1539         .late_init = NULL,
1540         .sw_init = sdma_v3_0_sw_init,
1541         .sw_fini = sdma_v3_0_sw_fini,
1542         .hw_init = sdma_v3_0_hw_init,
1543         .hw_fini = sdma_v3_0_hw_fini,
1544         .suspend = sdma_v3_0_suspend,
1545         .resume = sdma_v3_0_resume,
1546         .is_idle = sdma_v3_0_is_idle,
1547         .wait_for_idle = sdma_v3_0_wait_for_idle,
1548         .check_soft_reset = sdma_v3_0_check_soft_reset,
1549         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1550         .post_soft_reset = sdma_v3_0_post_soft_reset,
1551         .soft_reset = sdma_v3_0_soft_reset,
1552         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1553         .set_powergating_state = sdma_v3_0_set_powergating_state,
1554 };
1555
1556 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1557         .type = AMDGPU_RING_TYPE_SDMA,
1558         .align_mask = 0xf,
1559         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1560         .get_rptr = sdma_v3_0_ring_get_rptr,
1561         .get_wptr = sdma_v3_0_ring_get_wptr,
1562         .set_wptr = sdma_v3_0_ring_set_wptr,
1563         .emit_frame_size =
1564                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1565                 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
1566                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1567                 12 + /* sdma_v3_0_ring_emit_vm_flush */
1568                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1569         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1570         .emit_ib = sdma_v3_0_ring_emit_ib,
1571         .emit_fence = sdma_v3_0_ring_emit_fence,
1572         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1573         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1574         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1575         .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1576         .test_ring = sdma_v3_0_ring_test_ring,
1577         .test_ib = sdma_v3_0_ring_test_ib,
1578         .insert_nop = sdma_v3_0_ring_insert_nop,
1579         .pad_ib = sdma_v3_0_ring_pad_ib,
1580 };
1581
1582 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1583 {
1584         int i;
1585
1586         for (i = 0; i < adev->sdma.num_instances; i++)
1587                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1588 }
1589
1590 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1591         .set = sdma_v3_0_set_trap_irq_state,
1592         .process = sdma_v3_0_process_trap_irq,
1593 };
1594
1595 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1596         .process = sdma_v3_0_process_illegal_inst_irq,
1597 };
1598
1599 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1600 {
1601         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1602         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1603         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1604 }
1605
1606 /**
1607  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1608  *
1609  * @ring: amdgpu_ring structure holding ring information
1610  * @src_offset: src GPU address
1611  * @dst_offset: dst GPU address
1612  * @byte_count: number of bytes to xfer
1613  *
1614  * Copy GPU buffers using the DMA engine (VI).
1615  * Used by the amdgpu ttm implementation to move pages if
1616  * registered as the asic copy callback.
1617  */
1618 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1619                                        uint64_t src_offset,
1620                                        uint64_t dst_offset,
1621                                        uint32_t byte_count)
1622 {
1623         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1624                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1625         ib->ptr[ib->length_dw++] = byte_count;
1626         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1627         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1628         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1629         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1630         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1631 }
1632
1633 /**
1634  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1635  *
1636  * @ring: amdgpu_ring structure holding ring information
1637  * @src_data: value to write to buffer
1638  * @dst_offset: dst GPU address
1639  * @byte_count: number of bytes to xfer
1640  *
1641  * Fill GPU buffers using the DMA engine (VI).
1642  */
1643 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1644                                        uint32_t src_data,
1645                                        uint64_t dst_offset,
1646                                        uint32_t byte_count)
1647 {
1648         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1649         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1650         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1651         ib->ptr[ib->length_dw++] = src_data;
1652         ib->ptr[ib->length_dw++] = byte_count;
1653 }
1654
1655 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1656         .copy_max_bytes = 0x1fffff,
1657         .copy_num_dw = 7,
1658         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1659
1660         .fill_max_bytes = 0x1fffff,
1661         .fill_num_dw = 5,
1662         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1663 };
1664
1665 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1666 {
1667         if (adev->mman.buffer_funcs == NULL) {
1668                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1669                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1670         }
1671 }
1672
1673 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1674         .copy_pte = sdma_v3_0_vm_copy_pte,
1675         .write_pte = sdma_v3_0_vm_write_pte,
1676         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1677 };
1678
1679 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1680 {
1681         unsigned i;
1682
1683         if (adev->vm_manager.vm_pte_funcs == NULL) {
1684                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1685                 for (i = 0; i < adev->sdma.num_instances; i++)
1686                         adev->vm_manager.vm_pte_rings[i] =
1687                                 &adev->sdma.instance[i].ring;
1688
1689                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1690         }
1691 }
1692
1693 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1694 {
1695         .type = AMD_IP_BLOCK_TYPE_SDMA,
1696         .major = 3,
1697         .minor = 0,
1698         .rev = 0,
1699         .funcs = &sdma_v3_0_ip_funcs,
1700 };
1701
1702 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1703 {
1704         .type = AMD_IP_BLOCK_TYPE_SDMA,
1705         .major = 3,
1706         .minor = 1,
1707         .rev = 0,
1708         .funcs = &sdma_v3_0_ip_funcs,
1709 };