2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/firmware.h>
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ucode.h"
31 #include "soc15_common.h"
34 #include "vega10/soc15ip.h"
35 #include "vega10/MP/mp_9_0_offset.h"
36 #include "vega10/MP/mp_9_0_sh_mask.h"
37 #include "vega10/GC/gc_9_0_offset.h"
38 #include "vega10/SDMA0/sdma0_4_0_offset.h"
39 #include "vega10/NBIO/nbio_6_1_offset.h"
41 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
42 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
44 #define smnMP1_FIRMWARE_FLAGS 0x3010028
47 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
49 switch(ucode->ucode_id) {
50 case AMDGPU_UCODE_ID_SDMA0:
51 *type = GFX_FW_TYPE_SDMA0;
53 case AMDGPU_UCODE_ID_SDMA1:
54 *type = GFX_FW_TYPE_SDMA1;
56 case AMDGPU_UCODE_ID_CP_CE:
57 *type = GFX_FW_TYPE_CP_CE;
59 case AMDGPU_UCODE_ID_CP_PFP:
60 *type = GFX_FW_TYPE_CP_PFP;
62 case AMDGPU_UCODE_ID_CP_ME:
63 *type = GFX_FW_TYPE_CP_ME;
65 case AMDGPU_UCODE_ID_CP_MEC1:
66 *type = GFX_FW_TYPE_CP_MEC;
68 case AMDGPU_UCODE_ID_CP_MEC1_JT:
69 *type = GFX_FW_TYPE_CP_MEC_ME1;
71 case AMDGPU_UCODE_ID_CP_MEC2:
72 *type = GFX_FW_TYPE_CP_MEC;
74 case AMDGPU_UCODE_ID_CP_MEC2_JT:
75 *type = GFX_FW_TYPE_CP_MEC_ME2;
77 case AMDGPU_UCODE_ID_RLC_G:
78 *type = GFX_FW_TYPE_RLC_G;
80 case AMDGPU_UCODE_ID_SMC:
81 *type = GFX_FW_TYPE_SMU;
83 case AMDGPU_UCODE_ID_UVD:
84 *type = GFX_FW_TYPE_UVD;
86 case AMDGPU_UCODE_ID_VCE:
87 *type = GFX_FW_TYPE_VCE;
89 case AMDGPU_UCODE_ID_MAXIMUM:
97 int psp_v3_1_init_microcode(struct psp_context *psp)
99 struct amdgpu_device *adev = psp->adev;
100 const char *chip_name;
103 const struct psp_firmware_header_v1_0 *hdr;
107 switch (adev->asic_type) {
109 chip_name = "vega10";
114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
115 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
119 err = amdgpu_ucode_validate(adev->psp.sos_fw);
123 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
124 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
125 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
126 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
127 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
128 le32_to_cpu(hdr->sos_size_bytes);
129 adev->psp.sys_start_addr = (uint8_t *)hdr +
130 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
131 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
132 le32_to_cpu(hdr->sos_offset_bytes);
134 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
135 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
139 err = amdgpu_ucode_validate(adev->psp.asd_fw);
143 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
144 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
145 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
146 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
147 adev->psp.asd_start_addr = (uint8_t *)hdr +
148 le32_to_cpu(hdr->header.ucode_array_offset_bytes);
154 "psp v3.1: Failed to load firmware \"%s\"\n",
156 release_firmware(adev->psp.sos_fw);
157 adev->psp.sos_fw = NULL;
158 release_firmware(adev->psp.asd_fw);
159 adev->psp.asd_fw = NULL;
165 int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
168 uint32_t psp_gfxdrv_command_reg = 0;
169 struct amdgpu_bo *psp_sysdrv;
170 void *psp_sysdrv_virt = NULL;
171 uint64_t psp_sysdrv_mem;
172 struct amdgpu_device *adev = psp->adev;
173 uint32_t size, sol_reg;
175 /* Check sOS sign of life register to confirm sys driver and sOS
176 * are already been loaded.
178 sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81));
182 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
183 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
184 0x80000000, 0x80000000, false);
189 * Create a 1 meg GART memory to store the psp sys driver
190 * binary with a 1 meg aligned address
192 size = (psp->sys_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) &
193 (~(PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1));
195 ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT,
196 AMDGPU_GEM_DOMAIN_GTT,
203 /* Copy PSP System Driver binary to memory */
204 memcpy(psp_sysdrv_virt, psp->sys_start_addr, psp->sys_bin_size);
206 /* Provide the sys driver to bootrom */
207 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),
208 (uint32_t)(psp_sysdrv_mem >> 20));
209 psp_gfxdrv_command_reg = 1 << 16;
210 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
211 psp_gfxdrv_command_reg);
213 /* there might be handshake issue with hardware which needs delay */
216 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
217 0x80000000, 0x80000000, false);
219 amdgpu_bo_free_kernel(&psp_sysdrv, &psp_sysdrv_mem, &psp_sysdrv_virt);
224 int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
227 unsigned int psp_gfxdrv_command_reg = 0;
228 struct amdgpu_bo *psp_sos;
229 void *psp_sos_virt = NULL;
230 uint64_t psp_sos_mem;
231 struct amdgpu_device *adev = psp->adev;
232 uint32_t size, sol_reg;
234 /* Check sOS sign of life register to confirm sys driver and sOS
235 * are already been loaded.
237 sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81));
241 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
242 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
243 0x80000000, 0x80000000, false);
247 size = (psp->sos_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) &
248 (~((uint64_t)PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1));
250 ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT,
251 AMDGPU_GEM_DOMAIN_GTT,
258 /* Copy Secure OS binary to PSP memory */
259 memcpy(psp_sos_virt, psp->sos_start_addr, psp->sos_bin_size);
261 /* Provide the PSP secure OS to bootrom */
262 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),
263 (uint32_t)(psp_sos_mem >> 20));
264 psp_gfxdrv_command_reg = 2 << 16;
265 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
266 psp_gfxdrv_command_reg);
268 /* there might be handshake issue with hardware which needs delay */
271 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
272 RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)),
276 amdgpu_bo_free_kernel(&psp_sos, &psp_sos_mem, &psp_sos_virt);
281 int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
284 uint64_t fw_mem_mc_addr = ucode->mc_addr;
286 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
288 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
289 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
290 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
291 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
293 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
295 DRM_ERROR("Unknown firmware type\n");
300 int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
303 unsigned int psp_ring_reg = 0;
304 struct psp_ring *ring;
305 struct amdgpu_device *adev = psp->adev;
307 ring = &psp->km_ring;
309 ring->ring_type = ring_type;
311 /* allocate 4k Page of Local Frame Buffer memory for ring */
312 ring->ring_size = 0x1000;
313 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
314 AMDGPU_GEM_DOMAIN_VRAM,
315 &adev->firmware.rbuf,
316 &ring->ring_mem_mc_addr,
317 (void **)&ring->ring_mem);
323 /* Write low address of the ring to C2PMSG_69 */
324 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
325 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg);
326 /* Write high address of the ring to C2PMSG_70 */
327 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
328 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg);
329 /* Write size of ring to C2PMSG_71 */
330 psp_ring_reg = ring->ring_size;
331 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg);
332 /* Write the ring initialization command to C2PMSG_64 */
333 psp_ring_reg = ring_type;
334 psp_ring_reg = psp_ring_reg << 16;
335 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg);
337 /* there might be handshake issue with hardware which needs delay */
340 /* Wait for response flag (bit 31) in C2PMSG_64 */
341 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
342 0x80000000, 0x8000FFFF, false);
347 int psp_v3_1_cmd_submit(struct psp_context *psp,
348 struct amdgpu_firmware_info *ucode,
349 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
352 unsigned int psp_write_ptr_reg = 0;
353 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
354 struct psp_ring *ring = &psp->km_ring;
355 struct amdgpu_device *adev = psp->adev;
356 uint32_t ring_size_dw = ring->ring_size / 4;
357 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
359 /* KM (GPCOM) prepare write pointer */
360 psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67));
362 /* Update KM RB frame pointer to new frame */
363 /* write_frame ptr increments by size of rb_frame in bytes */
364 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
365 if ((psp_write_ptr_reg % ring_size_dw) == 0)
366 write_frame = ring->ring_mem;
368 write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
370 /* Initialize KM RB frame */
371 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
373 /* Update KM RB frame */
374 write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
375 write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
376 write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
377 write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
378 write_frame->fence_value = index;
380 /* Update the write Pointer in DWORDs */
381 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
382 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg);
388 psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
389 unsigned int *sram_data_reg_offset,
390 enum AMDGPU_UCODE_ID ucode_id)
395 /* TODO: needs to confirm */
397 case AMDGPU_UCODE_ID_SMC:
399 *sram_addr_reg_offset = 0;
400 *sram_data_reg_offset = 0;
404 case AMDGPU_UCODE_ID_CP_CE:
406 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
407 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
410 case AMDGPU_UCODE_ID_CP_PFP:
412 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
413 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
416 case AMDGPU_UCODE_ID_CP_ME:
418 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
419 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
422 case AMDGPU_UCODE_ID_CP_MEC1:
423 *sram_offset = 0x10000;
424 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
425 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
428 case AMDGPU_UCODE_ID_CP_MEC2:
429 *sram_offset = 0x10000;
430 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
431 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
434 case AMDGPU_UCODE_ID_RLC_G:
435 *sram_offset = 0x2000;
436 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
437 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
440 case AMDGPU_UCODE_ID_SDMA0:
442 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
443 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
446 /* TODO: needs to confirm */
448 case AMDGPU_UCODE_ID_SDMA1:
450 *sram_addr_reg_offset = ;
453 case AMDGPU_UCODE_ID_UVD:
455 *sram_addr_reg_offset = ;
458 case AMDGPU_UCODE_ID_VCE:
460 *sram_addr_reg_offset = ;
464 case AMDGPU_UCODE_ID_MAXIMUM:
473 bool psp_v3_1_compare_sram_data(struct psp_context *psp,
474 struct amdgpu_firmware_info *ucode,
475 enum AMDGPU_UCODE_ID ucode_type)
478 unsigned int fw_sram_reg_val = 0;
479 unsigned int fw_sram_addr_reg_offset = 0;
480 unsigned int fw_sram_data_reg_offset = 0;
481 unsigned int ucode_size;
482 uint32_t *ucode_mem = NULL;
483 struct amdgpu_device *adev = psp->adev;
485 err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
486 &fw_sram_data_reg_offset, ucode_type);
490 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
492 ucode_size = ucode->ucode_size;
493 ucode_mem = (uint32_t *)ucode->kaddr;
495 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
497 if (*ucode_mem != fw_sram_reg_val)
508 bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
510 struct amdgpu_device *adev = psp->adev;
513 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;
514 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg);
515 reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2));
516 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;