drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "mmhub_v1_0.h"
  25
  26 #include "mmhub/mmhub_1_0_offset.h"
  27 #include "mmhub/mmhub_1_0_sh_mask.h"
  28 #include "mmhub/mmhub_1_0_default.h"
  29 #include "athub/athub_1_0_offset.h"
  30 #include "athub/athub_1_0_sh_mask.h"
  31 #include "vega10_enum.h"
  32
  33 #include "soc15_common.h"
  34
  35 #define mmDAGB0_CNTL_MISC2_RV 0x008f
  36 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
  37
  38 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
  39 {
  40         u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
  41         u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);
  42
  43         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  44         base <<= 24;
  45
  46         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  47         top <<= 24;
  48
  49         adev->gmc.fb_start = base;
  50         adev->gmc.fb_end = top;
  51
  52         return base;
  53 }
  54
  55 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
  56 {
  57         uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
  58
  59         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  60                      lower_32_bits(value));
  61
  62         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  63                      upper_32_bits(value));
  64 }
  65
  66 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  67 {
  68         mmhub_v1_0_init_gart_pt_regs(adev);
  69
  70         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  71                      (u32)(adev->gmc.gart_start >> 12));
  72         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  73                      (u32)(adev->gmc.gart_start >> 44));
  74
  75         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  76                      (u32)(adev->gmc.gart_end >> 12));
  77         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  78                      (u32)(adev->gmc.gart_end >> 44));
  79 }
  80
  81 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  82 {
  83         uint64_t value;
  84         uint32_t tmp;
  85
  86         /* Program the AGP BAR */
  87         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
  88         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  89         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  90
  91         /* Program the system aperture low logical page number. */
  92         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  93                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
  94
  95         if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
  96                 /*
  97                  * Raven2 has a HW issue that it is unable to use the vram which
  98                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
  99                  * workaround that increase system aperture high address (add 1)
 100                  * to get rid of the VM fault and hardware hang.
 101                  */
 102                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 103                              max((adev->gmc.fb_end >> 18) + 0x1,
 104                                  adev->gmc.agp_end >> 18));
 105         else
 106                 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 107                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 108
 109         /* Set default page address. */
 110         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
 111                 adev->vm_manager.vram_base_offset;
 112         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 113                      (u32)(value >> 12));
 114         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 115                      (u32)(value >> 44));
 116
 117         /* Program "protection fault". */
 118         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 119                      (u32)(adev->dummy_page_addr >> 12));
 120         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 121                      (u32)((u64)adev->dummy_page_addr >> 44));
 122
 123         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
 124         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 125                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 126         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 127 }
 128
 129 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 130 {
 131         uint32_t tmp;
 132
 133         /* Setup TLB control */
 134         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 135
 136         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 137         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 138         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 139                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 140         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 141                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 142         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 143         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 144                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 145         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 146
 147         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 148 }
 149
 150 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 151 {
 152         uint32_t tmp;
 153
 154         /* Setup L2 cache */
 155         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 156         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 157         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 158         /* XXX for emulation, Refer to closed source code.*/
 159         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 160                             0);
 161         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
 162         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 163         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 164         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 165
 166         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
 167         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 168         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 169         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 170
 171         if (adev->gmc.translate_further) {
 172                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 173                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 174                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 175         } else {
 176                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 177                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 178                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 179         }
 180
 181         tmp = mmVM_L2_CNTL4_DEFAULT;
 182         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 183         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 184         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
 185 }
 186
 187 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 188 {
 189         uint32_t tmp;
 190
 191         tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 192         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 193         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 194         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
 195 }
 196
 197 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 198 {
 199         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 200                      0XFFFFFFFF);
 201         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 202                      0x0000000F);
 203
 204         WREG32_SOC15(MMHUB, 0,
 205                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 206         WREG32_SOC15(MMHUB, 0,
 207                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 208
 209         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 210                      0);
 211         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 212                      0);
 213 }
 214
 215 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 216 {
 217         unsigned num_level, block_size;
 218         uint32_t tmp;
 219         int i;
 220
 221         num_level = adev->vm_manager.num_level;
 222         block_size = adev->vm_manager.block_size;
 223         if (adev->gmc.translate_further)
 224                 num_level -= 1;
 225         else
 226                 block_size -= 9;
 227
 228         for (i = 0; i <= 14; i++) {
 229                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
 230                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 231                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 232                                     num_level);
 233                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 234                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 235                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 236                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 237                                     1);
 238                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 239                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 240                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 241                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 242                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 243                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 244                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 245                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 246                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 247                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 248                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 249                                     PAGE_TABLE_BLOCK_SIZE,
 250                                     block_size);
 251                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 252                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 253                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 254                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 255                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 256                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 257                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
 258                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 259                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 260                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 261         }
 262 }
 263
 264 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 265 {
 266         unsigned i;
 267
 268         for (i = 0; i < 18; ++i) {
 269                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 270                                     2 * i, 0xffffffff);
 271                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 272                                     2 * i, 0x1f);
 273         }
 274 }
 275
 276 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 277                                 bool enable)
 278 {
 279         if (amdgpu_sriov_vf(adev))
 280                 return;
 281
 282         if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
 283                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
 284                         amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
 285
 286         }
 287 }
 288
 289 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 290 {
 291         if (amdgpu_sriov_vf(adev)) {
 292                 /*
 293                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 294                  * VF copy registers so vbios post doesn't program them, for
 295                  * SRIOV driver need to program them
 296                  */
 297                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
 298                              adev->gmc.vram_start >> 24);
 299                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
 300                              adev->gmc.vram_end >> 24);
 301         }
 302
 303         /* GART Enable. */
 304         mmhub_v1_0_init_gart_aperture_regs(adev);
 305         mmhub_v1_0_init_system_aperture_regs(adev);
 306         mmhub_v1_0_init_tlb_regs(adev);
 307         mmhub_v1_0_init_cache_regs(adev);
 308
 309         mmhub_v1_0_enable_system_domain(adev);
 310         mmhub_v1_0_disable_identity_aperture(adev);
 311         mmhub_v1_0_setup_vmid_config(adev);
 312         mmhub_v1_0_program_invalidation(adev);
 313
 314         return 0;
 315 }
 316
 317 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
 318 {
 319         u32 tmp;
 320         u32 i;
 321
 322         /* Disable all tables */
 323         for (i = 0; i < 16; i++)
 324                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
 325
 326         /* Setup TLB control */
 327         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 328         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 329         tmp = REG_SET_FIELD(tmp,
 330                                 MC_VM_MX_L1_TLB_CNTL,
 331                                 ENABLE_ADVANCED_DRIVER_MODEL,
 332                                 0);
 333         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 334
 335         /* Setup L2 cache */
 336         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 337         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 338         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 339         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
 340 }
 341
 342 /**
 343  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 344  *
 345  * @adev: amdgpu_device pointer
 346  * @value: true redirects VM faults to the default page
 347  */
 348 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 349 {
 350         u32 tmp;
 351         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 352         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 353                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 354         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 355                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 356         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 357                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 358         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 359                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 360         tmp = REG_SET_FIELD(tmp,
 361                         VM_L2_PROTECTION_FAULT_CNTL,
 362                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 363                         value);
 364         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 365                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 366         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 367                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 368         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 369                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 370         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 371                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 372         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 373                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 374         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 375                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 376         if (!value) {
 377                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 378                                 CRASH_ON_NO_RETRY_FAULT, 1);
 379                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 380                                 CRASH_ON_RETRY_FAULT, 1);
 381     }
 382
 383         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 384 }
 385
 386 void mmhub_v1_0_init(struct amdgpu_device *adev)
 387 {
 388         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
 389
 390         hub->ctx0_ptb_addr_lo32 =
 391                 SOC15_REG_OFFSET(MMHUB, 0,
 392                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 393         hub->ctx0_ptb_addr_hi32 =
 394                 SOC15_REG_OFFSET(MMHUB, 0,
 395                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 396         hub->vm_inv_eng0_req =
 397                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
 398         hub->vm_inv_eng0_ack =
 399                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
 400         hub->vm_context0_cntl =
 401                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 402         hub->vm_l2_pro_fault_status =
 403                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 404         hub->vm_l2_pro_fault_cntl =
 405                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 406
 407 }
 408
 409 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 410                                                         bool enable)
 411 {
 412         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 413
 414         def  = data  = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 415
 416         if (adev->asic_type != CHIP_RAVEN) {
 417                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 418                 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
 419         } else
 420                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
 421
 422         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 423                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 424
 425                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 426                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 427                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 428                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 429                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 430                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 431
 432                 if (adev->asic_type != CHIP_RAVEN)
 433                         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 434                                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 435                                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 436                                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 437                                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 438                                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 439         } else {
 440                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 441
 442                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 443                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 444                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 445                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 446                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 447                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 448
 449                 if (adev->asic_type != CHIP_RAVEN)
 450                         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 451                                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 452                                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 453                                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 454                                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 455                                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 456         }
 457
 458         if (def != data)
 459                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 460
 461         if (def1 != data1) {
 462                 if (adev->asic_type != CHIP_RAVEN)
 463                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 464                 else
 465                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
 466         }
 467
 468         if (adev->asic_type != CHIP_RAVEN && def2 != data2)
 469                 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
 470 }
 471
 472 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 473                                                    bool enable)
 474 {
 475         uint32_t def, data;
 476
 477         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 478
 479         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 480                 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 481         else
 482                 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 483
 484         if (def != data)
 485                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
 486 }
 487
 488 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 489                                                        bool enable)
 490 {
 491         uint32_t def, data;
 492
 493         def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 494
 495         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 496                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 497         else
 498                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 499
 500         if (def != data)
 501                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 502 }
 503
 504 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 505                                                   bool enable)
 506 {
 507         uint32_t def, data;
 508
 509         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 510
 511         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
 512             (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 513                 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 514         else
 515                 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 516
 517         if(def != data)
 518                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
 519 }
 520
 521 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 522                                enum amd_clockgating_state state)
 523 {
 524         if (amdgpu_sriov_vf(adev))
 525                 return 0;
 526
 527         switch (adev->asic_type) {
 528         case CHIP_VEGA10:
 529         case CHIP_VEGA12:
 530         case CHIP_VEGA20:
 531         case CHIP_RAVEN:
 532                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
 533                                 state == AMD_CG_STATE_GATE ? true : false);
 534                 athub_update_medium_grain_clock_gating(adev,
 535                                 state == AMD_CG_STATE_GATE ? true : false);
 536                 mmhub_v1_0_update_medium_grain_light_sleep(adev,
 537                                 state == AMD_CG_STATE_GATE ? true : false);
 538                 athub_update_medium_grain_light_sleep(adev,
 539                                 state == AMD_CG_STATE_GATE ? true : false);
 540                 break;
 541         default:
 542                 break;
 543         }
 544
 545         return 0;
 546 }
 547
 548 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 549 {
 550         int data;
 551
 552         if (amdgpu_sriov_vf(adev))
 553                 *flags = 0;
 554
 555         /* AMD_CG_SUPPORT_MC_MGCG */
 556         data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 557         if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
 558                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 559
 560         /* AMD_CG_SUPPORT_MC_LS */
 561         data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 562         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 563                 *flags |= AMD_CG_SUPPORT_MC_LS;
 564 }