drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "mmhub_v1_0.h"
  25
  26 #include "vega10/soc15ip.h"
  27 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  28 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  29 #include "vega10/MMHUB/mmhub_1_0_default.h"
  30 #include "vega10/ATHUB/athub_1_0_offset.h"
  31 #include "vega10/ATHUB/athub_1_0_sh_mask.h"
  32 #include "vega10/ATHUB/athub_1_0_default.h"
  33 #include "vega10/vega10_enum.h"
  34
  35 #include "soc15_common.h"
  36
  37 #define mmDAGB0_CNTL_MISC2_RV 0x008f
  38 #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
  39
  40 u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
  41 {
  42         u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
  43
  44         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  45         base <<= 24;
  46
  47         return base;
  48 }
  49
  50 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
  51 {
  52         uint64_t value;
  53
  54         BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
  55         value = adev->gart.table_addr - adev->mc.vram_start +
  56                 adev->vm_manager.vram_base_offset;
  57         value &= 0x0000FFFFFFFFF000ULL;
  58         value |= 0x1; /* valid bit */
  59
  60         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  61                      lower_32_bits(value));
  62
  63         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  64                      upper_32_bits(value));
  65 }
  66
  67 static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  68 {
  69         mmhub_v1_0_init_gart_pt_regs(adev);
  70
  71         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  72                      (u32)(adev->mc.gart_start >> 12));
  73         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  74                      (u32)(adev->mc.gart_start >> 44));
  75
  76         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  77                      (u32)(adev->mc.gart_end >> 12));
  78         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  79                      (u32)(adev->mc.gart_end >> 44));
  80 }
  81
  82 static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  83 {
  84         uint64_t value;
  85         uint32_t tmp;
  86
  87         /* Disable AGP. */
  88         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
  89         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
  90         WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
  91
  92         /* Program the system aperture low logical page number. */
  93         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  94                      adev->mc.vram_start >> 18);
  95         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  96                      adev->mc.vram_end >> 18);
  97
  98         /* Set default page address. */
  99         value = adev->vram_scratch.gpu_addr - adev->mc.vram_start +
 100                 adev->vm_manager.vram_base_offset;
 101         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 102                      (u32)(value >> 12));
 103         WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 104                      (u32)(value >> 44));
 105
 106         /* Program "protection fault". */
 107         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 108                      (u32)(adev->dummy_page.addr >> 12));
 109         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 110                      (u32)((u64)adev->dummy_page.addr >> 44));
 111
 112         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
 113         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 114                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 115         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 116 }
 117
 118 static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 119 {
 120         uint32_t tmp;
 121
 122         /* Setup TLB control */
 123         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 124
 125         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 126         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 127         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 128                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 129         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 130                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 131         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 132         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 133                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 134         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 135
 136         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 137 }
 138
 139 static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 140 {
 141         uint32_t tmp, field;
 142
 143         /* Setup L2 cache */
 144         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 145         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 146         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 147         /* XXX for emulation, Refer to closed source code.*/
 148         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 149                             0);
 150         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
 151         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 152         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 153         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 154
 155         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
 156         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 157         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 158         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
 159
 160         field = adev->vm_manager.fragment_size;
 161         tmp = mmVM_L2_CNTL3_DEFAULT;
 162         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 163         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 164         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
 165
 166         tmp = mmVM_L2_CNTL4_DEFAULT;
 167         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 168         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 169         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
 170 }
 171
 172 static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 173 {
 174         uint32_t tmp;
 175
 176         tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 177         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 178         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 179         WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
 180 }
 181
 182 static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 183 {
 184         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 185                      0XFFFFFFFF);
 186         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 187                      0x0000000F);
 188
 189         WREG32_SOC15(MMHUB, 0,
 190                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 191         WREG32_SOC15(MMHUB, 0,
 192                      mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 193
 194         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 195                      0);
 196         WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 197                      0);
 198 }
 199
 200 static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 201 {
 202         int i;
 203         uint32_t tmp;
 204
 205         for (i = 0; i <= 14; i++) {
 206                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
 207                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 208                                 ENABLE_CONTEXT, 1);
 209                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 210                                 PAGE_TABLE_DEPTH, adev->vm_manager.num_level);
 211                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 212                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 213                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 214                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 215                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 216                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 217                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 218                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 219                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 220                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 221                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 222                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 223                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 224                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 225                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 226                                 PAGE_TABLE_BLOCK_SIZE,
 227                                 adev->vm_manager.block_size - 9);
 228                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 229                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 230                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 231                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 232                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 233                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 234                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
 235                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 236                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 237                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 238         }
 239 }
 240
 241 static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 242 {
 243         unsigned i;
 244
 245         for (i = 0; i < 18; ++i) {
 246                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 247                                     2 * i, 0xffffffff);
 248                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 249                                     2 * i, 0x1f);
 250         }
 251 }
 252
 253 struct pctl_data {
 254         uint32_t index;
 255         uint32_t data;
 256 };
 257
 258 static const struct pctl_data pctl0_data[] = {
 259         {0x0, 0x7a640},
 260         {0x9, 0x2a64a},
 261         {0xd, 0x2a680},
 262         {0x11, 0x6a684},
 263         {0x19, 0xea68e},
 264         {0x29, 0xa69e},
 265         {0x2b, 0x34a6c0},
 266         {0x61, 0x83a707},
 267         {0xe6, 0x8a7a4},
 268         {0xf0, 0x1a7b8},
 269         {0xf3, 0xfa7cc},
 270         {0x104, 0x17a7dd},
 271         {0x11d, 0xa7dc},
 272         {0x11f, 0x12a7f5},
 273         {0x133, 0xa808},
 274         {0x135, 0x12a810},
 275         {0x149, 0x7a82c}
 276 };
 277 #define PCTL0_DATA_LEN (sizeof(pctl0_data)/sizeof(pctl0_data[0]))
 278
 279 #define PCTL0_RENG_EXEC_END_PTR 0x151
 280 #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE  0xa640
 281 #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
 282
 283 static const struct pctl_data pctl1_data[] = {
 284         {0x0, 0x39a000},
 285         {0x3b, 0x44a040},
 286         {0x81, 0x2a08d},
 287         {0x85, 0x6ba094},
 288         {0xf2, 0x18a100},
 289         {0x10c, 0x4a132},
 290         {0x112, 0xca141},
 291         {0x120, 0x2fa158},
 292         {0x151, 0x17a1d0},
 293         {0x16a, 0x1a1e9},
 294         {0x16d, 0x13a1ec},
 295         {0x182, 0x7a201},
 296         {0x18b, 0x3a20a},
 297         {0x190, 0x7a580},
 298         {0x199, 0xa590},
 299         {0x19b, 0x4a594},
 300         {0x1a1, 0x1a59c},
 301         {0x1a4, 0x7a82c},
 302         {0x1ad, 0xfa7cc},
 303         {0x1be, 0x17a7dd},
 304         {0x1d7, 0x12a810},
 305         {0x1eb, 0x4000a7e1},
 306         {0x1ec, 0x5000a7f5},
 307         {0x1ed, 0x4000a7e2},
 308         {0x1ee, 0x5000a7dc},
 309         {0x1ef, 0x4000a7e3},
 310         {0x1f0, 0x5000a7f6},
 311         {0x1f1, 0x5000a7e4}
 312 };
 313 #define PCTL1_DATA_LEN (sizeof(pctl1_data)/sizeof(pctl1_data[0]))
 314
 315 #define PCTL1_RENG_EXEC_END_PTR 0x1f1
 316 #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE  0xa000
 317 #define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
 318 #define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE  0xa580
 319 #define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d
 320 #define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE  0xa82c
 321 #define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833
 322
 323 static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev)
 324 {
 325         uint32_t tmp = 0;
 326
 327         /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */
 328         tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
 329                         STCTRL_REGISTER_SAVE_BASE,
 330                         PCTL0_STCTRL_REG_SAVE_RANGE0_BASE);
 331         tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
 332                         STCTRL_REGISTER_SAVE_LIMIT,
 333                         PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT);
 334         WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp);
 335
 336         /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */
 337         tmp = 0;
 338         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
 339                         STCTRL_REGISTER_SAVE_BASE,
 340                         PCTL1_STCTRL_REG_SAVE_RANGE0_BASE);
 341         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
 342                         STCTRL_REGISTER_SAVE_LIMIT,
 343                         PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT);
 344         WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp);
 345
 346         /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */
 347         tmp = 0;
 348         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
 349                         STCTRL_REGISTER_SAVE_BASE,
 350                         PCTL1_STCTRL_REG_SAVE_RANGE1_BASE);
 351         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
 352                         STCTRL_REGISTER_SAVE_LIMIT,
 353                         PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT);
 354         WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp);
 355
 356         /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */
 357         tmp = 0;
 358         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
 359                         STCTRL_REGISTER_SAVE_BASE,
 360                         PCTL1_STCTRL_REG_SAVE_RANGE2_BASE);
 361         tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
 362                         STCTRL_REGISTER_SAVE_LIMIT,
 363                         PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT);
 364         WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp);
 365 }
 366
 367 void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev)
 368 {
 369         uint32_t pctl0_misc = 0;
 370         uint32_t pctl0_reng_execute = 0;
 371         uint32_t pctl1_misc = 0;
 372         uint32_t pctl1_reng_execute = 0;
 373         int i = 0;
 374
 375         if (amdgpu_sriov_vf(adev))
 376                 return;
 377
 378         pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
 379         pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
 380         pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
 381         pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
 382
 383         /* Light sleep must be disabled before writing to pctl0 registers */
 384         pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
 385         WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
 386
 387         /* Write data used to access ram of register engine */
 388         for (i = 0; i < PCTL0_DATA_LEN; i++) {
 389                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX,
 390                         pctl0_data[i].index);
 391                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA,
 392                         pctl0_data[i].data);
 393         }
 394
 395         /* Set the reng execute end ptr for pctl0 */
 396         pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 397                                         PCTL0_RENG_EXECUTE,
 398                                         RENG_EXECUTE_END_PTR,
 399                                         PCTL0_RENG_EXEC_END_PTR);
 400         WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
 401
 402         /* Light sleep must be disabled before writing to pctl1 registers */
 403         pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
 404         WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
 405
 406         /* Write data used to access ram of register engine */
 407         for (i = 0; i < PCTL1_DATA_LEN; i++) {
 408                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX,
 409                         pctl1_data[i].index);
 410                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA,
 411                         pctl1_data[i].data);
 412         }
 413
 414         /* Set the reng execute end ptr for pctl1 */
 415         pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 416                                         PCTL1_RENG_EXECUTE,
 417                                         RENG_EXECUTE_END_PTR,
 418                                         PCTL1_RENG_EXEC_END_PTR);
 419         WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 420
 421         mmhub_v1_0_power_gating_write_save_ranges(adev);
 422
 423         /* Re-enable light sleep */
 424         pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
 425         WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
 426         pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
 427         WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
 428 }
 429
 430 void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 431                                 bool enable)
 432 {
 433         uint32_t pctl0_reng_execute = 0;
 434         uint32_t pctl1_reng_execute = 0;
 435
 436         if (amdgpu_sriov_vf(adev))
 437                 return;
 438
 439         pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
 440         pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
 441
 442         if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
 443                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 444                                                 PCTL0_RENG_EXECUTE,
 445                                                 RENG_EXECUTE_ON_PWR_UP, 1);
 446                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 447                                                 PCTL0_RENG_EXECUTE,
 448                                                 RENG_EXECUTE_ON_REG_UPDATE, 1);
 449                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
 450
 451                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 452                                                 PCTL1_RENG_EXECUTE,
 453                                                 RENG_EXECUTE_ON_PWR_UP, 1);
 454                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 455                                                 PCTL1_RENG_EXECUTE,
 456                                                 RENG_EXECUTE_ON_REG_UPDATE, 1);
 457                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 458
 459         } else {
 460                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 461                                                 PCTL0_RENG_EXECUTE,
 462                                                 RENG_EXECUTE_ON_PWR_UP, 0);
 463                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
 464                                                 PCTL0_RENG_EXECUTE,
 465                                                 RENG_EXECUTE_ON_REG_UPDATE, 0);
 466                 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
 467
 468                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 469                                                 PCTL1_RENG_EXECUTE,
 470                                                 RENG_EXECUTE_ON_PWR_UP, 0);
 471                 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
 472                                                 PCTL1_RENG_EXECUTE,
 473                                                 RENG_EXECUTE_ON_REG_UPDATE, 0);
 474                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 475         }
 476 }
 477
 478 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 479 {
 480         if (amdgpu_sriov_vf(adev)) {
 481                 /*
 482                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 483                  * VF copy registers so vbios post doesn't program them, for
 484                  * SRIOV driver need to program them
 485                  */
 486                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
 487                              adev->mc.vram_start >> 24);
 488                 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
 489                              adev->mc.vram_end >> 24);
 490         }
 491
 492         /* GART Enable. */
 493         mmhub_v1_0_init_gart_aperture_regs(adev);
 494         mmhub_v1_0_init_system_aperture_regs(adev);
 495         mmhub_v1_0_init_tlb_regs(adev);
 496         mmhub_v1_0_init_cache_regs(adev);
 497
 498         mmhub_v1_0_enable_system_domain(adev);
 499         mmhub_v1_0_disable_identity_aperture(adev);
 500         mmhub_v1_0_setup_vmid_config(adev);
 501         mmhub_v1_0_program_invalidation(adev);
 502
 503         return 0;
 504 }
 505
 506 void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
 507 {
 508         u32 tmp;
 509         u32 i;
 510
 511         /* Disable all tables */
 512         for (i = 0; i < 16; i++)
 513                 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
 514
 515         /* Setup TLB control */
 516         tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
 517         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 518         tmp = REG_SET_FIELD(tmp,
 519                                 MC_VM_MX_L1_TLB_CNTL,
 520                                 ENABLE_ADVANCED_DRIVER_MODEL,
 521                                 0);
 522         WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 523
 524         /* Setup L2 cache */
 525         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
 526         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 527         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
 528         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
 529 }
 530
 531 /**
 532  * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 533  *
 534  * @adev: amdgpu_device pointer
 535  * @value: true redirects VM faults to the default page
 536  */
 537 void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 538 {
 539         u32 tmp;
 540         tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 541         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 542                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 543         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 544                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 545         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 546                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 547         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 548                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 549         tmp = REG_SET_FIELD(tmp,
 550                         VM_L2_PROTECTION_FAULT_CNTL,
 551                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 552                         value);
 553         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 554                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 555         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 556                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 557         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 558                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 559         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 560                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 561         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 562                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 563         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 564                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 565         WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 566 }
 567
 568 void mmhub_v1_0_init(struct amdgpu_device *adev)
 569 {
 570         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
 571
 572         hub->ctx0_ptb_addr_lo32 =
 573                 SOC15_REG_OFFSET(MMHUB, 0,
 574                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 575         hub->ctx0_ptb_addr_hi32 =
 576                 SOC15_REG_OFFSET(MMHUB, 0,
 577                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 578         hub->vm_inv_eng0_req =
 579                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
 580         hub->vm_inv_eng0_ack =
 581                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
 582         hub->vm_context0_cntl =
 583                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
 584         hub->vm_l2_pro_fault_status =
 585                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 586         hub->vm_l2_pro_fault_cntl =
 587                 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 588
 589 }
 590
 591 static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 592                                                         bool enable)
 593 {
 594         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 595
 596         def  = data  = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 597
 598         if (adev->asic_type != CHIP_RAVEN) {
 599                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 600                 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
 601         } else
 602                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
 603
 604         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
 605                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 606
 607                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 608                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 609                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 610                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 611                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 612                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 613
 614                 if (adev->asic_type != CHIP_RAVEN)
 615                         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 616                                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 617                                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 618                                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 619                                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 620                                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 621         } else {
 622                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 623
 624                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 625                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 626                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 627                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 628                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 629                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 630
 631                 if (adev->asic_type != CHIP_RAVEN)
 632                         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 633                                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 634                                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 635                                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 636                                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 637                                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 638         }
 639
 640         if (def != data)
 641                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 642
 643         if (def1 != data1) {
 644                 if (adev->asic_type != CHIP_RAVEN)
 645                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 646                 else
 647                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
 648         }
 649
 650         if (adev->asic_type != CHIP_RAVEN && def2 != data2)
 651                 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
 652 }
 653
 654 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 655                                                    bool enable)
 656 {
 657         uint32_t def, data;
 658
 659         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 660
 661         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 662                 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 663         else
 664                 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 665
 666         if (def != data)
 667                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
 668 }
 669
 670 static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 671                                                        bool enable)
 672 {
 673         uint32_t def, data;
 674
 675         def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 676
 677         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 678                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 679         else
 680                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 681
 682         if (def != data)
 683                 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
 684 }
 685
 686 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 687                                                   bool enable)
 688 {
 689         uint32_t def, data;
 690
 691         def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 692
 693         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
 694             (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 695                 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 696         else
 697                 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 698
 699         if(def != data)
 700                 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
 701 }
 702
 703 int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
 704                                enum amd_clockgating_state state)
 705 {
 706         if (amdgpu_sriov_vf(adev))
 707                 return 0;
 708
 709         switch (adev->asic_type) {
 710         case CHIP_VEGA10:
 711         case CHIP_RAVEN:
 712                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
 713                                 state == AMD_CG_STATE_GATE ? true : false);
 714                 athub_update_medium_grain_clock_gating(adev,
 715                                 state == AMD_CG_STATE_GATE ? true : false);
 716                 mmhub_v1_0_update_medium_grain_light_sleep(adev,
 717                                 state == AMD_CG_STATE_GATE ? true : false);
 718                 athub_update_medium_grain_light_sleep(adev,
 719                                 state == AMD_CG_STATE_GATE ? true : false);
 720                 break;
 721         default:
 722                 break;
 723         }
 724
 725         return 0;
 726 }
 727
 728 void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 729 {
 730         int data;
 731
 732         if (amdgpu_sriov_vf(adev))
 733                 *flags = 0;
 734
 735         /* AMD_CG_SUPPORT_MC_MGCG */
 736         data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
 737         if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
 738                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 739
 740         /* AMD_CG_SUPPORT_MC_LS */
 741         data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
 742         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 743                 *flags |= AMD_CG_SUPPORT_MC_LS;
 744 }