Merge branch 'drm-fixes-5.0' of git://people.freedesktop.org/~agd5f/linux into drm...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/kernel.h>
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include "vi.h"
29 #include "vi_structs.h"
30 #include "vid.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_atombios.h"
33 #include "atombios_i2c.h"
34 #include "clearstate_vi.h"
35
36 #include "gmc/gmc_8_2_d.h"
37 #include "gmc/gmc_8_2_sh_mask.h"
38
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
41
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 #include "gca/gfx_8_0_d.h"
45 #include "gca/gfx_8_0_enum.h"
46 #include "gca/gfx_8_0_sh_mask.h"
47
48 #include "dce/dce_10_0_d.h"
49 #include "dce/dce_10_0_sh_mask.h"
50
51 #include "smu/smu_7_1_3_d.h"
52
53 #include "ivsrcid/ivsrcid_vislands30.h"
54
55 #define GFX8_NUM_GFX_RINGS     1
56 #define GFX8_MEC_HPD_SIZE 4096
57
58 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
59 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
60 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
61 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
62
63 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
64 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
65 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
66 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
67 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
68 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
69 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
70 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
71 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
72
73 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
74 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
75 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
76 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
77 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
78 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
79
80 /* BPM SERDES CMD */
81 #define SET_BPM_SERDES_CMD    1
82 #define CLE_BPM_SERDES_CMD    0
83
84 /* BPM Register Address*/
85 enum {
86         BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
87         BPM_REG_CGLS_ON,            /* ON/OFF CGLS: shall be controlled by RLC FW */
88         BPM_REG_CGCG_OVERRIDE,      /* Set/Clear CGCG Override */
89         BPM_REG_MGCG_OVERRIDE,      /* Set/Clear MGCG Override */
90         BPM_REG_FGCG_OVERRIDE,      /* Set/Clear FGCG Override */
91         BPM_REG_FGCG_MAX
92 };
93
94 #define RLC_FormatDirectRegListLength        14
95
96 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
97 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
98 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
99 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
100 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
101 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
102
103 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
104 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
105 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
106 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
107 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
108
109 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
110 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
111 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
112 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
113 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
114 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
115
116 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
117 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
118 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
119 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
120 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
121
122 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
123 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
124 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
125 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
126 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
127 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
128
129 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
130 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
131 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
132 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
133 MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
134 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
135 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
136 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
137 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
138 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
139 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
140
141 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
142 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
143 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
144 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
145 MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
146 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
147 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
148 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
149 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
150 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
151 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
152
153 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
154 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
155 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
156 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
157 MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
158 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
159 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
160 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
161 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
162 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
163 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
164
165 MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
166 MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
167 MODULE_FIRMWARE("amdgpu/vegam_me.bin");
168 MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
169 MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
170 MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
171
172 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
173 {
174         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
175         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
176         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
177         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
178         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
179         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
180         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
181         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
182         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
183         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
184         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
185         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
186         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
187         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
188         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
189         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
190 };
191
192 static const u32 golden_settings_tonga_a11[] =
193 {
194         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
195         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
196         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
197         mmGB_GPU_ID, 0x0000000f, 0x00000000,
198         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
199         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
200         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
201         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
202         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
203         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
204         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
205         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
206         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
207         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
208         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
209         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
210 };
211
212 static const u32 tonga_golden_common_all[] =
213 {
214         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
215         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
216         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
217         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
218         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
219         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
220         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
221         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
222 };
223
224 static const u32 tonga_mgcg_cgcg_init[] =
225 {
226         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
227         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
228         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
229         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
230         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
231         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
232         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
233         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
234         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
235         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
236         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
237         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
238         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
239         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
240         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
241         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
242         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
243         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
244         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
245         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
246         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
247         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
248         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
249         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
250         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
251         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
252         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
253         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
254         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
255         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
256         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
257         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
258         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
259         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
260         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
261         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
262         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
265         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
270         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
275         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
280         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
285         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
290         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
295         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
298         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
299         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
300         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
301 };
302
303 static const u32 golden_settings_vegam_a11[] =
304 {
305         mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
306         mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
307         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
308         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
309         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
310         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
311         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
312         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
313         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
314         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
315         mmSQ_CONFIG, 0x07f80000, 0x01180000,
316         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
317         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
318         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
319         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
320         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
321         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
322 };
323
324 static const u32 vegam_golden_common_all[] =
325 {
326         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
327         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
328         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
329         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
330         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
331         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
332 };
333
334 static const u32 golden_settings_polaris11_a11[] =
335 {
336         mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
337         mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
338         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
339         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
340         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
341         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
342         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
343         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
344         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
345         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
346         mmSQ_CONFIG, 0x07f80000, 0x01180000,
347         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
348         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
349         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
350         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
351         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
352         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
353 };
354
355 static const u32 polaris11_golden_common_all[] =
356 {
357         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
358         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
359         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
360         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
361         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
362         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
363 };
364
365 static const u32 golden_settings_polaris10_a11[] =
366 {
367         mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
368         mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
369         mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
370         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
371         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
372         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
373         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
374         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
375         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
376         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
377         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
378         mmSQ_CONFIG, 0x07f80000, 0x07180000,
379         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
380         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
381         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
382         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
383         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
384 };
385
386 static const u32 polaris10_golden_common_all[] =
387 {
388         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
389         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
390         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
391         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
392         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
393         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
394         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
395         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
396 };
397
398 static const u32 fiji_golden_common_all[] =
399 {
400         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
401         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
402         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
403         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
404         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
405         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
406         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
407         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
408         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
409         mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
410 };
411
412 static const u32 golden_settings_fiji_a10[] =
413 {
414         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
415         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
416         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
417         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
418         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
419         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
420         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
421         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
422         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
423         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
424         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
425 };
426
427 static const u32 fiji_mgcg_cgcg_init[] =
428 {
429         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
430         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
431         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
432         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
433         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
434         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
435         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
436         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
437         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
438         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
439         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
440         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
441         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
442         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
443         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
444         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
445         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
446         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
447         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
448         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
449         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
450         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
451         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
452         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
453         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
454         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
455         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
456         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
457         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
458         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
459         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
460         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
461         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
462         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
463         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
464 };
465
466 static const u32 golden_settings_iceland_a11[] =
467 {
468         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
469         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
470         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
471         mmGB_GPU_ID, 0x0000000f, 0x00000000,
472         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
473         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
474         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
475         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
476         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
477         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
478         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
479         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
480         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
481         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
482         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
483         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
484 };
485
486 static const u32 iceland_golden_common_all[] =
487 {
488         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
489         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
490         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
491         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
492         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
493         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
494         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
495         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
496 };
497
498 static const u32 iceland_mgcg_cgcg_init[] =
499 {
500         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
501         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
502         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
503         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
504         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
505         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
506         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
507         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
508         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
509         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
510         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
511         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
512         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
513         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
514         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
515         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
516         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
517         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
518         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
519         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
520         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
521         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
522         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
523         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
524         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
525         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
526         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
527         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
528         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
529         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
530         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
531         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
532         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
533         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
534         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
535         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
536         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
539         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
544         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
549         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
554         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
559         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
562         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
563         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
564 };
565
566 static const u32 cz_golden_settings_a11[] =
567 {
568         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
569         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
570         mmGB_GPU_ID, 0x0000000f, 0x00000000,
571         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
572         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
573         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
574         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
575         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
576         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
577         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
578         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
579         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
580 };
581
582 static const u32 cz_golden_common_all[] =
583 {
584         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
585         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
586         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
587         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
588         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
589         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
590         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
591         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
592 };
593
594 static const u32 cz_mgcg_cgcg_init[] =
595 {
596         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
597         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
598         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
599         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
600         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
601         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
602         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
603         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
604         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
605         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
606         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
607         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
608         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
609         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
610         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
611         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
612         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
613         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
614         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
615         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
616         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
617         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
618         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
619         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
620         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
621         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
622         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
623         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
624         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
625         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
626         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
627         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
628         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
629         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
630         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
631         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
632         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
635         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
640         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
645         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
650         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
655         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
660         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
665         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
668         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
669         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
670         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
671 };
672
673 static const u32 stoney_golden_settings_a11[] =
674 {
675         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
676         mmGB_GPU_ID, 0x0000000f, 0x00000000,
677         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
678         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
679         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
680         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
681         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
682         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
683         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
684         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
685 };
686
687 static const u32 stoney_golden_common_all[] =
688 {
689         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
690         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
691         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
692         mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
693         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
694         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
695         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
696         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
697 };
698
699 static const u32 stoney_mgcg_cgcg_init[] =
700 {
701         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
702         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
703         mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
704         mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
705         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
706 };
707
708
709 static const char * const sq_edc_source_names[] = {
710         "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
711         "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
712         "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
713         "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
714         "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
715         "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
716         "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
717 };
718
719 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
720 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
721 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
722 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
723 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
724 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
725 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
726 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
727
728 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
729 {
730         switch (adev->asic_type) {
731         case CHIP_TOPAZ:
732                 amdgpu_device_program_register_sequence(adev,
733                                                         iceland_mgcg_cgcg_init,
734                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
735                 amdgpu_device_program_register_sequence(adev,
736                                                         golden_settings_iceland_a11,
737                                                         ARRAY_SIZE(golden_settings_iceland_a11));
738                 amdgpu_device_program_register_sequence(adev,
739                                                         iceland_golden_common_all,
740                                                         ARRAY_SIZE(iceland_golden_common_all));
741                 break;
742         case CHIP_FIJI:
743                 amdgpu_device_program_register_sequence(adev,
744                                                         fiji_mgcg_cgcg_init,
745                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
746                 amdgpu_device_program_register_sequence(adev,
747                                                         golden_settings_fiji_a10,
748                                                         ARRAY_SIZE(golden_settings_fiji_a10));
749                 amdgpu_device_program_register_sequence(adev,
750                                                         fiji_golden_common_all,
751                                                         ARRAY_SIZE(fiji_golden_common_all));
752                 break;
753
754         case CHIP_TONGA:
755                 amdgpu_device_program_register_sequence(adev,
756                                                         tonga_mgcg_cgcg_init,
757                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
758                 amdgpu_device_program_register_sequence(adev,
759                                                         golden_settings_tonga_a11,
760                                                         ARRAY_SIZE(golden_settings_tonga_a11));
761                 amdgpu_device_program_register_sequence(adev,
762                                                         tonga_golden_common_all,
763                                                         ARRAY_SIZE(tonga_golden_common_all));
764                 break;
765         case CHIP_VEGAM:
766                 amdgpu_device_program_register_sequence(adev,
767                                                         golden_settings_vegam_a11,
768                                                         ARRAY_SIZE(golden_settings_vegam_a11));
769                 amdgpu_device_program_register_sequence(adev,
770                                                         vegam_golden_common_all,
771                                                         ARRAY_SIZE(vegam_golden_common_all));
772                 break;
773         case CHIP_POLARIS11:
774         case CHIP_POLARIS12:
775                 amdgpu_device_program_register_sequence(adev,
776                                                         golden_settings_polaris11_a11,
777                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
778                 amdgpu_device_program_register_sequence(adev,
779                                                         polaris11_golden_common_all,
780                                                         ARRAY_SIZE(polaris11_golden_common_all));
781                 break;
782         case CHIP_POLARIS10:
783                 amdgpu_device_program_register_sequence(adev,
784                                                         golden_settings_polaris10_a11,
785                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
786                 amdgpu_device_program_register_sequence(adev,
787                                                         polaris10_golden_common_all,
788                                                         ARRAY_SIZE(polaris10_golden_common_all));
789                 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
790                 if (adev->pdev->revision == 0xc7 &&
791                     ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
792                      (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
793                      (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
794                         amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
795                         amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
796                 }
797                 break;
798         case CHIP_CARRIZO:
799                 amdgpu_device_program_register_sequence(adev,
800                                                         cz_mgcg_cgcg_init,
801                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
802                 amdgpu_device_program_register_sequence(adev,
803                                                         cz_golden_settings_a11,
804                                                         ARRAY_SIZE(cz_golden_settings_a11));
805                 amdgpu_device_program_register_sequence(adev,
806                                                         cz_golden_common_all,
807                                                         ARRAY_SIZE(cz_golden_common_all));
808                 break;
809         case CHIP_STONEY:
810                 amdgpu_device_program_register_sequence(adev,
811                                                         stoney_mgcg_cgcg_init,
812                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
813                 amdgpu_device_program_register_sequence(adev,
814                                                         stoney_golden_settings_a11,
815                                                         ARRAY_SIZE(stoney_golden_settings_a11));
816                 amdgpu_device_program_register_sequence(adev,
817                                                         stoney_golden_common_all,
818                                                         ARRAY_SIZE(stoney_golden_common_all));
819                 break;
820         default:
821                 break;
822         }
823 }
824
825 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
826 {
827         adev->gfx.scratch.num_reg = 8;
828         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
829         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
830 }
831
832 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
833 {
834         struct amdgpu_device *adev = ring->adev;
835         uint32_t scratch;
836         uint32_t tmp = 0;
837         unsigned i;
838         int r;
839
840         r = amdgpu_gfx_scratch_get(adev, &scratch);
841         if (r)
842                 return r;
843
844         WREG32(scratch, 0xCAFEDEAD);
845         r = amdgpu_ring_alloc(ring, 3);
846         if (r)
847                 goto error_free_scratch;
848
849         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
850         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
851         amdgpu_ring_write(ring, 0xDEADBEEF);
852         amdgpu_ring_commit(ring);
853
854         for (i = 0; i < adev->usec_timeout; i++) {
855                 tmp = RREG32(scratch);
856                 if (tmp == 0xDEADBEEF)
857                         break;
858                 DRM_UDELAY(1);
859         }
860
861         if (i >= adev->usec_timeout)
862                 r = -ETIMEDOUT;
863
864 error_free_scratch:
865         amdgpu_gfx_scratch_free(adev, scratch);
866         return r;
867 }
868
869 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
870 {
871         struct amdgpu_device *adev = ring->adev;
872         struct amdgpu_ib ib;
873         struct dma_fence *f = NULL;
874
875         unsigned int index;
876         uint64_t gpu_addr;
877         uint32_t tmp;
878         long r;
879
880         r = amdgpu_device_wb_get(adev, &index);
881         if (r)
882                 return r;
883
884         gpu_addr = adev->wb.gpu_addr + (index * 4);
885         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
886         memset(&ib, 0, sizeof(ib));
887         r = amdgpu_ib_get(adev, NULL, 16, &ib);
888         if (r)
889                 goto err1;
890
891         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
892         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
893         ib.ptr[2] = lower_32_bits(gpu_addr);
894         ib.ptr[3] = upper_32_bits(gpu_addr);
895         ib.ptr[4] = 0xDEADBEEF;
896         ib.length_dw = 5;
897
898         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
899         if (r)
900                 goto err2;
901
902         r = dma_fence_wait_timeout(f, false, timeout);
903         if (r == 0) {
904                 r = -ETIMEDOUT;
905                 goto err2;
906         } else if (r < 0) {
907                 goto err2;
908         }
909
910         tmp = adev->wb.wb[index];
911         if (tmp == 0xDEADBEEF)
912                 r = 0;
913         else
914                 r = -EINVAL;
915
916 err2:
917         amdgpu_ib_free(adev, &ib, NULL);
918         dma_fence_put(f);
919 err1:
920         amdgpu_device_wb_free(adev, index);
921         return r;
922 }
923
924
925 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
926 {
927         release_firmware(adev->gfx.pfp_fw);
928         adev->gfx.pfp_fw = NULL;
929         release_firmware(adev->gfx.me_fw);
930         adev->gfx.me_fw = NULL;
931         release_firmware(adev->gfx.ce_fw);
932         adev->gfx.ce_fw = NULL;
933         release_firmware(adev->gfx.rlc_fw);
934         adev->gfx.rlc_fw = NULL;
935         release_firmware(adev->gfx.mec_fw);
936         adev->gfx.mec_fw = NULL;
937         if ((adev->asic_type != CHIP_STONEY) &&
938             (adev->asic_type != CHIP_TOPAZ))
939                 release_firmware(adev->gfx.mec2_fw);
940         adev->gfx.mec2_fw = NULL;
941
942         kfree(adev->gfx.rlc.register_list_format);
943 }
944
945 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
946 {
947         const char *chip_name;
948         char fw_name[30];
949         int err;
950         struct amdgpu_firmware_info *info = NULL;
951         const struct common_firmware_header *header = NULL;
952         const struct gfx_firmware_header_v1_0 *cp_hdr;
953         const struct rlc_firmware_header_v2_0 *rlc_hdr;
954         unsigned int *tmp = NULL, i;
955
956         DRM_DEBUG("\n");
957
958         switch (adev->asic_type) {
959         case CHIP_TOPAZ:
960                 chip_name = "topaz";
961                 break;
962         case CHIP_TONGA:
963                 chip_name = "tonga";
964                 break;
965         case CHIP_CARRIZO:
966                 chip_name = "carrizo";
967                 break;
968         case CHIP_FIJI:
969                 chip_name = "fiji";
970                 break;
971         case CHIP_STONEY:
972                 chip_name = "stoney";
973                 break;
974         case CHIP_POLARIS10:
975                 chip_name = "polaris10";
976                 break;
977         case CHIP_POLARIS11:
978                 chip_name = "polaris11";
979                 break;
980         case CHIP_POLARIS12:
981                 chip_name = "polaris12";
982                 break;
983         case CHIP_VEGAM:
984                 chip_name = "vegam";
985                 break;
986         default:
987                 BUG();
988         }
989
990         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
991                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
992                 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
993                 if (err == -ENOENT) {
994                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
995                         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
996                 }
997         } else {
998                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
999                 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1000         }
1001         if (err)
1002                 goto out;
1003         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1004         if (err)
1005                 goto out;
1006         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1007         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1008         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1009
1010         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1011                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1012                 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1013                 if (err == -ENOENT) {
1014                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1015                         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1016                 }
1017         } else {
1018                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1019                 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1020         }
1021         if (err)
1022                 goto out;
1023         err = amdgpu_ucode_validate(adev->gfx.me_fw);
1024         if (err)
1025                 goto out;
1026         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1027         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1028
1029         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1030
1031         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1032                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1033                 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1034                 if (err == -ENOENT) {
1035                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1036                         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1037                 }
1038         } else {
1039                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1040                 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1041         }
1042         if (err)
1043                 goto out;
1044         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1045         if (err)
1046                 goto out;
1047         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1048         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1049         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1050
1051         /*
1052          * Support for MCBP/Virtualization in combination with chained IBs is
1053          * formal released on feature version #46
1054          */
1055         if (adev->gfx.ce_feature_version >= 46 &&
1056             adev->gfx.pfp_feature_version >= 46) {
1057                 adev->virt.chained_ib_support = true;
1058                 DRM_INFO("Chained IB support enabled!\n");
1059         } else
1060                 adev->virt.chained_ib_support = false;
1061
1062         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1063         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1064         if (err)
1065                 goto out;
1066         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1067         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1068         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1069         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1070
1071         adev->gfx.rlc.save_and_restore_offset =
1072                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
1073         adev->gfx.rlc.clear_state_descriptor_offset =
1074                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1075         adev->gfx.rlc.avail_scratch_ram_locations =
1076                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1077         adev->gfx.rlc.reg_restore_list_size =
1078                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
1079         adev->gfx.rlc.reg_list_format_start =
1080                         le32_to_cpu(rlc_hdr->reg_list_format_start);
1081         adev->gfx.rlc.reg_list_format_separate_start =
1082                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1083         adev->gfx.rlc.starting_offsets_start =
1084                         le32_to_cpu(rlc_hdr->starting_offsets_start);
1085         adev->gfx.rlc.reg_list_format_size_bytes =
1086                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1087         adev->gfx.rlc.reg_list_size_bytes =
1088                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1089
1090         adev->gfx.rlc.register_list_format =
1091                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1092                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1093
1094         if (!adev->gfx.rlc.register_list_format) {
1095                 err = -ENOMEM;
1096                 goto out;
1097         }
1098
1099         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1100                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1101         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1102                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1103
1104         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1105
1106         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1107                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1108         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1109                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1110
1111         if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1112                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1113                 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1114                 if (err == -ENOENT) {
1115                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1116                         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1117                 }
1118         } else {
1119                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1120                 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1121         }
1122         if (err)
1123                 goto out;
1124         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1125         if (err)
1126                 goto out;
1127         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1128         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1129         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1130
1131         if ((adev->asic_type != CHIP_STONEY) &&
1132             (adev->asic_type != CHIP_TOPAZ)) {
1133                 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1134                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1135                         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1136                         if (err == -ENOENT) {
1137                                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1138                                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1139                         }
1140                 } else {
1141                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1142                         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1143                 }
1144                 if (!err) {
1145                         err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1146                         if (err)
1147                                 goto out;
1148                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1149                                 adev->gfx.mec2_fw->data;
1150                         adev->gfx.mec2_fw_version =
1151                                 le32_to_cpu(cp_hdr->header.ucode_version);
1152                         adev->gfx.mec2_feature_version =
1153                                 le32_to_cpu(cp_hdr->ucode_feature_version);
1154                 } else {
1155                         err = 0;
1156                         adev->gfx.mec2_fw = NULL;
1157                 }
1158         }
1159
1160         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1161         info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1162         info->fw = adev->gfx.pfp_fw;
1163         header = (const struct common_firmware_header *)info->fw->data;
1164         adev->firmware.fw_size +=
1165                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1166
1167         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1168         info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1169         info->fw = adev->gfx.me_fw;
1170         header = (const struct common_firmware_header *)info->fw->data;
1171         adev->firmware.fw_size +=
1172                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1173
1174         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1175         info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1176         info->fw = adev->gfx.ce_fw;
1177         header = (const struct common_firmware_header *)info->fw->data;
1178         adev->firmware.fw_size +=
1179                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1180
1181         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1182         info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1183         info->fw = adev->gfx.rlc_fw;
1184         header = (const struct common_firmware_header *)info->fw->data;
1185         adev->firmware.fw_size +=
1186                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1187
1188         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1189         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1190         info->fw = adev->gfx.mec_fw;
1191         header = (const struct common_firmware_header *)info->fw->data;
1192         adev->firmware.fw_size +=
1193                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1194
1195         /* we need account JT in */
1196         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1197         adev->firmware.fw_size +=
1198                 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1199
1200         if (amdgpu_sriov_vf(adev)) {
1201                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1202                 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1203                 info->fw = adev->gfx.mec_fw;
1204                 adev->firmware.fw_size +=
1205                         ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1206         }
1207
1208         if (adev->gfx.mec2_fw) {
1209                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1210                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1211                 info->fw = adev->gfx.mec2_fw;
1212                 header = (const struct common_firmware_header *)info->fw->data;
1213                 adev->firmware.fw_size +=
1214                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1215         }
1216
1217 out:
1218         if (err) {
1219                 dev_err(adev->dev,
1220                         "gfx8: Failed to load firmware \"%s\"\n",
1221                         fw_name);
1222                 release_firmware(adev->gfx.pfp_fw);
1223                 adev->gfx.pfp_fw = NULL;
1224                 release_firmware(adev->gfx.me_fw);
1225                 adev->gfx.me_fw = NULL;
1226                 release_firmware(adev->gfx.ce_fw);
1227                 adev->gfx.ce_fw = NULL;
1228                 release_firmware(adev->gfx.rlc_fw);
1229                 adev->gfx.rlc_fw = NULL;
1230                 release_firmware(adev->gfx.mec_fw);
1231                 adev->gfx.mec_fw = NULL;
1232                 release_firmware(adev->gfx.mec2_fw);
1233                 adev->gfx.mec2_fw = NULL;
1234         }
1235         return err;
1236 }
1237
1238 static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1239                                     volatile u32 *buffer)
1240 {
1241         u32 count = 0, i;
1242         const struct cs_section_def *sect = NULL;
1243         const struct cs_extent_def *ext = NULL;
1244
1245         if (adev->gfx.rlc.cs_data == NULL)
1246                 return;
1247         if (buffer == NULL)
1248                 return;
1249
1250         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1251         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1252
1253         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1254         buffer[count++] = cpu_to_le32(0x80000000);
1255         buffer[count++] = cpu_to_le32(0x80000000);
1256
1257         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1258                 for (ext = sect->section; ext->extent != NULL; ++ext) {
1259                         if (sect->id == SECT_CONTEXT) {
1260                                 buffer[count++] =
1261                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1262                                 buffer[count++] = cpu_to_le32(ext->reg_index -
1263                                                 PACKET3_SET_CONTEXT_REG_START);
1264                                 for (i = 0; i < ext->reg_count; i++)
1265                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
1266                         } else {
1267                                 return;
1268                         }
1269                 }
1270         }
1271
1272         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1273         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1274                         PACKET3_SET_CONTEXT_REG_START);
1275         buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1276         buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1277
1278         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1279         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1280
1281         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1282         buffer[count++] = cpu_to_le32(0);
1283 }
1284
1285 static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1286 {
1287         if (adev->asic_type == CHIP_CARRIZO)
1288                 return 5;
1289         else
1290                 return 4;
1291 }
1292
1293 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1294 {
1295         const struct cs_section_def *cs_data;
1296         int r;
1297
1298         adev->gfx.rlc.cs_data = vi_cs_data;
1299
1300         cs_data = adev->gfx.rlc.cs_data;
1301
1302         if (cs_data) {
1303                 /* init clear state block */
1304                 r = amdgpu_gfx_rlc_init_csb(adev);
1305                 if (r)
1306                         return r;
1307         }
1308
1309         if ((adev->asic_type == CHIP_CARRIZO) ||
1310             (adev->asic_type == CHIP_STONEY)) {
1311                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1312                 r = amdgpu_gfx_rlc_init_cpt(adev);
1313                 if (r)
1314                         return r;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1321 {
1322         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1323 }
1324
1325 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1326 {
1327         int r;
1328         u32 *hpd;
1329         size_t mec_hpd_size;
1330
1331         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1332
1333         /* take ownership of the relevant compute queues */
1334         amdgpu_gfx_compute_queue_acquire(adev);
1335
1336         mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1337
1338         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1339                                       AMDGPU_GEM_DOMAIN_VRAM,
1340                                       &adev->gfx.mec.hpd_eop_obj,
1341                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1342                                       (void **)&hpd);
1343         if (r) {
1344                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1345                 return r;
1346         }
1347
1348         memset(hpd, 0, mec_hpd_size);
1349
1350         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1351         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1352
1353         return 0;
1354 }
1355
1356 static const u32 vgpr_init_compute_shader[] =
1357 {
1358         0x7e000209, 0x7e020208,
1359         0x7e040207, 0x7e060206,
1360         0x7e080205, 0x7e0a0204,
1361         0x7e0c0203, 0x7e0e0202,
1362         0x7e100201, 0x7e120200,
1363         0x7e140209, 0x7e160208,
1364         0x7e180207, 0x7e1a0206,
1365         0x7e1c0205, 0x7e1e0204,
1366         0x7e200203, 0x7e220202,
1367         0x7e240201, 0x7e260200,
1368         0x7e280209, 0x7e2a0208,
1369         0x7e2c0207, 0x7e2e0206,
1370         0x7e300205, 0x7e320204,
1371         0x7e340203, 0x7e360202,
1372         0x7e380201, 0x7e3a0200,
1373         0x7e3c0209, 0x7e3e0208,
1374         0x7e400207, 0x7e420206,
1375         0x7e440205, 0x7e460204,
1376         0x7e480203, 0x7e4a0202,
1377         0x7e4c0201, 0x7e4e0200,
1378         0x7e500209, 0x7e520208,
1379         0x7e540207, 0x7e560206,
1380         0x7e580205, 0x7e5a0204,
1381         0x7e5c0203, 0x7e5e0202,
1382         0x7e600201, 0x7e620200,
1383         0x7e640209, 0x7e660208,
1384         0x7e680207, 0x7e6a0206,
1385         0x7e6c0205, 0x7e6e0204,
1386         0x7e700203, 0x7e720202,
1387         0x7e740201, 0x7e760200,
1388         0x7e780209, 0x7e7a0208,
1389         0x7e7c0207, 0x7e7e0206,
1390         0xbf8a0000, 0xbf810000,
1391 };
1392
1393 static const u32 sgpr_init_compute_shader[] =
1394 {
1395         0xbe8a0100, 0xbe8c0102,
1396         0xbe8e0104, 0xbe900106,
1397         0xbe920108, 0xbe940100,
1398         0xbe960102, 0xbe980104,
1399         0xbe9a0106, 0xbe9c0108,
1400         0xbe9e0100, 0xbea00102,
1401         0xbea20104, 0xbea40106,
1402         0xbea60108, 0xbea80100,
1403         0xbeaa0102, 0xbeac0104,
1404         0xbeae0106, 0xbeb00108,
1405         0xbeb20100, 0xbeb40102,
1406         0xbeb60104, 0xbeb80106,
1407         0xbeba0108, 0xbebc0100,
1408         0xbebe0102, 0xbec00104,
1409         0xbec20106, 0xbec40108,
1410         0xbec60100, 0xbec80102,
1411         0xbee60004, 0xbee70005,
1412         0xbeea0006, 0xbeeb0007,
1413         0xbee80008, 0xbee90009,
1414         0xbefc0000, 0xbf8a0000,
1415         0xbf810000, 0x00000000,
1416 };
1417
1418 static const u32 vgpr_init_regs[] =
1419 {
1420         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1421         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1422         mmCOMPUTE_NUM_THREAD_X, 256*4,
1423         mmCOMPUTE_NUM_THREAD_Y, 1,
1424         mmCOMPUTE_NUM_THREAD_Z, 1,
1425         mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1426         mmCOMPUTE_PGM_RSRC2, 20,
1427         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1428         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1429         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1430         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1431         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1432         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1433         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1434         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1435         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1436         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1437 };
1438
1439 static const u32 sgpr1_init_regs[] =
1440 {
1441         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1442         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1443         mmCOMPUTE_NUM_THREAD_X, 256*5,
1444         mmCOMPUTE_NUM_THREAD_Y, 1,
1445         mmCOMPUTE_NUM_THREAD_Z, 1,
1446         mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1447         mmCOMPUTE_PGM_RSRC2, 20,
1448         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1449         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1450         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1451         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1452         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1453         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1454         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1455         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1456         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1457         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1458 };
1459
1460 static const u32 sgpr2_init_regs[] =
1461 {
1462         mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1463         mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1464         mmCOMPUTE_NUM_THREAD_X, 256*5,
1465         mmCOMPUTE_NUM_THREAD_Y, 1,
1466         mmCOMPUTE_NUM_THREAD_Z, 1,
1467         mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1468         mmCOMPUTE_PGM_RSRC2, 20,
1469         mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1470         mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1471         mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1472         mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1473         mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1474         mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1475         mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1476         mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1477         mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1478         mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1479 };
1480
1481 static const u32 sec_ded_counter_registers[] =
1482 {
1483         mmCPC_EDC_ATC_CNT,
1484         mmCPC_EDC_SCRATCH_CNT,
1485         mmCPC_EDC_UCODE_CNT,
1486         mmCPF_EDC_ATC_CNT,
1487         mmCPF_EDC_ROQ_CNT,
1488         mmCPF_EDC_TAG_CNT,
1489         mmCPG_EDC_ATC_CNT,
1490         mmCPG_EDC_DMA_CNT,
1491         mmCPG_EDC_TAG_CNT,
1492         mmDC_EDC_CSINVOC_CNT,
1493         mmDC_EDC_RESTORE_CNT,
1494         mmDC_EDC_STATE_CNT,
1495         mmGDS_EDC_CNT,
1496         mmGDS_EDC_GRBM_CNT,
1497         mmGDS_EDC_OA_DED,
1498         mmSPI_EDC_CNT,
1499         mmSQC_ATC_EDC_GATCL1_CNT,
1500         mmSQC_EDC_CNT,
1501         mmSQ_EDC_DED_CNT,
1502         mmSQ_EDC_INFO,
1503         mmSQ_EDC_SEC_CNT,
1504         mmTCC_EDC_CNT,
1505         mmTCP_ATC_EDC_GATCL1_CNT,
1506         mmTCP_EDC_CNT,
1507         mmTD_EDC_CNT
1508 };
1509
1510 static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1511 {
1512         struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1513         struct amdgpu_ib ib;
1514         struct dma_fence *f = NULL;
1515         int r, i;
1516         u32 tmp;
1517         unsigned total_size, vgpr_offset, sgpr_offset;
1518         u64 gpu_addr;
1519
1520         /* only supported on CZ */
1521         if (adev->asic_type != CHIP_CARRIZO)
1522                 return 0;
1523
1524         /* bail if the compute ring is not ready */
1525         if (!ring->sched.ready)
1526                 return 0;
1527
1528         tmp = RREG32(mmGB_EDC_MODE);
1529         WREG32(mmGB_EDC_MODE, 0);
1530
1531         total_size =
1532                 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1533         total_size +=
1534                 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1535         total_size +=
1536                 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1537         total_size = ALIGN(total_size, 256);
1538         vgpr_offset = total_size;
1539         total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1540         sgpr_offset = total_size;
1541         total_size += sizeof(sgpr_init_compute_shader);
1542
1543         /* allocate an indirect buffer to put the commands in */
1544         memset(&ib, 0, sizeof(ib));
1545         r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1546         if (r) {
1547                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1548                 return r;
1549         }
1550
1551         /* load the compute shaders */
1552         for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1553                 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1554
1555         for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1556                 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1557
1558         /* init the ib length to 0 */
1559         ib.length_dw = 0;
1560
1561         /* VGPR */
1562         /* write the register state for the compute dispatch */
1563         for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1564                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1565                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1566                 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1567         }
1568         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1569         gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1570         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1571         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1572         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1573         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1574
1575         /* write dispatch packet */
1576         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1577         ib.ptr[ib.length_dw++] = 8; /* x */
1578         ib.ptr[ib.length_dw++] = 1; /* y */
1579         ib.ptr[ib.length_dw++] = 1; /* z */
1580         ib.ptr[ib.length_dw++] =
1581                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1582
1583         /* write CS partial flush packet */
1584         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1585         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1586
1587         /* SGPR1 */
1588         /* write the register state for the compute dispatch */
1589         for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1590                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1591                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1592                 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1593         }
1594         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1595         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1596         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1597         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1598         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1599         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1600
1601         /* write dispatch packet */
1602         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1603         ib.ptr[ib.length_dw++] = 8; /* x */
1604         ib.ptr[ib.length_dw++] = 1; /* y */
1605         ib.ptr[ib.length_dw++] = 1; /* z */
1606         ib.ptr[ib.length_dw++] =
1607                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1608
1609         /* write CS partial flush packet */
1610         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1611         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1612
1613         /* SGPR2 */
1614         /* write the register state for the compute dispatch */
1615         for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1616                 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1617                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1618                 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1619         }
1620         /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1621         gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1622         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1623         ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1624         ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1625         ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1626
1627         /* write dispatch packet */
1628         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1629         ib.ptr[ib.length_dw++] = 8; /* x */
1630         ib.ptr[ib.length_dw++] = 1; /* y */
1631         ib.ptr[ib.length_dw++] = 1; /* z */
1632         ib.ptr[ib.length_dw++] =
1633                 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1634
1635         /* write CS partial flush packet */
1636         ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1637         ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1638
1639         /* shedule the ib on the ring */
1640         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1641         if (r) {
1642                 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1643                 goto fail;
1644         }
1645
1646         /* wait for the GPU to finish processing the IB */
1647         r = dma_fence_wait(f, false);
1648         if (r) {
1649                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1650                 goto fail;
1651         }
1652
1653         tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1654         tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1655         WREG32(mmGB_EDC_MODE, tmp);
1656
1657         tmp = RREG32(mmCC_GC_EDC_CONFIG);
1658         tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1659         WREG32(mmCC_GC_EDC_CONFIG, tmp);
1660
1661
1662         /* read back registers to clear the counters */
1663         for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1664                 RREG32(sec_ded_counter_registers[i]);
1665
1666 fail:
1667         amdgpu_ib_free(adev, &ib, NULL);
1668         dma_fence_put(f);
1669
1670         return r;
1671 }
1672
1673 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1674 {
1675         u32 gb_addr_config;
1676         u32 mc_shared_chmap, mc_arb_ramcfg;
1677         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1678         u32 tmp;
1679         int ret;
1680
1681         switch (adev->asic_type) {
1682         case CHIP_TOPAZ:
1683                 adev->gfx.config.max_shader_engines = 1;
1684                 adev->gfx.config.max_tile_pipes = 2;
1685                 adev->gfx.config.max_cu_per_sh = 6;
1686                 adev->gfx.config.max_sh_per_se = 1;
1687                 adev->gfx.config.max_backends_per_se = 2;
1688                 adev->gfx.config.max_texture_channel_caches = 2;
1689                 adev->gfx.config.max_gprs = 256;
1690                 adev->gfx.config.max_gs_threads = 32;
1691                 adev->gfx.config.max_hw_contexts = 8;
1692
1693                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1694                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1695                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1696                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1697                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1698                 break;
1699         case CHIP_FIJI:
1700                 adev->gfx.config.max_shader_engines = 4;
1701                 adev->gfx.config.max_tile_pipes = 16;
1702                 adev->gfx.config.max_cu_per_sh = 16;
1703                 adev->gfx.config.max_sh_per_se = 1;
1704                 adev->gfx.config.max_backends_per_se = 4;
1705                 adev->gfx.config.max_texture_channel_caches = 16;
1706                 adev->gfx.config.max_gprs = 256;
1707                 adev->gfx.config.max_gs_threads = 32;
1708                 adev->gfx.config.max_hw_contexts = 8;
1709
1710                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1711                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1712                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1713                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1714                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1715                 break;
1716         case CHIP_POLARIS11:
1717         case CHIP_POLARIS12:
1718                 ret = amdgpu_atombios_get_gfx_info(adev);
1719                 if (ret)
1720                         return ret;
1721                 adev->gfx.config.max_gprs = 256;
1722                 adev->gfx.config.max_gs_threads = 32;
1723                 adev->gfx.config.max_hw_contexts = 8;
1724
1725                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1726                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1727                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1728                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1729                 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1730                 break;
1731         case CHIP_POLARIS10:
1732         case CHIP_VEGAM:
1733                 ret = amdgpu_atombios_get_gfx_info(adev);
1734                 if (ret)
1735                         return ret;
1736                 adev->gfx.config.max_gprs = 256;
1737                 adev->gfx.config.max_gs_threads = 32;
1738                 adev->gfx.config.max_hw_contexts = 8;
1739
1740                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1741                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1742                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1743                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1744                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1745                 break;
1746         case CHIP_TONGA:
1747                 adev->gfx.config.max_shader_engines = 4;
1748                 adev->gfx.config.max_tile_pipes = 8;
1749                 adev->gfx.config.max_cu_per_sh = 8;
1750                 adev->gfx.config.max_sh_per_se = 1;
1751                 adev->gfx.config.max_backends_per_se = 2;
1752                 adev->gfx.config.max_texture_channel_caches = 8;
1753                 adev->gfx.config.max_gprs = 256;
1754                 adev->gfx.config.max_gs_threads = 32;
1755                 adev->gfx.config.max_hw_contexts = 8;
1756
1757                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1758                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1759                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1760                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1761                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1762                 break;
1763         case CHIP_CARRIZO:
1764                 adev->gfx.config.max_shader_engines = 1;
1765                 adev->gfx.config.max_tile_pipes = 2;
1766                 adev->gfx.config.max_sh_per_se = 1;
1767                 adev->gfx.config.max_backends_per_se = 2;
1768                 adev->gfx.config.max_cu_per_sh = 8;
1769                 adev->gfx.config.max_texture_channel_caches = 2;
1770                 adev->gfx.config.max_gprs = 256;
1771                 adev->gfx.config.max_gs_threads = 32;
1772                 adev->gfx.config.max_hw_contexts = 8;
1773
1774                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1775                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1776                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1777                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1778                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1779                 break;
1780         case CHIP_STONEY:
1781                 adev->gfx.config.max_shader_engines = 1;
1782                 adev->gfx.config.max_tile_pipes = 2;
1783                 adev->gfx.config.max_sh_per_se = 1;
1784                 adev->gfx.config.max_backends_per_se = 1;
1785                 adev->gfx.config.max_cu_per_sh = 3;
1786                 adev->gfx.config.max_texture_channel_caches = 2;
1787                 adev->gfx.config.max_gprs = 256;
1788                 adev->gfx.config.max_gs_threads = 16;
1789                 adev->gfx.config.max_hw_contexts = 8;
1790
1791                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1792                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1793                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1794                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1795                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1796                 break;
1797         default:
1798                 adev->gfx.config.max_shader_engines = 2;
1799                 adev->gfx.config.max_tile_pipes = 4;
1800                 adev->gfx.config.max_cu_per_sh = 2;
1801                 adev->gfx.config.max_sh_per_se = 1;
1802                 adev->gfx.config.max_backends_per_se = 2;
1803                 adev->gfx.config.max_texture_channel_caches = 4;
1804                 adev->gfx.config.max_gprs = 256;
1805                 adev->gfx.config.max_gs_threads = 32;
1806                 adev->gfx.config.max_hw_contexts = 8;
1807
1808                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1809                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1810                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1811                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1812                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1813                 break;
1814         }
1815
1816         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1817         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1818         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1819
1820         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1821         adev->gfx.config.mem_max_burst_length_bytes = 256;
1822         if (adev->flags & AMD_IS_APU) {
1823                 /* Get memory bank mapping mode. */
1824                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1825                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1826                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1827
1828                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1829                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1830                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1831
1832                 /* Validate settings in case only one DIMM installed. */
1833                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1834                         dimm00_addr_map = 0;
1835                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1836                         dimm01_addr_map = 0;
1837                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1838                         dimm10_addr_map = 0;
1839                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1840                         dimm11_addr_map = 0;
1841
1842                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1843                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1844                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1845                         adev->gfx.config.mem_row_size_in_kb = 2;
1846                 else
1847                         adev->gfx.config.mem_row_size_in_kb = 1;
1848         } else {
1849                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1850                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1851                 if (adev->gfx.config.mem_row_size_in_kb > 4)
1852                         adev->gfx.config.mem_row_size_in_kb = 4;
1853         }
1854
1855         adev->gfx.config.shader_engine_tile_size = 32;
1856         adev->gfx.config.num_gpus = 1;
1857         adev->gfx.config.multi_gpu_tile_size = 64;
1858
1859         /* fix up row size */
1860         switch (adev->gfx.config.mem_row_size_in_kb) {
1861         case 1:
1862         default:
1863                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1864                 break;
1865         case 2:
1866                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1867                 break;
1868         case 4:
1869                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1870                 break;
1871         }
1872         adev->gfx.config.gb_addr_config = gb_addr_config;
1873
1874         return 0;
1875 }
1876
1877 static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1878                                         int mec, int pipe, int queue)
1879 {
1880         int r;
1881         unsigned irq_type;
1882         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1883
1884         ring = &adev->gfx.compute_ring[ring_id];
1885
1886         /* mec0 is me1 */
1887         ring->me = mec + 1;
1888         ring->pipe = pipe;
1889         ring->queue = queue;
1890
1891         ring->ring_obj = NULL;
1892         ring->use_doorbell = true;
1893         ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1894         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1895                                 + (ring_id * GFX8_MEC_HPD_SIZE);
1896         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1897
1898         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1899                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1900                 + ring->pipe;
1901
1902         /* type-2 packets are deprecated on MEC, use type-3 instead */
1903         r = amdgpu_ring_init(adev, ring, 1024,
1904                         &adev->gfx.eop_irq, irq_type);
1905         if (r)
1906                 return r;
1907
1908
1909         return 0;
1910 }
1911
1912 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1913
1914 static int gfx_v8_0_sw_init(void *handle)
1915 {
1916         int i, j, k, r, ring_id;
1917         struct amdgpu_ring *ring;
1918         struct amdgpu_kiq *kiq;
1919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1920
1921         switch (adev->asic_type) {
1922         case CHIP_TONGA:
1923         case CHIP_CARRIZO:
1924         case CHIP_FIJI:
1925         case CHIP_POLARIS10:
1926         case CHIP_POLARIS11:
1927         case CHIP_POLARIS12:
1928         case CHIP_VEGAM:
1929                 adev->gfx.mec.num_mec = 2;
1930                 break;
1931         case CHIP_TOPAZ:
1932         case CHIP_STONEY:
1933         default:
1934                 adev->gfx.mec.num_mec = 1;
1935                 break;
1936         }
1937
1938         adev->gfx.mec.num_pipe_per_mec = 4;
1939         adev->gfx.mec.num_queue_per_pipe = 8;
1940
1941         /* EOP Event */
1942         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1943         if (r)
1944                 return r;
1945
1946         /* Privileged reg */
1947         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1948                               &adev->gfx.priv_reg_irq);
1949         if (r)
1950                 return r;
1951
1952         /* Privileged inst */
1953         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1954                               &adev->gfx.priv_inst_irq);
1955         if (r)
1956                 return r;
1957
1958         /* Add CP EDC/ECC irq  */
1959         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1960                               &adev->gfx.cp_ecc_error_irq);
1961         if (r)
1962                 return r;
1963
1964         /* SQ interrupts. */
1965         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1966                               &adev->gfx.sq_irq);
1967         if (r) {
1968                 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1969                 return r;
1970         }
1971
1972         INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
1973
1974         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1975
1976         gfx_v8_0_scratch_init(adev);
1977
1978         r = gfx_v8_0_init_microcode(adev);
1979         if (r) {
1980                 DRM_ERROR("Failed to load gfx firmware!\n");
1981                 return r;
1982         }
1983
1984         r = adev->gfx.rlc.funcs->init(adev);
1985         if (r) {
1986                 DRM_ERROR("Failed to init rlc BOs!\n");
1987                 return r;
1988         }
1989
1990         r = gfx_v8_0_mec_init(adev);
1991         if (r) {
1992                 DRM_ERROR("Failed to init MEC BOs!\n");
1993                 return r;
1994         }
1995
1996         /* set up the gfx ring */
1997         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1998                 ring = &adev->gfx.gfx_ring[i];
1999                 ring->ring_obj = NULL;
2000                 sprintf(ring->name, "gfx");
2001                 /* no gfx doorbells on iceland */
2002                 if (adev->asic_type != CHIP_TOPAZ) {
2003                         ring->use_doorbell = true;
2004                         ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2005                 }
2006
2007                 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2008                                      AMDGPU_CP_IRQ_GFX_EOP);
2009                 if (r)
2010                         return r;
2011         }
2012
2013
2014         /* set up the compute queues - allocate horizontally across pipes */
2015         ring_id = 0;
2016         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2017                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2018                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2019                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2020                                         continue;
2021
2022                                 r = gfx_v8_0_compute_ring_init(adev,
2023                                                                 ring_id,
2024                                                                 i, k, j);
2025                                 if (r)
2026                                         return r;
2027
2028                                 ring_id++;
2029                         }
2030                 }
2031         }
2032
2033         r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2034         if (r) {
2035                 DRM_ERROR("Failed to init KIQ BOs!\n");
2036                 return r;
2037         }
2038
2039         kiq = &adev->gfx.kiq;
2040         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2041         if (r)
2042                 return r;
2043
2044         /* create MQD for all compute queues as well as KIQ for SRIOV case */
2045         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2046         if (r)
2047                 return r;
2048
2049         adev->gfx.ce_ram_size = 0x8000;
2050
2051         r = gfx_v8_0_gpu_early_init(adev);
2052         if (r)
2053                 return r;
2054
2055         return 0;
2056 }
2057
2058 static int gfx_v8_0_sw_fini(void *handle)
2059 {
2060         int i;
2061         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2062
2063         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
2064         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
2065         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
2066
2067         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2068                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2069         for (i = 0; i < adev->gfx.num_compute_rings; i++)
2070                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2071
2072         amdgpu_gfx_compute_mqd_sw_fini(adev);
2073         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
2074         amdgpu_gfx_kiq_fini(adev);
2075
2076         gfx_v8_0_mec_fini(adev);
2077         amdgpu_gfx_rlc_fini(adev);
2078         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2079                                 &adev->gfx.rlc.clear_state_gpu_addr,
2080                                 (void **)&adev->gfx.rlc.cs_ptr);
2081         if ((adev->asic_type == CHIP_CARRIZO) ||
2082             (adev->asic_type == CHIP_STONEY)) {
2083                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2084                                 &adev->gfx.rlc.cp_table_gpu_addr,
2085                                 (void **)&adev->gfx.rlc.cp_table_ptr);
2086         }
2087         gfx_v8_0_free_microcode(adev);
2088
2089         return 0;
2090 }
2091
2092 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2093 {
2094         uint32_t *modearray, *mod2array;
2095         const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2096         const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2097         u32 reg_offset;
2098
2099         modearray = adev->gfx.config.tile_mode_array;
2100         mod2array = adev->gfx.config.macrotile_mode_array;
2101
2102         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2103                 modearray[reg_offset] = 0;
2104
2105         for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)
2106                 mod2array[reg_offset] = 0;
2107
2108         switch (adev->asic_type) {
2109         case CHIP_TOPAZ:
2110                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2111                                 PIPE_CONFIG(ADDR_SURF_P2) |
2112                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2113                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2114                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2115                                 PIPE_CONFIG(ADDR_SURF_P2) |
2116                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2117                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2118                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2119                                 PIPE_CONFIG(ADDR_SURF_P2) |
2120                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2121                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2122                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2123                                 PIPE_CONFIG(ADDR_SURF_P2) |
2124                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2125                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2126                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2127                                 PIPE_CONFIG(ADDR_SURF_P2) |
2128                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2129                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2130                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2131                                 PIPE_CONFIG(ADDR_SURF_P2) |
2132                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2133                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2134                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2135                                 PIPE_CONFIG(ADDR_SURF_P2) |
2136                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2137                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2138                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2139                                 PIPE_CONFIG(ADDR_SURF_P2));
2140                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2141                                 PIPE_CONFIG(ADDR_SURF_P2) |
2142                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2143                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2144                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2145                                  PIPE_CONFIG(ADDR_SURF_P2) |
2146                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2147                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2148                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2149                                  PIPE_CONFIG(ADDR_SURF_P2) |
2150                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2151                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2152                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2153                                  PIPE_CONFIG(ADDR_SURF_P2) |
2154                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2155                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2156                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2157                                  PIPE_CONFIG(ADDR_SURF_P2) |
2158                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2159                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2160                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2161                                  PIPE_CONFIG(ADDR_SURF_P2) |
2162                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2163                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2164                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2165                                  PIPE_CONFIG(ADDR_SURF_P2) |
2166                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2167                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2168                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2169                                  PIPE_CONFIG(ADDR_SURF_P2) |
2170                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2171                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2172                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2173                                  PIPE_CONFIG(ADDR_SURF_P2) |
2174                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2175                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2176                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2177                                  PIPE_CONFIG(ADDR_SURF_P2) |
2178                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2179                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2180                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2181                                  PIPE_CONFIG(ADDR_SURF_P2) |
2182                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2183                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2184                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2185                                  PIPE_CONFIG(ADDR_SURF_P2) |
2186                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2187                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2188                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2189                                  PIPE_CONFIG(ADDR_SURF_P2) |
2190                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2191                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2192                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2193                                  PIPE_CONFIG(ADDR_SURF_P2) |
2194                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2195                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2196                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2197                                  PIPE_CONFIG(ADDR_SURF_P2) |
2198                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2199                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2200                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2201                                  PIPE_CONFIG(ADDR_SURF_P2) |
2202                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2203                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2204                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2205                                  PIPE_CONFIG(ADDR_SURF_P2) |
2206                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2207                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2208                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2209                                  PIPE_CONFIG(ADDR_SURF_P2) |
2210                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2211                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2212
2213                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2214                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2215                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2216                                 NUM_BANKS(ADDR_SURF_8_BANK));
2217                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2218                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2219                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2220                                 NUM_BANKS(ADDR_SURF_8_BANK));
2221                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2222                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2223                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2224                                 NUM_BANKS(ADDR_SURF_8_BANK));
2225                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2226                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2227                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2228                                 NUM_BANKS(ADDR_SURF_8_BANK));
2229                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2230                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2231                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2232                                 NUM_BANKS(ADDR_SURF_8_BANK));
2233                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2234                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2235                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2236                                 NUM_BANKS(ADDR_SURF_8_BANK));
2237                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2238                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2239                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2240                                 NUM_BANKS(ADDR_SURF_8_BANK));
2241                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2242                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2243                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2244                                 NUM_BANKS(ADDR_SURF_16_BANK));
2245                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2246                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2247                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2248                                 NUM_BANKS(ADDR_SURF_16_BANK));
2249                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2250                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2251                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2252                                  NUM_BANKS(ADDR_SURF_16_BANK));
2253                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2254                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2255                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2256                                  NUM_BANKS(ADDR_SURF_16_BANK));
2257                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2258                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2259                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2260                                  NUM_BANKS(ADDR_SURF_16_BANK));
2261                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2262                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2263                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2264                                  NUM_BANKS(ADDR_SURF_16_BANK));
2265                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2266                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2267                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2268                                  NUM_BANKS(ADDR_SURF_8_BANK));
2269
2270                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2271                         if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2272                             reg_offset != 23)
2273                                 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2274
2275                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2276                         if (reg_offset != 7)
2277                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2278
2279                 break;
2280         case CHIP_FIJI:
2281         case CHIP_VEGAM:
2282                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2283                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2284                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2285                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2286                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2287                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2288                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2289                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2290                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2291                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2292                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2293                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2294                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2295                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2296                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2297                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2298                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2299                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2300                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2301                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2302                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2303                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2304                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2305                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2306                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2307                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2309                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2310                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2311                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2312                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2313                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2314                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2315                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2316                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2317                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2318                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2319                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2320                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2321                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2322                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2323                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2324                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2325                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2326                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2327                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2328                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2329                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2330                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2331                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2332                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2333                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2334                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2335                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2336                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2337                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2338                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2339                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2340                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2341                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2342                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2343                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2344                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2345                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2346                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2347                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2348                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2349                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2350                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2351                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2352                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2353                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2354                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2355                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2356                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2357                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2359                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2360                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2361                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2363                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2364                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2365                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2367                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2368                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2369                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2371                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2372                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2373                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2374                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2375                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2376                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2377                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2380                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2381                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2383                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2384                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2385                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2387                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2389                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2391                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2392                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2393                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2395                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2396                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2397                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2399                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2400                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2401                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2402                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2403                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2404
2405                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2406                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2407                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2408                                 NUM_BANKS(ADDR_SURF_8_BANK));
2409                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2410                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2411                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2412                                 NUM_BANKS(ADDR_SURF_8_BANK));
2413                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2414                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2415                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2416                                 NUM_BANKS(ADDR_SURF_8_BANK));
2417                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2418                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2419                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2420                                 NUM_BANKS(ADDR_SURF_8_BANK));
2421                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2422                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2423                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2424                                 NUM_BANKS(ADDR_SURF_8_BANK));
2425                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2426                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2427                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2428                                 NUM_BANKS(ADDR_SURF_8_BANK));
2429                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2430                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2431                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2432                                 NUM_BANKS(ADDR_SURF_8_BANK));
2433                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2434                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2435                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2436                                 NUM_BANKS(ADDR_SURF_8_BANK));
2437                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2439                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2440                                 NUM_BANKS(ADDR_SURF_8_BANK));
2441                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2443                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2444                                  NUM_BANKS(ADDR_SURF_8_BANK));
2445                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2447                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2448                                  NUM_BANKS(ADDR_SURF_8_BANK));
2449                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2451                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452                                  NUM_BANKS(ADDR_SURF_8_BANK));
2453                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2455                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2456                                  NUM_BANKS(ADDR_SURF_8_BANK));
2457                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2459                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2460                                  NUM_BANKS(ADDR_SURF_4_BANK));
2461
2462                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2463                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2464
2465                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2466                         if (reg_offset != 7)
2467                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2468
2469                 break;
2470         case CHIP_TONGA:
2471                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2472                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2473                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2474                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2475                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2476                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2477                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2478                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2479                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2480                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2481                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2482                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2483                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2484                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2485                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2486                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2487                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2488                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2489                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2490                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2491                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2492                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2493                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2494                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2495                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2496                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2498                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2499                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2500                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2501                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2502                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2503                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2504                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2505                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2506                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2507                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2508                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2509                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2510                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2511                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2512                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2513                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2514                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2515                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2516                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2517                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2518                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2519                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2520                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2521                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2522                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2523                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2524                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2525                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2526                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2527                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2528                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2529                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2530                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2532                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2533                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2534                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2536                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2537                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2538                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2539                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2540                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2541                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2542                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2543                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2544                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2545                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2546                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2548                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2549                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2550                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2552                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2553                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2554                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2556                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2557                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2558                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2560                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2561                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2562                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2563                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2564                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2565                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2566                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2569                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2570                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2572                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2573                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2574                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2576                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2578                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2580                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2581                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2582                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2584                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2585                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2586                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2587                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2588                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2589                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2590                                  PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2591                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2592                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2593
2594                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2595                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2596                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2597                                 NUM_BANKS(ADDR_SURF_16_BANK));
2598                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2599                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2600                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2601                                 NUM_BANKS(ADDR_SURF_16_BANK));
2602                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2603                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2604                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2605                                 NUM_BANKS(ADDR_SURF_16_BANK));
2606                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2607                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2608                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2609                                 NUM_BANKS(ADDR_SURF_16_BANK));
2610                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2611                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2612                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2613                                 NUM_BANKS(ADDR_SURF_16_BANK));
2614                 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2615                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2616                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2617                                 NUM_BANKS(ADDR_SURF_16_BANK));
2618                 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2620                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2621                                 NUM_BANKS(ADDR_SURF_16_BANK));
2622                 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2624                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2625                                 NUM_BANKS(ADDR_SURF_16_BANK));
2626                 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2628                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2629                                 NUM_BANKS(ADDR_SURF_16_BANK));
2630                 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2632                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2633                                  NUM_BANKS(ADDR_SURF_16_BANK));
2634                 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2636                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2637                                  NUM_BANKS(ADDR_SURF_16_BANK));
2638                 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2641                                  NUM_BANKS(ADDR_SURF_8_BANK));
2642                 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2644                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2645                                  NUM_BANKS(ADDR_SURF_4_BANK));
2646                 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2648                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2649                                  NUM_BANKS(ADDR_SURF_4_BANK));
2650
2651                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2652                         WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2653
2654                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2655                         if (reg_offset != 7)
2656                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2657
2658                 break;
2659         case CHIP_POLARIS11:
2660         case CHIP_POLARIS12:
2661                 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2662                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2663                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2664                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2665                 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2666                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2667                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2668                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2669                 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2670                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2671                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2672                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2673                 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2674                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2675                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2676                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2677                 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2678                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2680                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2681                 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2682                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2684                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2685                 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2686                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2688                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2689                 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2690                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2692                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2693                 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2694                                 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2695                 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2696                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2697                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2698                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2699                 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2700                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2701                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2702                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2703                 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2704                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2705                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2706                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2707                 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2708                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2709                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2710                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2711                 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2712                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2713                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2714                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2715                 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2716                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2717                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2718                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2719                 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2720                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2721                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2722                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723                 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2724                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2725                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2726                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2727                 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2728                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2729                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2730                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2731                 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2732                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2733                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2734                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2735                 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2736                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2737                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2738                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2739                 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2740                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2742                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2743                 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2744                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2746                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2747                 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2748                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2750                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2751                 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2752                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2754                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2755                 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2756                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2758                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2759                 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2760                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2762                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2763                 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2764                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2766                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2767                 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2768                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2770                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2771                 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2772                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2774                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2775                 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2776                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2778                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2779                 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2780                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2782                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2783
2784                 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2785                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2786                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2787                                 NUM_BANKS(ADDR_SURF_16_BANK));
2788
2789                 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2790                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2791                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2792                                 NUM_BANKS(ADDR_SURF_16_BANK));
2793
2794                 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2795                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2796                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2797                                 NUM_BANKS(ADDR_SURF_16_BANK));
2798
2799                 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2800                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2801                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2802                                 NUM_BANKS(ADDR_SURF_16_BANK));
2803
2804                 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2805                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2806                            &nbs