drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_ih.h"
  29 #include "amdgpu_gfx.h"
  30 #include "cikd.h"
  31 #include "cik.h"
  32 #include "cik_structs.h"
  33 #include "atom.h"
  34 #include "amdgpu_ucode.h"
  35 #include "clearstate_ci.h"
  36
  37 #include "dce/dce_8_0_d.h"
  38 #include "dce/dce_8_0_sh_mask.h"
  39
  40 #include "bif/bif_4_1_d.h"
  41 #include "bif/bif_4_1_sh_mask.h"
  42
  43 #include "gca/gfx_7_0_d.h"
  44 #include "gca/gfx_7_2_enum.h"
  45 #include "gca/gfx_7_2_sh_mask.h"
  46
  47 #include "gmc/gmc_7_0_d.h"
  48 #include "gmc/gmc_7_0_sh_mask.h"
  49
  50 #include "oss/oss_2_0_d.h"
  51 #include "oss/oss_2_0_sh_mask.h"
  52
  53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
  54
  55 #define GFX7_NUM_GFX_RINGS     1
  56 #define GFX7_MEC_HPD_SIZE      2048
  57
  58 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  59 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  60 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  61
  62 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin");
  63 MODULE_FIRMWARE("amdgpu/bonaire_me.bin");
  64 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin");
  65 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin");
  66 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin");
  67
  68 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin");
  69 MODULE_FIRMWARE("amdgpu/hawaii_me.bin");
  70 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin");
  71 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin");
  72 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin");
  73
  74 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin");
  75 MODULE_FIRMWARE("amdgpu/kaveri_me.bin");
  76 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin");
  78 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin");
  79 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin");
  80
  81 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin");
  82 MODULE_FIRMWARE("amdgpu/kabini_me.bin");
  83 MODULE_FIRMWARE("amdgpu/kabini_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin");
  85 MODULE_FIRMWARE("amdgpu/kabini_mec.bin");
  86
  87 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin");
  88 MODULE_FIRMWARE("amdgpu/mullins_me.bin");
  89 MODULE_FIRMWARE("amdgpu/mullins_ce.bin");
  90 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin");
  91 MODULE_FIRMWARE("amdgpu/mullins_mec.bin");
  92
  93 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  94 {
  95         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  96         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  97         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  98         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  99         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 100         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 101         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 102         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 103         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 104         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 105         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 106         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 107         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 108         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 109         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 110         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 111 };
 112
 113 static const u32 spectre_rlc_save_restore_register_list[] =
 114 {
 115         (0x0e00 << 16) | (0xc12c >> 2),
 116         0x00000000,
 117         (0x0e00 << 16) | (0xc140 >> 2),
 118         0x00000000,
 119         (0x0e00 << 16) | (0xc150 >> 2),
 120         0x00000000,
 121         (0x0e00 << 16) | (0xc15c >> 2),
 122         0x00000000,
 123         (0x0e00 << 16) | (0xc168 >> 2),
 124         0x00000000,
 125         (0x0e00 << 16) | (0xc170 >> 2),
 126         0x00000000,
 127         (0x0e00 << 16) | (0xc178 >> 2),
 128         0x00000000,
 129         (0x0e00 << 16) | (0xc204 >> 2),
 130         0x00000000,
 131         (0x0e00 << 16) | (0xc2b4 >> 2),
 132         0x00000000,
 133         (0x0e00 << 16) | (0xc2b8 >> 2),
 134         0x00000000,
 135         (0x0e00 << 16) | (0xc2bc >> 2),
 136         0x00000000,
 137         (0x0e00 << 16) | (0xc2c0 >> 2),
 138         0x00000000,
 139         (0x0e00 << 16) | (0x8228 >> 2),
 140         0x00000000,
 141         (0x0e00 << 16) | (0x829c >> 2),
 142         0x00000000,
 143         (0x0e00 << 16) | (0x869c >> 2),
 144         0x00000000,
 145         (0x0600 << 16) | (0x98f4 >> 2),
 146         0x00000000,
 147         (0x0e00 << 16) | (0x98f8 >> 2),
 148         0x00000000,
 149         (0x0e00 << 16) | (0x9900 >> 2),
 150         0x00000000,
 151         (0x0e00 << 16) | (0xc260 >> 2),
 152         0x00000000,
 153         (0x0e00 << 16) | (0x90e8 >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0x3c000 >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0x3c00c >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0x8c1c >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0x9700 >> 2),
 162         0x00000000,
 163         (0x0e00 << 16) | (0xcd20 >> 2),
 164         0x00000000,
 165         (0x4e00 << 16) | (0xcd20 >> 2),
 166         0x00000000,
 167         (0x5e00 << 16) | (0xcd20 >> 2),
 168         0x00000000,
 169         (0x6e00 << 16) | (0xcd20 >> 2),
 170         0x00000000,
 171         (0x7e00 << 16) | (0xcd20 >> 2),
 172         0x00000000,
 173         (0x8e00 << 16) | (0xcd20 >> 2),
 174         0x00000000,
 175         (0x9e00 << 16) | (0xcd20 >> 2),
 176         0x00000000,
 177         (0xae00 << 16) | (0xcd20 >> 2),
 178         0x00000000,
 179         (0xbe00 << 16) | (0xcd20 >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0x89bc >> 2),
 182         0x00000000,
 183         (0x0e00 << 16) | (0x8900 >> 2),
 184         0x00000000,
 185         0x3,
 186         (0x0e00 << 16) | (0xc130 >> 2),
 187         0x00000000,
 188         (0x0e00 << 16) | (0xc134 >> 2),
 189         0x00000000,
 190         (0x0e00 << 16) | (0xc1fc >> 2),
 191         0x00000000,
 192         (0x0e00 << 16) | (0xc208 >> 2),
 193         0x00000000,
 194         (0x0e00 << 16) | (0xc264 >> 2),
 195         0x00000000,
 196         (0x0e00 << 16) | (0xc268 >> 2),
 197         0x00000000,
 198         (0x0e00 << 16) | (0xc26c >> 2),
 199         0x00000000,
 200         (0x0e00 << 16) | (0xc270 >> 2),
 201         0x00000000,
 202         (0x0e00 << 16) | (0xc274 >> 2),
 203         0x00000000,
 204         (0x0e00 << 16) | (0xc278 >> 2),
 205         0x00000000,
 206         (0x0e00 << 16) | (0xc27c >> 2),
 207         0x00000000,
 208         (0x0e00 << 16) | (0xc280 >> 2),
 209         0x00000000,
 210         (0x0e00 << 16) | (0xc284 >> 2),
 211         0x00000000,
 212         (0x0e00 << 16) | (0xc288 >> 2),
 213         0x00000000,
 214         (0x0e00 << 16) | (0xc28c >> 2),
 215         0x00000000,
 216         (0x0e00 << 16) | (0xc290 >> 2),
 217         0x00000000,
 218         (0x0e00 << 16) | (0xc294 >> 2),
 219         0x00000000,
 220         (0x0e00 << 16) | (0xc298 >> 2),
 221         0x00000000,
 222         (0x0e00 << 16) | (0xc29c >> 2),
 223         0x00000000,
 224         (0x0e00 << 16) | (0xc2a0 >> 2),
 225         0x00000000,
 226         (0x0e00 << 16) | (0xc2a4 >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc2a8 >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0xc2ac  >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0xc2b0 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0x301d0 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0x30238 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0x30250 >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0x30254 >> 2),
 241         0x00000000,
 242         (0x0e00 << 16) | (0x30258 >> 2),
 243         0x00000000,
 244         (0x0e00 << 16) | (0x3025c >> 2),
 245         0x00000000,
 246         (0x4e00 << 16) | (0xc900 >> 2),
 247         0x00000000,
 248         (0x5e00 << 16) | (0xc900 >> 2),
 249         0x00000000,
 250         (0x6e00 << 16) | (0xc900 >> 2),
 251         0x00000000,
 252         (0x7e00 << 16) | (0xc900 >> 2),
 253         0x00000000,
 254         (0x8e00 << 16) | (0xc900 >> 2),
 255         0x00000000,
 256         (0x9e00 << 16) | (0xc900 >> 2),
 257         0x00000000,
 258         (0xae00 << 16) | (0xc900 >> 2),
 259         0x00000000,
 260         (0xbe00 << 16) | (0xc900 >> 2),
 261         0x00000000,
 262         (0x4e00 << 16) | (0xc904 >> 2),
 263         0x00000000,
 264         (0x5e00 << 16) | (0xc904 >> 2),
 265         0x00000000,
 266         (0x6e00 << 16) | (0xc904 >> 2),
 267         0x00000000,
 268         (0x7e00 << 16) | (0xc904 >> 2),
 269         0x00000000,
 270         (0x8e00 << 16) | (0xc904 >> 2),
 271         0x00000000,
 272         (0x9e00 << 16) | (0xc904 >> 2),
 273         0x00000000,
 274         (0xae00 << 16) | (0xc904 >> 2),
 275         0x00000000,
 276         (0xbe00 << 16) | (0xc904 >> 2),
 277         0x00000000,
 278         (0x4e00 << 16) | (0xc908 >> 2),
 279         0x00000000,
 280         (0x5e00 << 16) | (0xc908 >> 2),
 281         0x00000000,
 282         (0x6e00 << 16) | (0xc908 >> 2),
 283         0x00000000,
 284         (0x7e00 << 16) | (0xc908 >> 2),
 285         0x00000000,
 286         (0x8e00 << 16) | (0xc908 >> 2),
 287         0x00000000,
 288         (0x9e00 << 16) | (0xc908 >> 2),
 289         0x00000000,
 290         (0xae00 << 16) | (0xc908 >> 2),
 291         0x00000000,
 292         (0xbe00 << 16) | (0xc908 >> 2),
 293         0x00000000,
 294         (0x4e00 << 16) | (0xc90c >> 2),
 295         0x00000000,
 296         (0x5e00 << 16) | (0xc90c >> 2),
 297         0x00000000,
 298         (0x6e00 << 16) | (0xc90c >> 2),
 299         0x00000000,
 300         (0x7e00 << 16) | (0xc90c >> 2),
 301         0x00000000,
 302         (0x8e00 << 16) | (0xc90c >> 2),
 303         0x00000000,
 304         (0x9e00 << 16) | (0xc90c >> 2),
 305         0x00000000,
 306         (0xae00 << 16) | (0xc90c >> 2),
 307         0x00000000,
 308         (0xbe00 << 16) | (0xc90c >> 2),
 309         0x00000000,
 310         (0x4e00 << 16) | (0xc910 >> 2),
 311         0x00000000,
 312         (0x5e00 << 16) | (0xc910 >> 2),
 313         0x00000000,
 314         (0x6e00 << 16) | (0xc910 >> 2),
 315         0x00000000,
 316         (0x7e00 << 16) | (0xc910 >> 2),
 317         0x00000000,
 318         (0x8e00 << 16) | (0xc910 >> 2),
 319         0x00000000,
 320         (0x9e00 << 16) | (0xc910 >> 2),
 321         0x00000000,
 322         (0xae00 << 16) | (0xc910 >> 2),
 323         0x00000000,
 324         (0xbe00 << 16) | (0xc910 >> 2),
 325         0x00000000,
 326         (0x0e00 << 16) | (0xc99c >> 2),
 327         0x00000000,
 328         (0x0e00 << 16) | (0x9834 >> 2),
 329         0x00000000,
 330         (0x0000 << 16) | (0x30f00 >> 2),
 331         0x00000000,
 332         (0x0001 << 16) | (0x30f00 >> 2),
 333         0x00000000,
 334         (0x0000 << 16) | (0x30f04 >> 2),
 335         0x00000000,
 336         (0x0001 << 16) | (0x30f04 >> 2),
 337         0x00000000,
 338         (0x0000 << 16) | (0x30f08 >> 2),
 339         0x00000000,
 340         (0x0001 << 16) | (0x30f08 >> 2),
 341         0x00000000,
 342         (0x0000 << 16) | (0x30f0c >> 2),
 343         0x00000000,
 344         (0x0001 << 16) | (0x30f0c >> 2),
 345         0x00000000,
 346         (0x0600 << 16) | (0x9b7c >> 2),
 347         0x00000000,
 348         (0x0e00 << 16) | (0x8a14 >> 2),
 349         0x00000000,
 350         (0x0e00 << 16) | (0x8a18 >> 2),
 351         0x00000000,
 352         (0x0600 << 16) | (0x30a00 >> 2),
 353         0x00000000,
 354         (0x0e00 << 16) | (0x8bf0 >> 2),
 355         0x00000000,
 356         (0x0e00 << 16) | (0x8bcc >> 2),
 357         0x00000000,
 358         (0x0e00 << 16) | (0x8b24 >> 2),
 359         0x00000000,
 360         (0x0e00 << 16) | (0x30a04 >> 2),
 361         0x00000000,
 362         (0x0600 << 16) | (0x30a10 >> 2),
 363         0x00000000,
 364         (0x0600 << 16) | (0x30a14 >> 2),
 365         0x00000000,
 366         (0x0600 << 16) | (0x30a18 >> 2),
 367         0x00000000,
 368         (0x0600 << 16) | (0x30a2c >> 2),
 369         0x00000000,
 370         (0x0e00 << 16) | (0xc700 >> 2),
 371         0x00000000,
 372         (0x0e00 << 16) | (0xc704 >> 2),
 373         0x00000000,
 374         (0x0e00 << 16) | (0xc708 >> 2),
 375         0x00000000,
 376         (0x0e00 << 16) | (0xc768 >> 2),
 377         0x00000000,
 378         (0x0400 << 16) | (0xc770 >> 2),
 379         0x00000000,
 380         (0x0400 << 16) | (0xc774 >> 2),
 381         0x00000000,
 382         (0x0400 << 16) | (0xc778 >> 2),
 383         0x00000000,
 384         (0x0400 << 16) | (0xc77c >> 2),
 385         0x00000000,
 386         (0x0400 << 16) | (0xc780 >> 2),
 387         0x00000000,
 388         (0x0400 << 16) | (0xc784 >> 2),
 389         0x00000000,
 390         (0x0400 << 16) | (0xc788 >> 2),
 391         0x00000000,
 392         (0x0400 << 16) | (0xc78c >> 2),
 393         0x00000000,
 394         (0x0400 << 16) | (0xc798 >> 2),
 395         0x00000000,
 396         (0x0400 << 16) | (0xc79c >> 2),
 397         0x00000000,
 398         (0x0400 << 16) | (0xc7a0 >> 2),
 399         0x00000000,
 400         (0x0400 << 16) | (0xc7a4 >> 2),
 401         0x00000000,
 402         (0x0400 << 16) | (0xc7a8 >> 2),
 403         0x00000000,
 404         (0x0400 << 16) | (0xc7ac >> 2),
 405         0x00000000,
 406         (0x0400 << 16) | (0xc7b0 >> 2),
 407         0x00000000,
 408         (0x0400 << 16) | (0xc7b4 >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0x9100 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0x3c010 >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0x92a8 >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0x92ac >> 2),
 417         0x00000000,
 418         (0x0e00 << 16) | (0x92b4 >> 2),
 419         0x00000000,
 420         (0x0e00 << 16) | (0x92b8 >> 2),
 421         0x00000000,
 422         (0x0e00 << 16) | (0x92bc >> 2),
 423         0x00000000,
 424         (0x0e00 << 16) | (0x92c0 >> 2),
 425         0x00000000,
 426         (0x0e00 << 16) | (0x92c4 >> 2),
 427         0x00000000,
 428         (0x0e00 << 16) | (0x92c8 >> 2),
 429         0x00000000,
 430         (0x0e00 << 16) | (0x92cc >> 2),
 431         0x00000000,
 432         (0x0e00 << 16) | (0x92d0 >> 2),
 433         0x00000000,
 434         (0x0e00 << 16) | (0x8c00 >> 2),
 435         0x00000000,
 436         (0x0e00 << 16) | (0x8c04 >> 2),
 437         0x00000000,
 438         (0x0e00 << 16) | (0x8c20 >> 2),
 439         0x00000000,
 440         (0x0e00 << 16) | (0x8c38 >> 2),
 441         0x00000000,
 442         (0x0e00 << 16) | (0x8c3c >> 2),
 443         0x00000000,
 444         (0x0e00 << 16) | (0xae00 >> 2),
 445         0x00000000,
 446         (0x0e00 << 16) | (0x9604 >> 2),
 447         0x00000000,
 448         (0x0e00 << 16) | (0xac08 >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0xac0c >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0xac10 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0xac14 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0xac58 >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0xac68 >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0xac6c >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0xac70 >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0xac74 >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0xac78 >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0xac7c >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0xac80 >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0xac84 >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0xac88 >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0xac8c >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x970c >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x9714 >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x9718 >> 2),
 483         0x00000000,
 484         (0x0e00 << 16) | (0x971c >> 2),
 485         0x00000000,
 486         (0x0e00 << 16) | (0x31068 >> 2),
 487         0x00000000,
 488         (0x4e00 << 16) | (0x31068 >> 2),
 489         0x00000000,
 490         (0x5e00 << 16) | (0x31068 >> 2),
 491         0x00000000,
 492         (0x6e00 << 16) | (0x31068 >> 2),
 493         0x00000000,
 494         (0x7e00 << 16) | (0x31068 >> 2),
 495         0x00000000,
 496         (0x8e00 << 16) | (0x31068 >> 2),
 497         0x00000000,
 498         (0x9e00 << 16) | (0x31068 >> 2),
 499         0x00000000,
 500         (0xae00 << 16) | (0x31068 >> 2),
 501         0x00000000,
 502         (0xbe00 << 16) | (0x31068 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0xcd10 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0xcd14 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0x88b0 >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0x88b4 >> 2),
 511         0x00000000,
 512         (0x0e00 << 16) | (0x88b8 >> 2),
 513         0x00000000,
 514         (0x0e00 << 16) | (0x88bc >> 2),
 515         0x00000000,
 516         (0x0400 << 16) | (0x89c0 >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x88c4 >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x88c8 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x88d0 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x88d4 >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x88d8 >> 2),
 527         0x00000000,
 528         (0x0e00 << 16) | (0x8980 >> 2),
 529         0x00000000,
 530         (0x0e00 << 16) | (0x30938 >> 2),
 531         0x00000000,
 532         (0x0e00 << 16) | (0x3093c >> 2),
 533         0x00000000,
 534         (0x0e00 << 16) | (0x30940 >> 2),
 535         0x00000000,
 536         (0x0e00 << 16) | (0x89a0 >> 2),
 537         0x00000000,
 538         (0x0e00 << 16) | (0x30900 >> 2),
 539         0x00000000,
 540         (0x0e00 << 16) | (0x30904 >> 2),
 541         0x00000000,
 542         (0x0e00 << 16) | (0x89b4 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0x3c210 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0x3c214 >> 2),
 547         0x00000000,
 548         (0x0e00 << 16) | (0x3c218 >> 2),
 549         0x00000000,
 550         (0x0e00 << 16) | (0x8904 >> 2),
 551         0x00000000,
 552         0x5,
 553         (0x0e00 << 16) | (0x8c28 >> 2),
 554         (0x0e00 << 16) | (0x8c2c >> 2),
 555         (0x0e00 << 16) | (0x8c30 >> 2),
 556         (0x0e00 << 16) | (0x8c34 >> 2),
 557         (0x0e00 << 16) | (0x9600 >> 2),
 558 };
 559
 560 static const u32 kalindi_rlc_save_restore_register_list[] =
 561 {
 562         (0x0e00 << 16) | (0xc12c >> 2),
 563         0x00000000,
 564         (0x0e00 << 16) | (0xc140 >> 2),
 565         0x00000000,
 566         (0x0e00 << 16) | (0xc150 >> 2),
 567         0x00000000,
 568         (0x0e00 << 16) | (0xc15c >> 2),
 569         0x00000000,
 570         (0x0e00 << 16) | (0xc168 >> 2),
 571         0x00000000,
 572         (0x0e00 << 16) | (0xc170 >> 2),
 573         0x00000000,
 574         (0x0e00 << 16) | (0xc204 >> 2),
 575         0x00000000,
 576         (0x0e00 << 16) | (0xc2b4 >> 2),
 577         0x00000000,
 578         (0x0e00 << 16) | (0xc2b8 >> 2),
 579         0x00000000,
 580         (0x0e00 << 16) | (0xc2bc >> 2),
 581         0x00000000,
 582         (0x0e00 << 16) | (0xc2c0 >> 2),
 583         0x00000000,
 584         (0x0e00 << 16) | (0x8228 >> 2),
 585         0x00000000,
 586         (0x0e00 << 16) | (0x829c >> 2),
 587         0x00000000,
 588         (0x0e00 << 16) | (0x869c >> 2),
 589         0x00000000,
 590         (0x0600 << 16) | (0x98f4 >> 2),
 591         0x00000000,
 592         (0x0e00 << 16) | (0x98f8 >> 2),
 593         0x00000000,
 594         (0x0e00 << 16) | (0x9900 >> 2),
 595         0x00000000,
 596         (0x0e00 << 16) | (0xc260 >> 2),
 597         0x00000000,
 598         (0x0e00 << 16) | (0x90e8 >> 2),
 599         0x00000000,
 600         (0x0e00 << 16) | (0x3c000 >> 2),
 601         0x00000000,
 602         (0x0e00 << 16) | (0x3c00c >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0x8c1c >> 2),
 605         0x00000000,
 606         (0x0e00 << 16) | (0x9700 >> 2),
 607         0x00000000,
 608         (0x0e00 << 16) | (0xcd20 >> 2),
 609         0x00000000,
 610         (0x4e00 << 16) | (0xcd20 >> 2),
 611         0x00000000,
 612         (0x5e00 << 16) | (0xcd20 >> 2),
 613         0x00000000,
 614         (0x6e00 << 16) | (0xcd20 >> 2),
 615         0x00000000,
 616         (0x7e00 << 16) | (0xcd20 >> 2),
 617         0x00000000,
 618         (0x0e00 << 16) | (0x89bc >> 2),
 619         0x00000000,
 620         (0x0e00 << 16) | (0x8900 >> 2),
 621         0x00000000,
 622         0x3,
 623         (0x0e00 << 16) | (0xc130 >> 2),
 624         0x00000000,
 625         (0x0e00 << 16) | (0xc134 >> 2),
 626         0x00000000,
 627         (0x0e00 << 16) | (0xc1fc >> 2),
 628         0x00000000,
 629         (0x0e00 << 16) | (0xc208 >> 2),
 630         0x00000000,
 631         (0x0e00 << 16) | (0xc264 >> 2),
 632         0x00000000,
 633         (0x0e00 << 16) | (0xc268 >> 2),
 634         0x00000000,
 635         (0x0e00 << 16) | (0xc26c >> 2),
 636         0x00000000,
 637         (0x0e00 << 16) | (0xc270 >> 2),
 638         0x00000000,
 639         (0x0e00 << 16) | (0xc274 >> 2),
 640         0x00000000,
 641         (0x0e00 << 16) | (0xc28c >> 2),
 642         0x00000000,
 643         (0x0e00 << 16) | (0xc290 >> 2),
 644         0x00000000,
 645         (0x0e00 << 16) | (0xc294 >> 2),
 646         0x00000000,
 647         (0x0e00 << 16) | (0xc298 >> 2),
 648         0x00000000,
 649         (0x0e00 << 16) | (0xc2a0 >> 2),
 650         0x00000000,
 651         (0x0e00 << 16) | (0xc2a4 >> 2),
 652         0x00000000,
 653         (0x0e00 << 16) | (0xc2a8 >> 2),
 654         0x00000000,
 655         (0x0e00 << 16) | (0xc2ac >> 2),
 656         0x00000000,
 657         (0x0e00 << 16) | (0x301d0 >> 2),
 658         0x00000000,
 659         (0x0e00 << 16) | (0x30238 >> 2),
 660         0x00000000,
 661         (0x0e00 << 16) | (0x30250 >> 2),
 662         0x00000000,
 663         (0x0e00 << 16) | (0x30254 >> 2),
 664         0x00000000,
 665         (0x0e00 << 16) | (0x30258 >> 2),
 666         0x00000000,
 667         (0x0e00 << 16) | (0x3025c >> 2),
 668         0x00000000,
 669         (0x4e00 << 16) | (0xc900 >> 2),
 670         0x00000000,
 671         (0x5e00 << 16) | (0xc900 >> 2),
 672         0x00000000,
 673         (0x6e00 << 16) | (0xc900 >> 2),
 674         0x00000000,
 675         (0x7e00 << 16) | (0xc900 >> 2),
 676         0x00000000,
 677         (0x4e00 << 16) | (0xc904 >> 2),
 678         0x00000000,
 679         (0x5e00 << 16) | (0xc904 >> 2),
 680         0x00000000,
 681         (0x6e00 << 16) | (0xc904 >> 2),
 682         0x00000000,
 683         (0x7e00 << 16) | (0xc904 >> 2),
 684         0x00000000,
 685         (0x4e00 << 16) | (0xc908 >> 2),
 686         0x00000000,
 687         (0x5e00 << 16) | (0xc908 >> 2),
 688         0x00000000,
 689         (0x6e00 << 16) | (0xc908 >> 2),
 690         0x00000000,
 691         (0x7e00 << 16) | (0xc908 >> 2),
 692         0x00000000,
 693         (0x4e00 << 16) | (0xc90c >> 2),
 694         0x00000000,
 695         (0x5e00 << 16) | (0xc90c >> 2),
 696         0x00000000,
 697         (0x6e00 << 16) | (0xc90c >> 2),
 698         0x00000000,
 699         (0x7e00 << 16) | (0xc90c >> 2),
 700         0x00000000,
 701         (0x4e00 << 16) | (0xc910 >> 2),
 702         0x00000000,
 703         (0x5e00 << 16) | (0xc910 >> 2),
 704         0x00000000,
 705         (0x6e00 << 16) | (0xc910 >> 2),
 706         0x00000000,
 707         (0x7e00 << 16) | (0xc910 >> 2),
 708         0x00000000,
 709         (0x0e00 << 16) | (0xc99c >> 2),
 710         0x00000000,
 711         (0x0e00 << 16) | (0x9834 >> 2),
 712         0x00000000,
 713         (0x0000 << 16) | (0x30f00 >> 2),
 714         0x00000000,
 715         (0x0000 << 16) | (0x30f04 >> 2),
 716         0x00000000,
 717         (0x0000 << 16) | (0x30f08 >> 2),
 718         0x00000000,
 719         (0x0000 << 16) | (0x30f0c >> 2),
 720         0x00000000,
 721         (0x0600 << 16) | (0x9b7c >> 2),
 722         0x00000000,
 723         (0x0e00 << 16) | (0x8a14 >> 2),
 724         0x00000000,
 725         (0x0e00 << 16) | (0x8a18 >> 2),
 726         0x00000000,
 727         (0x0600 << 16) | (0x30a00 >> 2),
 728         0x00000000,
 729         (0x0e00 << 16) | (0x8bf0 >> 2),
 730         0x00000000,
 731         (0x0e00 << 16) | (0x8bcc >> 2),
 732         0x00000000,
 733         (0x0e00 << 16) | (0x8b24 >> 2),
 734         0x00000000,
 735         (0x0e00 << 16) | (0x30a04 >> 2),
 736         0x00000000,
 737         (0x0600 << 16) | (0x30a10 >> 2),
 738         0x00000000,
 739         (0x0600 << 16) | (0x30a14 >> 2),
 740         0x00000000,
 741         (0x0600 << 16) | (0x30a18 >> 2),
 742         0x00000000,
 743         (0x0600 << 16) | (0x30a2c >> 2),
 744         0x00000000,
 745         (0x0e00 << 16) | (0xc700 >> 2),
 746         0x00000000,
 747         (0x0e00 << 16) | (0xc704 >> 2),
 748         0x00000000,
 749         (0x0e00 << 16) | (0xc708 >> 2),
 750         0x00000000,
 751         (0x0e00 << 16) | (0xc768 >> 2),
 752         0x00000000,
 753         (0x0400 << 16) | (0xc770 >> 2),
 754         0x00000000,
 755         (0x0400 << 16) | (0xc774 >> 2),
 756         0x00000000,
 757         (0x0400 << 16) | (0xc798 >> 2),
 758         0x00000000,
 759         (0x0400 << 16) | (0xc79c >> 2),
 760         0x00000000,
 761         (0x0e00 << 16) | (0x9100 >> 2),
 762         0x00000000,
 763         (0x0e00 << 16) | (0x3c010 >> 2),
 764         0x00000000,
 765         (0x0e00 << 16) | (0x8c00 >> 2),
 766         0x00000000,
 767         (0x0e00 << 16) | (0x8c04 >> 2),
 768         0x00000000,
 769         (0x0e00 << 16) | (0x8c20 >> 2),
 770         0x00000000,
 771         (0x0e00 << 16) | (0x8c38 >> 2),
 772         0x00000000,
 773         (0x0e00 << 16) | (0x8c3c >> 2),
 774         0x00000000,
 775         (0x0e00 << 16) | (0xae00 >> 2),
 776         0x00000000,
 777         (0x0e00 << 16) | (0x9604 >> 2),
 778         0x00000000,
 779         (0x0e00 << 16) | (0xac08 >> 2),
 780         0x00000000,
 781         (0x0e00 << 16) | (0xac0c >> 2),
 782         0x00000000,
 783         (0x0e00 << 16) | (0xac10 >> 2),
 784         0x00000000,
 785         (0x0e00 << 16) | (0xac14 >> 2),
 786         0x00000000,
 787         (0x0e00 << 16) | (0xac58 >> 2),
 788         0x00000000,
 789         (0x0e00 << 16) | (0xac68 >> 2),
 790         0x00000000,
 791         (0x0e00 << 16) | (0xac6c >> 2),
 792         0x00000000,
 793         (0x0e00 << 16) | (0xac70 >> 2),
 794         0x00000000,
 795         (0x0e00 << 16) | (0xac74 >> 2),
 796         0x00000000,
 797         (0x0e00 << 16) | (0xac78 >> 2),
 798         0x00000000,
 799         (0x0e00 << 16) | (0xac7c >> 2),
 800         0x00000000,
 801         (0x0e00 << 16) | (0xac80 >> 2),
 802         0x00000000,
 803         (0x0e00 << 16) | (0xac84 >> 2),
 804         0x00000000,
 805         (0x0e00 << 16) | (0xac88 >> 2),
 806         0x00000000,
 807         (0x0e00 << 16) | (0xac8c >> 2),
 808         0x00000000,
 809         (0x0e00 << 16) | (0x970c >> 2),
 810         0x00000000,
 811         (0x0e00 << 16) | (0x9714 >> 2),
 812         0x00000000,
 813         (0x0e00 << 16) | (0x9718 >> 2),
 814         0x00000000,
 815         (0x0e00 << 16) | (0x971c >> 2),
 816         0x00000000,
 817         (0x0e00 << 16) | (0x31068 >> 2),
 818         0x00000000,
 819         (0x4e00 << 16) | (0x31068 >> 2),
 820         0x00000000,
 821         (0x5e00 << 16) | (0x31068 >> 2),
 822         0x00000000,
 823         (0x6e00 << 16) | (0x31068 >> 2),
 824         0x00000000,
 825         (0x7e00 << 16) | (0x31068 >> 2),
 826         0x00000000,
 827         (0x0e00 << 16) | (0xcd10 >> 2),
 828         0x00000000,
 829         (0x0e00 << 16) | (0xcd14 >> 2),
 830         0x00000000,
 831         (0x0e00 << 16) | (0x88b0 >> 2),
 832         0x00000000,
 833         (0x0e00 << 16) | (0x88b4 >> 2),
 834         0x00000000,
 835         (0x0e00 << 16) | (0x88b8 >> 2),
 836         0x00000000,
 837         (0x0e00 << 16) | (0x88bc >> 2),
 838         0x00000000,
 839         (0x0400 << 16) | (0x89c0 >> 2),
 840         0x00000000,
 841         (0x0e00 << 16) | (0x88c4 >> 2),
 842         0x00000000,
 843         (0x0e00 << 16) | (0x88c8 >> 2),
 844         0x00000000,
 845         (0x0e00 << 16) | (0x88d0 >> 2),
 846         0x00000000,
 847         (0x0e00 << 16) | (0x88d4 >> 2),
 848         0x00000000,
 849         (0x0e00 << 16) | (0x88d8 >> 2),
 850         0x00000000,
 851         (0x0e00 << 16) | (0x8980 >> 2),
 852         0x00000000,
 853         (0x0e00 << 16) | (0x30938 >> 2),
 854         0x00000000,
 855         (0x0e00 << 16) | (0x3093c >> 2),
 856         0x00000000,
 857         (0x0e00 << 16) | (0x30940 >> 2),
 858         0x00000000,
 859         (0x0e00 << 16) | (0x89a0 >> 2),
 860         0x00000000,
 861         (0x0e00 << 16) | (0x30900 >> 2),
 862         0x00000000,
 863         (0x0e00 << 16) | (0x30904 >> 2),
 864         0x00000000,
 865         (0x0e00 << 16) | (0x89b4 >> 2),
 866         0x00000000,
 867         (0x0e00 << 16) | (0x3e1fc >> 2),
 868         0x00000000,
 869         (0x0e00 << 16) | (0x3c210 >> 2),
 870         0x00000000,
 871         (0x0e00 << 16) | (0x3c214 >> 2),
 872         0x00000000,
 873         (0x0e00 << 16) | (0x3c218 >> 2),
 874         0x00000000,
 875         (0x0e00 << 16) | (0x8904 >> 2),
 876         0x00000000,
 877         0x5,
 878         (0x0e00 << 16) | (0x8c28 >> 2),
 879         (0x0e00 << 16) | (0x8c2c >> 2),
 880         (0x0e00 << 16) | (0x8c30 >> 2),
 881         (0x0e00 << 16) | (0x8c34 >> 2),
 882         (0x0e00 << 16) | (0x9600 >> 2),
 883 };
 884
 885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 886 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 887 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 888 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 889
 890 /*
 891  * Core functions
 892  */
 893 /**
 894  * gfx_v7_0_init_microcode - load ucode images from disk
 895  *
 896  * @adev: amdgpu_device pointer
 897  *
 898  * Use the firmware interface to load the ucode images into
 899  * the driver (not loaded into hw).
 900  * Returns 0 on success, error on failure.
 901  */
 902 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 903 {
 904         const char *chip_name;
 905         char fw_name[30];
 906         int err;
 907
 908         DRM_DEBUG("\n");
 909
 910         switch (adev->asic_type) {
 911         case CHIP_BONAIRE:
 912                 chip_name = "bonaire";
 913                 break;
 914         case CHIP_HAWAII:
 915                 chip_name = "hawaii";
 916                 break;
 917         case CHIP_KAVERI:
 918                 chip_name = "kaveri";
 919                 break;
 920         case CHIP_KABINI:
 921                 chip_name = "kabini";
 922                 break;
 923         case CHIP_MULLINS:
 924                 chip_name = "mullins";
 925                 break;
 926         default: BUG();
 927         }
 928
 929         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 930         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 931         if (err)
 932                 goto out;
 933         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 934         if (err)
 935                 goto out;
 936
 937         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 938         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 939         if (err)
 940                 goto out;
 941         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 942         if (err)
 943                 goto out;
 944
 945         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 946         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 947         if (err)
 948                 goto out;
 949         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 950         if (err)
 951                 goto out;
 952
 953         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 954         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 955         if (err)
 956                 goto out;
 957         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 958         if (err)
 959                 goto out;
 960
 961         if (adev->asic_type == CHIP_KAVERI) {
 962                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 963                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 964                 if (err)
 965                         goto out;
 966                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 967                 if (err)
 968                         goto out;
 969         }
 970
 971         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 972         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 973         if (err)
 974                 goto out;
 975         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 976
 977 out:
 978         if (err) {
 979                 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
 980                 release_firmware(adev->gfx.pfp_fw);
 981                 adev->gfx.pfp_fw = NULL;
 982                 release_firmware(adev->gfx.me_fw);
 983                 adev->gfx.me_fw = NULL;
 984                 release_firmware(adev->gfx.ce_fw);
 985                 adev->gfx.ce_fw = NULL;
 986                 release_firmware(adev->gfx.mec_fw);
 987                 adev->gfx.mec_fw = NULL;
 988                 release_firmware(adev->gfx.mec2_fw);
 989                 adev->gfx.mec2_fw = NULL;
 990                 release_firmware(adev->gfx.rlc_fw);
 991                 adev->gfx.rlc_fw = NULL;
 992         }
 993         return err;
 994 }
 995
 996 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 997 {
 998         release_firmware(adev->gfx.pfp_fw);
 999         adev->gfx.pfp_fw = NULL;
1000         release_firmware(adev->gfx.me_fw);
1001         adev->gfx.me_fw = NULL;
1002         release_firmware(adev->gfx.ce_fw);
1003         adev->gfx.ce_fw = NULL;
1004         release_firmware(adev->gfx.mec_fw);
1005         adev->gfx.mec_fw = NULL;
1006         release_firmware(adev->gfx.mec2_fw);
1007         adev->gfx.mec2_fw = NULL;
1008         release_firmware(adev->gfx.rlc_fw);
1009         adev->gfx.rlc_fw = NULL;
1010 }
1011
1012 /**
1013  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1014  *
1015  * @adev: amdgpu_device pointer
1016  *
1017  * Starting with SI, the tiling setup is done globally in a
1018  * set of 32 tiling modes.  Rather than selecting each set of
1019  * parameters per surface as on older asics, we just select
1020  * which index in the tiling table we want to use, and the
1021  * surface uses those parameters (CIK).
1022  */
1023 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1024 {
1025         const u32 num_tile_mode_states =
1026                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1027         const u32 num_secondary_tile_mode_states =
1028                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1029         u32 reg_offset, split_equal_to_row_size;
1030         uint32_t *tile, *macrotile;
1031
1032         tile = adev->gfx.config.tile_mode_array;
1033         macrotile = adev->gfx.config.macrotile_mode_array;
1034
1035         switch (adev->gfx.config.mem_row_size_in_kb) {
1036         case 1:
1037                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1038                 break;
1039         case 2:
1040         default:
1041                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1042                 break;
1043         case 4:
1044                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1045                 break;
1046         }
1047
1048         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1049                 tile[reg_offset] = 0;
1050         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1051                 macrotile[reg_offset] = 0;
1052
1053         switch (adev->asic_type) {
1054         case CHIP_BONAIRE:
1055                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1058                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1059                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1060                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1061                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1062                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1063                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1065                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1066                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1067                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1068                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1070                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1071                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1072                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1073                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1074                            TILE_SPLIT(split_equal_to_row_size));
1075                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1076                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1077                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1078                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1079                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1080                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1081                            TILE_SPLIT(split_equal_to_row_size));
1082                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1083                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1084                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1085                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1088                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1089                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1090                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1091                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1092                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1093                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1094                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1095                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1096                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1097                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1098                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1099                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1100                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1101                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1102                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1103                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1104                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1105                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1106                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1107                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1108                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1109                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1110                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1111                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1112                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1113                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1114                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1115                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1116                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1117                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1118                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1120                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1121                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1122                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1123                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1124                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1125                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1126                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1127                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1128                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1129                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1130                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1131                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1132                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1133                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1134                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1135                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1136                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1137                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1138                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1139                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1140                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1141                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1142                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1143                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1144                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1145                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1146                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1147                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1148                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1149                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1150                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1151                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1152                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1153                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1154                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1155                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1156                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1157
1158                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1159                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1160                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1161                                 NUM_BANKS(ADDR_SURF_16_BANK));
1162                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1164                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1165                                 NUM_BANKS(ADDR_SURF_16_BANK));
1166                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1167                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1168                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1169                                 NUM_BANKS(ADDR_SURF_16_BANK));
1170                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1171                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1172                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1173                                 NUM_BANKS(ADDR_SURF_16_BANK));
1174                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1175                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1176                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1177                                 NUM_BANKS(ADDR_SURF_16_BANK));
1178                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1179                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1180                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1181                                 NUM_BANKS(ADDR_SURF_8_BANK));
1182                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1183                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1184                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1185                                 NUM_BANKS(ADDR_SURF_4_BANK));
1186                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1187                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1188                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1189                                 NUM_BANKS(ADDR_SURF_16_BANK));
1190                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1191                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1192                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1193                                 NUM_BANKS(ADDR_SURF_16_BANK));
1194                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1195                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1196                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1197                                 NUM_BANKS(ADDR_SURF_16_BANK));
1198                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1199                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1200                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1201                                 NUM_BANKS(ADDR_SURF_16_BANK));
1202                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1203                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1204                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1205                                 NUM_BANKS(ADDR_SURF_16_BANK));
1206                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1207                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1208                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1209                                 NUM_BANKS(ADDR_SURF_8_BANK));
1210                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1211                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1212                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1213                                 NUM_BANKS(ADDR_SURF_4_BANK));
1214
1215                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1216                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1217                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1218                         if (reg_offset != 7)
1219                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1220                 break;
1221         case CHIP_HAWAII:
1222                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1223                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1224                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1225                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1226                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1228                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1229                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1230                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1231                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1232                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1233                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1234                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1236                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1237                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1238                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1239                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1241                            TILE_SPLIT(split_equal_to_row_size));
1242                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1243                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1244                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1245                            TILE_SPLIT(split_equal_to_row_size));
1246                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1247                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1248                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1249                            TILE_SPLIT(split_equal_to_row_size));
1250                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1251                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1252                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1253                            TILE_SPLIT(split_equal_to_row_size));
1254                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1255                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1256                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1257                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1259                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1260                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1261                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1262                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1263                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1264                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1265                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1266                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1267                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1268                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1269                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1270                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1271                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1272                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1273                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1274                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1275                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1276                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1277                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1278                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1279                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1280                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1281                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1282                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1283                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1284                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1285                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1286                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1287                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1288                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1289                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1290                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1291                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1292                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1293                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1294                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1295                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1296                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1297                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1298                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1299                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1300                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1301                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1302                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1303                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1304                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1305                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1306                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1307                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1308                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1309                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1310                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1311                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1312                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1313                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1314                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1315                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1316                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1317                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1318                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1319                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1320                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1321                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1322                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1323                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1324                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1325                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1326                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1327                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1328                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1329                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1330                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1331                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1332                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1333                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1334                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1335                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1336                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1337                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1338                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1339                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1340
1341                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1342                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1343                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1344                                 NUM_BANKS(ADDR_SURF_16_BANK));
1345                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1346                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1347                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1348                                 NUM_BANKS(ADDR_SURF_16_BANK));
1349                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1352                                 NUM_BANKS(ADDR_SURF_16_BANK));
1353                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1354                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1355                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1356                                 NUM_BANKS(ADDR_SURF_16_BANK));
1357                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1359                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1360                                 NUM_BANKS(ADDR_SURF_8_BANK));
1361                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1362                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1363                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1364                                 NUM_BANKS(ADDR_SURF_4_BANK));
1365                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1366                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1367                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1368                                 NUM_BANKS(ADDR_SURF_4_BANK));
1369                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1370                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1371                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1372                                 NUM_BANKS(ADDR_SURF_16_BANK));
1373                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1374                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1375                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1376                                 NUM_BANKS(ADDR_SURF_16_BANK));
1377                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1378                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1379                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1380                                 NUM_BANKS(ADDR_SURF_16_BANK));
1381                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1382                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1383                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1384                                 NUM_BANKS(ADDR_SURF_8_BANK));
1385                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1386                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1387                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1388                                 NUM_BANKS(ADDR_SURF_16_BANK));
1389                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1390                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1391                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1392                                 NUM_BANKS(ADDR_SURF_8_BANK));
1393                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1394                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1395                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1396                                 NUM_BANKS(ADDR_SURF_4_BANK));
1397
1398                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1399                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1400                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1401                         if (reg_offset != 7)
1402                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1403                 break;
1404         case CHIP_KABINI:
1405         case CHIP_KAVERI:
1406         case CHIP_MULLINS:
1407         default:
1408                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1409                            PIPE_CONFIG(ADDR_SURF_P2) |
1410                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1411                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1412                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1413                            PIPE_CONFIG(ADDR_SURF_P2) |
1414                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1415                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1416                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1417                            PIPE_CONFIG(ADDR_SURF_P2) |
1418                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1419                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1420                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1421                            PIPE_CONFIG(ADDR_SURF_P2) |
1422                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1423                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1424                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1425                            PIPE_CONFIG(ADDR_SURF_P2) |
1426                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1427                            TILE_SPLIT(split_equal_to_row_size));
1428                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1429                            PIPE_CONFIG(ADDR_SURF_P2) |
1430                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1431                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1432                            PIPE_CONFIG(ADDR_SURF_P2) |
1433                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1434                            TILE_SPLIT(split_equal_to_row_size));
1435                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1436                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1437                            PIPE_CONFIG(ADDR_SURF_P2));
1438                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1439                            PIPE_CONFIG(ADDR_SURF_P2) |
1440                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1441                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1442                             PIPE_CONFIG(ADDR_SURF_P2) |
1443                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1444                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1445                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1446                             PIPE_CONFIG(ADDR_SURF_P2) |
1447                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1448                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1449                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1450                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1451                             PIPE_CONFIG(ADDR_SURF_P2) |
1452                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1453                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1454                             PIPE_CONFIG(ADDR_SURF_P2) |
1455                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1456                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1457                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1458                             PIPE_CONFIG(ADDR_SURF_P2) |
1459                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1460                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1461                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1462                             PIPE_CONFIG(ADDR_SURF_P2) |
1463                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1464                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1465                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1466                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1467                             PIPE_CONFIG(ADDR_SURF_P2) |
1468                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1469                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1470                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1471                             PIPE_CONFIG(ADDR_SURF_P2) |
1472                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1473                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1474                             PIPE_CONFIG(ADDR_SURF_P2) |
1475                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1476                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1477                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1478                             PIPE_CONFIG(ADDR_SURF_P2) |
1479                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1480                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1481                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1482                             PIPE_CONFIG(ADDR_SURF_P2) |
1483                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1484                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1485                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1486                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1487                             PIPE_CONFIG(ADDR_SURF_P2) |
1488                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1489                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1490                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1491                             PIPE_CONFIG(ADDR_SURF_P2) |
1492                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1493                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1494                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1495                             PIPE_CONFIG(ADDR_SURF_P2) |
1496                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1497                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1498                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1499                             PIPE_CONFIG(ADDR_SURF_P2) |
1500                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1501                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1502                             PIPE_CONFIG(ADDR_SURF_P2) |
1503                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1504                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1505                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1506                             PIPE_CONFIG(ADDR_SURF_P2) |
1507                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1508                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1509                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1510
1511                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1512                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1513                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1514                                 NUM_BANKS(ADDR_SURF_8_BANK));
1515                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1516                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1517                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1518                                 NUM_BANKS(ADDR_SURF_8_BANK));
1519                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1520                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1521                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1522                                 NUM_BANKS(ADDR_SURF_8_BANK));
1523                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1524                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1525                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1526                                 NUM_BANKS(ADDR_SURF_8_BANK));
1527                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1528                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1529                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1530                                 NUM_BANKS(ADDR_SURF_8_BANK));
1531                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1532                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1533                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1534                                 NUM_BANKS(ADDR_SURF_8_BANK));
1535                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1536                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1537                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1538                                 NUM_BANKS(ADDR_SURF_8_BANK));
1539                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1540                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1541                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1542                                 NUM_BANKS(ADDR_SURF_16_BANK));
1543                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1544                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1545                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1546                                 NUM_BANKS(ADDR_SURF_16_BANK));
1547                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1548                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1549                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1550                                 NUM_BANKS(ADDR_SURF_16_BANK));
1551                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1552                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1553                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1554                                 NUM_BANKS(ADDR_SURF_16_BANK));
1555                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1556                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1557                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1558                                 NUM_BANKS(ADDR_SURF_16_BANK));
1559                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1560                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1561                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1562                                 NUM_BANKS(ADDR_SURF_16_BANK));
1563                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1564                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1565                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1566                                 NUM_BANKS(ADDR_SURF_8_BANK));
1567
1568                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1569                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1570                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1571                         if (reg_offset != 7)
1572                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1573                 break;
1574         }
1575 }
1576
1577 /**
1578  * gfx_v7_0_select_se_sh - select which SE, SH to address
1579  *
1580  * @adev: amdgpu_device pointer
1581  * @se_num: shader engine to address
1582  * @sh_num: sh block to address
1583  *
1584  * Select which SE, SH combinations to address. Certain
1585  * registers are instanced per SE or SH.  0xffffffff means
1586  * broadcast to all SEs or SHs (CIK).
1587  */
1588 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1589                                   u32 se_num, u32 sh_num, u32 instance)
1590 {
1591         u32 data;
1592
1593         if (instance == 0xffffffff)
1594                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1595         else
1596                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1597
1598         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1599                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1600                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1601         else if (se_num == 0xffffffff)
1602                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1603                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1604         else if (sh_num == 0xffffffff)
1605                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1606                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1607         else
1608                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1609                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1610         WREG32(mmGRBM_GFX_INDEX, data);
1611 }
1612
1613 /**
1614  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1615  *
1616  * @adev: amdgpu_device pointer
1617  *
1618  * Calculates the bitmask of enabled RBs (CIK).
1619  * Returns the enabled RB bitmask.
1620  */
1621 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1622 {
1623         u32 data, mask;
1624
1625         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1626         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1627
1628         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1629         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1630
1631         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1632                                          adev->gfx.config.max_sh_per_se);
1633
1634         return (~data) & mask;
1635 }
1636
1637 static void
1638 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1639 {
1640         switch (adev->asic_type) {
1641         case CHIP_BONAIRE:
1642                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1643                           SE_XSEL(1) | SE_YSEL(1);
1644                 *rconf1 |= 0x0;
1645                 break;
1646         case CHIP_HAWAII:
1647                 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1648                           RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1649                           PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1650                           SE_YSEL(3);
1651                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1652                            SE_PAIR_YSEL(2);
1653                 break;
1654         case CHIP_KAVERI:
1655                 *rconf |= RB_MAP_PKR0(2);
1656                 *rconf1 |= 0x0;
1657                 break;
1658         case CHIP_KABINI:
1659         case CHIP_MULLINS:
1660                 *rconf |= 0x0;
1661                 *rconf1 |= 0x0;
1662                 break;
1663         default:
1664                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1665                 break;
1666         }
1667 }
1668
1669 static void
1670 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1671                                         u32 raster_config, u32 raster_config_1,
1672                                         unsigned rb_mask, unsigned num_rb)
1673 {
1674         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1675         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1676         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1677         unsigned rb_per_se = num_rb / num_se;
1678         unsigned se_mask[4];
1679         unsigned se;
1680
1681         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1682         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1683         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1684         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1685
1686         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1687         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1688         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1689
1690         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1691                              (!se_mask[2] && !se_mask[3]))) {
1692                 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1693
1694                 if (!se_mask[0] && !se_mask[1]) {
1695                         raster_config_1 |=
1696                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1697                 } else {
1698                         raster_config_1 |=
1699                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1700                 }
1701         }
1702
1703         for (se = 0; se < num_se; se++) {
1704                 unsigned raster_config_se = raster_config;
1705                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1706                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1707                 int idx = (se / 2) * 2;
1708
1709                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1710                         raster_config_se &= ~SE_MAP_MASK;
1711
1712                         if (!se_mask[idx]) {
1713                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1714                         } else {
1715                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1716                         }
1717                 }
1718
1719                 pkr0_mask &= rb_mask;
1720                 pkr1_mask &= rb_mask;
1721                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1722                         raster_config_se &= ~PKR_MAP_MASK;
1723
1724                         if (!pkr0_mask) {
1725                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1726                         } else {
1727                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1728                         }
1729                 }
1730
1731                 if (rb_per_se >= 2) {
1732                         unsigned rb0_mask = 1 << (se * rb_per_se);
1733                         unsigned rb1_mask = rb0_mask << 1;
1734
1735                         rb0_mask &= rb_mask;
1736                         rb1_mask &= rb_mask;
1737                         if (!rb0_mask || !rb1_mask) {
1738                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
1739
1740                                 if (!rb0_mask) {
1741                                         raster_config_se |=
1742                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1743                                 } else {
1744                                         raster_config_se |=
1745                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1746                                 }
1747                         }
1748
1749                         if (rb_per_se > 2) {
1750                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1751                                 rb1_mask = rb0_mask << 1;
1752                                 rb0_mask &= rb_mask;
1753                                 rb1_mask &= rb_mask;
1754                                 if (!rb0_mask || !rb1_mask) {
1755                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
1756
1757                                         if (!rb0_mask) {
1758                                                 raster_config_se |=
1759                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1760                                         } else {
1761                                                 raster_config_se |=
1762                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1763                                         }
1764                                 }
1765                         }
1766                 }
1767
1768                 /* GRBM_GFX_INDEX has a different offset on CI+ */
1769                 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1770                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1771                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1772         }
1773
1774         /* GRBM_GFX_INDEX has a different offset on CI+ */
1775         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1776 }
1777
1778 /**
1779  * gfx_v7_0_setup_rb - setup the RBs on the asic
1780  *
1781  * @adev: amdgpu_device pointer
1782  * @se_num: number of SEs (shader engines) for the asic
1783  * @sh_per_se: number of SH blocks per SE for the asic
1784  *
1785  * Configures per-SE/SH RB registers (CIK).
1786  */
1787 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1788 {
1789         int i, j;
1790         u32 data;
1791         u32 raster_config = 0, raster_config_1 = 0;
1792         u32 active_rbs = 0;
1793         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1794                                         adev->gfx.config.max_sh_per_se;
1795         unsigned num_rb_pipes;
1796
1797         mutex_lock(&adev->grbm_idx_mutex);
1798         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1799                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1800                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1801                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1802                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1803                                                rb_bitmap_width_per_sh);
1804                 }
1805         }
1806         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1807
1808         adev->gfx.config.backend_enable_mask = active_rbs;
1809         adev->gfx.config.num_rbs = hweight32(active_rbs);
1810
1811         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1812                              adev->gfx.config.max_shader_engines, 16);
1813
1814         gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1815
1816         if (!adev->gfx.config.backend_enable_mask ||
1817                         adev->gfx.config.num_rbs >= num_rb_pipes) {
1818                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1819                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1820         } else {
1821                 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1822                                                         adev->gfx.config.backend_enable_mask,
1823                                                         num_rb_pipes);
1824         }
1825
1826         /* cache the values for userspace */
1827         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1828                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1829                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1830                         adev->gfx.config.rb_config[i][j].rb_backend_disable =
1831                                 RREG32(mmCC_RB_BACKEND_DISABLE);
1832                         adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1833                                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1834                         adev->gfx.config.rb_config[i][j].raster_config =
1835                                 RREG32(mmPA_SC_RASTER_CONFIG);
1836                         adev->gfx.config.rb_config[i][j].raster_config_1 =
1837                                 RREG32(mmPA_SC_RASTER_CONFIG_1);
1838                 }
1839         }
1840         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1841         mutex_unlock(&adev->grbm_idx_mutex);
1842 }
1843
1844 /**
1845  * gfx_v7_0_init_compute_vmid - gart enable
1846  *
1847  * @adev: amdgpu_device pointer
1848  *
1849  * Initialize compute vmid sh_mem registers
1850  *
1851  */
1852 #define DEFAULT_SH_MEM_BASES    (0x6000)
1853 #define FIRST_COMPUTE_VMID      (8)
1854 #define LAST_COMPUTE_VMID       (16)
1855 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1856 {
1857         int i;
1858         uint32_t sh_mem_config;
1859         uint32_t sh_mem_bases;
1860
1861         /*
1862          * Configure apertures:
1863          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1864          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1865          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1866         */
1867         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1868         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1869                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1870         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1871         mutex_lock(&adev->srbm_mutex);
1872         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1873                 cik_srbm_select(adev, 0, 0, 0, i);
1874                 /* CP and shaders */
1875                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1876                 WREG32(mmSH_MEM_APE1_BASE, 1);
1877                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1878                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1879         }
1880         cik_srbm_select(adev, 0, 0, 0, 0);
1881         mutex_unlock(&adev->srbm_mutex);
1882 }
1883
1884 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1885 {
1886         adev->gfx.config.double_offchip_lds_buf = 1;
1887 }
1888
1889 /**
1890  * gfx_v7_0_constants_init - setup the 3D engine
1891  *
1892  * @adev: amdgpu_device pointer
1893  *
1894  * init the gfx constants such as the 3D engine, tiling configuration
1895  * registers, maximum number of quad pipes, render backends...
1896  */
1897 static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
1898 {
1899         u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1900         u32 tmp;
1901         int i;
1902
1903         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1904
1905         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1906         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1907         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1908
1909         gfx_v7_0_tiling_mode_table_init(adev);
1910
1911         gfx_v7_0_setup_rb(adev);
1912         gfx_v7_0_get_cu_info(adev);
1913         gfx_v7_0_config_init(adev);
1914
1915         /* set HW defaults for 3D engine */
1916         WREG32(mmCP_MEQ_THRESHOLDS,
1917                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1918                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1919
1920         mutex_lock(&adev->grbm_idx_mutex);
1921         /*
1922          * making sure that the following register writes will be broadcasted
1923          * to all the shaders
1924          */
1925         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1926
1927         /* XXX SH_MEM regs */
1928         /* where to put LDS, scratch, GPUVM in FSA64 space */
1929         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1930                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1931         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1932                                    MTYPE_NC);
1933         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1934                                    MTYPE_UC);
1935         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1936
1937         sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1938                                    SWIZZLE_ENABLE, 1);
1939         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1940                                    ELEMENT_SIZE, 1);
1941         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1942                                    INDEX_STRIDE, 3);
1943         WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1944
1945         mutex_lock(&adev->srbm_mutex);
1946         for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1947                 if (i == 0)
1948                         sh_mem_base = 0;
1949                 else
1950                         sh_mem_base = adev->gmc.shared_aperture_start >> 48;
1951                 cik_srbm_select(adev, 0, 0, 0, i);
1952                 /* CP and shaders */
1953                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1954                 WREG32(mmSH_MEM_APE1_BASE, 1);
1955                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1956                 WREG32(mmSH_MEM_BASES, sh_mem_base);
1957         }
1958         cik_srbm_select(adev, 0, 0, 0, 0);
1959         mutex_unlock(&adev->srbm_mutex);
1960
1961         gfx_v7_0_init_compute_vmid(adev);
1962
1963         WREG32(mmSX_DEBUG_1, 0x20);
1964
1965         WREG32(mmTA_CNTL_AUX, 0x00010000);
1966
1967         tmp = RREG32(mmSPI_CONFIG_CNTL);
1968         tmp |= 0x03000000;
1969         WREG32(mmSPI_CONFIG_CNTL, tmp);
1970
1971         WREG32(mmSQ_CONFIG, 1);
1972
1973         WREG32(mmDB_DEBUG, 0);
1974
1975         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1976         tmp |= 0x00000400;
1977         WREG32(mmDB_DEBUG2, tmp);
1978
1979         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1980         tmp |= 0x00020200;
1981         WREG32(mmDB_DEBUG3, tmp);
1982
1983         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1984         tmp |= 0x00018208;
1985         WREG32(mmCB_HW_CONTROL, tmp);
1986
1987         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1988
1989         WREG32(mmPA_SC_FIFO_SIZE,
1990                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1991                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1992                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1993                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1994
1995         WREG32(mmVGT_NUM_INSTANCES, 1);
1996
1997         WREG32(mmCP_PERFMON_CNTL, 0);
1998
1999         WREG32(mmSQ_CONFIG, 0);
2000
2001         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
2002                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2003                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2004
2005         WREG32(mmVGT_CACHE_INVALIDATION,
2006                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2007                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2008
2009         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2010         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2011
2012         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2013                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2014         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2015
2016         tmp = RREG32(mmSPI_ARB_PRIORITY);
2017         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
2018         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2019         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2020         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2021         WREG32(mmSPI_ARB_PRIORITY, tmp);
2022
2023         mutex_unlock(&adev->grbm_idx_mutex);
2024
2025         udelay(50);
2026 }
2027
2028 /*
2029  * GPU scratch registers helpers function.
2030  */
2031 /**
2032  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2033  *
2034  * @adev: amdgpu_device pointer
2035  *
2036  * Set up the number and offset of the CP scratch registers.
2037  * NOTE: use of CP scratch registers is a legacy inferface and
2038  * is not used by default on newer asics (r6xx+).  On newer asics,
2039  * memory buffers are used for fences rather than scratch regs.
2040  */
2041 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2042 {
2043         adev->gfx.scratch.num_reg = 8;
2044         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2045         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2046 }
2047
2048 /**
2049  * gfx_v7_0_ring_test_ring - basic gfx ring test
2050  *
2051  * @adev: amdgpu_device pointer
2052  * @ring: amdgpu_ring structure holding ring information
2053  *
2054  * Allocate a scratch register and write to it using the gfx ring (CIK).
2055  * Provides a basic gfx ring test to verify that the ring is working.
2056  * Used by gfx_v7_0_cp_gfx_resume();
2057  * Returns 0 on success, error on failure.
2058  */
2059 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2060 {
2061         struct amdgpu_device *adev = ring->adev;
2062         uint32_t scratch;
2063         uint32_t tmp = 0;
2064         unsigned i;
2065         int r;
2066
2067         r = amdgpu_gfx_scratch_get(adev, &scratch);
2068         if (r)
2069                 return r;
2070
2071         WREG32(scratch, 0xCAFEDEAD);
2072         r = amdgpu_ring_alloc(ring, 3);
2073         if (r)
2074                 goto error_free_scratch;
2075
2076         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2077         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2078         amdgpu_ring_write(ring, 0xDEADBEEF);
2079         amdgpu_ring_commit(ring);
2080
2081         for (i = 0; i < adev->usec_timeout; i++) {
2082                 tmp = RREG32(scratch);
2083                 if (tmp == 0xDEADBEEF)
2084                         break;
2085                 udelay(1);
2086         }
2087         if (i >= adev->usec_timeout)
2088                 r = -ETIMEDOUT;
2089
2090 error_free_scratch:
2091         amdgpu_gfx_scratch_free(adev, scratch);
2092         return r;
2093 }
2094
2095 /**
2096  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2097  *
2098  * @adev: amdgpu_device pointer
2099  * @ridx: amdgpu ring index
2100  *
2101  * Emits an hdp flush on the cp.
2102  */
2103 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2104 {
2105         u32 ref_and_mask;
2106         int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2107
2108         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2109                 switch (ring->me) {
2110                 case 1:
2111                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2112                         break;
2113                 case 2:
2114                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2115                         break;
2116                 default:
2117                         return;
2118                 }
2119         } else {
2120                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2121         }
2122
2123         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2124         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2125                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2126                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2127         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2128         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2129         amdgpu_ring_write(ring, ref_and_mask);
2130         amdgpu_ring_write(ring, ref_and_mask);
2131         amdgpu_ring_write(ring, 0x20); /* poll interval */
2132 }
2133
2134 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2135 {
2136         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2137         amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2138                 EVENT_INDEX(4));
2139
2140         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2141         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2142                 EVENT_INDEX(0));
2143 }
2144
2145 /**
2146  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2147  *
2148  * @adev: amdgpu_device pointer
2149  * @fence: amdgpu fence object
2150  *
2151  * Emits a fence sequnce number on the gfx ring and flushes
2152  * GPU caches.
2153  */
2154 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2155                                          u64 seq, unsigned flags)
2156 {
2157         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2158         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2159         /* Workaround for cache flush problems. First send a dummy EOP
2160          * event down the pipe with seq one below.
2161          */
2162         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2163         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2164                                  EOP_TC_ACTION_EN |
2165                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2166                                  EVENT_INDEX(5)));
2167         amdgpu_ring_write(ring, addr & 0xfffffffc);
2168         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2169                                 DATA_SEL(1) | INT_SEL(0));
2170         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2171         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2172
2173         /* Then send the real EOP event down the pipe. */
2174         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2175         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2176                                  EOP_TC_ACTION_EN |
2177                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2178                                  EVENT_INDEX(5)));
2179         amdgpu_ring_write(ring, addr & 0xfffffffc);
2180         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2181                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2182         amdgpu_ring_write(ring, lower_32_bits(seq));
2183         amdgpu_ring_write(ring, upper_32_bits(seq));
2184 }
2185
2186 /**
2187  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2188  *
2189  * @adev: amdgpu_device pointer
2190  * @fence: amdgpu fence object
2191  *
2192  * Emits a fence sequnce number on the compute ring and flushes
2193  * GPU caches.
2194  */
2195 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2196                                              u64 addr, u64 seq,
2197                                              unsigned flags)
2198 {
2199         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2200         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2201
2202         /* RELEASE_MEM - flush caches, send int */
2203         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2204         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2205                                  EOP_TC_ACTION_EN |
2206                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2207                                  EVENT_INDEX(5)));
2208         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2209         amdgpu_ring_write(ring, addr & 0xfffffffc);
2210         amdgpu_ring_write(ring, upper_32_bits(addr));
2211         amdgpu_ring_write(ring, lower_32_bits(seq));
2212         amdgpu_ring_write(ring, upper_32_bits(seq));
2213 }
2214
2215 /*
2216  * IB stuff
2217  */
2218 /**
2219  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2220  *
2221  * @ring: amdgpu_ring structure holding ring information
2222  * @ib: amdgpu indirect buffer object
2223  *
2224  * Emits an DE (drawing engine) or CE (constant engine) IB
2225  * on the gfx ring.  IBs are usually generated by userspace
2226  * acceleration drivers and submitted to the kernel for
2227  * sheduling on the ring.  This function schedules the IB
2228  * on the gfx ring for execution by the GPU.
2229  */
2230 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2231                                         struct amdgpu_job *job,
2232                                         struct amdgpu_ib *ib,
2233                                         uint32_t flags)
2234 {
2235         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2236         u32 header, control = 0;
2237
2238         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2239         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2240                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2241                 amdgpu_ring_write(ring, 0);
2242         }
2243
2244         if (ib->flags & AMDGPU_IB_FLAG_CE)
2245                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2246         else
2247                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2248
2249         control |= ib->length_dw | (vmid << 24);
2250
2251         amdgpu_ring_write(ring, header);
2252         amdgpu_ring_write(ring,
2253 #ifdef __BIG_ENDIAN
2254                           (2 << 0) |
2255 #endif
2256                           (ib->gpu_addr & 0xFFFFFFFC));
2257         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2258         amdgpu_ring_write(ring, control);
2259 }
2260
2261 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2262                                           struct amdgpu_job *job,
2263                                           struct amdgpu_ib *ib,
2264                                           uint32_t flags)
2265 {
2266         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2267         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2268
2269         /* Currently, there is a high possibility to get wave ID mismatch
2270          * between ME and GDS, leading to a hw deadlock, because ME generates
2271          * different wave IDs than the GDS expects. This situation happens
2272          * randomly when at least 5 compute pipes use GDS ordered append.
2273          * The wave IDs generated by ME are also wrong after suspend/resume.
2274          * Those are probably bugs somewhere else in the kernel driver.
2275          *
2276          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2277          * GDS to 0 for this ring (me/pipe).
2278          */
2279         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2280                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2281                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
2282                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2283         }
2284
2285         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2286         amdgpu_ring_write(ring,
2287 #ifdef __BIG_ENDIAN
2288                                           (2 << 0) |
2289 #endif
2290                                           (ib->gpu_addr & 0xFFFFFFFC));
2291         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2292         amdgpu_ring_write(ring, control);
2293 }
2294
2295 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2296 {
2297         uint32_t dw2 = 0;
2298
2299         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2300         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2301                 gfx_v7_0_ring_emit_vgt_flush(ring);
2302                 /* set load_global_config & load_global_uconfig */
2303                 dw2 |= 0x8001;
2304                 /* set load_cs_sh_regs */
2305                 dw2 |= 0x01000000;
2306                 /* set load_per_context_state & load_gfx_sh_regs */
2307                 dw2 |= 0x10002;
2308         }
2309
2310         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2311         amdgpu_ring_write(ring, dw2);
2312         amdgpu_ring_write(ring, 0);
2313 }
2314
2315 /**
2316  * gfx_v7_0_ring_test_ib - basic ring IB test
2317  *
2318  * @ring: amdgpu_ring structure holding ring information
2319  *
2320  * Allocate an IB and execute it on the gfx ring (CIK).
2321  * Provides a basic gfx ring test to verify that IBs are working.
2322  * Returns 0 on success, error on failure.
2323  */
2324 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2325 {
2326         struct amdgpu_device *adev = ring->adev;
2327         struct amdgpu_ib ib;
2328         struct dma_fence *f = NULL;
2329         uint32_t scratch;
2330         uint32_t tmp = 0;
2331         long r;
2332
2333         r = amdgpu_gfx_scratch_get(adev, &scratch);
2334         if (r)
2335                 return r;
2336
2337         WREG32(scratch, 0xCAFEDEAD);
2338         memset(&ib, 0, sizeof(ib));
2339         r = amdgpu_ib_get(adev, NULL, 256, &ib);
2340         if (r)
2341                 goto err1;
2342
2343         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2344         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2345         ib.ptr[2] = 0xDEADBEEF;
2346         ib.length_dw = 3;
2347
2348         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2349         if (r)
2350                 goto err2;
2351
2352         r = dma_fence_wait_timeout(f, false, timeout);
2353         if (r == 0) {
2354                 r = -ETIMEDOUT;
2355                 goto err2;
2356         } else if (r < 0) {
2357                 goto err2;
2358         }
2359         tmp = RREG32(scratch);
2360         if (tmp == 0xDEADBEEF)
2361                 r = 0;
2362         else
2363                 r = -EINVAL;
2364
2365 err2:
2366         amdgpu_ib_free(adev, &ib, NULL);
2367         dma_fence_put(f);
2368 err1:
2369         amdgpu_gfx_scratch_free(adev, scratch);
2370         return r;
2371 }
2372
2373 /*
2374  * CP.
2375  * On CIK, gfx and compute now have independant command processors.
2376  *
2377  * GFX
2378  * Gfx consists of a single ring and can process both gfx jobs and
2379  * compute jobs.  The gfx CP consists of three microengines (ME):
2380  * PFP - Pre-Fetch Parser
2381  * ME - Micro Engine
2382  * CE - Constant Engine
2383  * The PFP and ME make up what is considered the Drawing Engine (DE).
2384  * The CE is an asynchronous engine used for updating buffer desciptors
2385  * used by the DE so that they can be loaded into cache in parallel
2386  * while the DE is processing state update packets.
2387  *
2388  * Compute
2389  * The compute CP consists of two microengines (ME):
2390  * MEC1 - Compute MicroEngine 1
2391  * MEC2 - Compute MicroEngine 2
2392  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2393  * The queues are exposed to userspace and are programmed directly
2394  * by the compute runtime.
2395  */
2396 /**
2397  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2398  *
2399  * @adev: amdgpu_device pointer
2400  * @enable: enable or disable the MEs
2401  *
2402  * Halts or unhalts the gfx MEs.
2403  */
2404 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2405 {
2406         int i;
2407
2408         if (enable) {
2409                 WREG32(mmCP_ME_CNTL, 0);
2410         } else {
2411                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2412                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2413                         adev->gfx.gfx_ring[i].sched.ready = false;
2414         }
2415         udelay(50);
2416 }
2417
2418 /**
2419  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2420  *
2421  * @adev: amdgpu_device pointer
2422  *
2423  * Loads the gfx PFP, ME, and CE ucode.
2424  * Returns 0 for success, -EINVAL if the ucode is not available.
2425  */
2426 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2427 {
2428         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2429         const struct gfx_firmware_header_v1_0 *ce_hdr;
2430         const struct gfx_firmware_header_v1_0 *me_hdr;
2431         const __le32 *fw_data;
2432         unsigned i, fw_size;
2433
2434         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2435                 return -EINVAL;
2436
2437         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2438         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2439         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2440
2441         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2442         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2443         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2444         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2445         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2446         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2447         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2448         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2449         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2450
2451         gfx_v7_0_cp_gfx_enable(adev, false);
2452
2453         /* PFP */
2454         fw_data = (const __le32 *)
2455                 (adev->gfx.pfp_fw->data +
2456                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2457         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2458         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2459         for (i = 0; i < fw_size; i++)
2460                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2461         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2462
2463         /* CE */
2464         fw_data = (const __le32 *)
2465                 (adev->gfx.ce_fw->data +
2466                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2467         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2468         WREG32(mmCP_CE_UCODE_ADDR, 0);
2469         for (i = 0; i < fw_size; i++)
2470                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2471         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2472
2473         /* ME */
2474         fw_data = (const __le32 *)
2475                 (adev->gfx.me_fw->data +
2476                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2477         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2478         WREG32(mmCP_ME_RAM_WADDR, 0);
2479         for (i = 0; i < fw_size; i++)
2480                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2481         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2482
2483         return 0;
2484 }
2485
2486 /**
2487  * gfx_v7_0_cp_gfx_start - start the gfx ring
2488  *
2489  * @adev: amdgpu_device pointer
2490  *
2491  * Enables the ring and loads the clear state context and other
2492  * packets required to init the ring.
2493  * Returns 0 for success, error for failure.
2494  */
2495 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2496 {
2497         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2498         const struct cs_section_def *sect = NULL;
2499         const struct cs_extent_def *ext = NULL;
2500         int r, i;
2501
2502         /* init the CP */
2503         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2504         WREG32(mmCP_ENDIAN_SWAP, 0);
2505         WREG32(mmCP_DEVICE_ID, 1);
2506
2507         gfx_v7_0_cp_gfx_enable(adev, true);
2508
2509         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2510         if (r) {
2511                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2512                 return r;
2513         }
2514
2515         /* init the CE partitions.  CE only used for gfx on CIK */
2516         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2517         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2518         amdgpu_ring_write(ring, 0x8000);
2519         amdgpu_ring_write(ring, 0x8000);
2520
2521         /* clear state buffer */
2522         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2523         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2524
2525         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2526         amdgpu_ring_write(ring, 0x80000000);
2527         amdgpu_ring_write(ring, 0x80000000);
2528
2529         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2530                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2531                         if (sect->id == SECT_CONTEXT) {
2532                                 amdgpu_ring_write(ring,
2533                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2534                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2535                                 for (i = 0; i < ext->reg_count; i++)
2536                                         amdgpu_ring_write(ring, ext->extent[i]);
2537                         }
2538                 }
2539         }
2540
2541         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2542         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2543         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2544         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2545
2546         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2547         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2548
2549         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2550         amdgpu_ring_write(ring, 0);
2551
2552         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2553         amdgpu_ring_write(ring, 0x00000316);
2554         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2555         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2556
2557         amdgpu_ring_commit(ring);
2558
2559         return 0;
2560 }
2561
2562 /**
2563  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2564  *
2565  * @adev: amdgpu_device pointer
2566  *
2567  * Program the location and size of the gfx ring buffer
2568  * and test it to make sure it's working.
2569  * Returns 0 for success, error for failure.
2570  */
2571 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2572 {
2573         struct amdgpu_ring *ring;
2574         u32 tmp;
2575         u32 rb_bufsz;
2576         u64 rb_addr, rptr_addr;
2577         int r;
2578
2579         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2580         if (adev->asic_type != CHIP_HAWAII)
2581                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2582
2583         /* Set the write pointer delay */
2584         WREG32(mmCP_RB_WPTR_DELAY, 0);
2585
2586         /* set the RB to use vmid 0 */
2587         WREG32(mmCP_RB_VMID, 0);
2588
2589         WREG32(mmSCRATCH_ADDR, 0);
2590
2591         /* ring 0 - compute and gfx */
2592         /* Set ring buffer size */
2593         ring = &adev->gfx.gfx_ring[0];
2594         rb_bufsz = order_base_2(ring->ring_size / 8);
2595         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2596 #ifdef __BIG_ENDIAN
2597         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2598 #endif
2599         WREG32(mmCP_RB0_CNTL, tmp);
2600
2601         /* Initialize the ring buffer's read and write pointers */
2602         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2603         ring->wptr = 0;
2604         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2605
2606         /* set the wb address wether it's enabled or not */
2607         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2608         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2609         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2610
2611         /* scratch register shadowing is no longer supported */
2612         WREG32(mmSCRATCH_UMSK, 0);
2613
2614         mdelay(1);
2615         WREG32(mmCP_RB0_CNTL, tmp);
2616
2617         rb_addr = ring->gpu_addr >> 8;
2618         WREG32(mmCP_RB0_BASE, rb_addr);
2619         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2620
2621         /* start the ring */
2622         gfx_v7_0_cp_gfx_start(adev);
2623         r = amdgpu_ring_test_helper(ring);
2624         if (r)
2625                 return r;
2626
2627         return 0;
2628 }
2629
2630 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2631 {
2632         return ring->adev->wb.wb[ring->rptr_offs];
2633 }
2634
2635 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2636 {
2637         struct amdgpu_device *adev = ring->adev;
2638
2639         return RREG32(mmCP_RB0_WPTR);
2640 }
2641
2642 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2643 {
2644         struct amdgpu_device *adev = ring->adev;
2645
2646         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2647         (void)RREG32(mmCP_RB0_WPTR);
2648 }
2649
2650 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2651 {
2652         /* XXX check if swapping is necessary on BE */
2653         return ring->adev->wb.wb[ring->wptr_offs];
2654 }
2655
2656 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2657 {
2658         struct amdgpu_device *adev = ring->adev;
2659
2660         /* XXX check if swapping is necessary on BE */
2661         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2662         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2663 }
2664
2665 /**
2666  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2667  *
2668  * @adev: amdgpu_device pointer
2669  * @enable: enable or disable the MEs
2670  *
2671  * Halts or unhalts the compute MEs.
2672  */
2673 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2674 {
2675         int i;
2676
2677         if (enable) {
2678                 WREG32(mmCP_MEC_CNTL, 0);
2679         } else {
2680                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2681                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2682                         adev->gfx.compute_ring[i].sched.ready = false;
2683         }
2684         udelay(50);
2685 }
2686
2687 /**
2688  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2689  *
2690  * @adev: amdgpu_device pointer
2691  *
2692  * Loads the compute MEC1&2 ucode.
2693  * Returns 0 for success, -EINVAL if the ucode is not available.
2694  */
2695 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2696 {
2697         const struct gfx_firmware_header_v1_0 *mec_hdr;
2698         const __le32 *fw_data;
2699         unsigned i, fw_size;
2700
2701         if (!adev->gfx.mec_fw)
2702                 return -EINVAL;
2703
2704         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2705         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2706         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2707         adev->gfx.mec_feature_version = le32_to_cpu(
2708                                         mec_hdr->ucode_feature_version);
2709
2710         gfx_v7_0_cp_compute_enable(adev, false);
2711
2712         /* MEC1 */
2713         fw_data = (const __le32 *)
2714                 (adev->gfx.mec_fw->data +
2715                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2716         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2717         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2718         for (i = 0; i < fw_size; i++)
2719                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2720         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2721
2722         if (adev->asic_type == CHIP_KAVERI) {
2723                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2724
2725                 if (!adev->gfx.mec2_fw)
2726                         return -EINVAL;
2727
2728                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2729                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2730                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2731                 adev->gfx.mec2_feature_version = le32_to_cpu(
2732                                 mec2_hdr->ucode_feature_version);
2733
2734                 /* MEC2 */
2735                 fw_data = (const __le32 *)
2736                         (adev->gfx.mec2_fw->data +
2737                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2738                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2739                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2740                 for (i = 0; i < fw_size; i++)
2741                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2742                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2743         }
2744
2745         return 0;
2746 }
2747
2748 /**
2749  * gfx_v7_0_cp_compute_fini - stop the compute queues
2750  *
2751  * @adev: amdgpu_device pointer
2752  *
2753  * Stop the compute queues and tear down the driver queue
2754  * info.
2755  */
2756 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2757 {
2758         int i;
2759
2760         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2761                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2762
2763                 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2764         }
2765 }
2766
2767 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2768 {
2769         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2770 }
2771
2772 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2773 {
2774         int r;
2775         u32 *hpd;
2776         size_t mec_hpd_size;
2777
2778         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2779
2780         /* take ownership of the relevant compute queues */
2781         amdgpu_gfx_compute_queue_acquire(adev);
2782
2783         /* allocate space for ALL pipes (even the ones we don't own) */
2784         mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2785                 * GFX7_MEC_HPD_SIZE * 2;
2786
2787         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2788                                       AMDGPU_GEM_DOMAIN_VRAM,
2789                                       &adev->gfx.mec.hpd_eop_obj,
2790                                       &adev->gfx.mec.hpd_eop_gpu_addr,
2791                                       (void **)&hpd);
2792         if (r) {
2793                 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2794                 gfx_v7_0_mec_fini(adev);
2795                 return r;
2796         }
2797
2798         /* clear memory.  Not sure if this is required or not */
2799         memset(hpd, 0, mec_hpd_size);
2800
2801         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2802         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2803
2804         return 0;
2805 }
2806
2807 struct hqd_registers
2808 {
2809         u32 cp_mqd_base_addr;
2810         u32 cp_mqd_base_addr_hi;
2811         u32 cp_hqd_active;
2812         u32 cp_hqd_vmid;
2813         u32 cp_hqd_persistent_state;
2814         u32 cp_hqd_pipe_priority;
2815         u32 cp_hqd_queue_priority;
2816         u32 cp_hqd_quantum;
2817         u32 cp_hqd_pq_base;
2818         u32 cp_hqd_pq_base_hi;
2819         u32 cp_hqd_pq_rptr;
2820         u32 cp_hqd_pq_rptr_report_addr;
2821         u32 cp_hqd_pq_rptr_report_addr_hi;
2822         u32 cp_hqd_pq_wptr_poll_addr;
2823         u32 cp_hqd_pq_wptr_poll_addr_hi;
2824         u32 cp_hqd_pq_doorbell_control;
2825         u32 cp_hqd_pq_wptr;
2826         u32 cp_hqd_pq_control;
2827         u32 cp_hqd_ib_base_addr;
2828         u32 cp_hqd_ib_base_addr_hi;
2829         u32 cp_hqd_ib_rptr;
2830         u32 cp_hqd_ib_control;
2831         u32 cp_hqd_iq_timer;
2832         u32 cp_hqd_iq_rptr;
2833         u32 cp_hqd_dequeue_request;
2834         u32 cp_hqd_dma_offload;
2835         u32 cp_hqd_sema_cmd;
2836         u32 cp_hqd_msg_type;
2837         u32 cp_hqd_atomic0_preop_lo;
2838         u32 cp_hqd_atomic0_preop_hi;
2839         u32 cp_hqd_atomic1_preop_lo;
2840         u32 cp_hqd_atomic1_preop_hi;
2841         u32 cp_hqd_hq_scheduler0;
2842         u32 cp_hqd_hq_scheduler1;
2843         u32 cp_mqd_control;
2844 };
2845
2846 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2847                                        int mec, int pipe)
2848 {
2849         u64 eop_gpu_addr;
2850         u32 tmp;
2851         size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2852                             * GFX7_MEC_HPD_SIZE * 2;
2853
2854         mutex_lock(&adev->srbm_mutex);
2855         eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2856
2857         cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2858
2859         /* write the EOP addr */
2860         WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2861         WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2862
2863         /* set the VMID assigned */
2864         WREG32(mmCP_HPD_EOP_VMID, 0);
2865
2866         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2867         tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2868         tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2869         tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2870         WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2871
2872         cik_srbm_select(adev, 0, 0, 0, 0);
2873         mutex_unlock(&adev->srbm_mutex);
2874 }
2875
2876 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2877 {
2878         int i;
2879
2880         /* disable the queue if it's active */
2881         if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2882                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2883                 for (i = 0; i < adev->usec_timeout; i++) {
2884                         if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2885                                 break;
2886                         udelay(1);
2887                 }
2888
2889                 if (i == adev->usec_timeout)
2890                         return -ETIMEDOUT;
2891
2892                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2893                 WREG32(mmCP_HQD_PQ_RPTR, 0);
2894                 WREG32(mmCP_HQD_PQ_WPTR, 0);
2895         }
2896
2897         return 0;
2898 }
2899
2900 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2901                              struct cik_mqd *mqd,
2902                              uint64_t mqd_gpu_addr,
2903                              struct amdgpu_ring *ring)
2904 {
2905         u64 hqd_gpu_addr;
2906         u64 wb_gpu_addr;
2907
2908         /* init the mqd struct */
2909         memset(mqd, 0, sizeof(struct cik_mqd));
2910
2911         mqd->header = 0xC0310800;
2912         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2913         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2914         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2915         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2916
2917         /* enable doorbell? */
2918         mqd->cp_hqd_pq_doorbell_control =
2919                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2920         if (ring->use_doorbell)
2921                 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2922         else
2923                 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2924
2925         /* set the pointer to the MQD */
2926         mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2927         mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2928
2929         /* set MQD vmid to 0 */
2930         mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2931         mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2932
2933         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2934         hqd_gpu_addr = ring->gpu_addr >> 8;
2935         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2936         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2937
2938         /* set up the HQD, this is similar to CP_RB0_CNTL */
2939         mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2940         mqd->cp_hqd_pq_control &=
2941                 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2942                                 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2943
2944         mqd->cp_hqd_pq_control |=
2945                 order_base_2(ring->ring_size / 8);
2946         mqd->cp_hqd_pq_control |=
2947                 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2948 #ifdef __BIG_ENDIAN
2949         mqd->cp_hqd_pq_control |=
2950                 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2951 #endif
2952         mqd->cp_hqd_pq_control &=
2953                 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2954                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2955                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2956         mqd->cp_hqd_pq_control |=
2957                 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2958                 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2959
2960         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2961         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2962         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2963         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2964
2965         /* set the wb address wether it's enabled or not */
2966         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2967         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2968         mqd->cp_hqd_pq_rptr_report_addr_hi =
2969                 upper_32_bits(wb_gpu_addr) & 0xffff;
2970
2971         /* enable the doorbell if requested */
2972         if (ring->use_doorbell) {
2973                 mqd->cp_hqd_pq_doorbell_control =
2974                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2975                 mqd->cp_hqd_pq_doorbell_control &=
2976                         ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2977                 mqd->cp_hqd_pq_doorbell_control |=
2978                         (ring->doorbell_index <<
2979                          CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2980                 mqd->cp_hqd_pq_doorbell_control |=
2981                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2982                 mqd->cp_hqd_pq_doorbell_control &=
2983                         ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2984                                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2985
2986         } else {
2987                 mqd->cp_hqd_pq_doorbell_control = 0;
2988         }
2989
2990         /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2991         ring->wptr = 0;
2992         mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2993         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2994
2995         /* set the vmid for the queue */
2996         mqd->cp_hqd_vmid = 0;
2997
2998         /* defaults */
2999         mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
3000         mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
3001         mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
3002         mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
3003         mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
3004         mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
3005         mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
3006         mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
3007         mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
3008         mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
3009         mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
3010         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3011         mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
3012         mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
3013         mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
3014         mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
3015
3016         /* activate the queue */
3017         mqd->cp_hqd_active = 1;
3018 }
3019
3020 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
3021 {
3022         uint32_t tmp;
3023         uint32_t mqd_reg;
3024         uint32_t *mqd_data;
3025
3026         /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3027         mqd_data = &mqd->cp_mqd_base_addr_lo;
3028
3029         /* disable wptr polling */
3030         tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3031         tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3032         WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3033
3034         /* program all HQD registers */
3035         for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3036                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3037
3038         /* activate the HQD */
3039         for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3040                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3041
3042         return 0;
3043 }
3044
3045 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3046 {
3047         int r;
3048         u64 mqd_gpu_addr;
3049         struct cik_mqd *mqd;
3050         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3051
3052         r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
3053                                       AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
3054                                       &mqd_gpu_addr, (void **)&mqd);
3055         if (r) {
3056                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3057                 return r;
3058         }
3059
3060         mutex_lock(&adev->srbm_mutex);
3061         cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3062
3063         gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3064         gfx_v7_0_mqd_deactivate(adev);
3065         gfx_v7_0_mqd_commit(adev, mqd);
3066
3067         cik_srbm_select(adev, 0, 0, 0, 0);
3068         mutex_unlock(&adev->srbm_mutex);
3069
3070         amdgpu_bo_kunmap(ring->mqd_obj);
3071         amdgpu_bo_unreserve(ring->mqd_obj);
3072         return 0;
3073 }
3074
3075 /**
3076  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3077  *
3078  * @adev: amdgpu_device pointer
3079  *
3080  * Program the compute queues and test them to make sure they
3081  * are working.
3082  * Returns 0 for success, error for failure.
3083  */
3084 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3085 {
3086         int r, i, j;
3087         u32 tmp;
3088         struct amdgpu_ring *ring;
3089
3090         /* fix up chicken bits */
3091         tmp = RREG32(mmCP_CPF_DEBUG);
3092         tmp |= (1 << 23);
3093         WREG32(mmCP_CPF_DEBUG, tmp);
3094
3095         /* init all pipes (even the ones we don't own) */
3096         for (i = 0; i < adev->gfx.mec.num_mec; i++)
3097                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3098                         gfx_v7_0_compute_pipe_init(adev, i, j);
3099
3100         /* init the queues */
3101         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3102                 r = gfx_v7_0_compute_queue_init(adev, i);
3103                 if (r) {
3104                         gfx_v7_0_cp_compute_fini(adev);
3105                         return r;
3106                 }
3107         }
3108
3109         gfx_v7_0_cp_compute_enable(adev, true);
3110
3111         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3112                 ring = &adev->gfx.compute_ring[i];
3113                 amdgpu_ring_test_helper(ring);
3114         }
3115
3116         return 0;
3117 }
3118
3119 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3120 {
3121         gfx_v7_0_cp_gfx_enable(adev, enable);
3122         gfx_v7_0_cp_compute_enable(adev, enable);
3123 }
3124
3125 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3126 {
3127         int r;
3128
3129         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3130         if (r)
3131                 return r;
3132         r = gfx_v7_0_cp_compute_load_microcode(adev);
3133         if (r)
3134                 return r;
3135
3136         return 0;
3137 }
3138
3139 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3140                                                bool enable)
3141 {
3142         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3143
3144         if (enable)
3145                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3146                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3147         else
3148                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3149                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3150         WREG32(mmCP_INT_CNTL_RING0, tmp);
3151 }
3152
3153 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3154 {
3155         int r;
3156
3157         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3158
3159         r = gfx_v7_0_cp_load_microcode(adev);
3160         if (r)
3161                 return r;
3162
3163         r = gfx_v7_0_cp_gfx_resume(adev);
3164         if (r)
3165                 return r;
3166         r = gfx_v7_0_cp_compute_resume(adev);
3167         if (r)
3168                 return r;
3169
3170         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3171
3172         return 0;
3173 }
3174
3175 /**
3176  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3177  *
3178  * @ring: the ring to emmit the commands to
3179  *
3180  * Sync the command pipeline with the PFP. E.g. wait for everything
3181  * to be completed.
3182  */
3183 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3184 {
3185         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3186         uint32_t seq = ring->fence_drv.sync_seq;
3187         uint64_t addr = ring->fence_drv.gpu_addr;
3188
3189         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3190         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3191                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3192                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3193         amdgpu_ring_write(ring, addr & 0xfffffffc);
3194         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3195         amdgpu_ring_write(ring, seq);
3196         amdgpu_ring_write(ring, 0xffffffff);
3197         amdgpu_ring_write(ring, 4); /* poll interval */
3198
3199         if (usepfp) {
3200                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3201                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3202                 amdgpu_ring_write(ring, 0);
3203                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3204                 amdgpu_ring_write(ring, 0);
3205         }
3206 }
3207
3208 /*
3209  * vm
3210  * VMID 0 is the physical GPU addresses as used by the kernel.
3211  * VMIDs 1-15 are used for userspace clients and are handled
3212  * by the amdgpu vm/hsa code.
3213  */
3214 /**
3215  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3216  *
3217  * @adev: amdgpu_device pointer
3218  *
3219  * Update the page table base and flush the VM TLB
3220  * using the CP (CIK).
3221  */
3222 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3223                                         unsigned vmid, uint64_t pd_addr)
3224 {
3225         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3226
3227         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3228
3229         /* wait for the invalidate to complete */
3230         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3231         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3232                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3233                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3234         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3235         amdgpu_ring_write(ring, 0);
3236         amdgpu_ring_write(ring, 0); /* ref */
3237         amdgpu_ring_write(ring, 0); /* mask */
3238         amdgpu_ring_write(ring, 0x20); /* poll interval */
3239
3240         /* compute doesn't have PFP */
3241         if (usepfp) {
3242                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3243                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3244                 amdgpu_ring_write(ring, 0x0);
3245
3246                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3247                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3248                 amdgpu_ring_write(ring, 0);
3249                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3250                 amdgpu_ring_write(ring, 0);
3251         }
3252 }
3253
3254 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
3255                                     uint32_t reg, uint32_t val)
3256 {
3257         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3258
3259         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3260         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3261                                  WRITE_DATA_DST_SEL(0)));
3262         amdgpu_ring_write(ring, reg);
3263         amdgpu_ring_write(ring, 0);
3264         amdgpu_ring_write(ring, val);
3265 }
3266
3267 /*
3268  * RLC
3269  * The RLC is a multi-purpose microengine that handles a
3270  * variety of functions.
3271  */
3272 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3273 {
3274         const u32 *src_ptr;
3275         u32 dws;
3276         const struct cs_section_def *cs_data;
3277         int r;
3278
3279         /* allocate rlc buffers */
3280         if (adev->flags & AMD_IS_APU) {
3281                 if (adev->asic_type == CHIP_KAVERI) {
3282                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3283                         adev->gfx.rlc.reg_list_size =
3284                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3285                 } else {
3286                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3287                         adev->gfx.rlc.reg_list_size =
3288                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3289                 }
3290         }
3291         adev->gfx.rlc.cs_data = ci_cs_data;
3292         adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3293         adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3294
3295         src_ptr = adev->gfx.rlc.reg_list;
3296         dws = adev->gfx.rlc.reg_list_size;
3297         dws += (5 * 16) + 48 + 48 + 64;
3298
3299         cs_data = adev->gfx.rlc.cs_data;
3300
3301         if (src_ptr) {
3302                 /* init save restore block */
3303                 r = amdgpu_gfx_rlc_init_sr(adev, dws);
3304                 if (r)
3305                         return r;
3306         }
3307
3308         if (cs_data) {
3309                 /* init clear state block */
3310                 r = amdgpu_gfx_rlc_init_csb(adev);
3311                 if (r)
3312                         return r;
3313         }
3314
3315         if (adev->gfx.rlc.cp_table_size) {
3316                 r = amdgpu_gfx_rlc_init_cpt(adev);
3317                 if (r)
3318                         return r;
3319         }
3320
3321         return 0;
3322 }
3323
3324 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3325 {
3326         u32 tmp;
3327
3328         tmp = RREG32(mmRLC_LB_CNTL);
3329         if (enable)
3330                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3331         else
3332                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3333         WREG32(mmRLC_LB_CNTL, tmp);
3334 }
3335
3336 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3337 {
3338         u32 i, j, k;
3339         u32 mask;
3340
3341         mutex_lock(&adev->grbm_idx_mutex);
3342         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3343                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3344                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3345                         for (k = 0; k < adev->usec_timeout; k++) {
3346                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3347                                         break;
3348                                 udelay(1);
3349                         }
3350                 }
3351         }
3352         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3353         mutex_unlock(&adev->grbm_idx_mutex);
3354
3355         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3356                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3357                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3358                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3359         for (k = 0; k < adev->usec_timeout; k++) {
3360                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3361                         break;
3362                 udelay(1);
3363         }
3364 }
3365
3366 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3367 {
3368         u32 tmp;
3369
3370         tmp = RREG32(mmRLC_CNTL);
3371         if (tmp != rlc)
3372                 WREG32(mmRLC_CNTL, rlc);
3373 }
3374
3375 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3376 {
3377         u32 data, orig;
3378
3379         orig = data = RREG32(mmRLC_CNTL);
3380
3381         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3382                 u32 i;
3383
3384                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3385                 WREG32(mmRLC_CNTL, data);
3386
3387                 for (i = 0; i < adev->usec_timeout; i++) {
3388                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3389                                 break;
3390                         udelay(1);
3391                 }
3392
3393                 gfx_v7_0_wait_for_rlc_serdes(adev);
3394         }
3395
3396         return orig;
3397 }
3398
3399 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev)
3400 {
3401         return true;
3402 }
3403
3404 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev)
3405 {
3406         u32 tmp, i, mask;
3407
3408         tmp = 0x1 | (1 << 1);
3409         WREG32(mmRLC_GPR_REG2, tmp);
3410
3411         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3412                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3413         for (i = 0; i < adev->usec_timeout; i++) {
3414                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3415                         break;
3416                 udelay(1);
3417         }
3418
3419         for (i = 0; i < adev->usec_timeout; i++) {
3420                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3421                         break;
3422                 udelay(1);
3423         }
3424 }
3425
3426 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev)
3427 {
3428         u32 tmp;
3429
3430         tmp = 0x1 | (0 << 1);
3431         WREG32(mmRLC_GPR_REG2, tmp);
3432 }
3433
3434 /**
3435  * gfx_v7_0_rlc_stop - stop the RLC ME
3436  *
3437  * @adev: amdgpu_device pointer
3438  *
3439  * Halt the RLC ME (MicroEngine) (CIK).
3440  */
3441 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3442 {
3443         WREG32(mmRLC_CNTL, 0);
3444
3445         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3446
3447         gfx_v7_0_wait_for_rlc_serdes(adev);
3448 }
3449
3450 /**
3451  * gfx_v7_0_rlc_start - start the RLC ME
3452  *
3453  * @adev: amdgpu_device pointer
3454  *
3455  * Unhalt the RLC ME (MicroEngine) (CIK).
3456  */
3457 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3458 {
3459         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3460
3461         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3462
3463         udelay(50);
3464 }
3465
3466 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3467 {
3468         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3469
3470         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3471         WREG32(mmGRBM_SOFT_RESET, tmp);
3472         udelay(50);
3473         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3474         WREG32(mmGRBM_SOFT_RESET, tmp);
3475         udelay(50);
3476 }
3477
3478 /**
3479  * gfx_v7_0_rlc_resume - setup the RLC hw
3480  *
3481  * @adev: amdgpu_device pointer
3482  *
3483  * Initialize the RLC registers, load the ucode,
3484  * and start the RLC (CIK).
3485  * Returns 0 for success, -EINVAL if the ucode is not available.
3486  */
3487 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3488 {
3489         const struct rlc_firmware_header_v1_0 *hdr;
3490         const __le32 *fw_data;
3491         unsigned i, fw_size;
3492         u32 tmp;
3493
3494         if (!adev->gfx.rlc_fw)
3495                 return -EINVAL;
3496
3497         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3498         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3499         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3500         adev->gfx.rlc_feature_version = le32_to_cpu(
3501                                         hdr->ucode_feature_version);
3502
3503         adev->gfx.rlc.funcs->stop(adev);
3504
3505         /* disable CG */
3506         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3507         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3508
3509         adev->gfx.rlc.funcs->reset(adev);
3510
3511         gfx_v7_0_init_pg(adev);
3512
3513         WREG32(mmRLC_LB_CNTR_INIT, 0);
3514         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3515
3516         mutex_lock(&adev->grbm_idx_mutex);
3517         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3518         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3519         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3520         WREG32(mmRLC_LB_CNTL, 0x80000004);
3521         mutex_unlock(&adev->grbm_idx_mutex);
3522
3523         WREG32(mmRLC_MC_CNTL, 0);
3524         WREG32(mmRLC_UCODE_CNTL, 0);
3525
3526         fw_data = (const __le32 *)
3527                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3528         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3529         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3530         for (i = 0; i < fw_size; i++)
3531                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3532         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3533
3534         /* XXX - find out what chips support lbpw */
3535         gfx_v7_0_enable_lbpw(adev, false);
3536
3537         if (adev->asic_type == CHIP_BONAIRE)
3538                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3539
3540         adev->gfx.rlc.funcs->start(adev);
3541
3542         return 0;
3543 }
3544
3545 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3546 {
3547         u32 data, orig, tmp, tmp2;
3548
3549         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3550
3551         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3552                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3553
3554                 tmp = gfx_v7_0_halt_rlc(adev);
3555
3556                 mutex_lock(&adev->grbm_idx_mutex);
3557                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3558                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3559                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3560                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3561                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3562                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3563                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3564                 mutex_unlock(&adev->grbm_idx_mutex);
3565
3566                 gfx_v7_0_update_rlc(adev, tmp);
3567
3568                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3569                 if (orig != data)
3570                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3571
3572         } else {
3573                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3574
3575                 RREG32(mmCB_CGTT_SCLK_CTRL);
3576                 RREG32(mmCB_CGTT_SCLK_CTRL);
3577                 RREG32(mmCB_CGTT_SCLK_CTRL);
3578                 RREG32(mmCB_CGTT_SCLK_CTRL);
3579
3580                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3581                 if (orig != data)
3582                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3583
3584                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3585         }
3586 }
3587
3588 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3589 {
3590         u32 data, orig, tmp = 0;
3591
3592         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3593                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3594                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3595                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3596                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3597                                 if (orig != data)
3598                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3599                         }
3600                 }
3601
3602                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3603                 data |= 0x00000001;
3604                 data &= 0xfffffffd;
3605                 if (orig != data)
3606                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3607
3608                 tmp = gfx_v7_0_halt_rlc(adev);
3609
3610                 mutex_lock(&adev->grbm_idx_mutex);
3611                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3612                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3613                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3614                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3615                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3616                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3617                 mutex_unlock(&adev->grbm_idx_mutex);
3618
3619                 gfx_v7_0_update_rlc(adev, tmp);
3620
3621                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3622                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3623                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3624                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3625                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3626                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3627                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3628                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3629                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3630                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3631                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3632                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3633                         if (orig != data)
3634                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3635                 }
3636         } else {
3637                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3638                 data |= 0x00000003;
3639                 if (orig != data)
3640                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3641
3642                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3643                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3644                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3645                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3646                 }
3647
3648                 data = RREG32(mmCP_MEM_SLP_CNTL);
3649                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3650                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3651                         WREG32(mmCP_MEM_SLP_CNTL, data);
3652                 }
3653
3654                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3655                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3656                 if (orig != data)
3657                         WREG32(mmCGTS_SM_CTRL_REG, data);
3658
3659                 tmp = gfx_v7_0_halt_rlc(adev);
3660
3661                 mutex_lock(&adev->grbm_idx_mutex);
3662                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3663                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3664                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3665                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3666                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3667                 mutex_unlock(&adev->grbm_idx_mutex);
3668
3669                 gfx_v7_0_update_rlc(adev, tmp);
3670         }
3671 }
3672
3673 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3674                                bool enable)
3675 {
3676         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3677         /* order matters! */
3678         if (enable) {
3679                 gfx_v7_0_enable_mgcg(adev, true);
3680                 gfx_v7_0_enable_cgcg(adev, true);
3681         } else {
3682                 gfx_v7_0_enable_cgcg(adev, false);
3683                 gfx_v7_0_enable_mgcg(adev, false);
3684         }
3685         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3686 }
3687
3688 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3689                                                 bool enable)
3690 {
3691         u32 data, orig;
3692
3693         orig = data = RREG32(mmRLC_PG_CNTL);
3694         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3695                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3696         else
3697                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3698         if (orig != data)
3699                 WREG32(mmRLC_PG_CNTL, data);
3700 }
3701
3702 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3703                                                 bool enable)
3704 {
3705         u32 data, orig;
3706
3707         orig = data = RREG32(mmRLC_PG_CNTL);
3708         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3709                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3710         else
3711                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3712         if (orig != data)
3713                 WREG32(mmRLC_PG_CNTL, data);
3714 }
3715
3716 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3717 {
3718         u32 data, orig;
3719
3720         orig = data = RREG32(mmRLC_PG_CNTL);
3721         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3722                 data &= ~0x8000;
3723         else
3724                 data |= 0x8000;
3725         if (orig != data)
3726                 WREG32(mmRLC_PG_CNTL, data);
3727 }
3728
3729 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3730 {
3731         u32 data, orig;
3732
3733         orig = data = RREG32(mmRLC_PG_CNTL);
3734         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3735                 data &= ~0x2000;
3736         else
3737                 data |= 0x2000;
3738         if (orig != data)
3739                 WREG32(mmRLC_PG_CNTL, data);
3740 }
3741
3742 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev)
3743 {
3744         if (adev->asic_type == CHIP_KAVERI)
3745                 return 5;
3746         else
3747                 return 4;
3748 }
3749
3750 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3751                                      bool enable)
3752 {
3753         u32 data, orig;
3754
3755         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3756                 orig = data = RREG32(mmRLC_PG_CNTL);
3757                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3758                 if (orig != data)
3759                         WREG32(mmRLC_PG_CNTL, data);
3760
3761                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3762                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3763                 if (orig != data)
3764                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3765         } else {
3766                 orig = data = RREG32(mmRLC_PG_CNTL);
3767                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3768                 if (orig != data)
3769                         WREG32(mmRLC_PG_CNTL, data);
3770
3771                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3772                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3773                 if (orig != data)
3774                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3775
3776                 data = RREG32(mmDB_RENDER_CONTROL);
3777         }
3778 }
3779
3780 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3781                                                  u32 bitmap)
3782 {
3783         u32 data;
3784
3785         if (!bitmap)
3786                 return;
3787
3788         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3789         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3790
3791         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3792 }
3793
3794 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3795 {
3796         u32 data, mask;
3797
3798         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3799         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3800
3801         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3802         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3803
3804         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3805
3806         return (~data) & mask;
3807 }
3808
3809 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3810 {
3811         u32 tmp;
3812
3813         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3814
3815         tmp = RREG32(mmRLC_MAX_PG_CU);
3816         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3817         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3818         WREG32(mmRLC_MAX_PG_CU, tmp);
3819 }
3820
3821 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3822                                             bool enable)
3823 {
3824         u32 data, orig;
3825
3826         orig = data = RREG32(mmRLC_PG_CNTL);
3827         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3828                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3829         else
3830                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3831         if (orig != data)
3832                 WREG32(mmRLC_PG_CNTL, data);
3833 }
3834
3835 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3836                                              bool enable)
3837 {
3838         u32 data, orig;
3839
3840         orig = data = RREG32(mmRLC_PG_CNTL);
3841         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3842                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3843         else
3844                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3845         if (orig != data)
3846                 WREG32(mmRLC_PG_CNTL, data);
3847 }
3848
3849 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3850 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3851
3852 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3853 {
3854         u32 data, orig;
3855         u32 i;
3856
3857         if (adev->gfx.rlc.cs_data) {
3858                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3859                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3860                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3861                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3862         } else {
3863                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3864                 for (i = 0; i < 3; i++)
3865                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3866         }
3867         if (adev->gfx.rlc.reg_list) {
3868                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3869                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3870                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3871         }
3872
3873         orig = data = RREG32(mmRLC_PG_CNTL);
3874         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3875         if (orig != data)
3876                 WREG32(mmRLC_PG_CNTL, data);
3877
3878         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3879         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3880
3881         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3882         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3883         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3884         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3885
3886         data = 0x10101010;
3887         WREG32(mmRLC_PG_DELAY, data);
3888
3889         data = RREG32(mmRLC_PG_DELAY_2);
3890         data &= ~0xff;
3891         data |= 0x3;
3892         WREG32(mmRLC_PG_DELAY_2, data);
3893
3894         data = RREG32(mmRLC_AUTO_PG_CTRL);
3895         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3896         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3897         WREG32(mmRLC_AUTO_PG_CTRL, data);
3898
3899 }
3900
3901 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3902 {
3903         gfx_v7_0_enable_gfx_cgpg(adev, enable);
3904         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3905         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3906 }
3907
3908 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3909 {
3910         u32 count = 0;
3911         const struct cs_section_def *sect = NULL;
3912         const struct cs_extent_def *ext = NULL;
3913
3914         if (adev->gfx.rlc.cs_data == NULL)
3915                 return 0;
3916
3917         /* begin clear state */
3918         count += 2;
3919         /* context control state */
3920         count += 3;
3921
3922         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3923                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3924                         if (sect->id == SECT_CONTEXT)
3925                                 count += 2 + ext->reg_count;
3926                         else
3927                                 return 0;
3928                 }
3929         }
3930         /* pa_sc_raster_config/pa_sc_raster_config1 */
3931         count += 4;
3932         /* end clear state */
3933         count += 2;
3934         /* clear state */
3935         count += 2;
3936
3937         return count;
3938 }
3939
3940 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
3941                                     volatile u32 *buffer)
3942 {
3943         u32 count = 0, i;
3944         const struct cs_section_def *sect = NULL;
3945         const struct cs_extent_def *ext = NULL;
3946
3947         if (adev->gfx.rlc.cs_data == NULL)
3948                 return;
3949         if (buffer == NULL)
3950                 return;
3951
3952         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3953         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3954
3955         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3956         buffer[count++] = cpu_to_le32(0x80000000);
3957         buffer[count++] = cpu_to_le32(0x80000000);
3958
3959         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3960                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3961                         if (sect->id == SECT_CONTEXT) {
3962                                 buffer[count++] =
3963                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3964                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3965                                 for (i = 0; i < ext->reg_count; i++)
3966                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3967                         } else {
3968                                 return;
3969                         }
3970                 }
3971         }
3972
3973         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3974         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3975         switch (adev->asic_type) {
3976         case CHIP_BONAIRE:
3977                 buffer[count++] = cpu_to_le32(0x16000012);
3978                 buffer[count++] = cpu_to_le32(0x00000000);
3979                 break;
3980         case CHIP_KAVERI:
3981                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
3982                 buffer[count++] = cpu_to_le32(0x00000000);
3983                 break;
3984         case CHIP_KABINI:
3985         case CHIP_MULLINS:
3986                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
3987                 buffer[count++] = cpu_to_le32(0x00000000);
3988                 break;
3989         case CHIP_HAWAII:
3990                 buffer[count++] = cpu_to_le32(0x3a00161a);
3991                 buffer[count++] = cpu_to_le32(0x0000002e);
3992                 break;
3993         default:
3994                 buffer[count++] = cpu_to_le32(0x00000000);
3995                 buffer[count++] = cpu_to_le32(0x00000000);
3996                 break;
3997         }
3998
3999         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4000         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4001
4002         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4003         buffer[count++] = cpu_to_le32(0);
4004 }
4005
4006 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4007 {
4008         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4009                               AMD_PG_SUPPORT_GFX_SMG |
4010                               AMD_PG_SUPPORT_GFX_DMG |
4011                               AMD_PG_SUPPORT_CP |
4012                               AMD_PG_SUPPORT_GDS |
4013                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4014                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4015                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4016                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4017                         gfx_v7_0_init_gfx_cgpg(adev);
4018                         gfx_v7_0_enable_cp_pg(adev, true);
4019                         gfx_v7_0_enable_gds_pg(adev, true);
4020                 }
4021                 gfx_v7_0_init_ao_cu_mask(adev);
4022                 gfx_v7_0_update_gfx_pg(adev, true);
4023         }
4024 }
4025
4026 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4027 {
4028         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4029                               AMD_PG_SUPPORT_GFX_SMG |
4030                               AMD_PG_SUPPORT_GFX_DMG |
4031                               AMD_PG_SUPPORT_CP |
4032                               AMD_PG_SUPPORT_GDS |
4033                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4034                 gfx_v7_0_update_gfx_pg(adev, false);
4035                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4036                         gfx_v7_0_enable_cp_pg(adev, false);
4037                         gfx_v7_0_enable_gds_pg(adev, false);
4038                 }
4039         }
4040 }
4041
4042 /**
4043  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4044  *
4045  * @adev: amdgpu_device pointer
4046  *
4047  * Fetches a GPU clock counter snapshot (SI).
4048  * Returns the 64 bit clock counter snapshot.
4049  */
4050 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4051 {
4052         uint64_t clock;
4053
4054         mutex_lock(&adev->gfx.gpu_clock_mutex);
4055         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4056         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4057                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4058         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4059         return clock;
4060 }
4061
4062 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4063                                           uint32_t vmid,
4064                                           uint32_t gds_base, uint32_t gds_size,
4065                                           uint32_t gws_base, uint32_t gws_size,
4066                                           uint32_t oa_base, uint32_t oa_size)
4067 {
4068         /* GDS Base */
4069         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4070         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4071                                 WRITE_DATA_DST_SEL(0)));
4072         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4073         amdgpu_ring_write(ring, 0);
4074         amdgpu_ring_write(ring, gds_base);
4075
4076         /* GDS Size */
4077         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4078         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4079                                 WRITE_DATA_DST_SEL(0)));
4080         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4081         amdgpu_ring_write(ring, 0);
4082         amdgpu_ring_write(ring, gds_size);
4083
4084         /* GWS */
4085         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4086         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4087                                 WRITE_DATA_DST_SEL(0)));
4088         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4089         amdgpu_ring_write(ring, 0);
4090         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4091
4092         /* OA */
4093         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4094         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4095                                 WRITE_DATA_DST_SEL(0)));
4096         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4097         amdgpu_ring_write(ring, 0);
4098         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4099 }
4100
4101 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4102 {
4103         struct amdgpu_device *adev = ring->adev;
4104         uint32_t value = 0;
4105
4106         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4107         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4108         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4109         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4110         WREG32(mmSQ_CMD, value);
4111 }
4112
4113 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4114 {
4115         WREG32(mmSQ_IND_INDEX,
4116                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4117                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4118                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4119                 (SQ_IND_INDEX__FORCE_READ_MASK));
4120         return RREG32(mmSQ_IND_DATA);
4121 }
4122
4123 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4124                            uint32_t wave, uint32_t thread,
4125                            uint32_t regno, uint32_t num, uint32_t *out)
4126 {
4127         WREG32(mmSQ_IND_INDEX,
4128                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4129                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4130                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4131                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4132                 (SQ_IND_INDEX__FORCE_READ_MASK) |
4133                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4134         while (num--)
4135                 *(out++) = RREG32(mmSQ_IND_DATA);
4136 }
4137
4138 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4139 {
4140         /* type 0 wave data */
4141         dst[(*no_fields)++] = 0;
4142         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4143         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4144         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4145         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4146         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4147         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4148         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4149         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4150         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4151         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4152         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4153         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4154         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4155         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4156         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4157         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4158         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4159         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4160 }
4161
4162 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4163                                      uint32_t wave, uint32_t start,
4164                                      uint32_t size, uint32_t *dst)
4165 {
4166         wave_read_regs(
4167                 adev, simd, wave, 0,
4168                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4169 }
4170
4171 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4172                                   u32 me, u32 pipe, u32 q, u32 vm)
4173 {
4174         cik_srbm_select(adev, me, pipe, q, vm);
4175 }
4176
4177 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4178         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4179         .select_se_sh = &gfx_v7_0_select_se_sh,
4180         .read_wave_data = &gfx_v7_0_read_wave_data,
4181         .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4182         .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
4183 };
4184
4185 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4186         .is_rlc_enabled = gfx_v7_0_is_rlc_enabled,
4187         .set_safe_mode = gfx_v7_0_set_safe_mode,
4188         .unset_safe_mode = gfx_v7_0_unset_safe_mode,
4189         .init = gfx_v7_0_rlc_init,
4190         .get_csb_size = gfx_v7_0_get_csb_size,
4191         .get_csb_buffer = gfx_v7_0_get_csb_buffer,
4192         .get_cp_table_num = gfx_v7_0_cp_pg_table_num,
4193         .resume = gfx_v7_0_rlc_resume,
4194         .stop = gfx_v7_0_rlc_stop,
4195         .reset = gfx_v7_0_rlc_reset,
4196         .start = gfx_v7_0_rlc_start
4197 };
4198
4199 static int gfx_v7_0_early_init(void *handle)
4200 {
4201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4202
4203         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4204         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4205         adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4206         adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4207         gfx_v7_0_set_ring_funcs(adev);
4208         gfx_v7_0_set_irq_funcs(adev);
4209         gfx_v7_0_set_gds_init(adev);
4210
4211         return 0;
4212 }
4213
4214 static int gfx_v7_0_late_init(void *handle)
4215 {
4216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4217         int r;
4218
4219         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4220         if (r)
4221                 return r;
4222
4223         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4224         if (r)
4225                 return r;
4226
4227         return 0;
4228 }
4229
4230 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4231 {
4232         u32 gb_addr_config;
4233         u32 mc_shared_chmap, mc_arb_ramcfg;
4234         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4235         u32 tmp;
4236
4237         switch (adev->asic_type) {
4238         case CHIP_BONAIRE:
4239                 adev->gfx.config.max_shader_engines = 2;
4240                 adev->gfx.config.max_tile_pipes = 4;
4241                 adev->gfx.config.max_cu_per_sh = 7;
4242                 adev->gfx.config.max_sh_per_se = 1;
4243                 adev->gfx.config.max_backends_per_se = 2;
4244                 adev->gfx.config.max_texture_channel_caches = 4;
4245                 adev->gfx.config.max_gprs = 256;
4246                 adev->gfx.config.max_gs_threads = 32;
4247                 adev->gfx.config.max_hw_contexts = 8;
4248
4249                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4250                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4251                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4252                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4253                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4254                 break;
4255         case CHIP_HAWAII:
4256                 adev->gfx.config.max_shader_engines = 4;
4257                 adev->gfx.config.max_tile_pipes = 16;
4258                 adev->gfx.config.max_cu_per_sh = 11;
4259                 adev->gfx.config.max_sh_per_se = 1;
4260                 adev->gfx.config.max_backends_per_se = 4;
4261                 adev->gfx.config.max_texture_channel_caches = 16;
4262                 adev->gfx.config.max_gprs = 256;
4263                 adev->gfx.config.max_gs_threads = 32;
4264                 adev->gfx.config.max_hw_contexts = 8;
4265
4266                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4267                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4268                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4269                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4270                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4271                 break;
4272         case CHIP_KAVERI:
4273                 adev->gfx.config.max_shader_engines = 1;
4274                 adev->gfx.config.max_tile_pipes = 4;
4275                 adev->gfx.config.max_cu_per_sh = 8;
4276                 adev->gfx.config.max_backends_per_se = 2;
4277                 adev->gfx.config.max_sh_per_se = 1;
4278                 adev->gfx.config.max_texture_channel_caches = 4;
4279                 adev->gfx.config.max_gprs = 256;
4280                 adev->gfx.config.max_gs_threads = 16;
4281                 adev->gfx.config.max_hw_contexts = 8;
4282
4283                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4284                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4285                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4286                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4287                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4288                 break;
4289         case CHIP_KABINI:
4290         case CHIP_MULLINS:
4291         default:
4292                 adev->gfx.config.max_shader_engines = 1;
4293                 adev->gfx.config.max_tile_pipes = 2;
4294                 adev->gfx.config.max_cu_per_sh = 2;
4295                 adev->gfx.config.max_sh_per_se = 1;
4296                 adev->gfx.config.max_backends_per_se = 1;
4297                 adev->gfx.config.max_texture_channel_caches = 2;
4298                 adev->gfx.config.max_gprs = 256;
4299                 adev->gfx.config.max_gs_threads = 16;
4300                 adev->gfx.config.max_hw_contexts = 8;
4301
4302                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4303                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4304                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4305                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4306                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4307                 break;
4308         }
4309
4310         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4311         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4312         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4313
4314         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4315         adev->gfx.config.mem_max_burst_length_bytes = 256;
4316         if (adev->flags & AMD_IS_APU) {
4317                 /* Get memory bank mapping mode. */
4318                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4319                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4320                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4321
4322                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4323                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4324                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4325
4326                 /* Validate settings in case only one DIMM installed. */
4327                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4328                         dimm00_addr_map = 0;
4329                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4330                         dimm01_addr_map = 0;
4331                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4332                         dimm10_addr_map = 0;
4333                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4334                         dimm11_addr_map = 0;
4335
4336                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4337                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4338                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4339                         adev->gfx.config.mem_row_size_in_kb = 2;
4340                 else
4341                         adev->gfx.config.mem_row_size_in_kb = 1;
4342         } else {
4343                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4344                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4345                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4346                         adev->gfx.config.mem_row_size_in_kb = 4;
4347         }
4348         /* XXX use MC settings? */
4349         adev->gfx.config.shader_engine_tile_size = 32;
4350         adev->gfx.config.num_gpus = 1;
4351         adev->gfx.config.multi_gpu_tile_size = 64;
4352
4353         /* fix up row size */
4354         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4355         switch (adev->gfx.config.mem_row_size_in_kb) {
4356         case 1:
4357         default:
4358                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4359                 break;
4360         case 2:
4361                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4362                 break;
4363         case 4:
4364                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4365                 break;
4366         }
4367         adev->gfx.config.gb_addr_config = gb_addr_config;
4368 }
4369
4370 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4371                                         int mec, int pipe, int queue)
4372 {
4373         int r;
4374         unsigned irq_type;
4375         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4376
4377         /* mec0 is me1 */
4378         ring->me = mec + 1;
4379         ring->pipe = pipe;
4380         ring->queue = queue;
4381
4382         ring->ring_obj = NULL;
4383         ring->use_doorbell = true;
4384         ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
4385         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4386
4387         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4388                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4389                 + ring->pipe;
4390
4391         /* type-2 packets are deprecated on MEC, use type-3 instead */
4392         r = amdgpu_ring_init(adev, ring, 1024,
4393                         &adev->gfx.eop_irq, irq_type);
4394         if (r)
4395                 return r;
4396
4397
4398         return 0;
4399 }
4400
4401 static int gfx_v7_0_sw_init(void *handle)
4402 {
4403         struct amdgpu_ring *ring;
4404         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4405         int i, j, k, r, ring_id;
4406
4407         switch (adev->asic_type) {
4408         case CHIP_KAVERI:
4409                 adev->gfx.mec.num_mec = 2;
4410                 break;
4411         case CHIP_BONAIRE:
4412         case CHIP_HAWAII:
4413         case CHIP_KABINI:
4414         case CHIP_MULLINS:
4415         default:
4416                 adev->gfx.mec.num_mec = 1;
4417                 break;
4418         }
4419         adev->gfx.mec.num_pipe_per_mec = 4;
4420         adev->gfx.mec.num_queue_per_pipe = 8;
4421
4422         /* EOP Event */
4423         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4424         if (r)
4425                 return r;
4426
4427         /* Privileged reg */
4428         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184,
4429                               &adev->gfx.priv_reg_irq);
4430         if (r)
4431                 return r;
4432
4433         /* Privileged inst */
4434         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185,
4435                               &adev->gfx.priv_inst_irq);
4436         if (r)
4437                 return r;
4438
4439         gfx_v7_0_scratch_init(adev);
4440
4441         r = gfx_v7_0_init_microcode(adev);
4442         if (r) {
4443                 DRM_ERROR("Failed to load gfx firmware!\n");
4444                 return r;
4445         }
4446
4447         r = adev->gfx.rlc.funcs->init(adev);
4448         if (r) {
4449                 DRM_ERROR("Failed to init rlc BOs!\n");
4450                 return r;
4451         }
4452
4453         /* allocate mec buffers */
4454         r = gfx_v7_0_mec_init(adev);
4455         if (r) {
4456                 DRM_ERROR("Failed to init MEC BOs!\n");
4457                 return r;
4458         }
4459
4460         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4461                 ring = &adev->gfx.gfx_ring[i];
4462                 ring->ring_obj = NULL;
4463                 sprintf(ring->name, "gfx");
4464                 r = amdgpu_ring_init(adev, ring, 1024,
4465                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
4466                 if (r)
4467                         return r;
4468         }
4469
4470         /* set up the compute queues - allocate horizontally across pipes */
4471         ring_id = 0;
4472         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4473                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4474                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4475                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4476                                         continue;
4477
4478                                 r = gfx_v7_0_compute_ring_init(adev,
4479                                                                 ring_id,
4480                                                                 i, k, j);
4481                                 if (r)
4482                                         return r;
4483
4484                                 ring_id++;
4485                         }
4486                 }
4487         }
4488
4489         adev->gfx.ce_ram_size = 0x8000;
4490
4491         gfx_v7_0_gpu_early_init(adev);
4492
4493         return r;
4494 }
4495
4496 static int gfx_v7_0_sw_fini(void *handle)
4497 {
4498         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4499         int i;
4500
4501         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4502                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4503         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4504                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4505
4506         gfx_v7_0_cp_compute_fini(adev);
4507         amdgpu_gfx_rlc_fini(adev);
4508         gfx_v7_0_mec_fini(adev);
4509         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4510                                 &adev->gfx.rlc.clear_state_gpu_addr,
4511                                 (void **)&adev->gfx.rlc.cs_ptr);
4512         if (adev->gfx.rlc.cp_table_size) {
4513                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4514                                 &adev->gfx.rlc.cp_table_gpu_addr,
4515                                 (void **)&adev->gfx.rlc.cp_table_ptr);
4516         }
4517         gfx_v7_0_free_microcode(adev);
4518
4519         return 0;
4520 }
4521
4522 static int gfx_v7_0_hw_init(void *handle)
4523 {
4524         int r;
4525         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4526
4527         gfx_v7_0_constants_init(adev);
4528
4529         /* init rlc */
4530         r = adev->gfx.rlc.funcs->resume(adev);
4531         if (r)
4532                 return r;
4533
4534         r = gfx_v7_0_cp_resume(adev);
4535         if (r)
4536                 return r;
4537
4538         return r;
4539 }
4540
4541 static int gfx_v7_0_hw_fini(void *handle)
4542 {
4543         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4544
4545         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4546         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4547         gfx_v7_0_cp_enable(adev, false);
4548         adev->gfx.rlc.funcs->stop(adev);
4549         gfx_v7_0_fini_pg(adev);
4550
4551         return 0;
4552 }
4553
4554 static int gfx_v7_0_suspend(void *handle)
4555 {
4556         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4557
4558         return gfx_v7_0_hw_fini(adev);
4559 }
4560
4561 static int gfx_v7_0_resume(void *handle)
4562 {
4563         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4564
4565         return gfx_v7_0_hw_init(adev);
4566 }
4567
4568 static bool gfx_v7_0_is_idle(void *handle)
4569 {
4570         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4571
4572         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4573                 return false;
4574         else
4575                 return true;
4576 }
4577
4578 static int gfx_v7_0_wait_for_idle(void *handle)
4579 {
4580         unsigned i;
4581         u32 tmp;
4582         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4583
4584         for (i = 0; i < adev->usec_timeout; i++) {
4585                 /* read MC_STATUS */
4586                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4587
4588                 if (!tmp)
4589                         return 0;
4590                 udelay(1);
4591         }
4592         return -ETIMEDOUT;
4593 }
4594
4595 static int gfx_v7_0_soft_reset(void *handle)
4596 {
4597         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4598         u32 tmp;
4599         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4600
4601         /* GRBM_STATUS */
4602         tmp = RREG32(mmGRBM_STATUS);
4603         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4604                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4605                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4606                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4607                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4608                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4609                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4610                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4611
4612         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4613                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4614                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4615         }
4616
4617         /* GRBM_STATUS2 */
4618         tmp = RREG32(mmGRBM_STATUS2);
4619         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4620                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4621
4622         /* SRBM_STATUS */
4623         tmp = RREG32(mmSRBM_STATUS);
4624         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4625                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4626
4627         if (grbm_soft_reset || srbm_soft_reset) {
4628                 /* disable CG/PG */
4629                 gfx_v7_0_fini_pg(adev);
4630                 gfx_v7_0_update_cg(adev, false);
4631
4632                 /* stop the rlc */
4633                 adev->gfx.rlc.funcs->stop(adev);
4634
4635                 /* Disable GFX parsing/prefetching */
4636                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4637
4638                 /* Disable MEC parsing/prefetching */
4639                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4640
4641                 if (grbm_soft_reset) {
4642                         tmp = RREG32(mmGRBM_SOFT_RESET);
4643                         tmp |= grbm_soft_reset;
4644                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4645                         WREG32(mmGRBM_SOFT_RESET, tmp);
4646                         tmp = RREG32(mmGRBM_SOFT_RESET);
4647
4648                         udelay(50);
4649
4650                         tmp &= ~grbm_soft_reset;
4651                         WREG32(mmGRBM_SOFT_RESET, tmp);
4652                         tmp = RREG32(mmGRBM_SOFT_RESET);
4653                 }
4654
4655                 if (srbm_soft_reset) {
4656                         tmp = RREG32(mmSRBM_SOFT_RESET);
4657                         tmp |= srbm_soft_reset;
4658                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4659                         WREG32(mmSRBM_SOFT_RESET, tmp);
4660                         tmp = RREG32(mmSRBM_SOFT_RESET);
4661
4662                         udelay(50);
4663
4664                         tmp &= ~srbm_soft_reset;
4665                         WREG32(mmSRBM_SOFT_RESET, tmp);
4666                         tmp = RREG32(mmSRBM_SOFT_RESET);
4667                 }
4668                 /* Wait a little for things to settle down */
4669                 udelay(50);
4670         }
4671         return 0;
4672 }
4673
4674 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4675                                                  enum amdgpu_interrupt_state state)
4676 {
4677         u32 cp_int_cntl;
4678
4679         switch (state) {
4680         case AMDGPU_IRQ_STATE_DISABLE:
4681                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4682                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4683                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4684                 break;
4685         case AMDGPU_IRQ_STATE_ENABLE:
4686                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4687                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4688                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4689                 break;
4690         default:
4691                 break;
4692         }
4693 }
4694
4695 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4696                                                      int me, int pipe,
4697                                                      enum amdgpu_interrupt_state state)
4698 {
4699         u32 mec_int_cntl, mec_int_cntl_reg;
4700
4701         /*
4702          * amdgpu controls only the first MEC. That's why this function only
4703          * handles the setting of interrupts for this specific MEC. All other
4704          * pipes' interrupts are set by amdkfd.
4705          */
4706
4707         if (me == 1) {
4708                 switch (pipe) {
4709                 case 0:
4710                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4711                         break;
4712                 case 1:
4713                         mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4714                         break;
4715                 case 2:
4716                         mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4717                         break;
4718                 case 3:
4719                         mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4720                         break;
4721                 default:
4722                         DRM_DEBUG("invalid pipe %d\n", pipe);
4723                         return;
4724                 }
4725         } else {
4726                 DRM_DEBUG("invalid me %d\n", me);
4727                 return;
4728         }
4729
4730         switch (state) {
4731         case AMDGPU_IRQ_STATE_DISABLE:
4732                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4733                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4734                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4735                 break;
4736         case AMDGPU_IRQ_STATE_ENABLE:
4737                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4738                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4739                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4740                 break;
4741         default:
4742                 break;
4743         }
4744 }
4745
4746 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4747                                              struct amdgpu_irq_src *src,
4748                                              unsigned type,
4749                                              enum amdgpu_interrupt_state state)
4750 {
4751         u32 cp_int_cntl;
4752
4753         switch (state) {
4754         case AMDGPU_IRQ_STATE_DISABLE:
4755                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4756                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4757                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4758                 break;
4759         case AMDGPU_IRQ_STATE_ENABLE:
4760                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4761                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4762                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4763                 break;
4764         default:
4765                 break;
4766         }
4767
4768         return 0;
4769 }
4770
4771 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4772                                               struct amdgpu_irq_src *src,
4773                                               unsigned type,
4774                                               enum amdgpu_interrupt_state state)
4775 {
4776         u32 cp_int_cntl;
4777
4778         switch (state) {
4779         case AMDGPU_IRQ_STATE_DISABLE:
4780                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4781                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4782                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4783                 break;
4784         case AMDGPU_IRQ_STATE_ENABLE:
4785                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4786                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4787                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4788                 break;
4789         default:
4790                 break;
4791         }
4792
4793         return 0;
4794 }
4795
4796 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4797                                             struct amdgpu_irq_src *src,
4798                                             unsigned type,
4799                                             enum amdgpu_interrupt_state state)
4800 {
4801         switch (type) {
4802         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4803                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4804                 break;
4805         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4806                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4807                 break;
4808         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4809                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4810                 break;
4811         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4812                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4813                 break;
4814         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4815                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4816                 break;
4817         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4818                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4819                 break;
4820         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4821                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4822                 break;
4823         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4824                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4825                 break;
4826         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4827                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4828                 break;
4829         default:
4830                 break;
4831         }
4832         return 0;
4833 }
4834
4835 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4836                             struct amdgpu_irq_src *source,
4837                             struct amdgpu_iv_entry *entry)
4838 {
4839         u8 me_id, pipe_id;
4840         struct amdgpu_ring *ring;
4841         int i;
4842
4843         DRM_DEBUG("IH: CP EOP\n");
4844         me_id = (entry->ring_id & 0x0c) >> 2;
4845         pipe_id = (entry->ring_id & 0x03) >> 0;
4846         switch (me_id) {
4847         case 0:
4848                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4849                 break;
4850         case 1:
4851         case 2:
4852                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4853                         ring = &adev->gfx.compute_ring[i];
4854                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
4855                                 amdgpu_fence_process(ring);
4856                 }
4857                 break;
4858         }
4859         return 0;
4860 }
4861
4862 static void gfx_v7_0_fault(struct amdgpu_device *adev,
4863                            struct amdgpu_iv_entry *entry)
4864 {
4865         struct amdgpu_ring *ring;
4866         u8 me_id, pipe_id;
4867         int i;
4868
4869         me_id = (entry->ring_id & 0x0c) >> 2;
4870         pipe_id = (entry->ring_id & 0x03) >> 0;
4871         switch (me_id) {
4872         case 0:
4873                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4874                 break;
4875         case 1:
4876         case 2:
4877                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4878                         ring = &adev->gfx.compute_ring[i];
4879                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
4880                                 drm_sched_fault(&ring->sched);
4881                 }
4882                 break;
4883         }
4884 }
4885
4886 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4887                                  struct amdgpu_irq_src *source,
4888                                  struct amdgpu_iv_entry *entry)
4889 {
4890         DRM_ERROR("Illegal register access in command stream\n");
4891         gfx_v7_0_fault(adev, entry);
4892         return 0;
4893 }
4894
4895 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4896                                   struct amdgpu_irq_src *source,
4897                                   struct amdgpu_iv_entry *entry)
4898 {
4899         DRM_ERROR("Illegal instruction in command stream\n");
4900         // XXX soft reset the gfx block only
4901         gfx_v7_0_fault(adev, entry);
4902         return 0;
4903 }
4904
4905 static int gfx_v7_0_set_clockgating_state(void *handle,
4906                                           enum amd_clockgating_state state)
4907 {
4908         bool gate = false;
4909         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4910
4911         if (state == AMD_CG_STATE_GATE)
4912                 gate = true;
4913
4914         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4915         /* order matters! */
4916         if (gate) {
4917                 gfx_v7_0_enable_mgcg(adev, true);
4918                 gfx_v7_0_enable_cgcg(adev, true);
4919         } else {
4920                 gfx_v7_0_enable_cgcg(adev, false);
4921                 gfx_v7_0_enable_mgcg(adev, false);
4922         }
4923         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4924
4925         return 0;
4926 }
4927
4928 static int gfx_v7_0_set_powergating_state(void *handle,
4929                                           enum amd_powergating_state state)
4930 {
4931         bool gate = false;
4932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4933
4934         if (state == AMD_PG_STATE_GATE)
4935                 gate = true;
4936
4937         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4938                               AMD_PG_SUPPORT_GFX_SMG |
4939                               AMD_PG_SUPPORT_GFX_DMG |
4940                               AMD_PG_SUPPORT_CP |
4941                               AMD_PG_SUPPORT_GDS |
4942                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4943                 gfx_v7_0_update_gfx_pg(adev, gate);
4944                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4945                         gfx_v7_0_enable_cp_pg(adev, gate);
4946                         gfx_v7_0_enable_gds_pg(adev, gate);
4947                 }
4948         }
4949
4950         return 0;
4951 }
4952
4953 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
4954         .name = "gfx_v7_0",
4955         .early_init = gfx_v7_0_early_init,
4956         .late_init = gfx_v7_0_late_init,
4957         .sw_init = gfx_v7_0_sw_init,
4958         .sw_fini = gfx_v7_0_sw_fini,
4959         .hw_init = gfx_v7_0_hw_init,
4960         .hw_fini = gfx_v7_0_hw_fini,
4961         .suspend = gfx_v7_0_suspend,
4962         .resume = gfx_v7_0_resume,
4963         .is_idle = gfx_v7_0_is_idle,
4964         .wait_for_idle = gfx_v7_0_wait_for_idle,
4965         .soft_reset = gfx_v7_0_soft_reset,
4966         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4967         .set_powergating_state = gfx_v7_0_set_powergating_state,
4968 };
4969
4970 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4971         .type = AMDGPU_RING_TYPE_GFX,
4972         .align_mask = 0xff,
4973         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4974         .support_64bit_ptrs = false,
4975         .get_rptr = gfx_v7_0_ring_get_rptr,
4976         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4977         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4978         .emit_frame_size =
4979                 20 + /* gfx_v7_0_ring_emit_gds_switch */
4980                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
4981                 5 + /* hdp invalidate */
4982                 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
4983                 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
4984                 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
4985                 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
4986         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
4987         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
4988         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
4989         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4990         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4991         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4992         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4993         .test_ring = gfx_v7_0_ring_test_ring,
4994         .test_ib = gfx_v7_0_ring_test_ib,
4995         .insert_nop = amdgpu_ring_insert_nop,
4996         .pad_ib = amdgpu_ring_generic_pad_ib,
4997         .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
4998         .emit_wreg = gfx_v7_0_ring_emit_wreg,
4999         .soft_recovery = gfx_v7_0_ring_soft_recovery,
5000 };
5001
5002 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5003         .type = AMDGPU_RING_TYPE_COMPUTE,
5004         .align_mask = 0xff,
5005         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5006         .support_64bit_ptrs = false,
5007         .get_rptr = gfx_v7_0_ring_get_rptr,
5008         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5009         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5010         .emit_frame_size =
5011                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5012                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5013                 5 + /* hdp invalidate */
5014                 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5015                 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
5016                 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5017         .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */
5018         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5019         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5020         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5021         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5022         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5023         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5024         .test_ring = gfx_v7_0_ring_test_ring,
5025         .test_ib = gfx_v7_0_ring_test_ib,
5026         .insert_nop = amdgpu_ring_insert_nop,
5027         .pad_ib = amdgpu_ring_generic_pad_ib,
5028         .emit_wreg = gfx_v7_0_ring_emit_wreg,
5029 };
5030
5031 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5032 {
5033         int i;
5034
5035         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5036                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5037         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5038                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5039 }
5040
5041 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5042         .set = gfx_v7_0_set_eop_interrupt_state,
5043         .process = gfx_v7_0_eop_irq,
5044 };
5045
5046 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5047         .set = gfx_v7_0_set_priv_reg_fault_state,
5048         .process = gfx_v7_0_priv_reg_irq,
5049 };
5050
5051 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5052         .set = gfx_v7_0_set_priv_inst_fault_state,
5053         .process = gfx_v7_0_priv_inst_irq,
5054 };
5055
5056 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5057 {
5058         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5059         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5060
5061         adev->gfx.priv_reg_irq.num_types = 1;
5062         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5063
5064         adev->gfx.priv_inst_irq.num_types = 1;
5065         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5066 }
5067
5068 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5069 {
5070         /* init asci gds info */
5071         adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
5072         adev->gds.gws_size = 64;
5073         adev->gds.oa_size = 16;
5074         adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
5075 }
5076
5077
5078 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5079 {
5080         int i, j, k, counter, active_cu_number = 0;
5081         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5082         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5083         unsigned disable_masks[4 * 2];
5084         u32 ao_cu_num;
5085
5086         if (adev->flags & AMD_IS_APU)
5087                 ao_cu_num = 2;
5088         else
5089                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5090
5091         memset(cu_info, 0, sizeof(*cu_info));
5092
5093         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5094
5095         mutex_lock(&adev->grbm_idx_mutex);
5096         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5097                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5098                         mask = 1;
5099                         ao_bitmap = 0;
5100                         counter = 0;
5101                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5102                         if (i < 4 && j < 2)
5103                                 gfx_v7_0_set_user_cu_inactive_bitmap(
5104                                         adev, disable_masks[i * 2 + j]);
5105                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5106                         cu_info->bitmap[i][j] = bitmap;
5107
5108                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5109                                 if (bitmap & mask) {
5110                                         if (counter < ao_cu_num)
5111                                                 ao_bitmap |= mask;
5112                                         counter ++;
5113                                 }
5114                                 mask <<= 1;
5115                         }
5116                         active_cu_number += counter;
5117                         if (i < 2 && j < 2)
5118                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5119                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5120                 }
5121         }
5122         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5123         mutex_unlock(&adev->grbm_idx_mutex);
5124
5125         cu_info->number = active_cu_number;
5126         cu_info->ao_cu_mask = ao_cu_mask;
5127         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5128         cu_info->max_waves_per_simd = 10;
5129         cu_info->max_scratch_slots_per_cu = 32;
5130         cu_info->wave_front_size = 64;
5131         cu_info->lds_size = 64;
5132 }
5133
5134 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5135 {
5136         .type = AMD_IP_BLOCK_TYPE_GFX,
5137         .major = 7,
5138         .minor = 0,
5139         .rev = 0,
5140         .funcs = &gfx_v7_0_ip_funcs,
5141 };
5142
5143 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5144 {
5145         .type = AMD_IP_BLOCK_TYPE_GFX,
5146         .major = 7,
5147         .minor = 1,
5148         .rev = 0,
5149         .funcs = &gfx_v7_0_ip_funcs,
5150 };
5151
5152 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5153 {
5154         .type = AMD_IP_BLOCK_TYPE_GFX,
5155         .major = 7,
5156         .minor = 2,
5157         .rev = 0,
5158         .funcs = &gfx_v7_0_ip_funcs,
5159 };
5160
5161 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5162 {
5163         .type = AMD_IP_BLOCK_TYPE_GFX,
5164         .major = 7,
5165         .minor = 3,
5166         .rev = 0,
5167         .funcs = &gfx_v7_0_ip_funcs,
5168 };