drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "cik_structs.h"
  31 #include "atom.h"
  32 #include "amdgpu_ucode.h"
  33 #include "clearstate_ci.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "bif/bif_4_1_d.h"
  39 #include "bif/bif_4_1_sh_mask.h"
  40
  41 #include "gca/gfx_7_0_d.h"
  42 #include "gca/gfx_7_2_enum.h"
  43 #include "gca/gfx_7_2_sh_mask.h"
  44
  45 #include "gmc/gmc_7_0_d.h"
  46 #include "gmc/gmc_7_0_sh_mask.h"
  47
  48 #include "oss/oss_2_0_d.h"
  49 #include "oss/oss_2_0_sh_mask.h"
  50
  51 #define GFX7_NUM_GFX_RINGS     1
  52 #define GFX7_MEC_HPD_SIZE      2048
  53
  54 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  55 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  56 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  57
  58 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  59 MODULE_FIRMWARE("radeon/bonaire_me.bin");
  60 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  61 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  62 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  63
  64 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  65 MODULE_FIRMWARE("radeon/hawaii_me.bin");
  66 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  67 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  68 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  69
  70 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  71 MODULE_FIRMWARE("radeon/kaveri_me.bin");
  72 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  73 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  74 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  75 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  76
  77 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  78 MODULE_FIRMWARE("radeon/kabini_me.bin");
  79 MODULE_FIRMWARE("radeon/kabini_ce.bin");
  80 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  81 MODULE_FIRMWARE("radeon/kabini_mec.bin");
  82
  83 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  84 MODULE_FIRMWARE("radeon/mullins_me.bin");
  85 MODULE_FIRMWARE("radeon/mullins_ce.bin");
  86 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  87 MODULE_FIRMWARE("radeon/mullins_mec.bin");
  88
  89 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  90 {
  91         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  92         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  93         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  94         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  95         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  96         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  97         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  98         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  99         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 100         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 101         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 102         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 103         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 104         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 105         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 106         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 107 };
 108
 109 static const u32 spectre_rlc_save_restore_register_list[] =
 110 {
 111         (0x0e00 << 16) | (0xc12c >> 2),
 112         0x00000000,
 113         (0x0e00 << 16) | (0xc140 >> 2),
 114         0x00000000,
 115         (0x0e00 << 16) | (0xc150 >> 2),
 116         0x00000000,
 117         (0x0e00 << 16) | (0xc15c >> 2),
 118         0x00000000,
 119         (0x0e00 << 16) | (0xc168 >> 2),
 120         0x00000000,
 121         (0x0e00 << 16) | (0xc170 >> 2),
 122         0x00000000,
 123         (0x0e00 << 16) | (0xc178 >> 2),
 124         0x00000000,
 125         (0x0e00 << 16) | (0xc204 >> 2),
 126         0x00000000,
 127         (0x0e00 << 16) | (0xc2b4 >> 2),
 128         0x00000000,
 129         (0x0e00 << 16) | (0xc2b8 >> 2),
 130         0x00000000,
 131         (0x0e00 << 16) | (0xc2bc >> 2),
 132         0x00000000,
 133         (0x0e00 << 16) | (0xc2c0 >> 2),
 134         0x00000000,
 135         (0x0e00 << 16) | (0x8228 >> 2),
 136         0x00000000,
 137         (0x0e00 << 16) | (0x829c >> 2),
 138         0x00000000,
 139         (0x0e00 << 16) | (0x869c >> 2),
 140         0x00000000,
 141         (0x0600 << 16) | (0x98f4 >> 2),
 142         0x00000000,
 143         (0x0e00 << 16) | (0x98f8 >> 2),
 144         0x00000000,
 145         (0x0e00 << 16) | (0x9900 >> 2),
 146         0x00000000,
 147         (0x0e00 << 16) | (0xc260 >> 2),
 148         0x00000000,
 149         (0x0e00 << 16) | (0x90e8 >> 2),
 150         0x00000000,
 151         (0x0e00 << 16) | (0x3c000 >> 2),
 152         0x00000000,
 153         (0x0e00 << 16) | (0x3c00c >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0x8c1c >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0x9700 >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0xcd20 >> 2),
 160         0x00000000,
 161         (0x4e00 << 16) | (0xcd20 >> 2),
 162         0x00000000,
 163         (0x5e00 << 16) | (0xcd20 >> 2),
 164         0x00000000,
 165         (0x6e00 << 16) | (0xcd20 >> 2),
 166         0x00000000,
 167         (0x7e00 << 16) | (0xcd20 >> 2),
 168         0x00000000,
 169         (0x8e00 << 16) | (0xcd20 >> 2),
 170         0x00000000,
 171         (0x9e00 << 16) | (0xcd20 >> 2),
 172         0x00000000,
 173         (0xae00 << 16) | (0xcd20 >> 2),
 174         0x00000000,
 175         (0xbe00 << 16) | (0xcd20 >> 2),
 176         0x00000000,
 177         (0x0e00 << 16) | (0x89bc >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0x8900 >> 2),
 180         0x00000000,
 181         0x3,
 182         (0x0e00 << 16) | (0xc130 >> 2),
 183         0x00000000,
 184         (0x0e00 << 16) | (0xc134 >> 2),
 185         0x00000000,
 186         (0x0e00 << 16) | (0xc1fc >> 2),
 187         0x00000000,
 188         (0x0e00 << 16) | (0xc208 >> 2),
 189         0x00000000,
 190         (0x0e00 << 16) | (0xc264 >> 2),
 191         0x00000000,
 192         (0x0e00 << 16) | (0xc268 >> 2),
 193         0x00000000,
 194         (0x0e00 << 16) | (0xc26c >> 2),
 195         0x00000000,
 196         (0x0e00 << 16) | (0xc270 >> 2),
 197         0x00000000,
 198         (0x0e00 << 16) | (0xc274 >> 2),
 199         0x00000000,
 200         (0x0e00 << 16) | (0xc278 >> 2),
 201         0x00000000,
 202         (0x0e00 << 16) | (0xc27c >> 2),
 203         0x00000000,
 204         (0x0e00 << 16) | (0xc280 >> 2),
 205         0x00000000,
 206         (0x0e00 << 16) | (0xc284 >> 2),
 207         0x00000000,
 208         (0x0e00 << 16) | (0xc288 >> 2),
 209         0x00000000,
 210         (0x0e00 << 16) | (0xc28c >> 2),
 211         0x00000000,
 212         (0x0e00 << 16) | (0xc290 >> 2),
 213         0x00000000,
 214         (0x0e00 << 16) | (0xc294 >> 2),
 215         0x00000000,
 216         (0x0e00 << 16) | (0xc298 >> 2),
 217         0x00000000,
 218         (0x0e00 << 16) | (0xc29c >> 2),
 219         0x00000000,
 220         (0x0e00 << 16) | (0xc2a0 >> 2),
 221         0x00000000,
 222         (0x0e00 << 16) | (0xc2a4 >> 2),
 223         0x00000000,
 224         (0x0e00 << 16) | (0xc2a8 >> 2),
 225         0x00000000,
 226         (0x0e00 << 16) | (0xc2ac  >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc2b0 >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0x301d0 >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0x30238 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0x30250 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0x30254 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0x30258 >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0x3025c >> 2),
 241         0x00000000,
 242         (0x4e00 << 16) | (0xc900 >> 2),
 243         0x00000000,
 244         (0x5e00 << 16) | (0xc900 >> 2),
 245         0x00000000,
 246         (0x6e00 << 16) | (0xc900 >> 2),
 247         0x00000000,
 248         (0x7e00 << 16) | (0xc900 >> 2),
 249         0x00000000,
 250         (0x8e00 << 16) | (0xc900 >> 2),
 251         0x00000000,
 252         (0x9e00 << 16) | (0xc900 >> 2),
 253         0x00000000,
 254         (0xae00 << 16) | (0xc900 >> 2),
 255         0x00000000,
 256         (0xbe00 << 16) | (0xc900 >> 2),
 257         0x00000000,
 258         (0x4e00 << 16) | (0xc904 >> 2),
 259         0x00000000,
 260         (0x5e00 << 16) | (0xc904 >> 2),
 261         0x00000000,
 262         (0x6e00 << 16) | (0xc904 >> 2),
 263         0x00000000,
 264         (0x7e00 << 16) | (0xc904 >> 2),
 265         0x00000000,
 266         (0x8e00 << 16) | (0xc904 >> 2),
 267         0x00000000,
 268         (0x9e00 << 16) | (0xc904 >> 2),
 269         0x00000000,
 270         (0xae00 << 16) | (0xc904 >> 2),
 271         0x00000000,
 272         (0xbe00 << 16) | (0xc904 >> 2),
 273         0x00000000,
 274         (0x4e00 << 16) | (0xc908 >> 2),
 275         0x00000000,
 276         (0x5e00 << 16) | (0xc908 >> 2),
 277         0x00000000,
 278         (0x6e00 << 16) | (0xc908 >> 2),
 279         0x00000000,
 280         (0x7e00 << 16) | (0xc908 >> 2),
 281         0x00000000,
 282         (0x8e00 << 16) | (0xc908 >> 2),
 283         0x00000000,
 284         (0x9e00 << 16) | (0xc908 >> 2),
 285         0x00000000,
 286         (0xae00 << 16) | (0xc908 >> 2),
 287         0x00000000,
 288         (0xbe00 << 16) | (0xc908 >> 2),
 289         0x00000000,
 290         (0x4e00 << 16) | (0xc90c >> 2),
 291         0x00000000,
 292         (0x5e00 << 16) | (0xc90c >> 2),
 293         0x00000000,
 294         (0x6e00 << 16) | (0xc90c >> 2),
 295         0x00000000,
 296         (0x7e00 << 16) | (0xc90c >> 2),
 297         0x00000000,
 298         (0x8e00 << 16) | (0xc90c >> 2),
 299         0x00000000,
 300         (0x9e00 << 16) | (0xc90c >> 2),
 301         0x00000000,
 302         (0xae00 << 16) | (0xc90c >> 2),
 303         0x00000000,
 304         (0xbe00 << 16) | (0xc90c >> 2),
 305         0x00000000,
 306         (0x4e00 << 16) | (0xc910 >> 2),
 307         0x00000000,
 308         (0x5e00 << 16) | (0xc910 >> 2),
 309         0x00000000,
 310         (0x6e00 << 16) | (0xc910 >> 2),
 311         0x00000000,
 312         (0x7e00 << 16) | (0xc910 >> 2),
 313         0x00000000,
 314         (0x8e00 << 16) | (0xc910 >> 2),
 315         0x00000000,
 316         (0x9e00 << 16) | (0xc910 >> 2),
 317         0x00000000,
 318         (0xae00 << 16) | (0xc910 >> 2),
 319         0x00000000,
 320         (0xbe00 << 16) | (0xc910 >> 2),
 321         0x00000000,
 322         (0x0e00 << 16) | (0xc99c >> 2),
 323         0x00000000,
 324         (0x0e00 << 16) | (0x9834 >> 2),
 325         0x00000000,
 326         (0x0000 << 16) | (0x30f00 >> 2),
 327         0x00000000,
 328         (0x0001 << 16) | (0x30f00 >> 2),
 329         0x00000000,
 330         (0x0000 << 16) | (0x30f04 >> 2),
 331         0x00000000,
 332         (0x0001 << 16) | (0x30f04 >> 2),
 333         0x00000000,
 334         (0x0000 << 16) | (0x30f08 >> 2),
 335         0x00000000,
 336         (0x0001 << 16) | (0x30f08 >> 2),
 337         0x00000000,
 338         (0x0000 << 16) | (0x30f0c >> 2),
 339         0x00000000,
 340         (0x0001 << 16) | (0x30f0c >> 2),
 341         0x00000000,
 342         (0x0600 << 16) | (0x9b7c >> 2),
 343         0x00000000,
 344         (0x0e00 << 16) | (0x8a14 >> 2),
 345         0x00000000,
 346         (0x0e00 << 16) | (0x8a18 >> 2),
 347         0x00000000,
 348         (0x0600 << 16) | (0x30a00 >> 2),
 349         0x00000000,
 350         (0x0e00 << 16) | (0x8bf0 >> 2),
 351         0x00000000,
 352         (0x0e00 << 16) | (0x8bcc >> 2),
 353         0x00000000,
 354         (0x0e00 << 16) | (0x8b24 >> 2),
 355         0x00000000,
 356         (0x0e00 << 16) | (0x30a04 >> 2),
 357         0x00000000,
 358         (0x0600 << 16) | (0x30a10 >> 2),
 359         0x00000000,
 360         (0x0600 << 16) | (0x30a14 >> 2),
 361         0x00000000,
 362         (0x0600 << 16) | (0x30a18 >> 2),
 363         0x00000000,
 364         (0x0600 << 16) | (0x30a2c >> 2),
 365         0x00000000,
 366         (0x0e00 << 16) | (0xc700 >> 2),
 367         0x00000000,
 368         (0x0e00 << 16) | (0xc704 >> 2),
 369         0x00000000,
 370         (0x0e00 << 16) | (0xc708 >> 2),
 371         0x00000000,
 372         (0x0e00 << 16) | (0xc768 >> 2),
 373         0x00000000,
 374         (0x0400 << 16) | (0xc770 >> 2),
 375         0x00000000,
 376         (0x0400 << 16) | (0xc774 >> 2),
 377         0x00000000,
 378         (0x0400 << 16) | (0xc778 >> 2),
 379         0x00000000,
 380         (0x0400 << 16) | (0xc77c >> 2),
 381         0x00000000,
 382         (0x0400 << 16) | (0xc780 >> 2),
 383         0x00000000,
 384         (0x0400 << 16) | (0xc784 >> 2),
 385         0x00000000,
 386         (0x0400 << 16) | (0xc788 >> 2),
 387         0x00000000,
 388         (0x0400 << 16) | (0xc78c >> 2),
 389         0x00000000,
 390         (0x0400 << 16) | (0xc798 >> 2),
 391         0x00000000,
 392         (0x0400 << 16) | (0xc79c >> 2),
 393         0x00000000,
 394         (0x0400 << 16) | (0xc7a0 >> 2),
 395         0x00000000,
 396         (0x0400 << 16) | (0xc7a4 >> 2),
 397         0x00000000,
 398         (0x0400 << 16) | (0xc7a8 >> 2),
 399         0x00000000,
 400         (0x0400 << 16) | (0xc7ac >> 2),
 401         0x00000000,
 402         (0x0400 << 16) | (0xc7b0 >> 2),
 403         0x00000000,
 404         (0x0400 << 16) | (0xc7b4 >> 2),
 405         0x00000000,
 406         (0x0e00 << 16) | (0x9100 >> 2),
 407         0x00000000,
 408         (0x0e00 << 16) | (0x3c010 >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0x92a8 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0x92ac >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0x92b4 >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0x92b8 >> 2),
 417         0x00000000,
 418         (0x0e00 << 16) | (0x92bc >> 2),
 419         0x00000000,
 420         (0x0e00 << 16) | (0x92c0 >> 2),
 421         0x00000000,
 422         (0x0e00 << 16) | (0x92c4 >> 2),
 423         0x00000000,
 424         (0x0e00 << 16) | (0x92c8 >> 2),
 425         0x00000000,
 426         (0x0e00 << 16) | (0x92cc >> 2),
 427         0x00000000,
 428         (0x0e00 << 16) | (0x92d0 >> 2),
 429         0x00000000,
 430         (0x0e00 << 16) | (0x8c00 >> 2),
 431         0x00000000,
 432         (0x0e00 << 16) | (0x8c04 >> 2),
 433         0x00000000,
 434         (0x0e00 << 16) | (0x8c20 >> 2),
 435         0x00000000,
 436         (0x0e00 << 16) | (0x8c38 >> 2),
 437         0x00000000,
 438         (0x0e00 << 16) | (0x8c3c >> 2),
 439         0x00000000,
 440         (0x0e00 << 16) | (0xae00 >> 2),
 441         0x00000000,
 442         (0x0e00 << 16) | (0x9604 >> 2),
 443         0x00000000,
 444         (0x0e00 << 16) | (0xac08 >> 2),
 445         0x00000000,
 446         (0x0e00 << 16) | (0xac0c >> 2),
 447         0x00000000,
 448         (0x0e00 << 16) | (0xac10 >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0xac14 >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0xac58 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0xac68 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0xac6c >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0xac70 >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0xac74 >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0xac78 >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0xac7c >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0xac80 >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0xac84 >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0xac88 >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0xac8c >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0x970c >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0x9714 >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x9718 >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x971c >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x31068 >> 2),
 483         0x00000000,
 484         (0x4e00 << 16) | (0x31068 >> 2),
 485         0x00000000,
 486         (0x5e00 << 16) | (0x31068 >> 2),
 487         0x00000000,
 488         (0x6e00 << 16) | (0x31068 >> 2),
 489         0x00000000,
 490         (0x7e00 << 16) | (0x31068 >> 2),
 491         0x00000000,
 492         (0x8e00 << 16) | (0x31068 >> 2),
 493         0x00000000,
 494         (0x9e00 << 16) | (0x31068 >> 2),
 495         0x00000000,
 496         (0xae00 << 16) | (0x31068 >> 2),
 497         0x00000000,
 498         (0xbe00 << 16) | (0x31068 >> 2),
 499         0x00000000,
 500         (0x0e00 << 16) | (0xcd10 >> 2),
 501         0x00000000,
 502         (0x0e00 << 16) | (0xcd14 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0x88b0 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0x88b4 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0x88b8 >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0x88bc >> 2),
 511         0x00000000,
 512         (0x0400 << 16) | (0x89c0 >> 2),
 513         0x00000000,
 514         (0x0e00 << 16) | (0x88c4 >> 2),
 515         0x00000000,
 516         (0x0e00 << 16) | (0x88c8 >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x88d0 >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x88d4 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x88d8 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x8980 >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x30938 >> 2),
 527         0x00000000,
 528         (0x0e00 << 16) | (0x3093c >> 2),
 529         0x00000000,
 530         (0x0e00 << 16) | (0x30940 >> 2),
 531         0x00000000,
 532         (0x0e00 << 16) | (0x89a0 >> 2),
 533         0x00000000,
 534         (0x0e00 << 16) | (0x30900 >> 2),
 535         0x00000000,
 536         (0x0e00 << 16) | (0x30904 >> 2),
 537         0x00000000,
 538         (0x0e00 << 16) | (0x89b4 >> 2),
 539         0x00000000,
 540         (0x0e00 << 16) | (0x3c210 >> 2),
 541         0x00000000,
 542         (0x0e00 << 16) | (0x3c214 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0x3c218 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0x8904 >> 2),
 547         0x00000000,
 548         0x5,
 549         (0x0e00 << 16) | (0x8c28 >> 2),
 550         (0x0e00 << 16) | (0x8c2c >> 2),
 551         (0x0e00 << 16) | (0x8c30 >> 2),
 552         (0x0e00 << 16) | (0x8c34 >> 2),
 553         (0x0e00 << 16) | (0x9600 >> 2),
 554 };
 555
 556 static const u32 kalindi_rlc_save_restore_register_list[] =
 557 {
 558         (0x0e00 << 16) | (0xc12c >> 2),
 559         0x00000000,
 560         (0x0e00 << 16) | (0xc140 >> 2),
 561         0x00000000,
 562         (0x0e00 << 16) | (0xc150 >> 2),
 563         0x00000000,
 564         (0x0e00 << 16) | (0xc15c >> 2),
 565         0x00000000,
 566         (0x0e00 << 16) | (0xc168 >> 2),
 567         0x00000000,
 568         (0x0e00 << 16) | (0xc170 >> 2),
 569         0x00000000,
 570         (0x0e00 << 16) | (0xc204 >> 2),
 571         0x00000000,
 572         (0x0e00 << 16) | (0xc2b4 >> 2),
 573         0x00000000,
 574         (0x0e00 << 16) | (0xc2b8 >> 2),
 575         0x00000000,
 576         (0x0e00 << 16) | (0xc2bc >> 2),
 577         0x00000000,
 578         (0x0e00 << 16) | (0xc2c0 >> 2),
 579         0x00000000,
 580         (0x0e00 << 16) | (0x8228 >> 2),
 581         0x00000000,
 582         (0x0e00 << 16) | (0x829c >> 2),
 583         0x00000000,
 584         (0x0e00 << 16) | (0x869c >> 2),
 585         0x00000000,
 586         (0x0600 << 16) | (0x98f4 >> 2),
 587         0x00000000,
 588         (0x0e00 << 16) | (0x98f8 >> 2),
 589         0x00000000,
 590         (0x0e00 << 16) | (0x9900 >> 2),
 591         0x00000000,
 592         (0x0e00 << 16) | (0xc260 >> 2),
 593         0x00000000,
 594         (0x0e00 << 16) | (0x90e8 >> 2),
 595         0x00000000,
 596         (0x0e00 << 16) | (0x3c000 >> 2),
 597         0x00000000,
 598         (0x0e00 << 16) | (0x3c00c >> 2),
 599         0x00000000,
 600         (0x0e00 << 16) | (0x8c1c >> 2),
 601         0x00000000,
 602         (0x0e00 << 16) | (0x9700 >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0xcd20 >> 2),
 605         0x00000000,
 606         (0x4e00 << 16) | (0xcd20 >> 2),
 607         0x00000000,
 608         (0x5e00 << 16) | (0xcd20 >> 2),
 609         0x00000000,
 610         (0x6e00 << 16) | (0xcd20 >> 2),
 611         0x00000000,
 612         (0x7e00 << 16) | (0xcd20 >> 2),
 613         0x00000000,
 614         (0x0e00 << 16) | (0x89bc >> 2),
 615         0x00000000,
 616         (0x0e00 << 16) | (0x8900 >> 2),
 617         0x00000000,
 618         0x3,
 619         (0x0e00 << 16) | (0xc130 >> 2),
 620         0x00000000,
 621         (0x0e00 << 16) | (0xc134 >> 2),
 622         0x00000000,
 623         (0x0e00 << 16) | (0xc1fc >> 2),
 624         0x00000000,
 625         (0x0e00 << 16) | (0xc208 >> 2),
 626         0x00000000,
 627         (0x0e00 << 16) | (0xc264 >> 2),
 628         0x00000000,
 629         (0x0e00 << 16) | (0xc268 >> 2),
 630         0x00000000,
 631         (0x0e00 << 16) | (0xc26c >> 2),
 632         0x00000000,
 633         (0x0e00 << 16) | (0xc270 >> 2),
 634         0x00000000,
 635         (0x0e00 << 16) | (0xc274 >> 2),
 636         0x00000000,
 637         (0x0e00 << 16) | (0xc28c >> 2),
 638         0x00000000,
 639         (0x0e00 << 16) | (0xc290 >> 2),
 640         0x00000000,
 641         (0x0e00 << 16) | (0xc294 >> 2),
 642         0x00000000,
 643         (0x0e00 << 16) | (0xc298 >> 2),
 644         0x00000000,
 645         (0x0e00 << 16) | (0xc2a0 >> 2),
 646         0x00000000,
 647         (0x0e00 << 16) | (0xc2a4 >> 2),
 648         0x00000000,
 649         (0x0e00 << 16) | (0xc2a8 >> 2),
 650         0x00000000,
 651         (0x0e00 << 16) | (0xc2ac >> 2),
 652         0x00000000,
 653         (0x0e00 << 16) | (0x301d0 >> 2),
 654         0x00000000,
 655         (0x0e00 << 16) | (0x30238 >> 2),
 656         0x00000000,
 657         (0x0e00 << 16) | (0x30250 >> 2),
 658         0x00000000,
 659         (0x0e00 << 16) | (0x30254 >> 2),
 660         0x00000000,
 661         (0x0e00 << 16) | (0x30258 >> 2),
 662         0x00000000,
 663         (0x0e00 << 16) | (0x3025c >> 2),
 664         0x00000000,
 665         (0x4e00 << 16) | (0xc900 >> 2),
 666         0x00000000,
 667         (0x5e00 << 16) | (0xc900 >> 2),
 668         0x00000000,
 669         (0x6e00 << 16) | (0xc900 >> 2),
 670         0x00000000,
 671         (0x7e00 << 16) | (0xc900 >> 2),
 672         0x00000000,
 673         (0x4e00 << 16) | (0xc904 >> 2),
 674         0x00000000,
 675         (0x5e00 << 16) | (0xc904 >> 2),
 676         0x00000000,
 677         (0x6e00 << 16) | (0xc904 >> 2),
 678         0x00000000,
 679         (0x7e00 << 16) | (0xc904 >> 2),
 680         0x00000000,
 681         (0x4e00 << 16) | (0xc908 >> 2),
 682         0x00000000,
 683         (0x5e00 << 16) | (0xc908 >> 2),
 684         0x00000000,
 685         (0x6e00 << 16) | (0xc908 >> 2),
 686         0x00000000,
 687         (0x7e00 << 16) | (0xc908 >> 2),
 688         0x00000000,
 689         (0x4e00 << 16) | (0xc90c >> 2),
 690         0x00000000,
 691         (0x5e00 << 16) | (0xc90c >> 2),
 692         0x00000000,
 693         (0x6e00 << 16) | (0xc90c >> 2),
 694         0x00000000,
 695         (0x7e00 << 16) | (0xc90c >> 2),
 696         0x00000000,
 697         (0x4e00 << 16) | (0xc910 >> 2),
 698         0x00000000,
 699         (0x5e00 << 16) | (0xc910 >> 2),
 700         0x00000000,
 701         (0x6e00 << 16) | (0xc910 >> 2),
 702         0x00000000,
 703         (0x7e00 << 16) | (0xc910 >> 2),
 704         0x00000000,
 705         (0x0e00 << 16) | (0xc99c >> 2),
 706         0x00000000,
 707         (0x0e00 << 16) | (0x9834 >> 2),
 708         0x00000000,
 709         (0x0000 << 16) | (0x30f00 >> 2),
 710         0x00000000,
 711         (0x0000 << 16) | (0x30f04 >> 2),
 712         0x00000000,
 713         (0x0000 << 16) | (0x30f08 >> 2),
 714         0x00000000,
 715         (0x0000 << 16) | (0x30f0c >> 2),
 716         0x00000000,
 717         (0x0600 << 16) | (0x9b7c >> 2),
 718         0x00000000,
 719         (0x0e00 << 16) | (0x8a14 >> 2),
 720         0x00000000,
 721         (0x0e00 << 16) | (0x8a18 >> 2),
 722         0x00000000,
 723         (0x0600 << 16) | (0x30a00 >> 2),
 724         0x00000000,
 725         (0x0e00 << 16) | (0x8bf0 >> 2),
 726         0x00000000,
 727         (0x0e00 << 16) | (0x8bcc >> 2),
 728         0x00000000,
 729         (0x0e00 << 16) | (0x8b24 >> 2),
 730         0x00000000,
 731         (0x0e00 << 16) | (0x30a04 >> 2),
 732         0x00000000,
 733         (0x0600 << 16) | (0x30a10 >> 2),
 734         0x00000000,
 735         (0x0600 << 16) | (0x30a14 >> 2),
 736         0x00000000,
 737         (0x0600 << 16) | (0x30a18 >> 2),
 738         0x00000000,
 739         (0x0600 << 16) | (0x30a2c >> 2),
 740         0x00000000,
 741         (0x0e00 << 16) | (0xc700 >> 2),
 742         0x00000000,
 743         (0x0e00 << 16) | (0xc704 >> 2),
 744         0x00000000,
 745         (0x0e00 << 16) | (0xc708 >> 2),
 746         0x00000000,
 747         (0x0e00 << 16) | (0xc768 >> 2),
 748         0x00000000,
 749         (0x0400 << 16) | (0xc770 >> 2),
 750         0x00000000,
 751         (0x0400 << 16) | (0xc774 >> 2),
 752         0x00000000,
 753         (0x0400 << 16) | (0xc798 >> 2),
 754         0x00000000,
 755         (0x0400 << 16) | (0xc79c >> 2),
 756         0x00000000,
 757         (0x0e00 << 16) | (0x9100 >> 2),
 758         0x00000000,
 759         (0x0e00 << 16) | (0x3c010 >> 2),
 760         0x00000000,
 761         (0x0e00 << 16) | (0x8c00 >> 2),
 762         0x00000000,
 763         (0x0e00 << 16) | (0x8c04 >> 2),
 764         0x00000000,
 765         (0x0e00 << 16) | (0x8c20 >> 2),
 766         0x00000000,
 767         (0x0e00 << 16) | (0x8c38 >> 2),
 768         0x00000000,
 769         (0x0e00 << 16) | (0x8c3c >> 2),
 770         0x00000000,
 771         (0x0e00 << 16) | (0xae00 >> 2),
 772         0x00000000,
 773         (0x0e00 << 16) | (0x9604 >> 2),
 774         0x00000000,
 775         (0x0e00 << 16) | (0xac08 >> 2),
 776         0x00000000,
 777         (0x0e00 << 16) | (0xac0c >> 2),
 778         0x00000000,
 779         (0x0e00 << 16) | (0xac10 >> 2),
 780         0x00000000,
 781         (0x0e00 << 16) | (0xac14 >> 2),
 782         0x00000000,
 783         (0x0e00 << 16) | (0xac58 >> 2),
 784         0x00000000,
 785         (0x0e00 << 16) | (0xac68 >> 2),
 786         0x00000000,
 787         (0x0e00 << 16) | (0xac6c >> 2),
 788         0x00000000,
 789         (0x0e00 << 16) | (0xac70 >> 2),
 790         0x00000000,
 791         (0x0e00 << 16) | (0xac74 >> 2),
 792         0x00000000,
 793         (0x0e00 << 16) | (0xac78 >> 2),
 794         0x00000000,
 795         (0x0e00 << 16) | (0xac7c >> 2),
 796         0x00000000,
 797         (0x0e00 << 16) | (0xac80 >> 2),
 798         0x00000000,
 799         (0x0e00 << 16) | (0xac84 >> 2),
 800         0x00000000,
 801         (0x0e00 << 16) | (0xac88 >> 2),
 802         0x00000000,
 803         (0x0e00 << 16) | (0xac8c >> 2),
 804         0x00000000,
 805         (0x0e00 << 16) | (0x970c >> 2),
 806         0x00000000,
 807         (0x0e00 << 16) | (0x9714 >> 2),
 808         0x00000000,
 809         (0x0e00 << 16) | (0x9718 >> 2),
 810         0x00000000,
 811         (0x0e00 << 16) | (0x971c >> 2),
 812         0x00000000,
 813         (0x0e00 << 16) | (0x31068 >> 2),
 814         0x00000000,
 815         (0x4e00 << 16) | (0x31068 >> 2),
 816         0x00000000,
 817         (0x5e00 << 16) | (0x31068 >> 2),
 818         0x00000000,
 819         (0x6e00 << 16) | (0x31068 >> 2),
 820         0x00000000,
 821         (0x7e00 << 16) | (0x31068 >> 2),
 822         0x00000000,
 823         (0x0e00 << 16) | (0xcd10 >> 2),
 824         0x00000000,
 825         (0x0e00 << 16) | (0xcd14 >> 2),
 826         0x00000000,
 827         (0x0e00 << 16) | (0x88b0 >> 2),
 828         0x00000000,
 829         (0x0e00 << 16) | (0x88b4 >> 2),
 830         0x00000000,
 831         (0x0e00 << 16) | (0x88b8 >> 2),
 832         0x00000000,
 833         (0x0e00 << 16) | (0x88bc >> 2),
 834         0x00000000,
 835         (0x0400 << 16) | (0x89c0 >> 2),
 836         0x00000000,
 837         (0x0e00 << 16) | (0x88c4 >> 2),
 838         0x00000000,
 839         (0x0e00 << 16) | (0x88c8 >> 2),
 840         0x00000000,
 841         (0x0e00 << 16) | (0x88d0 >> 2),
 842         0x00000000,
 843         (0x0e00 << 16) | (0x88d4 >> 2),
 844         0x00000000,
 845         (0x0e00 << 16) | (0x88d8 >> 2),
 846         0x00000000,
 847         (0x0e00 << 16) | (0x8980 >> 2),
 848         0x00000000,
 849         (0x0e00 << 16) | (0x30938 >> 2),
 850         0x00000000,
 851         (0x0e00 << 16) | (0x3093c >> 2),
 852         0x00000000,
 853         (0x0e00 << 16) | (0x30940 >> 2),
 854         0x00000000,
 855         (0x0e00 << 16) | (0x89a0 >> 2),
 856         0x00000000,
 857         (0x0e00 << 16) | (0x30900 >> 2),
 858         0x00000000,
 859         (0x0e00 << 16) | (0x30904 >> 2),
 860         0x00000000,
 861         (0x0e00 << 16) | (0x89b4 >> 2),
 862         0x00000000,
 863         (0x0e00 << 16) | (0x3e1fc >> 2),
 864         0x00000000,
 865         (0x0e00 << 16) | (0x3c210 >> 2),
 866         0x00000000,
 867         (0x0e00 << 16) | (0x3c214 >> 2),
 868         0x00000000,
 869         (0x0e00 << 16) | (0x3c218 >> 2),
 870         0x00000000,
 871         (0x0e00 << 16) | (0x8904 >> 2),
 872         0x00000000,
 873         0x5,
 874         (0x0e00 << 16) | (0x8c28 >> 2),
 875         (0x0e00 << 16) | (0x8c2c >> 2),
 876         (0x0e00 << 16) | (0x8c30 >> 2),
 877         (0x0e00 << 16) | (0x8c34 >> 2),
 878         (0x0e00 << 16) | (0x9600 >> 2),
 879 };
 880
 881 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 882 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 883 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 884 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 885 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 886
 887 /*
 888  * Core functions
 889  */
 890 /**
 891  * gfx_v7_0_init_microcode - load ucode images from disk
 892  *
 893  * @adev: amdgpu_device pointer
 894  *
 895  * Use the firmware interface to load the ucode images into
 896  * the driver (not loaded into hw).
 897  * Returns 0 on success, error on failure.
 898  */
 899 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 900 {
 901         const char *chip_name;
 902         char fw_name[30];
 903         int err;
 904
 905         DRM_DEBUG("\n");
 906
 907         switch (adev->asic_type) {
 908         case CHIP_BONAIRE:
 909                 chip_name = "bonaire";
 910                 break;
 911         case CHIP_HAWAII:
 912                 chip_name = "hawaii";
 913                 break;
 914         case CHIP_KAVERI:
 915                 chip_name = "kaveri";
 916                 break;
 917         case CHIP_KABINI:
 918                 chip_name = "kabini";
 919                 break;
 920         case CHIP_MULLINS:
 921                 chip_name = "mullins";
 922                 break;
 923         default: BUG();
 924         }
 925
 926         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 927         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 928         if (err)
 929                 goto out;
 930         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 931         if (err)
 932                 goto out;
 933
 934         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 935         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 936         if (err)
 937                 goto out;
 938         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 939         if (err)
 940                 goto out;
 941
 942         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 943         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 944         if (err)
 945                 goto out;
 946         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 947         if (err)
 948                 goto out;
 949
 950         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 951         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 952         if (err)
 953                 goto out;
 954         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 955         if (err)
 956                 goto out;
 957
 958         if (adev->asic_type == CHIP_KAVERI) {
 959                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 960                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 961                 if (err)
 962                         goto out;
 963                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 964                 if (err)
 965                         goto out;
 966         }
 967
 968         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 969         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 970         if (err)
 971                 goto out;
 972         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 973
 974 out:
 975         if (err) {
 976                 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
 977                 release_firmware(adev->gfx.pfp_fw);
 978                 adev->gfx.pfp_fw = NULL;
 979                 release_firmware(adev->gfx.me_fw);
 980                 adev->gfx.me_fw = NULL;
 981                 release_firmware(adev->gfx.ce_fw);
 982                 adev->gfx.ce_fw = NULL;
 983                 release_firmware(adev->gfx.mec_fw);
 984                 adev->gfx.mec_fw = NULL;
 985                 release_firmware(adev->gfx.mec2_fw);
 986                 adev->gfx.mec2_fw = NULL;
 987                 release_firmware(adev->gfx.rlc_fw);
 988                 adev->gfx.rlc_fw = NULL;
 989         }
 990         return err;
 991 }
 992
 993 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 994 {
 995         release_firmware(adev->gfx.pfp_fw);
 996         adev->gfx.pfp_fw = NULL;
 997         release_firmware(adev->gfx.me_fw);
 998         adev->gfx.me_fw = NULL;
 999         release_firmware(adev->gfx.ce_fw);
1000         adev->gfx.ce_fw = NULL;
1001         release_firmware(adev->gfx.mec_fw);
1002         adev->gfx.mec_fw = NULL;
1003         release_firmware(adev->gfx.mec2_fw);
1004         adev->gfx.mec2_fw = NULL;
1005         release_firmware(adev->gfx.rlc_fw);
1006         adev->gfx.rlc_fw = NULL;
1007 }
1008
1009 /**
1010  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1011  *
1012  * @adev: amdgpu_device pointer
1013  *
1014  * Starting with SI, the tiling setup is done globally in a
1015  * set of 32 tiling modes.  Rather than selecting each set of
1016  * parameters per surface as on older asics, we just select
1017  * which index in the tiling table we want to use, and the
1018  * surface uses those parameters (CIK).
1019  */
1020 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1021 {
1022         const u32 num_tile_mode_states =
1023                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1024         const u32 num_secondary_tile_mode_states =
1025                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1026         u32 reg_offset, split_equal_to_row_size;
1027         uint32_t *tile, *macrotile;
1028
1029         tile = adev->gfx.config.tile_mode_array;
1030         macrotile = adev->gfx.config.macrotile_mode_array;
1031
1032         switch (adev->gfx.config.mem_row_size_in_kb) {
1033         case 1:
1034                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1035                 break;
1036         case 2:
1037         default:
1038                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1039                 break;
1040         case 4:
1041                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1042                 break;
1043         }
1044
1045         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1046                 tile[reg_offset] = 0;
1047         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1048                 macrotile[reg_offset] = 0;
1049
1050         switch (adev->asic_type) {
1051         case CHIP_BONAIRE:
1052                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1053                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1054                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1055                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1056                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1057                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1058                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1059                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1063                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1064                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1065                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1066                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1067                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1068                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1070                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1071                            TILE_SPLIT(split_equal_to_row_size));
1072                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1073                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1074                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1075                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1076                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1077                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1078                            TILE_SPLIT(split_equal_to_row_size));
1079                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1080                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1081                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1082                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1083                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1085                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1088                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1089                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1090                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1091                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1092                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1093                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1094                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1095                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1096                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1097                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1098                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1099                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1100                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1101                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1102                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1103                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1104                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1105                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1106                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1109                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1110                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1111                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1115                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1116                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1117                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1118                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1120                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1121                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1122                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1123                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1124                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1125                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1126                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1127                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1128                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1129                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1130                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1131                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1133                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1134                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1135                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1137                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1138                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1139                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1140                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1141                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1142                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1143                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1144                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1145                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1147                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1148                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1149                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1150                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1151                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1152                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1153                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1154
1155                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1156                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1157                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1158                                 NUM_BANKS(ADDR_SURF_16_BANK));
1159                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1161                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1162                                 NUM_BANKS(ADDR_SURF_16_BANK));
1163                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1164                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1165                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1166                                 NUM_BANKS(ADDR_SURF_16_BANK));
1167                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1169                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1170                                 NUM_BANKS(ADDR_SURF_16_BANK));
1171                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1172                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1173                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1174                                 NUM_BANKS(ADDR_SURF_16_BANK));
1175                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1177                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1178                                 NUM_BANKS(ADDR_SURF_8_BANK));
1179                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1182                                 NUM_BANKS(ADDR_SURF_4_BANK));
1183                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1184                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1185                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1186                                 NUM_BANKS(ADDR_SURF_16_BANK));
1187                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1188                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1189                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1190                                 NUM_BANKS(ADDR_SURF_16_BANK));
1191                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1192                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1193                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1194                                 NUM_BANKS(ADDR_SURF_16_BANK));
1195                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1197                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1198                                 NUM_BANKS(ADDR_SURF_16_BANK));
1199                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1201                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1202                                 NUM_BANKS(ADDR_SURF_16_BANK));
1203                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1204                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1205                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1206                                 NUM_BANKS(ADDR_SURF_8_BANK));
1207                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1209                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1210                                 NUM_BANKS(ADDR_SURF_4_BANK));
1211
1212                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1213                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1214                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1215                         if (reg_offset != 7)
1216                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1217                 break;
1218         case CHIP_HAWAII:
1219                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1220                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1221                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1222                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1223                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1224                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1225                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1226                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1227                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1229                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1230                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1231                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1233                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1234                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1235                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1236                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1237                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1238                            TILE_SPLIT(split_equal_to_row_size));
1239                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1240                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1241                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1242                            TILE_SPLIT(split_equal_to_row_size));
1243                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1244                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1245                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1246                            TILE_SPLIT(split_equal_to_row_size));
1247                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1248                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1249                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1250                            TILE_SPLIT(split_equal_to_row_size));
1251                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1252                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1253                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1256                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1259                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1261                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1263                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1264                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1265                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1266                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1267                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1269                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1270                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1271                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1273                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1274                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1275                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1276                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1277                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1278                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1279                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1280                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1282                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1283                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1284                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1285                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1286                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1287                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1288                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1290                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1292                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1293                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1294                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1295                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1296                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1297                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1298                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1299                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1300                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1301                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1302                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1303                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1304                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1305                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1306                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1307                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1308                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1309                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1310                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1311                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1313                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1314                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1315                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1317                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1318                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1319                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1320                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1321                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1322                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1323                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1324                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1325                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1326                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1327                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1328                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1329                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1330                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1331                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1332                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1333                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1334                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1335                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1336                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1337
1338                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1339                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1340                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1341                                 NUM_BANKS(ADDR_SURF_16_BANK));
1342                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1343                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1344                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1345                                 NUM_BANKS(ADDR_SURF_16_BANK));
1346                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1347                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1348                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1349                                 NUM_BANKS(ADDR_SURF_16_BANK));
1350                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1351                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1352                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1353                                 NUM_BANKS(ADDR_SURF_16_BANK));
1354                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1355                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1356                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1357                                 NUM_BANKS(ADDR_SURF_8_BANK));
1358                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1359                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1360                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1361                                 NUM_BANKS(ADDR_SURF_4_BANK));
1362                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1363                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1364                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1365                                 NUM_BANKS(ADDR_SURF_4_BANK));
1366                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1367                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1368                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1369                                 NUM_BANKS(ADDR_SURF_16_BANK));
1370                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1371                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1372                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1373                                 NUM_BANKS(ADDR_SURF_16_BANK));
1374                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1375                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1376                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1377                                 NUM_BANKS(ADDR_SURF_16_BANK));
1378                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1379                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1380                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1381                                 NUM_BANKS(ADDR_SURF_8_BANK));
1382                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1383                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1384                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1385                                 NUM_BANKS(ADDR_SURF_16_BANK));
1386                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1387                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1388                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1389                                 NUM_BANKS(ADDR_SURF_8_BANK));
1390                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1391                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1392                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1393                                 NUM_BANKS(ADDR_SURF_4_BANK));
1394
1395                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1396                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1397                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1398                         if (reg_offset != 7)
1399                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1400                 break;
1401         case CHIP_KABINI:
1402         case CHIP_KAVERI:
1403         case CHIP_MULLINS:
1404         default:
1405                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1406                            PIPE_CONFIG(ADDR_SURF_P2) |
1407                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1408                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1409                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1410                            PIPE_CONFIG(ADDR_SURF_P2) |
1411                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1412                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1414                            PIPE_CONFIG(ADDR_SURF_P2) |
1415                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1416                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1417                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1418                            PIPE_CONFIG(ADDR_SURF_P2) |
1419                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1420                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1421                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1422                            PIPE_CONFIG(ADDR_SURF_P2) |
1423                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1424                            TILE_SPLIT(split_equal_to_row_size));
1425                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1426                            PIPE_CONFIG(ADDR_SURF_P2) |
1427                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1428                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1429                            PIPE_CONFIG(ADDR_SURF_P2) |
1430                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1431                            TILE_SPLIT(split_equal_to_row_size));
1432                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1433                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1434                            PIPE_CONFIG(ADDR_SURF_P2));
1435                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1436                            PIPE_CONFIG(ADDR_SURF_P2) |
1437                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1438                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1439                             PIPE_CONFIG(ADDR_SURF_P2) |
1440                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1441                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1442                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1443                             PIPE_CONFIG(ADDR_SURF_P2) |
1444                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1445                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1446                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1447                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1448                             PIPE_CONFIG(ADDR_SURF_P2) |
1449                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1450                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1451                             PIPE_CONFIG(ADDR_SURF_P2) |
1452                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1453                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1454                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1455                             PIPE_CONFIG(ADDR_SURF_P2) |
1456                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1457                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1458                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1459                             PIPE_CONFIG(ADDR_SURF_P2) |
1460                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1461                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1462                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1463                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1464                             PIPE_CONFIG(ADDR_SURF_P2) |
1465                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1466                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1468                             PIPE_CONFIG(ADDR_SURF_P2) |
1469                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1470                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1471                             PIPE_CONFIG(ADDR_SURF_P2) |
1472                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1473                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1474                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1475                             PIPE_CONFIG(ADDR_SURF_P2) |
1476                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1477                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1478                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1479                             PIPE_CONFIG(ADDR_SURF_P2) |
1480                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1481                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1482                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1483                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1484                             PIPE_CONFIG(ADDR_SURF_P2) |
1485                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1486                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1487                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1488                             PIPE_CONFIG(ADDR_SURF_P2) |
1489                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1490                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1491                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1492                             PIPE_CONFIG(ADDR_SURF_P2) |
1493                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1494                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1495                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1496                             PIPE_CONFIG(ADDR_SURF_P2) |
1497                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1498                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1499                             PIPE_CONFIG(ADDR_SURF_P2) |
1500                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1501                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1502                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1503                             PIPE_CONFIG(ADDR_SURF_P2) |
1504                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1505                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1506                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1507
1508                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1510                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1511                                 NUM_BANKS(ADDR_SURF_8_BANK));
1512                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1513                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1514                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1515                                 NUM_BANKS(ADDR_SURF_8_BANK));
1516                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1517                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1518                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1519                                 NUM_BANKS(ADDR_SURF_8_BANK));
1520                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1521                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1522                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1523                                 NUM_BANKS(ADDR_SURF_8_BANK));
1524                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1525                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1526                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1527                                 NUM_BANKS(ADDR_SURF_8_BANK));
1528                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1529                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1530                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1531                                 NUM_BANKS(ADDR_SURF_8_BANK));
1532                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1534                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535                                 NUM_BANKS(ADDR_SURF_8_BANK));
1536                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1537                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1538                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1539                                 NUM_BANKS(ADDR_SURF_16_BANK));
1540                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1541                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1542                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1543                                 NUM_BANKS(ADDR_SURF_16_BANK));
1544                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1545                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1546                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1547                                 NUM_BANKS(ADDR_SURF_16_BANK));
1548                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1549                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1550                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1551                                 NUM_BANKS(ADDR_SURF_16_BANK));
1552                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1553                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1554                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1555                                 NUM_BANKS(ADDR_SURF_16_BANK));
1556                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1559                                 NUM_BANKS(ADDR_SURF_16_BANK));
1560                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1561                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1562                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1563                                 NUM_BANKS(ADDR_SURF_8_BANK));
1564
1565                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1566                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1567                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1568                         if (reg_offset != 7)
1569                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1570                 break;
1571         }
1572 }
1573
1574 /**
1575  * gfx_v7_0_select_se_sh - select which SE, SH to address
1576  *
1577  * @adev: amdgpu_device pointer
1578  * @se_num: shader engine to address
1579  * @sh_num: sh block to address
1580  *
1581  * Select which SE, SH combinations to address. Certain
1582  * registers are instanced per SE or SH.  0xffffffff means
1583  * broadcast to all SEs or SHs (CIK).
1584  */
1585 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1586                                   u32 se_num, u32 sh_num, u32 instance)
1587 {
1588         u32 data;
1589
1590         if (instance == 0xffffffff)
1591                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1592         else
1593                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1594
1595         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1596                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1597                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1598         else if (se_num == 0xffffffff)
1599                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1600                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1601         else if (sh_num == 0xffffffff)
1602                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1603                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1604         else
1605                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1606                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1607         WREG32(mmGRBM_GFX_INDEX, data);
1608 }
1609
1610 /**
1611  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1612  *
1613  * @adev: amdgpu_device pointer
1614  *
1615  * Calculates the bitmask of enabled RBs (CIK).
1616  * Returns the enabled RB bitmask.
1617  */
1618 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1619 {
1620         u32 data, mask;
1621
1622         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1623         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1624
1625         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1626         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1627
1628         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1629                                          adev->gfx.config.max_sh_per_se);
1630
1631         return (~data) & mask;
1632 }
1633
1634 static void
1635 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1636 {
1637         switch (adev->asic_type) {
1638         case CHIP_BONAIRE:
1639                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1640                           SE_XSEL(1) | SE_YSEL(1);
1641                 *rconf1 |= 0x0;
1642                 break;
1643         case CHIP_HAWAII:
1644                 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1645                           RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1646                           PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1647                           SE_YSEL(3);
1648                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1649                            SE_PAIR_YSEL(2);
1650                 break;
1651         case CHIP_KAVERI:
1652                 *rconf |= RB_MAP_PKR0(2);
1653                 *rconf1 |= 0x0;
1654                 break;
1655         case CHIP_KABINI:
1656         case CHIP_MULLINS:
1657                 *rconf |= 0x0;
1658                 *rconf1 |= 0x0;
1659                 break;
1660         default:
1661                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1662                 break;
1663         }
1664 }
1665
1666 static void
1667 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1668                                         u32 raster_config, u32 raster_config_1,
1669                                         unsigned rb_mask, unsigned num_rb)
1670 {
1671         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1672         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1673         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1674         unsigned rb_per_se = num_rb / num_se;
1675         unsigned se_mask[4];
1676         unsigned se;
1677
1678         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1679         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1680         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1681         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1682
1683         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1684         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1685         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1686
1687         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1688                              (!se_mask[2] && !se_mask[3]))) {
1689                 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1690
1691                 if (!se_mask[0] && !se_mask[1]) {
1692                         raster_config_1 |=
1693                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1694                 } else {
1695                         raster_config_1 |=
1696                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1697                 }
1698         }
1699
1700         for (se = 0; se < num_se; se++) {
1701                 unsigned raster_config_se = raster_config;
1702                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1703                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1704                 int idx = (se / 2) * 2;
1705
1706                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1707                         raster_config_se &= ~SE_MAP_MASK;
1708
1709                         if (!se_mask[idx]) {
1710                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1711                         } else {
1712                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1713                         }
1714                 }
1715
1716                 pkr0_mask &= rb_mask;
1717                 pkr1_mask &= rb_mask;
1718                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1719                         raster_config_se &= ~PKR_MAP_MASK;
1720
1721                         if (!pkr0_mask) {
1722                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1723                         } else {
1724                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1725                         }
1726                 }
1727
1728                 if (rb_per_se >= 2) {
1729                         unsigned rb0_mask = 1 << (se * rb_per_se);
1730                         unsigned rb1_mask = rb0_mask << 1;
1731
1732                         rb0_mask &= rb_mask;
1733                         rb1_mask &= rb_mask;
1734                         if (!rb0_mask || !rb1_mask) {
1735                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
1736
1737                                 if (!rb0_mask) {
1738                                         raster_config_se |=
1739                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1740                                 } else {
1741                                         raster_config_se |=
1742                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1743                                 }
1744                         }
1745
1746                         if (rb_per_se > 2) {
1747                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1748                                 rb1_mask = rb0_mask << 1;
1749                                 rb0_mask &= rb_mask;
1750                                 rb1_mask &= rb_mask;
1751                                 if (!rb0_mask || !rb1_mask) {
1752                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
1753
1754                                         if (!rb0_mask) {
1755                                                 raster_config_se |=
1756                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1757                                         } else {
1758                                                 raster_config_se |=
1759                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1760                                         }
1761                                 }
1762                         }
1763                 }
1764
1765                 /* GRBM_GFX_INDEX has a different offset on CI+ */
1766                 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1767                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1768                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1769         }
1770
1771         /* GRBM_GFX_INDEX has a different offset on CI+ */
1772         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1773 }
1774
1775 /**
1776  * gfx_v7_0_setup_rb - setup the RBs on the asic
1777  *
1778  * @adev: amdgpu_device pointer
1779  * @se_num: number of SEs (shader engines) for the asic
1780  * @sh_per_se: number of SH blocks per SE for the asic
1781  *
1782  * Configures per-SE/SH RB registers (CIK).
1783  */
1784 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1785 {
1786         int i, j;
1787         u32 data;
1788         u32 raster_config = 0, raster_config_1 = 0;
1789         u32 active_rbs = 0;
1790         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1791                                         adev->gfx.config.max_sh_per_se;
1792         unsigned num_rb_pipes;
1793
1794         mutex_lock(&adev->grbm_idx_mutex);
1795         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1796                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1797                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1798                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1799                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1800                                                rb_bitmap_width_per_sh);
1801                 }
1802         }
1803         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1804
1805         adev->gfx.config.backend_enable_mask = active_rbs;
1806         adev->gfx.config.num_rbs = hweight32(active_rbs);
1807
1808         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1809                              adev->gfx.config.max_shader_engines, 16);
1810
1811         gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1812
1813         if (!adev->gfx.config.backend_enable_mask ||
1814                         adev->gfx.config.num_rbs >= num_rb_pipes) {
1815                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1816                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1817         } else {
1818                 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1819                                                         adev->gfx.config.backend_enable_mask,
1820                                                         num_rb_pipes);
1821         }
1822
1823         /* cache the values for userspace */
1824         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1825                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1826                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1827                         adev->gfx.config.rb_config[i][j].rb_backend_disable =
1828                                 RREG32(mmCC_RB_BACKEND_DISABLE);
1829                         adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1830                                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1831                         adev->gfx.config.rb_config[i][j].raster_config =
1832                                 RREG32(mmPA_SC_RASTER_CONFIG);
1833                         adev->gfx.config.rb_config[i][j].raster_config_1 =
1834                                 RREG32(mmPA_SC_RASTER_CONFIG_1);
1835                 }
1836         }
1837         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1838         mutex_unlock(&adev->grbm_idx_mutex);
1839 }
1840
1841 /**
1842  * gfx_v7_0_init_compute_vmid - gart enable
1843  *
1844  * @adev: amdgpu_device pointer
1845  *
1846  * Initialize compute vmid sh_mem registers
1847  *
1848  */
1849 #define DEFAULT_SH_MEM_BASES    (0x6000)
1850 #define FIRST_COMPUTE_VMID      (8)
1851 #define LAST_COMPUTE_VMID       (16)
1852 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1853 {
1854         int i;
1855         uint32_t sh_mem_config;
1856         uint32_t sh_mem_bases;
1857
1858         /*
1859          * Configure apertures:
1860          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1861          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1862          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1863         */
1864         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1865         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1866                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1867         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1868         mutex_lock(&adev->srbm_mutex);
1869         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1870                 cik_srbm_select(adev, 0, 0, 0, i);
1871                 /* CP and shaders */
1872                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1873                 WREG32(mmSH_MEM_APE1_BASE, 1);
1874                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1875                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1876         }
1877         cik_srbm_select(adev, 0, 0, 0, 0);
1878         mutex_unlock(&adev->srbm_mutex);
1879 }
1880
1881 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1882 {
1883         adev->gfx.config.double_offchip_lds_buf = 1;
1884 }
1885
1886 /**
1887  * gfx_v7_0_gpu_init - setup the 3D engine
1888  *
1889  * @adev: amdgpu_device pointer
1890  *
1891  * Configures the 3D engine and tiling configuration
1892  * registers so that the 3D engine is usable.
1893  */
1894 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1895 {
1896         u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1897         u32 tmp;
1898         int i;
1899
1900         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1901
1902         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1903         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1904         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1905
1906         gfx_v7_0_tiling_mode_table_init(adev);
1907
1908         gfx_v7_0_setup_rb(adev);
1909         gfx_v7_0_get_cu_info(adev);
1910         gfx_v7_0_config_init(adev);
1911
1912         /* set HW defaults for 3D engine */
1913         WREG32(mmCP_MEQ_THRESHOLDS,
1914                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1915                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1916
1917         mutex_lock(&adev->grbm_idx_mutex);
1918         /*
1919          * making sure that the following register writes will be broadcasted
1920          * to all the shaders
1921          */
1922         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1923
1924         /* XXX SH_MEM regs */
1925         /* where to put LDS, scratch, GPUVM in FSA64 space */
1926         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1927                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1928         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1929                                    MTYPE_NC);
1930         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1931                                    MTYPE_UC);
1932         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1933
1934         sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1935                                    SWIZZLE_ENABLE, 1);
1936         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1937                                    ELEMENT_SIZE, 1);
1938         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1939                                    INDEX_STRIDE, 3);
1940         WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1941
1942         mutex_lock(&adev->srbm_mutex);
1943         for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1944                 if (i == 0)
1945                         sh_mem_base = 0;
1946                 else
1947                         sh_mem_base = adev->mc.shared_aperture_start >> 48;
1948                 cik_srbm_select(adev, 0, 0, 0, i);
1949                 /* CP and shaders */
1950                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1951                 WREG32(mmSH_MEM_APE1_BASE, 1);
1952                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1953                 WREG32(mmSH_MEM_BASES, sh_mem_base);
1954         }
1955         cik_srbm_select(adev, 0, 0, 0, 0);
1956         mutex_unlock(&adev->srbm_mutex);
1957
1958         gfx_v7_0_init_compute_vmid(adev);
1959
1960         WREG32(mmSX_DEBUG_1, 0x20);
1961
1962         WREG32(mmTA_CNTL_AUX, 0x00010000);
1963
1964         tmp = RREG32(mmSPI_CONFIG_CNTL);
1965         tmp |= 0x03000000;
1966         WREG32(mmSPI_CONFIG_CNTL, tmp);
1967
1968         WREG32(mmSQ_CONFIG, 1);
1969
1970         WREG32(mmDB_DEBUG, 0);
1971
1972         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1973         tmp |= 0x00000400;
1974         WREG32(mmDB_DEBUG2, tmp);
1975
1976         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1977         tmp |= 0x00020200;
1978         WREG32(mmDB_DEBUG3, tmp);
1979
1980         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1981         tmp |= 0x00018208;
1982         WREG32(mmCB_HW_CONTROL, tmp);
1983
1984         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1985
1986         WREG32(mmPA_SC_FIFO_SIZE,
1987                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1988                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1989                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1990                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1991
1992         WREG32(mmVGT_NUM_INSTANCES, 1);
1993
1994         WREG32(mmCP_PERFMON_CNTL, 0);
1995
1996         WREG32(mmSQ_CONFIG, 0);
1997
1998         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1999                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2000                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2001
2002         WREG32(mmVGT_CACHE_INVALIDATION,
2003                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2004                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2005
2006         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2007         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2008
2009         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2010                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2011         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2012
2013         tmp = RREG32(mmSPI_ARB_PRIORITY);
2014         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
2015         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2016         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2017         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2018         WREG32(mmSPI_ARB_PRIORITY, tmp);
2019
2020         mutex_unlock(&adev->grbm_idx_mutex);
2021
2022         udelay(50);
2023 }
2024
2025 /*
2026  * GPU scratch registers helpers function.
2027  */
2028 /**
2029  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2030  *
2031  * @adev: amdgpu_device pointer
2032  *
2033  * Set up the number and offset of the CP scratch registers.
2034  * NOTE: use of CP scratch registers is a legacy inferface and
2035  * is not used by default on newer asics (r6xx+).  On newer asics,
2036  * memory buffers are used for fences rather than scratch regs.
2037  */
2038 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2039 {
2040         adev->gfx.scratch.num_reg = 8;
2041         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2042         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2043 }
2044
2045 /**
2046  * gfx_v7_0_ring_test_ring - basic gfx ring test
2047  *
2048  * @adev: amdgpu_device pointer
2049  * @ring: amdgpu_ring structure holding ring information
2050  *
2051  * Allocate a scratch register and write to it using the gfx ring (CIK).
2052  * Provides a basic gfx ring test to verify that the ring is working.
2053  * Used by gfx_v7_0_cp_gfx_resume();
2054  * Returns 0 on success, error on failure.
2055  */
2056 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2057 {
2058         struct amdgpu_device *adev = ring->adev;
2059         uint32_t scratch;
2060         uint32_t tmp = 0;
2061         unsigned i;
2062         int r;
2063
2064         r = amdgpu_gfx_scratch_get(adev, &scratch);
2065         if (r) {
2066                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2067                 return r;
2068         }
2069         WREG32(scratch, 0xCAFEDEAD);
2070         r = amdgpu_ring_alloc(ring, 3);
2071         if (r) {
2072                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2073                 amdgpu_gfx_scratch_free(adev, scratch);
2074                 return r;
2075         }
2076         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2077         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2078         amdgpu_ring_write(ring, 0xDEADBEEF);
2079         amdgpu_ring_commit(ring);
2080
2081         for (i = 0; i < adev->usec_timeout; i++) {
2082                 tmp = RREG32(scratch);
2083                 if (tmp == 0xDEADBEEF)
2084                         break;
2085                 DRM_UDELAY(1);
2086         }
2087         if (i < adev->usec_timeout) {
2088                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2089         } else {
2090                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2091                           ring->idx, scratch, tmp);
2092                 r = -EINVAL;
2093         }
2094         amdgpu_gfx_scratch_free(adev, scratch);
2095         return r;
2096 }
2097
2098 /**
2099  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2100  *
2101  * @adev: amdgpu_device pointer
2102  * @ridx: amdgpu ring index
2103  *
2104  * Emits an hdp flush on the cp.
2105  */
2106 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2107 {
2108         u32 ref_and_mask;
2109         int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2110
2111         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2112                 switch (ring->me) {
2113                 case 1:
2114                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2115                         break;
2116                 case 2:
2117                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2118                         break;
2119                 default:
2120                         return;
2121                 }
2122         } else {
2123                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2124         }
2125
2126         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2127         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2128                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2129                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2130         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2131         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2132         amdgpu_ring_write(ring, ref_and_mask);
2133         amdgpu_ring_write(ring, ref_and_mask);
2134         amdgpu_ring_write(ring, 0x20); /* poll interval */
2135 }
2136
2137 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2138 {
2139         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2140         amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2141                 EVENT_INDEX(4));
2142
2143         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2144         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2145                 EVENT_INDEX(0));
2146 }
2147
2148
2149 /**
2150  * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2151  *
2152  * @adev: amdgpu_device pointer
2153  * @ridx: amdgpu ring index
2154  *
2155  * Emits an hdp invalidate on the cp.
2156  */
2157 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2158 {
2159         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2160         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2161                                  WRITE_DATA_DST_SEL(0) |
2162                                  WR_CONFIRM));
2163         amdgpu_ring_write(ring, mmHDP_DEBUG0);
2164         amdgpu_ring_write(ring, 0);
2165         amdgpu_ring_write(ring, 1);
2166 }
2167
2168 /**
2169  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2170  *
2171  * @adev: amdgpu_device pointer
2172  * @fence: amdgpu fence object
2173  *
2174  * Emits a fence sequnce number on the gfx ring and flushes
2175  * GPU caches.
2176  */
2177 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2178                                          u64 seq, unsigned flags)
2179 {
2180         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2181         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2182         /* Workaround for cache flush problems. First send a dummy EOP
2183          * event down the pipe with seq one below.
2184          */
2185         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2186         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2187                                  EOP_TC_ACTION_EN |
2188                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2189                                  EVENT_INDEX(5)));
2190         amdgpu_ring_write(ring, addr & 0xfffffffc);
2191         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2192                                 DATA_SEL(1) | INT_SEL(0));
2193         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2194         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2195
2196         /* Then send the real EOP event down the pipe. */
2197         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2198         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2199                                  EOP_TC_ACTION_EN |
2200                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2201                                  EVENT_INDEX(5)));
2202         amdgpu_ring_write(ring, addr & 0xfffffffc);
2203         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2204                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2205         amdgpu_ring_write(ring, lower_32_bits(seq));
2206         amdgpu_ring_write(ring, upper_32_bits(seq));
2207 }
2208
2209 /**
2210  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2211  *
2212  * @adev: amdgpu_device pointer
2213  * @fence: amdgpu fence object
2214  *
2215  * Emits a fence sequnce number on the compute ring and flushes
2216  * GPU caches.
2217  */
2218 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2219                                              u64 addr, u64 seq,
2220                                              unsigned flags)
2221 {
2222         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2223         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2224
2225         /* RELEASE_MEM - flush caches, send int */
2226         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2227         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2228                                  EOP_TC_ACTION_EN |
2229                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2230                                  EVENT_INDEX(5)));
2231         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2232         amdgpu_ring_write(ring, addr & 0xfffffffc);
2233         amdgpu_ring_write(ring, upper_32_bits(addr));
2234         amdgpu_ring_write(ring, lower_32_bits(seq));
2235         amdgpu_ring_write(ring, upper_32_bits(seq));
2236 }
2237
2238 /*
2239  * IB stuff
2240  */
2241 /**
2242  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2243  *
2244  * @ring: amdgpu_ring structure holding ring information
2245  * @ib: amdgpu indirect buffer object
2246  *
2247  * Emits an DE (drawing engine) or CE (constant engine) IB
2248  * on the gfx ring.  IBs are usually generated by userspace
2249  * acceleration drivers and submitted to the kernel for
2250  * sheduling on the ring.  This function schedules the IB
2251  * on the gfx ring for execution by the GPU.
2252  */
2253 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2254                                       struct amdgpu_ib *ib,
2255                                       unsigned vm_id, bool ctx_switch)
2256 {
2257         u32 header, control = 0;
2258
2259         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2260         if (ctx_switch) {
2261                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2262                 amdgpu_ring_write(ring, 0);
2263         }
2264
2265         if (ib->flags & AMDGPU_IB_FLAG_CE)
2266                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2267         else
2268                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2269
2270         control |= ib->length_dw | (vm_id << 24);
2271
2272         amdgpu_ring_write(ring, header);
2273         amdgpu_ring_write(ring,
2274 #ifdef __BIG_ENDIAN
2275                           (2 << 0) |
2276 #endif
2277                           (ib->gpu_addr & 0xFFFFFFFC));
2278         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2279         amdgpu_ring_write(ring, control);
2280 }
2281
2282 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2283                                           struct amdgpu_ib *ib,
2284                                           unsigned vm_id, bool ctx_switch)
2285 {
2286         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2287
2288         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2289         amdgpu_ring_write(ring,
2290 #ifdef __BIG_ENDIAN
2291                                           (2 << 0) |
2292 #endif
2293                                           (ib->gpu_addr & 0xFFFFFFFC));
2294         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2295         amdgpu_ring_write(ring, control);
2296 }
2297
2298 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2299 {
2300         uint32_t dw2 = 0;
2301
2302         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2303         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2304                 gfx_v7_0_ring_emit_vgt_flush(ring);
2305                 /* set load_global_config & load_global_uconfig */
2306                 dw2 |= 0x8001;
2307                 /* set load_cs_sh_regs */
2308                 dw2 |= 0x01000000;
2309                 /* set load_per_context_state & load_gfx_sh_regs */
2310                 dw2 |= 0x10002;
2311         }
2312
2313         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2314         amdgpu_ring_write(ring, dw2);
2315         amdgpu_ring_write(ring, 0);
2316 }
2317
2318 /**
2319  * gfx_v7_0_ring_test_ib - basic ring IB test
2320  *
2321  * @ring: amdgpu_ring structure holding ring information
2322  *
2323  * Allocate an IB and execute it on the gfx ring (CIK).
2324  * Provides a basic gfx ring test to verify that IBs are working.
2325  * Returns 0 on success, error on failure.
2326  */
2327 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2328 {
2329         struct amdgpu_device *adev = ring->adev;
2330         struct amdgpu_ib ib;
2331         struct dma_fence *f = NULL;
2332         uint32_t scratch;
2333         uint32_t tmp = 0;
2334         long r;
2335
2336         r = amdgpu_gfx_scratch_get(adev, &scratch);
2337         if (r) {
2338                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2339                 return r;
2340         }
2341         WREG32(scratch, 0xCAFEDEAD);
2342         memset(&ib, 0, sizeof(ib));
2343         r = amdgpu_ib_get(adev, NULL, 256, &ib);
2344         if (r) {
2345                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2346                 goto err1;
2347         }
2348         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2349         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2350         ib.ptr[2] = 0xDEADBEEF;
2351         ib.length_dw = 3;
2352
2353         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2354         if (r)
2355                 goto err2;
2356
2357         r = dma_fence_wait_timeout(f, false, timeout);
2358         if (r == 0) {
2359                 DRM_ERROR("amdgpu: IB test timed out\n");
2360                 r = -ETIMEDOUT;
2361                 goto err2;
2362         } else if (r < 0) {
2363                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2364                 goto err2;
2365         }
2366         tmp = RREG32(scratch);
2367         if (tmp == 0xDEADBEEF) {
2368                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
2369                 r = 0;
2370         } else {
2371                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2372                           scratch, tmp);
2373                 r = -EINVAL;
2374         }
2375
2376 err2:
2377         amdgpu_ib_free(adev, &ib, NULL);
2378         dma_fence_put(f);
2379 err1:
2380         amdgpu_gfx_scratch_free(adev, scratch);
2381         return r;
2382 }
2383
2384 /*
2385  * CP.
2386  * On CIK, gfx and compute now have independant command processors.
2387  *
2388  * GFX
2389  * Gfx consists of a single ring and can process both gfx jobs and
2390  * compute jobs.  The gfx CP consists of three microengines (ME):
2391  * PFP - Pre-Fetch Parser
2392  * ME - Micro Engine
2393  * CE - Constant Engine
2394  * The PFP and ME make up what is considered the Drawing Engine (DE).
2395  * The CE is an asynchronous engine used for updating buffer desciptors
2396  * used by the DE so that they can be loaded into cache in parallel
2397  * while the DE is processing state update packets.
2398  *
2399  * Compute
2400  * The compute CP consists of two microengines (ME):
2401  * MEC1 - Compute MicroEngine 1
2402  * MEC2 - Compute MicroEngine 2
2403  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2404  * The queues are exposed to userspace and are programmed directly
2405  * by the compute runtime.
2406  */
2407 /**
2408  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2409  *
2410  * @adev: amdgpu_device pointer
2411  * @enable: enable or disable the MEs
2412  *
2413  * Halts or unhalts the gfx MEs.
2414  */
2415 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2416 {
2417         int i;
2418
2419         if (enable) {
2420                 WREG32(mmCP_ME_CNTL, 0);
2421         } else {
2422                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2423                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2424                         adev->gfx.gfx_ring[i].ready = false;
2425         }
2426         udelay(50);
2427 }
2428
2429 /**
2430  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2431  *
2432  * @adev: amdgpu_device pointer
2433  *
2434  * Loads the gfx PFP, ME, and CE ucode.
2435  * Returns 0 for success, -EINVAL if the ucode is not available.
2436  */
2437 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2438 {
2439         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2440         const struct gfx_firmware_header_v1_0 *ce_hdr;
2441         const struct gfx_firmware_header_v1_0 *me_hdr;
2442         const __le32 *fw_data;
2443         unsigned i, fw_size;
2444
2445         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2446                 return -EINVAL;
2447
2448         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2449         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2450         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2451
2452         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2453         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2454         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2455         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2456         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2457         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2458         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2459         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2460         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2461
2462         gfx_v7_0_cp_gfx_enable(adev, false);
2463
2464         /* PFP */
2465         fw_data = (const __le32 *)
2466                 (adev->gfx.pfp_fw->data +
2467                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2468         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2469         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2470         for (i = 0; i < fw_size; i++)
2471                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2472         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2473
2474         /* CE */
2475         fw_data = (const __le32 *)
2476                 (adev->gfx.ce_fw->data +
2477                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2478         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2479         WREG32(mmCP_CE_UCODE_ADDR, 0);
2480         for (i = 0; i < fw_size; i++)
2481                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2482         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2483
2484         /* ME */
2485         fw_data = (const __le32 *)
2486                 (adev->gfx.me_fw->data +
2487                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2488         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2489         WREG32(mmCP_ME_RAM_WADDR, 0);
2490         for (i = 0; i < fw_size; i++)
2491                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2492         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2493
2494         return 0;
2495 }
2496
2497 /**
2498  * gfx_v7_0_cp_gfx_start - start the gfx ring
2499  *
2500  * @adev: amdgpu_device pointer
2501  *
2502  * Enables the ring and loads the clear state context and other
2503  * packets required to init the ring.
2504  * Returns 0 for success, error for failure.
2505  */
2506 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2507 {
2508         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2509         const struct cs_section_def *sect = NULL;
2510         const struct cs_extent_def *ext = NULL;
2511         int r, i;
2512
2513         /* init the CP */
2514         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2515         WREG32(mmCP_ENDIAN_SWAP, 0);
2516         WREG32(mmCP_DEVICE_ID, 1);
2517
2518         gfx_v7_0_cp_gfx_enable(adev, true);
2519
2520         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2521         if (r) {
2522                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2523                 return r;
2524         }
2525
2526         /* init the CE partitions.  CE only used for gfx on CIK */
2527         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2528         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2529         amdgpu_ring_write(ring, 0x8000);
2530         amdgpu_ring_write(ring, 0x8000);
2531
2532         /* clear state buffer */
2533         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2534         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2535
2536         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2537         amdgpu_ring_write(ring, 0x80000000);
2538         amdgpu_ring_write(ring, 0x80000000);
2539
2540         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2541                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2542                         if (sect->id == SECT_CONTEXT) {
2543                                 amdgpu_ring_write(ring,
2544                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2545                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2546                                 for (i = 0; i < ext->reg_count; i++)
2547                                         amdgpu_ring_write(ring, ext->extent[i]);
2548                         }
2549                 }
2550         }
2551
2552         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2553         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2554         switch (adev->asic_type) {
2555         case CHIP_BONAIRE:
2556                 amdgpu_ring_write(ring, 0x16000012);
2557                 amdgpu_ring_write(ring, 0x00000000);
2558                 break;
2559         case CHIP_KAVERI:
2560                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2561                 amdgpu_ring_write(ring, 0x00000000);
2562                 break;
2563         case CHIP_KABINI:
2564         case CHIP_MULLINS:
2565                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2566                 amdgpu_ring_write(ring, 0x00000000);
2567                 break;
2568         case CHIP_HAWAII:
2569                 amdgpu_ring_write(ring, 0x3a00161a);
2570                 amdgpu_ring_write(ring, 0x0000002e);
2571                 break;
2572         default:
2573                 amdgpu_ring_write(ring, 0x00000000);
2574                 amdgpu_ring_write(ring, 0x00000000);
2575                 break;
2576         }
2577
2578         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2579         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2580
2581         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2582         amdgpu_ring_write(ring, 0);
2583
2584         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2585         amdgpu_ring_write(ring, 0x00000316);
2586         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2587         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2588
2589         amdgpu_ring_commit(ring);
2590
2591         return 0;
2592 }
2593
2594 /**
2595  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2596  *
2597  * @adev: amdgpu_device pointer
2598  *
2599  * Program the location and size of the gfx ring buffer
2600  * and test it to make sure it's working.
2601  * Returns 0 for success, error for failure.
2602  */
2603 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2604 {
2605         struct amdgpu_ring *ring;
2606         u32 tmp;
2607         u32 rb_bufsz;
2608         u64 rb_addr, rptr_addr;
2609         int r;
2610
2611         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2612         if (adev->asic_type != CHIP_HAWAII)
2613                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2614
2615         /* Set the write pointer delay */
2616         WREG32(mmCP_RB_WPTR_DELAY, 0);
2617
2618         /* set the RB to use vmid 0 */
2619         WREG32(mmCP_RB_VMID, 0);
2620
2621         WREG32(mmSCRATCH_ADDR, 0);
2622
2623         /* ring 0 - compute and gfx */
2624         /* Set ring buffer size */
2625         ring = &adev->gfx.gfx_ring[0];
2626         rb_bufsz = order_base_2(ring->ring_size / 8);
2627         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2628 #ifdef __BIG_ENDIAN
2629         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2630 #endif
2631         WREG32(mmCP_RB0_CNTL, tmp);
2632
2633         /* Initialize the ring buffer's read and write pointers */
2634         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2635         ring->wptr = 0;
2636         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2637
2638         /* set the wb address wether it's enabled or not */
2639         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2640         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2641         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2642
2643         /* scratch register shadowing is no longer supported */
2644         WREG32(mmSCRATCH_UMSK, 0);
2645
2646         mdelay(1);
2647         WREG32(mmCP_RB0_CNTL, tmp);
2648
2649         rb_addr = ring->gpu_addr >> 8;
2650         WREG32(mmCP_RB0_BASE, rb_addr);
2651         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2652
2653         /* start the ring */
2654         gfx_v7_0_cp_gfx_start(adev);
2655         ring->ready = true;
2656         r = amdgpu_ring_test_ring(ring);
2657         if (r) {
2658                 ring->ready = false;
2659                 return r;
2660         }
2661
2662         return 0;
2663 }
2664
2665 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2666 {
2667         return ring->adev->wb.wb[ring->rptr_offs];
2668 }
2669
2670 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2671 {
2672         struct amdgpu_device *adev = ring->adev;
2673
2674         return RREG32(mmCP_RB0_WPTR);
2675 }
2676
2677 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2678 {
2679         struct amdgpu_device *adev = ring->adev;
2680
2681         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2682         (void)RREG32(mmCP_RB0_WPTR);
2683 }
2684
2685 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2686 {
2687         /* XXX check if swapping is necessary on BE */
2688         return ring->adev->wb.wb[ring->wptr_offs];
2689 }
2690
2691 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2692 {
2693         struct amdgpu_device *adev = ring->adev;
2694
2695         /* XXX check if swapping is necessary on BE */
2696         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2697         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2698 }
2699
2700 /**
2701  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2702  *
2703  * @adev: amdgpu_device pointer
2704  * @enable: enable or disable the MEs
2705  *
2706  * Halts or unhalts the compute MEs.
2707  */
2708 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2709 {
2710         int i;
2711
2712         if (enable) {
2713                 WREG32(mmCP_MEC_CNTL, 0);
2714         } else {
2715                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2716                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2717                         adev->gfx.compute_ring[i].ready = false;
2718         }
2719         udelay(50);
2720 }
2721
2722 /**
2723  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2724  *
2725  * @adev: amdgpu_device pointer
2726  *
2727  * Loads the compute MEC1&2 ucode.
2728  * Returns 0 for success, -EINVAL if the ucode is not available.
2729  */
2730 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2731 {
2732         const struct gfx_firmware_header_v1_0 *mec_hdr;
2733         const __le32 *fw_data;
2734         unsigned i, fw_size;
2735
2736         if (!adev->gfx.mec_fw)
2737                 return -EINVAL;
2738
2739         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2740         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2741         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2742         adev->gfx.mec_feature_version = le32_to_cpu(
2743                                         mec_hdr->ucode_feature_version);
2744
2745         gfx_v7_0_cp_compute_enable(adev, false);
2746
2747         /* MEC1 */
2748         fw_data = (const __le32 *)
2749                 (adev->gfx.mec_fw->data +
2750                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2751         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2752         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2753         for (i = 0; i < fw_size; i++)
2754                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2755         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2756
2757         if (adev->asic_type == CHIP_KAVERI) {
2758                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2759
2760                 if (!adev->gfx.mec2_fw)
2761                         return -EINVAL;
2762
2763                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2764                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2765                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2766                 adev->gfx.mec2_feature_version = le32_to_cpu(
2767                                 mec2_hdr->ucode_feature_version);
2768
2769                 /* MEC2 */
2770                 fw_data = (const __le32 *)
2771                         (adev->gfx.mec2_fw->data +
2772                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2773                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2774                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2775                 for (i = 0; i < fw_size; i++)
2776                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2777                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2778         }
2779
2780         return 0;
2781 }
2782
2783 /**
2784  * gfx_v7_0_cp_compute_fini - stop the compute queues
2785  *
2786  * @adev: amdgpu_device pointer
2787  *
2788  * Stop the compute queues and tear down the driver queue
2789  * info.
2790  */
2791 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2792 {
2793         int i;
2794
2795         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2796                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2797
2798                 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2799         }
2800 }
2801
2802 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2803 {
2804         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2805 }
2806
2807 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2808 {
2809         int r;
2810         u32 *hpd;
2811         size_t mec_hpd_size;
2812
2813         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2814
2815         /* take ownership of the relevant compute queues */
2816         amdgpu_gfx_compute_queue_acquire(adev);
2817
2818         /* allocate space for ALL pipes (even the ones we don't own) */
2819         mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2820                 * GFX7_MEC_HPD_SIZE * 2;
2821
2822         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2823                                       AMDGPU_GEM_DOMAIN_GTT,
2824                                       &adev->gfx.mec.hpd_eop_obj,
2825                                       &adev->gfx.mec.hpd_eop_gpu_addr,
2826                                       (void **)&hpd);
2827         if (r) {
2828                 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2829                 gfx_v7_0_mec_fini(adev);
2830                 return r;
2831         }
2832
2833         /* clear memory.  Not sure if this is required or not */
2834         memset(hpd, 0, mec_hpd_size);
2835
2836         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2837         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2838
2839         return 0;
2840 }
2841
2842 struct hqd_registers
2843 {
2844         u32 cp_mqd_base_addr;
2845         u32 cp_mqd_base_addr_hi;
2846         u32 cp_hqd_active;
2847         u32 cp_hqd_vmid;
2848         u32 cp_hqd_persistent_state;
2849         u32 cp_hqd_pipe_priority;
2850         u32 cp_hqd_queue_priority;
2851         u32 cp_hqd_quantum;
2852         u32 cp_hqd_pq_base;
2853         u32 cp_hqd_pq_base_hi;
2854         u32 cp_hqd_pq_rptr;
2855         u32 cp_hqd_pq_rptr_report_addr;
2856         u32 cp_hqd_pq_rptr_report_addr_hi;
2857         u32 cp_hqd_pq_wptr_poll_addr;
2858         u32 cp_hqd_pq_wptr_poll_addr_hi;
2859         u32 cp_hqd_pq_doorbell_control;
2860         u32 cp_hqd_pq_wptr;
2861         u32 cp_hqd_pq_control;
2862         u32 cp_hqd_ib_base_addr;
2863         u32 cp_hqd_ib_base_addr_hi;
2864         u32 cp_hqd_ib_rptr;
2865         u32 cp_hqd_ib_control;
2866         u32 cp_hqd_iq_timer;
2867         u32 cp_hqd_iq_rptr;
2868         u32 cp_hqd_dequeue_request;
2869         u32 cp_hqd_dma_offload;
2870         u32 cp_hqd_sema_cmd;
2871         u32 cp_hqd_msg_type;
2872         u32 cp_hqd_atomic0_preop_lo;
2873         u32 cp_hqd_atomic0_preop_hi;
2874         u32 cp_hqd_atomic1_preop_lo;
2875         u32 cp_hqd_atomic1_preop_hi;
2876         u32 cp_hqd_hq_scheduler0;
2877         u32 cp_hqd_hq_scheduler1;
2878         u32 cp_mqd_control;
2879 };
2880
2881 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2882                                        int mec, int pipe)
2883 {
2884         u64 eop_gpu_addr;
2885         u32 tmp;
2886         size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2887                             * GFX7_MEC_HPD_SIZE * 2;
2888
2889         mutex_lock(&adev->srbm_mutex);
2890         eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2891
2892         cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2893
2894         /* write the EOP addr */
2895         WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2896         WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2897
2898         /* set the VMID assigned */
2899         WREG32(mmCP_HPD_EOP_VMID, 0);
2900
2901         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2902         tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2903         tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2904         tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2905         WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2906
2907         cik_srbm_select(adev, 0, 0, 0, 0);
2908         mutex_unlock(&adev->srbm_mutex);
2909 }
2910
2911 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2912 {
2913         int i;
2914
2915         /* disable the queue if it's active */
2916         if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2917                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2918                 for (i = 0; i < adev->usec_timeout; i++) {
2919                         if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2920                                 break;
2921                         udelay(1);
2922                 }
2923
2924                 if (i == adev->usec_timeout)
2925                         return -ETIMEDOUT;
2926
2927                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2928                 WREG32(mmCP_HQD_PQ_RPTR, 0);
2929                 WREG32(mmCP_HQD_PQ_WPTR, 0);
2930         }
2931
2932         return 0;
2933 }
2934
2935 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2936                              struct cik_mqd *mqd,
2937                              uint64_t mqd_gpu_addr,
2938                              struct amdgpu_ring *ring)
2939 {
2940         u64 hqd_gpu_addr;
2941         u64 wb_gpu_addr;
2942
2943         /* init the mqd struct */
2944         memset(mqd, 0, sizeof(struct cik_mqd));
2945
2946         mqd->header = 0xC0310800;
2947         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2948         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2949         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2950         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2951
2952         /* enable doorbell? */
2953         mqd->cp_hqd_pq_doorbell_control =
2954                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2955         if (ring->use_doorbell)
2956                 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2957         else
2958                 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2959
2960         /* set the pointer to the MQD */
2961         mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2962         mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2963
2964         /* set MQD vmid to 0 */
2965         mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2966         mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2967
2968         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2969         hqd_gpu_addr = ring->gpu_addr >> 8;
2970         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2971         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2972
2973         /* set up the HQD, this is similar to CP_RB0_CNTL */
2974         mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2975         mqd->cp_hqd_pq_control &=
2976                 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2977                                 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2978
2979         mqd->cp_hqd_pq_control |=
2980                 order_base_2(ring->ring_size / 8);
2981         mqd->cp_hqd_pq_control |=
2982                 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2983 #ifdef __BIG_ENDIAN
2984         mqd->cp_hqd_pq_control |=
2985                 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2986 #endif
2987         mqd->cp_hqd_pq_control &=
2988                 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2989                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2990                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2991         mqd->cp_hqd_pq_control |=
2992                 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2993                 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2994
2995         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2996         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2997         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2998         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2999
3000         /* set the wb address wether it's enabled or not */
3001         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3002         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3003         mqd->cp_hqd_pq_rptr_report_addr_hi =
3004                 upper_32_bits(wb_gpu_addr) & 0xffff;
3005
3006         /* enable the doorbell if requested */
3007         if (ring->use_doorbell) {
3008                 mqd->cp_hqd_pq_doorbell_control =
3009                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3010                 mqd->cp_hqd_pq_doorbell_control &=
3011                         ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3012                 mqd->cp_hqd_pq_doorbell_control |=
3013                         (ring->doorbell_index <<
3014                          CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3015                 mqd->cp_hqd_pq_doorbell_control |=
3016                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3017                 mqd->cp_hqd_pq_doorbell_control &=
3018                         ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3019                                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3020
3021         } else {
3022                 mqd->cp_hqd_pq_doorbell_control = 0;
3023         }
3024
3025         /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3026         ring->wptr = 0;
3027         mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
3028         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3029
3030         /* set the vmid for the queue */
3031         mqd->cp_hqd_vmid = 0;
3032
3033         /* defaults */
3034         mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
3035         mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
3036         mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
3037         mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
3038         mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
3039         mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
3040         mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
3041         mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
3042         mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
3043         mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
3044         mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
3045         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3046         mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
3047         mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
3048         mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
3049         mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
3050
3051         /* activate the queue */
3052         mqd->cp_hqd_active = 1;
3053 }
3054
3055 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
3056 {
3057         uint32_t tmp;
3058         uint32_t mqd_reg;
3059         uint32_t *mqd_data;
3060
3061         /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3062         mqd_data = &mqd->cp_mqd_base_addr_lo;
3063
3064         /* disable wptr polling */
3065         tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3066         tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3067         WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3068
3069         /* program all HQD registers */
3070         for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3071                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3072
3073         /* activate the HQD */
3074         for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3075                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3076
3077         return 0;
3078 }
3079
3080 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3081 {
3082         int r;
3083         u64 mqd_gpu_addr;
3084         struct cik_mqd *mqd;
3085         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3086
3087         r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
3088                                       AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
3089                                       &mqd_gpu_addr, (void **)&mqd);
3090         if (r) {
3091                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3092                 return r;
3093         }
3094
3095         mutex_lock(&adev->srbm_mutex);
3096         cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3097
3098         gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3099         gfx_v7_0_mqd_deactivate(adev);
3100         gfx_v7_0_mqd_commit(adev, mqd);
3101
3102         cik_srbm_select(adev, 0, 0, 0, 0);
3103         mutex_unlock(&adev->srbm_mutex);
3104
3105         amdgpu_bo_kunmap(ring->mqd_obj);
3106         amdgpu_bo_unreserve(ring->mqd_obj);
3107         return 0;
3108 }
3109
3110 /**
3111  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3112  *
3113  * @adev: amdgpu_device pointer
3114  *
3115  * Program the compute queues and test them to make sure they
3116  * are working.
3117  * Returns 0 for success, error for failure.
3118  */
3119 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3120 {
3121         int r, i, j;
3122         u32 tmp;
3123         struct amdgpu_ring *ring;
3124
3125         /* fix up chicken bits */
3126         tmp = RREG32(mmCP_CPF_DEBUG);
3127         tmp |= (1 << 23);
3128         WREG32(mmCP_CPF_DEBUG, tmp);
3129
3130         /* init all pipes (even the ones we don't own) */
3131         for (i = 0; i < adev->gfx.mec.num_mec; i++)
3132                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3133                         gfx_v7_0_compute_pipe_init(adev, i, j);
3134
3135         /* init the queues */
3136         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3137                 r = gfx_v7_0_compute_queue_init(adev, i);
3138                 if (r) {
3139                         gfx_v7_0_cp_compute_fini(adev);
3140                         return r;
3141                 }
3142         }
3143
3144         gfx_v7_0_cp_compute_enable(adev, true);
3145
3146         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3147                 ring = &adev->gfx.compute_ring[i];
3148                 ring->ready = true;
3149                 r = amdgpu_ring_test_ring(ring);
3150                 if (r)
3151                         ring->ready = false;
3152         }
3153
3154         return 0;
3155 }
3156
3157 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3158 {
3159         gfx_v7_0_cp_gfx_enable(adev, enable);
3160         gfx_v7_0_cp_compute_enable(adev, enable);
3161 }
3162
3163 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3164 {
3165         int r;
3166
3167         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3168         if (r)
3169                 return r;
3170         r = gfx_v7_0_cp_compute_load_microcode(adev);
3171         if (r)
3172                 return r;
3173
3174         return 0;
3175 }
3176
3177 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3178                                                bool enable)
3179 {
3180         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3181
3182         if (enable)
3183                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3184                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3185         else
3186                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3187                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3188         WREG32(mmCP_INT_CNTL_RING0, tmp);
3189 }
3190
3191 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3192 {
3193         int r;
3194
3195         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3196
3197         r = gfx_v7_0_cp_load_microcode(adev);
3198         if (r)
3199                 return r;
3200
3201         r = gfx_v7_0_cp_gfx_resume(adev);
3202         if (r)
3203                 return r;
3204         r = gfx_v7_0_cp_compute_resume(adev);
3205         if (r)
3206                 return r;
3207
3208         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3209
3210         return 0;
3211 }
3212
3213 /**
3214  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3215  *
3216  * @ring: the ring to emmit the commands to
3217  *
3218  * Sync the command pipeline with the PFP. E.g. wait for everything
3219  * to be completed.
3220  */
3221 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3222 {
3223         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3224         uint32_t seq = ring->fence_drv.sync_seq;
3225         uint64_t addr = ring->fence_drv.gpu_addr;
3226
3227         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3228         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3229                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3230                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3231         amdgpu_ring_write(ring, addr & 0xfffffffc);
3232         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3233         amdgpu_ring_write(ring, seq);
3234         amdgpu_ring_write(ring, 0xffffffff);
3235         amdgpu_ring_write(ring, 4); /* poll interval */
3236
3237         if (usepfp) {
3238                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3239                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3240                 amdgpu_ring_write(ring, 0);
3241                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3242                 amdgpu_ring_write(ring, 0);
3243         }
3244 }
3245
3246 /*
3247  * vm
3248  * VMID 0 is the physical GPU addresses as used by the kernel.
3249  * VMIDs 1-15 are used for userspace clients and are handled
3250  * by the amdgpu vm/hsa code.
3251  */
3252 /**
3253  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3254  *
3255  * @adev: amdgpu_device pointer
3256  *
3257  * Update the page table base and flush the VM TLB
3258  * using the CP (CIK).
3259  */
3260 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3261                                         unsigned vm_id, uint64_t pd_addr)
3262 {
3263         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3264
3265         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3266         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3267                                  WRITE_DATA_DST_SEL(0)));
3268         if (vm_id < 8) {
3269                 amdgpu_ring_write(ring,
3270                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3271         } else {
3272                 amdgpu_ring_write(ring,
3273                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3274         }
3275         amdgpu_ring_write(ring, 0);
3276         amdgpu_ring_write(ring, pd_addr >> 12);
3277
3278         /* bits 0-15 are the VM contexts0-15 */
3279         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3280         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3281                                  WRITE_DATA_DST_SEL(0)));
3282         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3283         amdgpu_ring_write(ring, 0);
3284         amdgpu_ring_write(ring, 1 << vm_id);
3285
3286         /* wait for the invalidate to complete */
3287         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3288         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3289                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3290                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3291         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3292         amdgpu_ring_write(ring, 0);
3293         amdgpu_ring_write(ring, 0); /* ref */
3294         amdgpu_ring_write(ring, 0); /* mask */
3295         amdgpu_ring_write(ring, 0x20); /* poll interval */
3296
3297         /* compute doesn't have PFP */
3298         if (usepfp) {
3299                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3300                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3301                 amdgpu_ring_write(ring, 0x0);
3302
3303                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3304                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3305                 amdgpu_ring_write(ring, 0);
3306                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3307                 amdgpu_ring_write(ring, 0);
3308         }
3309 }
3310
3311 /*
3312  * RLC
3313  * The RLC is a multi-purpose microengine that handles a
3314  * variety of functions.
3315  */
3316 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3317 {
3318         amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
3319         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
3320         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
3321 }
3322
3323 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3324 {
3325         const u32 *src_ptr;
3326         volatile u32 *dst_ptr;
3327         u32 dws, i;
3328         const struct cs_section_def *cs_data;
3329         int r;
3330
3331         /* allocate rlc buffers */
3332         if (adev->flags & AMD_IS_APU) {
3333                 if (adev->asic_type == CHIP_KAVERI) {
3334                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3335                         adev->gfx.rlc.reg_list_size =
3336                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3337                 } else {
3338                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3339                         adev->gfx.rlc.reg_list_size =
3340                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3341                 }
3342         }
3343         adev->gfx.rlc.cs_data = ci_cs_data;
3344         adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3345         adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3346
3347         src_ptr = adev->gfx.rlc.reg_list;
3348         dws = adev->gfx.rlc.reg_list_size;
3349         dws += (5 * 16) + 48 + 48 + 64;
3350
3351         cs_data = adev->gfx.rlc.cs_data;
3352
3353         if (src_ptr) {
3354                 /* save restore block */
3355                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3356                                               AMDGPU_GEM_DOMAIN_VRAM,
3357                                               &adev->gfx.rlc.save_restore_obj,
3358                                               &adev->gfx.rlc.save_restore_gpu_addr,
3359                                               (void **)&adev->gfx.rlc.sr_ptr);
3360                 if (r) {
3361                         dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);
3362                         gfx_v7_0_rlc_fini(adev);
3363                         return r;
3364                 }
3365
3366                 /* write the sr buffer */
3367                 dst_ptr = adev->gfx.rlc.sr_ptr;
3368                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3369                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3370                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3371                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3372         }
3373
3374         if (cs_data) {
3375                 /* clear state block */
3376                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3377
3378                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3379                                               AMDGPU_GEM_DOMAIN_VRAM,
3380                                               &adev->gfx.rlc.clear_state_obj,
3381                                               &adev->gfx.rlc.clear_state_gpu_addr,
3382                                               (void **)&adev->gfx.rlc.cs_ptr);
3383                 if (r) {
3384                         dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3385                         gfx_v7_0_rlc_fini(adev);
3386                         return r;
3387                 }
3388
3389                 /* set up the cs buffer */
3390                 dst_ptr = adev->gfx.rlc.cs_ptr;
3391                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3392                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3393                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3394         }
3395
3396         if (adev->gfx.rlc.cp_table_size) {
3397
3398                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
3399                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
3400                                               &adev->gfx.rlc.cp_table_obj,
3401                                               &adev->gfx.rlc.cp_table_gpu_addr,
3402                                               (void **)&adev->gfx.rlc.cp_table_ptr);
3403                 if (r) {
3404                         dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3405                         gfx_v7_0_rlc_fini(adev);
3406                         return r;
3407                 }
3408
3409                 gfx_v7_0_init_cp_pg_table(adev);
3410
3411                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3412                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3413
3414         }
3415
3416         return 0;
3417 }
3418
3419 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3420 {
3421         u32 tmp;
3422
3423         tmp = RREG32(mmRLC_LB_CNTL);
3424         if (enable)
3425                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3426         else
3427                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3428         WREG32(mmRLC_LB_CNTL, tmp);
3429 }
3430
3431 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3432 {
3433         u32 i, j, k;
3434         u32 mask;
3435
3436         mutex_lock(&adev->grbm_idx_mutex);
3437         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3438                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3439                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3440                         for (k = 0; k < adev->usec_timeout; k++) {
3441                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3442                                         break;
3443                                 udelay(1);
3444                         }
3445                 }
3446         }
3447         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3448         mutex_unlock(&adev->grbm_idx_mutex);
3449
3450         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3451                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3452                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3453                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3454         for (k = 0; k < adev->usec_timeout; k++) {
3455                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3456                         break;
3457                 udelay(1);
3458         }
3459 }
3460
3461 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3462 {
3463         u32 tmp;
3464
3465         tmp = RREG32(mmRLC_CNTL);
3466         if (tmp != rlc)
3467                 WREG32(mmRLC_CNTL, rlc);
3468 }
3469
3470 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3471 {
3472         u32 data, orig;
3473
3474         orig = data = RREG32(mmRLC_CNTL);
3475
3476         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3477                 u32 i;
3478
3479                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3480                 WREG32(mmRLC_CNTL, data);
3481
3482                 for (i = 0; i < adev->usec_timeout; i++) {
3483                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3484                                 break;
3485                         udelay(1);
3486                 }
3487
3488                 gfx_v7_0_wait_for_rlc_serdes(adev);
3489         }
3490
3491         return orig;
3492 }
3493
3494 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3495 {
3496         u32 tmp, i, mask;
3497
3498         tmp = 0x1 | (1 << 1);
3499         WREG32(mmRLC_GPR_REG2, tmp);
3500
3501         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3502                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3503         for (i = 0; i < adev->usec_timeout; i++) {
3504                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3505                         break;
3506                 udelay(1);
3507         }
3508
3509         for (i = 0; i < adev->usec_timeout; i++) {
3510                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3511                         break;
3512                 udelay(1);
3513         }
3514 }
3515
3516 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3517 {
3518         u32 tmp;
3519
3520         tmp = 0x1 | (0 << 1);
3521         WREG32(mmRLC_GPR_REG2, tmp);
3522 }
3523
3524 /**
3525  * gfx_v7_0_rlc_stop - stop the RLC ME
3526  *
3527  * @adev: amdgpu_device pointer
3528  *
3529  * Halt the RLC ME (MicroEngine) (CIK).
3530  */
3531 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3532 {
3533         WREG32(mmRLC_CNTL, 0);
3534
3535         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3536
3537         gfx_v7_0_wait_for_rlc_serdes(adev);
3538 }
3539
3540 /**
3541  * gfx_v7_0_rlc_start - start the RLC ME
3542  *
3543  * @adev: amdgpu_device pointer
3544  *
3545  * Unhalt the RLC ME (MicroEngine) (CIK).
3546  */
3547 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3548 {
3549         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3550
3551         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3552
3553         udelay(50);
3554 }
3555
3556 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3557 {
3558         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3559
3560         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3561         WREG32(mmGRBM_SOFT_RESET, tmp);
3562         udelay(50);
3563         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3564         WREG32(mmGRBM_SOFT_RESET, tmp);
3565         udelay(50);
3566 }
3567
3568 /**
3569  * gfx_v7_0_rlc_resume - setup the RLC hw
3570  *
3571  * @adev: amdgpu_device pointer
3572  *
3573  * Initialize the RLC registers, load the ucode,
3574  * and start the RLC (CIK).
3575  * Returns 0 for success, -EINVAL if the ucode is not available.
3576  */
3577 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3578 {
3579         const struct rlc_firmware_header_v1_0 *hdr;
3580         const __le32 *fw_data;
3581         unsigned i, fw_size;
3582         u32 tmp;
3583
3584         if (!adev->gfx.rlc_fw)
3585                 return -EINVAL;
3586
3587         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3588         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3589         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3590         adev->gfx.rlc_feature_version = le32_to_cpu(
3591                                         hdr->ucode_feature_version);
3592
3593         gfx_v7_0_rlc_stop(adev);
3594
3595         /* disable CG */
3596         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3597         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3598
3599         gfx_v7_0_rlc_reset(adev);
3600
3601         gfx_v7_0_init_pg(adev);
3602
3603         WREG32(mmRLC_LB_CNTR_INIT, 0);
3604         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3605
3606         mutex_lock(&adev->grbm_idx_mutex);
3607         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3608         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3609         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3610         WREG32(mmRLC_LB_CNTL, 0x80000004);
3611         mutex_unlock(&adev->grbm_idx_mutex);
3612
3613         WREG32(mmRLC_MC_CNTL, 0);
3614         WREG32(mmRLC_UCODE_CNTL, 0);
3615
3616         fw_data = (const __le32 *)
3617                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3618         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3619         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3620         for (i = 0; i < fw_size; i++)
3621                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3622         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3623
3624         /* XXX - find out what chips support lbpw */
3625         gfx_v7_0_enable_lbpw(adev, false);
3626
3627         if (adev->asic_type == CHIP_BONAIRE)
3628                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3629
3630         gfx_v7_0_rlc_start(adev);
3631
3632         return 0;
3633 }
3634
3635 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3636 {
3637         u32 data, orig, tmp, tmp2;
3638
3639         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3640
3641         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3642                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3643
3644                 tmp = gfx_v7_0_halt_rlc(adev);
3645
3646                 mutex_lock(&adev->grbm_idx_mutex);
3647                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3648                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3649                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3650                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3651                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3652                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3653                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3654                 mutex_unlock(&adev->grbm_idx_mutex);
3655
3656                 gfx_v7_0_update_rlc(adev, tmp);
3657
3658                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3659                 if (orig != data)
3660                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3661
3662         } else {
3663                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3664
3665                 RREG32(mmCB_CGTT_SCLK_CTRL);
3666                 RREG32(mmCB_CGTT_SCLK_CTRL);
3667                 RREG32(mmCB_CGTT_SCLK_CTRL);
3668                 RREG32(mmCB_CGTT_SCLK_CTRL);
3669
3670                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3671                 if (orig != data)
3672                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3673
3674                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3675         }
3676 }
3677
3678 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3679 {
3680         u32 data, orig, tmp = 0;
3681
3682         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3683                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3684                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3685                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3686                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3687                                 if (orig != data)
3688                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3689                         }
3690                 }
3691
3692                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3693                 data |= 0x00000001;
3694                 data &= 0xfffffffd;
3695                 if (orig != data)
3696                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3697
3698                 tmp = gfx_v7_0_halt_rlc(adev);
3699
3700                 mutex_lock(&adev->grbm_idx_mutex);
3701                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3702                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3703                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3704                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3705                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3706                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3707                 mutex_unlock(&adev->grbm_idx_mutex);
3708
3709                 gfx_v7_0_update_rlc(adev, tmp);
3710
3711                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3712                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3713                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3714                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3715                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3716                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3717                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3718                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3719                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3720                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3721                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3722                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3723                         if (orig != data)
3724                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3725                 }
3726         } else {
3727                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3728                 data |= 0x00000003;
3729                 if (orig != data)
3730                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3731
3732                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3733                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3734                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3735                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3736                 }
3737
3738                 data = RREG32(mmCP_MEM_SLP_CNTL);
3739                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3740                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3741                         WREG32(mmCP_MEM_SLP_CNTL, data);
3742                 }
3743
3744                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3745                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3746                 if (orig != data)
3747                         WREG32(mmCGTS_SM_CTRL_REG, data);
3748
3749                 tmp = gfx_v7_0_halt_rlc(adev);
3750
3751                 mutex_lock(&adev->grbm_idx_mutex);
3752                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3753                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3754                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3755                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3756                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3757                 mutex_unlock(&adev->grbm_idx_mutex);
3758
3759                 gfx_v7_0_update_rlc(adev, tmp);
3760         }
3761 }
3762
3763 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3764                                bool enable)
3765 {
3766         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3767         /* order matters! */
3768         if (enable) {
3769                 gfx_v7_0_enable_mgcg(adev, true);
3770                 gfx_v7_0_enable_cgcg(adev, true);
3771         } else {
3772                 gfx_v7_0_enable_cgcg(adev, false);
3773                 gfx_v7_0_enable_mgcg(adev, false);
3774         }
3775         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3776 }
3777
3778 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3779                                                 bool enable)
3780 {
3781         u32 data, orig;
3782
3783         orig = data = RREG32(mmRLC_PG_CNTL);
3784         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3785                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3786         else
3787                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3788         if (orig != data)
3789                 WREG32(mmRLC_PG_CNTL, data);
3790 }
3791
3792 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3793                                                 bool enable)
3794 {
3795         u32 data, orig;
3796
3797         orig = data = RREG32(mmRLC_PG_CNTL);
3798         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3799                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3800         else
3801                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3802         if (orig != data)
3803                 WREG32(mmRLC_PG_CNTL, data);
3804 }
3805
3806 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3807 {
3808         u32 data, orig;
3809
3810         orig = data = RREG32(mmRLC_PG_CNTL);
3811         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3812                 data &= ~0x8000;
3813         else
3814                 data |= 0x8000;
3815         if (orig != data)
3816                 WREG32(mmRLC_PG_CNTL, data);
3817 }
3818
3819 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3820 {
3821         u32 data, orig;
3822
3823         orig = data = RREG32(mmRLC_PG_CNTL);
3824         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3825                 data &= ~0x2000;
3826         else
3827                 data |= 0x2000;
3828         if (orig != data)
3829                 WREG32(mmRLC_PG_CNTL, data);
3830 }
3831
3832 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3833 {
3834         const __le32 *fw_data;
3835         volatile u32 *dst_ptr;
3836         int me, i, max_me = 4;
3837         u32 bo_offset = 0;
3838         u32 table_offset, table_size;
3839
3840         if (adev->asic_type == CHIP_KAVERI)
3841                 max_me = 5;
3842
3843         if (adev->gfx.rlc.cp_table_ptr == NULL)
3844                 return;
3845
3846         /* write the cp table buffer */
3847         dst_ptr = adev->gfx.rlc.cp_table_ptr;
3848         for (me = 0; me < max_me; me++) {
3849                 if (me == 0) {
3850                         const struct gfx_firmware_header_v1_0 *hdr =
3851                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3852                         fw_data = (const __le32 *)
3853                                 (adev->gfx.ce_fw->data +
3854                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3855                         table_offset = le32_to_cpu(hdr->jt_offset);
3856                         table_size = le32_to_cpu(hdr->jt_size);
3857                 } else if (me == 1) {
3858                         const struct gfx_firmware_header_v1_0 *hdr =
3859                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3860                         fw_data = (const __le32 *)
3861                                 (adev->gfx.pfp_fw->data +
3862                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3863                         table_offset = le32_to_cpu(hdr->jt_offset);
3864                         table_size = le32_to_cpu(hdr->jt_size);
3865                 } else if (me == 2) {
3866                         const struct gfx_firmware_header_v1_0 *hdr =
3867                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3868                         fw_data = (const __le32 *)
3869                                 (adev->gfx.me_fw->data +
3870                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3871                         table_offset = le32_to_cpu(hdr->jt_offset);
3872                         table_size = le32_to_cpu(hdr->jt_size);
3873                 } else if (me == 3) {
3874                         const struct gfx_firmware_header_v1_0 *hdr =
3875                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3876                         fw_data = (const __le32 *)
3877                                 (adev->gfx.mec_fw->data +
3878                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3879                         table_offset = le32_to_cpu(hdr->jt_offset);
3880                         table_size = le32_to_cpu(hdr->jt_size);
3881                 } else {
3882                         const struct gfx_firmware_header_v1_0 *hdr =
3883                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3884                         fw_data = (const __le32 *)
3885                                 (adev->gfx.mec2_fw->data +
3886                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3887                         table_offset = le32_to_cpu(hdr->jt_offset);
3888                         table_size = le32_to_cpu(hdr->jt_size);
3889                 }
3890
3891                 for (i = 0; i < table_size; i ++) {
3892                         dst_ptr[bo_offset + i] =
3893                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3894                 }
3895
3896                 bo_offset += table_size;
3897         }
3898 }
3899
3900 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3901                                      bool enable)
3902 {
3903         u32 data, orig;
3904
3905         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3906                 orig = data = RREG32(mmRLC_PG_CNTL);
3907                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3908                 if (orig != data)
3909                         WREG32(mmRLC_PG_CNTL, data);
3910
3911                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3912                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3913                 if (orig != data)
3914                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3915         } else {
3916                 orig = data = RREG32(mmRLC_PG_CNTL);
3917                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3918                 if (orig != data)
3919                         WREG32(mmRLC_PG_CNTL, data);
3920
3921                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3922                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3923                 if (orig != data)
3924                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3925
3926                 data = RREG32(mmDB_RENDER_CONTROL);
3927         }
3928 }
3929
3930 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3931                                                  u32 bitmap)
3932 {
3933         u32 data;
3934
3935         if (!bitmap)
3936                 return;
3937
3938         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3939         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3940
3941         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3942 }
3943
3944 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3945 {
3946         u32 data, mask;
3947
3948         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3949         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3950
3951         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3952         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3953
3954         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3955
3956         return (~data) & mask;
3957 }
3958
3959 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3960 {
3961         u32 tmp;
3962
3963         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3964
3965         tmp = RREG32(mmRLC_MAX_PG_CU);
3966         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3967         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3968         WREG32(mmRLC_MAX_PG_CU, tmp);
3969 }
3970
3971 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3972                                             bool enable)
3973 {
3974         u32 data, orig;
3975
3976         orig = data = RREG32(mmRLC_PG_CNTL);
3977         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3978                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3979         else
3980                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3981         if (orig != data)
3982                 WREG32(mmRLC_PG_CNTL, data);
3983 }
3984
3985 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3986                                              bool enable)
3987 {
3988         u32 data, orig;
3989
3990         orig = data = RREG32(mmRLC_PG_CNTL);
3991         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3992                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3993         else
3994                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3995         if (orig != data)
3996                 WREG32(mmRLC_PG_CNTL, data);
3997 }
3998
3999 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4000 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
4001
4002 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4003 {
4004         u32 data, orig;
4005         u32 i;
4006
4007         if (adev->gfx.rlc.cs_data) {
4008                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4009                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4010                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4011                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4012         } else {
4013                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4014                 for (i = 0; i < 3; i++)
4015                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4016         }
4017         if (adev->gfx.rlc.reg_list) {
4018                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4019                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4020                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4021         }
4022
4023         orig = data = RREG32(mmRLC_PG_CNTL);
4024         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4025         if (orig != data)
4026                 WREG32(mmRLC_PG_CNTL, data);
4027
4028         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4029         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4030
4031         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4032         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4033         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4034         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4035
4036         data = 0x10101010;
4037         WREG32(mmRLC_PG_DELAY, data);
4038
4039         data = RREG32(mmRLC_PG_DELAY_2);
4040         data &= ~0xff;
4041         data |= 0x3;
4042         WREG32(mmRLC_PG_DELAY_2, data);
4043
4044         data = RREG32(mmRLC_AUTO_PG_CTRL);
4045         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4046         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4047         WREG32(mmRLC_AUTO_PG_CTRL, data);
4048
4049 }
4050
4051 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4052 {
4053         gfx_v7_0_enable_gfx_cgpg(adev, enable);
4054         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4055         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4056 }
4057
4058 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4059 {
4060         u32 count = 0;
4061         const struct cs_section_def *sect = NULL;
4062         const struct cs_extent_def *ext = NULL;
4063
4064         if (adev->gfx.rlc.cs_data == NULL)
4065                 return 0;
4066
4067         /* begin clear state */
4068         count += 2;
4069         /* context control state */
4070         count += 3;
4071
4072         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4073                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4074                         if (sect->id == SECT_CONTEXT)
4075                                 count += 2 + ext->reg_count;
4076                         else
4077                                 return 0;
4078                 }
4079         }
4080         /* pa_sc_raster_config/pa_sc_raster_config1 */
4081         count += 4;
4082         /* end clear state */
4083         count += 2;
4084         /* clear state */
4085         count += 2;
4086
4087         return count;
4088 }
4089
4090 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4091                                     volatile u32 *buffer)
4092 {
4093         u32 count = 0, i;
4094         const struct cs_section_def *sect = NULL;
4095         const struct cs_extent_def *ext = NULL;
4096
4097         if (adev->gfx.rlc.cs_data == NULL)
4098                 return;
4099         if (buffer == NULL)
4100                 return;
4101
4102         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4103         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4104
4105         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4106         buffer[count++] = cpu_to_le32(0x80000000);
4107         buffer[count++] = cpu_to_le32(0x80000000);
4108
4109         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4110                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4111                         if (sect->id == SECT_CONTEXT) {
4112                                 buffer[count++] =
4113                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4114                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4115                                 for (i = 0; i < ext->reg_count; i++)
4116                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4117                         } else {
4118                                 return;
4119                         }
4120                 }
4121         }
4122
4123         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4124         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4125         switch (adev->asic_type) {
4126         case CHIP_BONAIRE:
4127                 buffer[count++] = cpu_to_le32(0x16000012);
4128                 buffer[count++] = cpu_to_le32(0x00000000);
4129                 break;
4130         case CHIP_KAVERI:
4131                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4132                 buffer[count++] = cpu_to_le32(0x00000000);
4133                 break;
4134         case CHIP_KABINI:
4135         case CHIP_MULLINS:
4136                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4137                 buffer[count++] = cpu_to_le32(0x00000000);
4138                 break;
4139         case CHIP_HAWAII:
4140                 buffer[count++] = cpu_to_le32(0x3a00161a);
4141                 buffer[count++] = cpu_to_le32(0x0000002e);
4142                 break;
4143         default:
4144                 buffer[count++] = cpu_to_le32(0x00000000);
4145                 buffer[count++] = cpu_to_le32(0x00000000);
4146                 break;
4147         }
4148
4149         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4150         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4151
4152         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4153         buffer[count++] = cpu_to_le32(0);
4154 }
4155
4156 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4157 {
4158         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4159                               AMD_PG_SUPPORT_GFX_SMG |
4160                               AMD_PG_SUPPORT_GFX_DMG |
4161                               AMD_PG_SUPPORT_CP |
4162                               AMD_PG_SUPPORT_GDS |
4163                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4164                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4165                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4166                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4167                         gfx_v7_0_init_gfx_cgpg(adev);
4168                         gfx_v7_0_enable_cp_pg(adev, true);
4169                         gfx_v7_0_enable_gds_pg(adev, true);
4170                 }
4171                 gfx_v7_0_init_ao_cu_mask(adev);
4172                 gfx_v7_0_update_gfx_pg(adev, true);
4173         }
4174 }
4175
4176 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4177 {
4178         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4179                               AMD_PG_SUPPORT_GFX_SMG |
4180                               AMD_PG_SUPPORT_GFX_DMG |
4181                               AMD_PG_SUPPORT_CP |
4182                               AMD_PG_SUPPORT_GDS |
4183                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4184                 gfx_v7_0_update_gfx_pg(adev, false);
4185                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4186                         gfx_v7_0_enable_cp_pg(adev, false);
4187                         gfx_v7_0_enable_gds_pg(adev, false);
4188                 }
4189         }
4190 }
4191
4192 /**
4193  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4194  *
4195  * @adev: amdgpu_device pointer
4196  *
4197  * Fetches a GPU clock counter snapshot (SI).
4198  * Returns the 64 bit clock counter snapshot.
4199  */
4200 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4201 {
4202         uint64_t clock;
4203
4204         mutex_lock(&adev->gfx.gpu_clock_mutex);
4205         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4206         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4207                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4208         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4209         return clock;
4210 }
4211
4212 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4213                                           uint32_t vmid,
4214                                           uint32_t gds_base, uint32_t gds_size,
4215                                           uint32_t gws_base, uint32_t gws_size,
4216                                           uint32_t oa_base, uint32_t oa_size)
4217 {
4218         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4219         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4220
4221         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4222         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4223
4224         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4225         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4226
4227         /* GDS Base */
4228         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4229         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4230                                 WRITE_DATA_DST_SEL(0)));
4231         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4232         amdgpu_ring_write(ring, 0);
4233         amdgpu_ring_write(ring, gds_base);
4234
4235         /* GDS Size */
4236         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4237         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4238                                 WRITE_DATA_DST_SEL(0)));
4239         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4240         amdgpu_ring_write(ring, 0);
4241         amdgpu_ring_write(ring, gds_size);
4242
4243         /* GWS */
4244         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4245         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4246                                 WRITE_DATA_DST_SEL(0)));
4247         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4248         amdgpu_ring_write(ring, 0);
4249         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4250
4251         /* OA */
4252         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4253         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4254                                 WRITE_DATA_DST_SEL(0)));
4255         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4256         amdgpu_ring_write(ring, 0);
4257         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4258 }
4259
4260 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4261 {
4262         WREG32(mmSQ_IND_INDEX,
4263                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4264                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4265                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4266                 (SQ_IND_INDEX__FORCE_READ_MASK));
4267         return RREG32(mmSQ_IND_DATA);
4268 }
4269
4270 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4271                            uint32_t wave, uint32_t thread,
4272                            uint32_t regno, uint32_t num, uint32_t *out)
4273 {
4274         WREG32(mmSQ_IND_INDEX,
4275                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4276                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4277                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4278                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4279                 (SQ_IND_INDEX__FORCE_READ_MASK) |
4280                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4281         while (num--)
4282                 *(out++) = RREG32(mmSQ_IND_DATA);
4283 }
4284
4285 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4286 {
4287         /* type 0 wave data */
4288         dst[(*no_fields)++] = 0;
4289         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4290         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4291         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4292         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4293         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4294         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4295         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4296         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4297         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4298         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4299         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4300         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4301         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4302         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4303         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4304         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4305         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4306         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4307 }
4308
4309 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4310                                      uint32_t wave, uint32_t start,
4311                                      uint32_t size, uint32_t *dst)
4312 {
4313         wave_read_regs(
4314                 adev, simd, wave, 0,
4315                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4316 }
4317
4318 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4319         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4320         .select_se_sh = &gfx_v7_0_select_se_sh,
4321         .read_wave_data = &gfx_v7_0_read_wave_data,
4322         .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4323 };
4324
4325 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4326         .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4327         .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4328 };
4329
4330 static int gfx_v7_0_early_init(void *handle)
4331 {
4332         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4333
4334         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4335         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4336         adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4337         adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4338         gfx_v7_0_set_ring_funcs(adev);
4339         gfx_v7_0_set_irq_funcs(adev);
4340         gfx_v7_0_set_gds_init(adev);
4341
4342         return 0;
4343 }
4344
4345 static int gfx_v7_0_late_init(void *handle)
4346 {
4347         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4348         int r;
4349
4350         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4351         if (r)
4352                 return r;
4353
4354         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4355         if (r)
4356                 return r;
4357
4358         return 0;
4359 }
4360
4361 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4362 {
4363         u32 gb_addr_config;
4364         u32 mc_shared_chmap, mc_arb_ramcfg;
4365         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4366         u32 tmp;
4367
4368         switch (adev->asic_type) {
4369         case CHIP_BONAIRE:
4370                 adev->gfx.config.max_shader_engines = 2;
4371                 adev->gfx.config.max_tile_pipes = 4;
4372                 adev->gfx.config.max_cu_per_sh = 7;
4373                 adev->gfx.config.max_sh_per_se = 1;
4374                 adev->gfx.config.max_backends_per_se = 2;
4375                 adev->gfx.config.max_texture_channel_caches = 4;
4376                 adev->gfx.config.max_gprs = 256;
4377                 adev->gfx.config.max_gs_threads = 32;
4378                 adev->gfx.config.max_hw_contexts = 8;
4379
4380                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4381                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4382                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4383                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4384                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4385                 break;
4386         case CHIP_HAWAII:
4387                 adev->gfx.config.max_shader_engines = 4;
4388                 adev->gfx.config.max_tile_pipes = 16;
4389                 adev->gfx.config.max_cu_per_sh = 11;
4390                 adev->gfx.config.max_sh_per_se = 1;
4391                 adev->gfx.config.max_backends_per_se = 4;
4392                 adev->gfx.config.max_texture_channel_caches = 16;
4393                 adev->gfx.config.max_gprs = 256;
4394                 adev->gfx.config.max_gs_threads = 32;
4395                 adev->gfx.config.max_hw_contexts = 8;
4396
4397                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4398                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4399                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4400                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4401                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4402                 break;
4403         case CHIP_KAVERI:
4404                 adev->gfx.config.max_shader_engines = 1;
4405                 adev->gfx.config.max_tile_pipes = 4;
4406                 if ((adev->pdev->device == 0x1304) ||
4407                     (adev->pdev->device == 0x1305) ||
4408                     (adev->pdev->device == 0x130C) ||
4409                     (adev->pdev->device == 0x130F) ||
4410                     (adev->pdev->device == 0x1310) ||
4411                     (adev->pdev->device == 0x1311) ||
4412                     (adev->pdev->device == 0x131C)) {
4413                         adev->gfx.config.max_cu_per_sh = 8;
4414                         adev->gfx.config.max_backends_per_se = 2;
4415                 } else if ((adev->pdev->device == 0x1309) ||
4416                            (adev->pdev->device == 0x130A) ||
4417                            (adev->pdev->device == 0x130D) ||
4418                            (adev->pdev->device == 0x1313) ||
4419                            (adev->pdev->device == 0x131D)) {
4420                         adev->gfx.config.max_cu_per_sh = 6;
4421                         adev->gfx.config.max_backends_per_se = 2;
4422                 } else if ((adev->pdev->device == 0x1306) ||
4423                            (adev->pdev->device == 0x1307) ||
4424                            (adev->pdev->device == 0x130B) ||
4425                            (adev->pdev->device == 0x130E) ||
4426                            (adev->pdev->device == 0x1315) ||
4427                            (adev->pdev->device == 0x131B)) {
4428                         adev->gfx.config.max_cu_per_sh = 4;
4429                         adev->gfx.config.max_backends_per_se = 1;
4430                 } else {
4431                         adev->gfx.config.max_cu_per_sh = 3;
4432                         adev->gfx.config.max_backends_per_se = 1;
4433                 }
4434                 adev->gfx.config.max_sh_per_se = 1;
4435                 adev->gfx.config.max_texture_channel_caches = 4;
4436                 adev->gfx.config.max_gprs = 256;
4437                 adev->gfx.config.max_gs_threads = 16;
4438                 adev->gfx.config.max_hw_contexts = 8;
4439
4440                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4441                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4442                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4443                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4444                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4445                 break;
4446         case CHIP_KABINI:
4447         case CHIP_MULLINS:
4448         default:
4449                 adev->gfx.config.max_shader_engines = 1;
4450                 adev->gfx.config.max_tile_pipes = 2;
4451                 adev->gfx.config.max_cu_per_sh = 2;
4452                 adev->gfx.config.max_sh_per_se = 1;
4453                 adev->gfx.config.max_backends_per_se = 1;
4454                 adev->gfx.config.max_texture_channel_caches = 2;
4455                 adev->gfx.config.max_gprs = 256;
4456                 adev->gfx.config.max_gs_threads = 16;
4457                 adev->gfx.config.max_hw_contexts = 8;
4458
4459                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4460                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4461                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4462                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4463                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4464                 break;
4465         }
4466
4467         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4468         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4469         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4470
4471         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4472         adev->gfx.config.mem_max_burst_length_bytes = 256;
4473         if (adev->flags & AMD_IS_APU) {
4474                 /* Get memory bank mapping mode. */
4475                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4476                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4477                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4478
4479                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4480                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4481                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4482
4483                 /* Validate settings in case only one DIMM installed. */
4484                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4485                         dimm00_addr_map = 0;
4486                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4487                         dimm01_addr_map = 0;
4488                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4489                         dimm10_addr_map = 0;
4490                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4491                         dimm11_addr_map = 0;
4492
4493                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4494                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4495                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4496                         adev->gfx.config.mem_row_size_in_kb = 2;
4497                 else
4498                         adev->gfx.config.mem_row_size_in_kb = 1;
4499         } else {
4500                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4501                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4502                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4503                         adev->gfx.config.mem_row_size_in_kb = 4;
4504         }
4505         /* XXX use MC settings? */
4506         adev->gfx.config.shader_engine_tile_size = 32;
4507         adev->gfx.config.num_gpus = 1;
4508         adev->gfx.config.multi_gpu_tile_size = 64;
4509
4510         /* fix up row size */
4511         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4512         switch (adev->gfx.config.mem_row_size_in_kb) {
4513         case 1:
4514         default:
4515                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4516                 break;
4517         case 2:
4518                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4519                 break;
4520         case 4:
4521                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4522                 break;
4523         }
4524         adev->gfx.config.gb_addr_config = gb_addr_config;
4525 }
4526
4527 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4528                                         int mec, int pipe, int queue)
4529 {
4530         int r;
4531         unsigned irq_type;
4532         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4533
4534         /* mec0 is me1 */
4535         ring->me = mec + 1;
4536         ring->pipe = pipe;
4537         ring->queue = queue;
4538
4539         ring->ring_obj = NULL;
4540         ring->use_doorbell = true;
4541         ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
4542         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4543
4544         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4545                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4546                 + ring->pipe;
4547
4548         /* type-2 packets are deprecated on MEC, use type-3 instead */
4549         r = amdgpu_ring_init(adev, ring, 1024,
4550                         &adev->gfx.eop_irq, irq_type);
4551         if (r)
4552                 return r;
4553
4554
4555         return 0;
4556 }
4557
4558 static int gfx_v7_0_sw_init(void *handle)
4559 {
4560         struct amdgpu_ring *ring;
4561         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4562         int i, j, k, r, ring_id;
4563
4564         switch (adev->asic_type) {
4565         case CHIP_KAVERI:
4566                 adev->gfx.mec.num_mec = 2;
4567                 break;
4568         case CHIP_BONAIRE:
4569         case CHIP_HAWAII:
4570         case CHIP_KABINI:
4571         case CHIP_MULLINS:
4572         default:
4573                 adev->gfx.mec.num_mec = 1;
4574                 break;
4575         }
4576         adev->gfx.mec.num_pipe_per_mec = 4;
4577         adev->gfx.mec.num_queue_per_pipe = 8;
4578
4579         /* EOP Event */
4580         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4581         if (r)
4582                 return r;
4583
4584         /* Privileged reg */
4585         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
4586                               &adev->gfx.priv_reg_irq);
4587         if (r)
4588                 return r;
4589
4590         /* Privileged inst */
4591         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
4592                               &adev->gfx.priv_inst_irq);
4593         if (r)
4594                 return r;
4595
4596         gfx_v7_0_scratch_init(adev);
4597
4598         r = gfx_v7_0_init_microcode(adev);
4599         if (r) {
4600                 DRM_ERROR("Failed to load gfx firmware!\n");
4601                 return r;
4602         }
4603
4604         r = gfx_v7_0_rlc_init(adev);
4605         if (r) {
4606                 DRM_ERROR("Failed to init rlc BOs!\n");
4607                 return r;
4608         }
4609
4610         /* allocate mec buffers */
4611         r = gfx_v7_0_mec_init(adev);
4612         if (r) {
4613                 DRM_ERROR("Failed to init MEC BOs!\n");
4614                 return r;
4615         }
4616
4617         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4618                 ring = &adev->gfx.gfx_ring[i];
4619                 ring->ring_obj = NULL;
4620                 sprintf(ring->name, "gfx");
4621                 r = amdgpu_ring_init(adev, ring, 1024,
4622                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4623                 if (r)
4624                         return r;
4625         }
4626
4627         /* set up the compute queues - allocate horizontally across pipes */
4628         ring_id = 0;
4629         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4630                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4631                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4632                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4633                                         continue;
4634
4635                                 r = gfx_v7_0_compute_ring_init(adev,
4636                                                                 ring_id,
4637                                                                 i, k, j);
4638                                 if (r)
4639                                         return r;
4640
4641                                 ring_id++;
4642                         }
4643                 }
4644         }
4645
4646         /* reserve GDS, GWS and OA resource for gfx */
4647         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4648                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4649                                     &adev->gds.gds_gfx_bo, NULL, NULL);
4650         if (r)
4651                 return r;
4652
4653         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4654                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4655                                     &adev->gds.gws_gfx_bo, NULL, NULL);
4656         if (r)
4657                 return r;
4658
4659         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4660                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4661                                     &adev->gds.oa_gfx_bo, NULL, NULL);
4662         if (r)
4663                 return r;
4664
4665         adev->gfx.ce_ram_size = 0x8000;
4666
4667         gfx_v7_0_gpu_early_init(adev);
4668
4669         return r;
4670 }
4671
4672 static int gfx_v7_0_sw_fini(void *handle)
4673 {
4674         int i;
4675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4676
4677         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4678         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4679         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4680
4681         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4682                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4683         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4684                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4685
4686         gfx_v7_0_cp_compute_fini(adev);
4687         gfx_v7_0_rlc_fini(adev);
4688         gfx_v7_0_mec_fini(adev);
4689         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4690                                 &adev->gfx.rlc.clear_state_gpu_addr,
4691                                 (void **)&adev->gfx.rlc.cs_ptr);
4692         if (adev->gfx.rlc.cp_table_size) {
4693                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4694                                 &adev->gfx.rlc.cp_table_gpu_addr,
4695                                 (void **)&adev->gfx.rlc.cp_table_ptr);
4696         }
4697         gfx_v7_0_free_microcode(adev);
4698
4699         return 0;
4700 }
4701
4702 static int gfx_v7_0_hw_init(void *handle)
4703 {
4704         int r;
4705         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4706
4707         gfx_v7_0_gpu_init(adev);
4708
4709         /* init rlc */
4710         r = gfx_v7_0_rlc_resume(adev);
4711         if (r)
4712                 return r;
4713
4714         r = gfx_v7_0_cp_resume(adev);
4715         if (r)
4716                 return r;
4717
4718         return r;
4719 }
4720
4721 static int gfx_v7_0_hw_fini(void *handle)
4722 {
4723         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4724
4725         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4726         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4727         gfx_v7_0_cp_enable(adev, false);
4728         gfx_v7_0_rlc_stop(adev);
4729         gfx_v7_0_fini_pg(adev);
4730
4731         return 0;
4732 }
4733
4734 static int gfx_v7_0_suspend(void *handle)
4735 {
4736         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4737
4738         return gfx_v7_0_hw_fini(adev);
4739 }
4740
4741 static int gfx_v7_0_resume(void *handle)
4742 {
4743         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4744
4745         return gfx_v7_0_hw_init(adev);
4746 }
4747
4748 static bool gfx_v7_0_is_idle(void *handle)
4749 {
4750         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4751
4752         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4753                 return false;
4754         else
4755                 return true;
4756 }
4757
4758 static int gfx_v7_0_wait_for_idle(void *handle)
4759 {
4760         unsigned i;
4761         u32 tmp;
4762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4763
4764         for (i = 0; i < adev->usec_timeout; i++) {
4765                 /* read MC_STATUS */
4766                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4767
4768                 if (!tmp)
4769                         return 0;
4770                 udelay(1);
4771         }
4772         return -ETIMEDOUT;
4773 }
4774
4775 static int gfx_v7_0_soft_reset(void *handle)
4776 {
4777         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4778         u32 tmp;
4779         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4780
4781         /* GRBM_STATUS */
4782         tmp = RREG32(mmGRBM_STATUS);
4783         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4784                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4785                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4786                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4787                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4788                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4789                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4790                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4791
4792         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4793                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4794                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4795         }
4796
4797         /* GRBM_STATUS2 */
4798         tmp = RREG32(mmGRBM_STATUS2);
4799         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4800                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4801
4802         /* SRBM_STATUS */
4803         tmp = RREG32(mmSRBM_STATUS);
4804         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4805                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4806
4807         if (grbm_soft_reset || srbm_soft_reset) {
4808                 /* disable CG/PG */
4809                 gfx_v7_0_fini_pg(adev);
4810                 gfx_v7_0_update_cg(adev, false);
4811
4812                 /* stop the rlc */
4813                 gfx_v7_0_rlc_stop(adev);
4814
4815                 /* Disable GFX parsing/prefetching */
4816                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4817
4818                 /* Disable MEC parsing/prefetching */
4819                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4820
4821                 if (grbm_soft_reset) {
4822                         tmp = RREG32(mmGRBM_SOFT_RESET);
4823                         tmp |= grbm_soft_reset;
4824                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4825                         WREG32(mmGRBM_SOFT_RESET, tmp);
4826                         tmp = RREG32(mmGRBM_SOFT_RESET);
4827
4828                         udelay(50);
4829
4830                         tmp &= ~grbm_soft_reset;
4831                         WREG32(mmGRBM_SOFT_RESET, tmp);
4832                         tmp = RREG32(mmGRBM_SOFT_RESET);
4833                 }
4834
4835                 if (srbm_soft_reset) {
4836                         tmp = RREG32(mmSRBM_SOFT_RESET);
4837                         tmp |= srbm_soft_reset;
4838                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4839                         WREG32(mmSRBM_SOFT_RESET, tmp);
4840                         tmp = RREG32(mmSRBM_SOFT_RESET);
4841
4842                         udelay(50);
4843
4844                         tmp &= ~srbm_soft_reset;
4845                         WREG32(mmSRBM_SOFT_RESET, tmp);
4846                         tmp = RREG32(mmSRBM_SOFT_RESET);
4847                 }
4848                 /* Wait a little for things to settle down */
4849                 udelay(50);
4850         }
4851         return 0;
4852 }
4853
4854 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4855                                                  enum amdgpu_interrupt_state state)
4856 {
4857         u32 cp_int_cntl;
4858
4859         switch (state) {
4860         case AMDGPU_IRQ_STATE_DISABLE:
4861                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4862                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4863                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4864                 break;
4865         case AMDGPU_IRQ_STATE_ENABLE:
4866                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4867                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4868                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4869                 break;
4870         default:
4871                 break;
4872         }
4873 }
4874
4875 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4876                                                      int me, int pipe,
4877                                                      enum amdgpu_interrupt_state state)
4878 {
4879         u32 mec_int_cntl, mec_int_cntl_reg;
4880
4881         /*
4882          * amdgpu controls only the first MEC. That's why this function only
4883          * handles the setting of interrupts for this specific MEC. All other
4884          * pipes' interrupts are set by amdkfd.
4885          */
4886
4887         if (me == 1) {
4888                 switch (pipe) {
4889                 case 0:
4890                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4891                         break;
4892                 case 1:
4893                         mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4894                         break;
4895                 case 2:
4896                         mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4897                         break;
4898                 case 3:
4899                         mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4900                         break;
4901                 default:
4902                         DRM_DEBUG("invalid pipe %d\n", pipe);
4903                         return;
4904                 }
4905         } else {
4906                 DRM_DEBUG("invalid me %d\n", me);
4907                 return;
4908         }
4909
4910         switch (state) {
4911         case AMDGPU_IRQ_STATE_DISABLE:
4912                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4913                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4914                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4915                 break;
4916         case AMDGPU_IRQ_STATE_ENABLE:
4917                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4918                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4919                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4920                 break;
4921         default:
4922                 break;
4923         }
4924 }
4925
4926 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4927                                              struct amdgpu_irq_src *src,
4928                                              unsigned type,
4929                                              enum amdgpu_interrupt_state state)
4930 {
4931         u32 cp_int_cntl;
4932
4933         switch (state) {
4934         case AMDGPU_IRQ_STATE_DISABLE:
4935                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4936                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4937                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4938                 break;
4939         case AMDGPU_IRQ_STATE_ENABLE:
4940                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4941                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4942                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4943                 break;
4944         default:
4945                 break;
4946         }
4947
4948         return 0;
4949 }
4950
4951 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4952                                               struct amdgpu_irq_src *src,
4953                                               unsigned type,
4954                                               enum amdgpu_interrupt_state state)
4955 {
4956         u32 cp_int_cntl;
4957
4958         switch (state) {
4959         case AMDGPU_IRQ_STATE_DISABLE:
4960                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4961                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4962                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4963                 break;
4964         case AMDGPU_IRQ_STATE_ENABLE:
4965                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4966                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4967                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4968                 break;
4969         default:
4970                 break;
4971         }
4972
4973         return 0;
4974 }
4975
4976 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4977                                             struct amdgpu_irq_src *src,
4978                                             unsigned type,
4979                                             enum amdgpu_interrupt_state state)
4980 {
4981         switch (type) {
4982         case AMDGPU_CP_IRQ_GFX_EOP:
4983                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4984                 break;
4985         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4986                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4987                 break;
4988         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4989                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4990                 break;
4991         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4992                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4993                 break;
4994         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4995                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4996                 break;
4997         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4998                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4999                 break;
5000         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5001                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5002                 break;
5003         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5004                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5005                 break;
5006         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5007                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5008                 break;
5009         default:
5010                 break;
5011         }
5012         return 0;
5013 }
5014
5015 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5016                             struct amdgpu_irq_src *source,
5017                             struct amdgpu_iv_entry *entry)
5018 {
5019         u8 me_id, pipe_id;
5020         struct amdgpu_ring *ring;
5021         int i;
5022
5023         DRM_DEBUG("IH: CP EOP\n");
5024         me_id = (entry->ring_id & 0x0c) >> 2;
5025         pipe_id = (entry->ring_id & 0x03) >> 0;
5026         switch (me_id) {
5027         case 0:
5028                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5029                 break;
5030         case 1:
5031         case 2:
5032                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5033                         ring = &adev->gfx.compute_ring[i];
5034                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
5035                                 amdgpu_fence_process(ring);
5036                 }
5037                 break;
5038         }
5039         return 0;
5040 }
5041
5042 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5043                                  struct amdgpu_irq_src *source,
5044                                  struct amdgpu_iv_entry *entry)
5045 {
5046         DRM_ERROR("Illegal register access in command stream\n");
5047         schedule_work(&adev->reset_work);
5048         return 0;
5049 }
5050
5051 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5052                                   struct amdgpu_irq_src *source,
5053                                   struct amdgpu_iv_entry *entry)
5054 {
5055         DRM_ERROR("Illegal instruction in command stream\n");
5056         // XXX soft reset the gfx block only
5057         schedule_work(&adev->reset_work);
5058         return 0;
5059 }
5060
5061 static int gfx_v7_0_set_clockgating_state(void *handle,
5062                                           enum amd_clockgating_state state)
5063 {
5064         bool gate = false;
5065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5066
5067         if (state == AMD_CG_STATE_GATE)
5068                 gate = true;
5069
5070         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5071         /* order matters! */
5072         if (gate) {
5073                 gfx_v7_0_enable_mgcg(adev, true);
5074                 gfx_v7_0_enable_cgcg(adev, true);
5075         } else {
5076                 gfx_v7_0_enable_cgcg(adev, false);
5077                 gfx_v7_0_enable_mgcg(adev, false);
5078         }
5079         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5080
5081         return 0;
5082 }
5083
5084 static int gfx_v7_0_set_powergating_state(void *handle,
5085                                           enum amd_powergating_state state)
5086 {
5087         bool gate = false;
5088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5089
5090         if (state == AMD_PG_STATE_GATE)
5091                 gate = true;
5092
5093         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5094                               AMD_PG_SUPPORT_GFX_SMG |
5095                               AMD_PG_SUPPORT_GFX_DMG |
5096                               AMD_PG_SUPPORT_CP |
5097                               AMD_PG_SUPPORT_GDS |
5098                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
5099                 gfx_v7_0_update_gfx_pg(adev, gate);
5100                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5101                         gfx_v7_0_enable_cp_pg(adev, gate);
5102                         gfx_v7_0_enable_gds_pg(adev, gate);
5103                 }
5104         }
5105
5106         return 0;
5107 }
5108
5109 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5110         .name = "gfx_v7_0",
5111         .early_init = gfx_v7_0_early_init,
5112         .late_init = gfx_v7_0_late_init,
5113         .sw_init = gfx_v7_0_sw_init,
5114         .sw_fini = gfx_v7_0_sw_fini,
5115         .hw_init = gfx_v7_0_hw_init,
5116         .hw_fini = gfx_v7_0_hw_fini,
5117         .suspend = gfx_v7_0_suspend,
5118         .resume = gfx_v7_0_resume,
5119         .is_idle = gfx_v7_0_is_idle,
5120         .wait_for_idle = gfx_v7_0_wait_for_idle,
5121         .soft_reset = gfx_v7_0_soft_reset,
5122         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5123         .set_powergating_state = gfx_v7_0_set_powergating_state,
5124 };
5125
5126 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5127         .type = AMDGPU_RING_TYPE_GFX,
5128         .align_mask = 0xff,
5129         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5130         .support_64bit_ptrs = false,
5131         .get_rptr = gfx_v7_0_ring_get_rptr,
5132         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5133         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5134         .emit_frame_size =
5135                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5136                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5137                 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5138                 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5139                 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5140                 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5141                 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5142         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5143         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5144         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5145         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5146         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5147         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5148         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5149         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5150         .test_ring = gfx_v7_0_ring_test_ring,
5151         .test_ib = gfx_v7_0_ring_test_ib,
5152         .insert_nop = amdgpu_ring_insert_nop,
5153         .pad_ib = amdgpu_ring_generic_pad_ib,
5154         .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5155 };
5156
5157 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5158         .type = AMDGPU_RING_TYPE_COMPUTE,
5159         .align_mask = 0xff,
5160         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5161         .support_64bit_ptrs = false,
5162         .get_rptr = gfx_v7_0_ring_get_rptr,
5163         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5164         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5165         .emit_frame_size =
5166                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5167                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5168                 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5169                 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5170                 17 + /* gfx_v7_0_ring_emit_vm_flush */
5171                 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5172         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5173         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5174         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5175         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5176         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5177         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5178         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5179         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5180         .test_ring = gfx_v7_0_ring_test_ring,
5181         .test_ib = gfx_v7_0_ring_test_ib,
5182         .insert_nop = amdgpu_ring_insert_nop,
5183         .pad_ib = amdgpu_ring_generic_pad_ib,
5184 };
5185
5186 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5187 {
5188         int i;
5189
5190         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5191                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5192         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5193                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5194 }
5195
5196 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5197         .set = gfx_v7_0_set_eop_interrupt_state,
5198         .process = gfx_v7_0_eop_irq,
5199 };
5200
5201 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5202         .set = gfx_v7_0_set_priv_reg_fault_state,
5203         .process = gfx_v7_0_priv_reg_irq,
5204 };
5205
5206 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5207         .set = gfx_v7_0_set_priv_inst_fault_state,
5208         .process = gfx_v7_0_priv_inst_irq,
5209 };
5210
5211 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5212 {
5213         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5214         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5215
5216         adev->gfx.priv_reg_irq.num_types = 1;
5217         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5218
5219         adev->gfx.priv_inst_irq.num_types = 1;
5220         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5221 }
5222
5223 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5224 {
5225         /* init asci gds info */
5226         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5227         adev->gds.gws.total_size = 64;
5228         adev->gds.oa.total_size = 16;
5229
5230         if (adev->gds.mem.total_size == 64 * 1024) {
5231                 adev->gds.mem.gfx_partition_size = 4096;
5232                 adev->gds.mem.cs_partition_size = 4096;
5233
5234                 adev->gds.gws.gfx_partition_size = 4;
5235                 adev->gds.gws.cs_partition_size = 4;
5236
5237                 adev->gds.oa.gfx_partition_size = 4;
5238                 adev->gds.oa.cs_partition_size = 1;
5239         } else {
5240                 adev->gds.mem.gfx_partition_size = 1024;
5241                 adev->gds.mem.cs_partition_size = 1024;
5242
5243                 adev->gds.gws.gfx_partition_size = 16;
5244                 adev->gds.gws.cs_partition_size = 16;
5245
5246                 adev->gds.oa.gfx_partition_size = 4;
5247                 adev->gds.oa.cs_partition_size = 4;
5248         }
5249 }
5250
5251
5252 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5253 {
5254         int i, j, k, counter, active_cu_number = 0;
5255         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5256         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5257         unsigned disable_masks[4 * 2];
5258         u32 ao_cu_num;
5259
5260         if (adev->flags & AMD_IS_APU)
5261                 ao_cu_num = 2;
5262         else
5263                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5264
5265         memset(cu_info, 0, sizeof(*cu_info));
5266
5267         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5268
5269         mutex_lock(&adev->grbm_idx_mutex);
5270         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5271                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5272                         mask = 1;
5273                         ao_bitmap = 0;
5274                         counter = 0;
5275                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5276                         if (i < 4 && j < 2)
5277                                 gfx_v7_0_set_user_cu_inactive_bitmap(
5278                                         adev, disable_masks[i * 2 + j]);
5279                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5280                         cu_info->bitmap[i][j] = bitmap;
5281
5282                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5283                                 if (bitmap & mask) {
5284                                         if (counter < ao_cu_num)
5285                                                 ao_bitmap |= mask;
5286                                         counter ++;
5287                                 }
5288                                 mask <<= 1;
5289                         }
5290                         active_cu_number += counter;
5291                         if (i < 2 && j < 2)
5292                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5293                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5294                 }
5295         }
5296         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5297         mutex_unlock(&adev->grbm_idx_mutex);
5298
5299         cu_info->number = active_cu_number;
5300         cu_info->ao_cu_mask = ao_cu_mask;
5301 }
5302
5303 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5304 {
5305         .type = AMD_IP_BLOCK_TYPE_GFX,
5306         .major = 7,
5307         .minor = 0,
5308         .rev = 0,
5309         .funcs = &gfx_v7_0_ip_funcs,
5310 };
5311
5312 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5313 {
5314         .type = AMD_IP_BLOCK_TYPE_GFX,
5315         .major = 7,
5316         .minor = 1,
5317         .rev = 0,
5318         .funcs = &gfx_v7_0_ip_funcs,
5319 };
5320
5321 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5322 {
5323         .type = AMD_IP_BLOCK_TYPE_GFX,
5324         .major = 7,
5325         .minor = 2,
5326         .rev = 0,
5327         .funcs = &gfx_v7_0_ip_funcs,
5328 };
5329
5330 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5331 {
5332         .type = AMD_IP_BLOCK_TYPE_GFX,
5333         .major = 7,
5334         .minor = 3,
5335         .rev = 0,
5336         .funcs = &gfx_v7_0_ip_funcs,
5337 };