ec71e2a7d7b71c0af24f9e0a6f2818b3c5b06029
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / gfx_v10_0.c
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
33 #include "nv.h"
34 #include "nvd.h"
35
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "navi10_enum.h"
39 #include "hdp/hdp_5_0_0_offset.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "nbio_v2_3.h"
48
49 /**
50  * Navi10 has two graphic rings to share each graphic pipe.
51  * 1. Primary ring
52  * 2. Async ring
53  *
54  * In bring-up phase, it just used primary ring so set gfx ring number as 1 at
55  * first.
56  */
57 #define GFX10_NUM_GFX_RINGS     2
58 #define GFX10_MEC_HPD_SIZE      2048
59
60 #define F32_CE_PROGRAM_RAM_SIZE         65536
61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
62
63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
65
66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
68 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
72
73 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
74 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
75 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
76 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
77 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
78 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
79
80 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
81 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
82 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
83 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
84 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
85 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
86
87 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
88 {
89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
126 };
127
128 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
129 {
130         /* Pending on emulation bring up */
131 };
132
133 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
134 {
135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
170 };
171
172 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
173 {
174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
214 };
215
216 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
217 {
218         /* Pending on emulation bring up */
219 };
220
221 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
222 {
223         /* Pending on emulation bring up */
224 };
225
226 #define DEFAULT_SH_MEM_CONFIG \
227         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
228          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
229          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
230          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
231
232
233 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
234 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
235 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
236 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
237 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
238                                  struct amdgpu_cu_info *cu_info);
239 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
240 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
241                                    u32 sh_num, u32 instance);
242 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
243
244 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
245 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
246 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
247 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
248 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
249 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
250 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
251
252 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
253 {
254         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
255         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
256                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
257         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
258         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
259         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
260         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
261         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
262         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
263 }
264
265 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
266                                  struct amdgpu_ring *ring)
267 {
268         struct amdgpu_device *adev = kiq_ring->adev;
269         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
270         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
271         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
272
273         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
274         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
275         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
276                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
277                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
278                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
279                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
280                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
281                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
282                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
283                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
284                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
285         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
286         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
287         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
288         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
289         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
290 }
291
292 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
293                                    struct amdgpu_ring *ring,
294                                    enum amdgpu_unmap_queues_action action,
295                                    u64 gpu_addr, u64 seq)
296 {
297         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
298
299         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
300         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
301                           PACKET3_UNMAP_QUEUES_ACTION(action) |
302                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
303                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
304                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
305         amdgpu_ring_write(kiq_ring,
306                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
307
308         if (action == PREEMPT_QUEUES_NO_UNMAP) {
309                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
310                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
311                 amdgpu_ring_write(kiq_ring, seq);
312         } else {
313                 amdgpu_ring_write(kiq_ring, 0);
314                 amdgpu_ring_write(kiq_ring, 0);
315                 amdgpu_ring_write(kiq_ring, 0);
316         }
317 }
318
319 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
320                                    struct amdgpu_ring *ring,
321                                    u64 addr,
322                                    u64 seq)
323 {
324         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
325
326         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
327         amdgpu_ring_write(kiq_ring,
328                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
329                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
330                           PACKET3_QUERY_STATUS_COMMAND(2));
331         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
332                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
333                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
334         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
335         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
336         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
337         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
338 }
339
340 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
341         .kiq_set_resources = gfx10_kiq_set_resources,
342         .kiq_map_queues = gfx10_kiq_map_queues,
343         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
344         .kiq_query_status = gfx10_kiq_query_status,
345         .set_resources_size = 8,
346         .map_queues_size = 7,
347         .unmap_queues_size = 6,
348         .query_status_size = 7,
349 };
350
351 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
352 {
353         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
354 }
355
356 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
357 {
358         switch (adev->asic_type) {
359         case CHIP_NAVI10:
360                 soc15_program_register_sequence(adev,
361                                                 golden_settings_gc_10_1,
362                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
363                 soc15_program_register_sequence(adev,
364                                                 golden_settings_gc_10_0_nv10,
365                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
366                 break;
367         case CHIP_NAVI14:
368                 soc15_program_register_sequence(adev,
369                                                 golden_settings_gc_10_1_1,
370                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
371                 soc15_program_register_sequence(adev,
372                                                 golden_settings_gc_10_1_nv14,
373                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
374                 break;
375         case CHIP_NAVI12:
376                 soc15_program_register_sequence(adev,
377                                                 golden_settings_gc_10_1_2,
378                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
379                 soc15_program_register_sequence(adev,
380                                                 golden_settings_gc_10_1_2_nv12,
381                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
382                 break;
383         default:
384                 break;
385         }
386 }
387
388 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
389 {
390         adev->gfx.scratch.num_reg = 8;
391         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
392         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
393 }
394
395 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
396                                        bool wc, uint32_t reg, uint32_t val)
397 {
398         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
399         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
400                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
401         amdgpu_ring_write(ring, reg);
402         amdgpu_ring_write(ring, 0);
403         amdgpu_ring_write(ring, val);
404 }
405
406 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
407                                   int mem_space, int opt, uint32_t addr0,
408                                   uint32_t addr1, uint32_t ref, uint32_t mask,
409                                   uint32_t inv)
410 {
411         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
412         amdgpu_ring_write(ring,
413                           /* memory (1) or register (0) */
414                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
415                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
416                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
417                            WAIT_REG_MEM_ENGINE(eng_sel)));
418
419         if (mem_space)
420                 BUG_ON(addr0 & 0x3); /* Dword align */
421         amdgpu_ring_write(ring, addr0);
422         amdgpu_ring_write(ring, addr1);
423         amdgpu_ring_write(ring, ref);
424         amdgpu_ring_write(ring, mask);
425         amdgpu_ring_write(ring, inv); /* poll interval */
426 }
427
428 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
429 {
430         struct amdgpu_device *adev = ring->adev;
431         uint32_t scratch;
432         uint32_t tmp = 0;
433         unsigned i;
434         int r;
435
436         r = amdgpu_gfx_scratch_get(adev, &scratch);
437         if (r) {
438                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
439                 return r;
440         }
441
442         WREG32(scratch, 0xCAFEDEAD);
443
444         r = amdgpu_ring_alloc(ring, 3);
445         if (r) {
446                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
447                           ring->idx, r);
448                 amdgpu_gfx_scratch_free(adev, scratch);
449                 return r;
450         }
451
452         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
453         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
454         amdgpu_ring_write(ring, 0xDEADBEEF);
455         amdgpu_ring_commit(ring);
456
457         for (i = 0; i < adev->usec_timeout; i++) {
458                 tmp = RREG32(scratch);
459                 if (tmp == 0xDEADBEEF)
460                         break;
461                 if (amdgpu_emu_mode == 1)
462                         msleep(1);
463                 else
464                         udelay(1);
465         }
466         if (i < adev->usec_timeout) {
467                 if (amdgpu_emu_mode == 1)
468                         DRM_INFO("ring test on %d succeeded in %d msecs\n",
469                                  ring->idx, i);
470                 else
471                         DRM_INFO("ring test on %d succeeded in %d usecs\n",
472                                  ring->idx, i);
473         } else {
474                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
475                           ring->idx, scratch, tmp);
476                 r = -EINVAL;
477         }
478         amdgpu_gfx_scratch_free(adev, scratch);
479
480         return r;
481 }
482
483 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
484 {
485         struct amdgpu_device *adev = ring->adev;
486         struct amdgpu_ib ib;
487         struct dma_fence *f = NULL;
488         uint32_t scratch;
489         uint32_t tmp = 0;
490         long r;
491
492         r = amdgpu_gfx_scratch_get(adev, &scratch);
493         if (r) {
494                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
495                 return r;
496         }
497
498         WREG32(scratch, 0xCAFEDEAD);
499
500         memset(&ib, 0, sizeof(ib));
501         r = amdgpu_ib_get(adev, NULL, 256, &ib);
502         if (r) {
503                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
504                 goto err1;
505         }
506
507         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
508         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
509         ib.ptr[2] = 0xDEADBEEF;
510         ib.length_dw = 3;
511
512         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
513         if (r)
514                 goto err2;
515
516         r = dma_fence_wait_timeout(f, false, timeout);
517         if (r == 0) {
518                 DRM_ERROR("amdgpu: IB test timed out.\n");
519                 r = -ETIMEDOUT;
520                 goto err2;
521         } else if (r < 0) {
522                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
523                 goto err2;
524         }
525
526         tmp = RREG32(scratch);
527         if (tmp == 0xDEADBEEF) {
528                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
529                 r = 0;
530         } else {
531                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
532                           scratch, tmp);
533                 r = -EINVAL;
534         }
535 err2:
536         amdgpu_ib_free(adev, &ib, NULL);
537         dma_fence_put(f);
538 err1:
539         amdgpu_gfx_scratch_free(adev, scratch);
540
541         return r;
542 }
543
544 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
545 {
546         release_firmware(adev->gfx.pfp_fw);
547         adev->gfx.pfp_fw = NULL;
548         release_firmware(adev->gfx.me_fw);
549         adev->gfx.me_fw = NULL;
550         release_firmware(adev->gfx.ce_fw);
551         adev->gfx.ce_fw = NULL;
552         release_firmware(adev->gfx.rlc_fw);
553         adev->gfx.rlc_fw = NULL;
554         release_firmware(adev->gfx.mec_fw);
555         adev->gfx.mec_fw = NULL;
556         release_firmware(adev->gfx.mec2_fw);
557         adev->gfx.mec2_fw = NULL;
558
559         kfree(adev->gfx.rlc.register_list_format);
560 }
561
562 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
563 {
564         const struct rlc_firmware_header_v2_1 *rlc_hdr;
565
566         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
567         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
568         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
569         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
570         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
571         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
572         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
573         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
574         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
575         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
576         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
577         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
578         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
579         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
580                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
581 }
582
583 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
584 {
585         switch (adev->asic_type) {
586         case CHIP_NAVI10:
587                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
588                 break;
589         default:
590                 break;
591         }
592 }
593
594 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
595 {
596         const char *chip_name;
597         char fw_name[30];
598         int err;
599         struct amdgpu_firmware_info *info = NULL;
600         const struct common_firmware_header *header = NULL;
601         const struct gfx_firmware_header_v1_0 *cp_hdr;
602         const struct rlc_firmware_header_v2_0 *rlc_hdr;
603         unsigned int *tmp = NULL;
604         unsigned int i = 0;
605         uint16_t version_major;
606         uint16_t version_minor;
607
608         DRM_DEBUG("\n");
609
610         switch (adev->asic_type) {
611         case CHIP_NAVI10:
612                 chip_name = "navi10";
613                 break;
614         case CHIP_NAVI14:
615                 chip_name = "navi14";
616                 break;
617         case CHIP_NAVI12:
618                 chip_name = "navi12";
619                 break;
620         default:
621                 BUG();
622         }
623
624         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
625         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
626         if (err)
627                 goto out;
628         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
629         if (err)
630                 goto out;
631         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
632         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
633         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
634
635         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
636         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
637         if (err)
638                 goto out;
639         err = amdgpu_ucode_validate(adev->gfx.me_fw);
640         if (err)
641                 goto out;
642         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
643         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
644         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
645
646         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
647         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
648         if (err)
649                 goto out;
650         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
651         if (err)
652                 goto out;
653         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
654         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
655         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
656
657         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
658         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
659         if (err)
660                 goto out;
661         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
662         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
663         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
664         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
665         if (version_major == 2 && version_minor == 1)
666                 adev->gfx.rlc.is_rlc_v2_1 = true;
667
668         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
669         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
670         adev->gfx.rlc.save_and_restore_offset =
671                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
672         adev->gfx.rlc.clear_state_descriptor_offset =
673                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
674         adev->gfx.rlc.avail_scratch_ram_locations =
675                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
676         adev->gfx.rlc.reg_restore_list_size =
677                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
678         adev->gfx.rlc.reg_list_format_start =
679                         le32_to_cpu(rlc_hdr->reg_list_format_start);
680         adev->gfx.rlc.reg_list_format_separate_start =
681                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
682         adev->gfx.rlc.starting_offsets_start =
683                         le32_to_cpu(rlc_hdr->starting_offsets_start);
684         adev->gfx.rlc.reg_list_format_size_bytes =
685                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
686         adev->gfx.rlc.reg_list_size_bytes =
687                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
688         adev->gfx.rlc.register_list_format =
689                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
690                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
691         if (!adev->gfx.rlc.register_list_format) {
692                 err = -ENOMEM;
693                 goto out;
694         }
695
696         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
697                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
698         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
699                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
700
701         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
702
703         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
704                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
705         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
706                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
707
708         if (adev->gfx.rlc.is_rlc_v2_1)
709                 gfx_v10_0_init_rlc_ext_microcode(adev);
710
711         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
712         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
713         if (err)
714                 goto out;
715         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
716         if (err)
717                 goto out;
718         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
719         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
720         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
721
722         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
723         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
724         if (!err) {
725                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
726                 if (err)
727                         goto out;
728                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
729                 adev->gfx.mec2_fw->data;
730                 adev->gfx.mec2_fw_version =
731                 le32_to_cpu(cp_hdr->header.ucode_version);
732                 adev->gfx.mec2_feature_version =
733                 le32_to_cpu(cp_hdr->ucode_feature_version);
734         } else {
735                 err = 0;
736                 adev->gfx.mec2_fw = NULL;
737         }
738
739         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
740                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
741                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
742                 info->fw = adev->gfx.pfp_fw;
743                 header = (const struct common_firmware_header *)info->fw->data;
744                 adev->firmware.fw_size +=
745                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
746
747                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
748                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
749                 info->fw = adev->gfx.me_fw;
750                 header = (const struct common_firmware_header *)info->fw->data;
751                 adev->firmware.fw_size +=
752                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
753
754                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
755                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
756                 info->fw = adev->gfx.ce_fw;
757                 header = (const struct common_firmware_header *)info->fw->data;
758                 adev->firmware.fw_size +=
759                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
760
761                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
762                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
763                 info->fw = adev->gfx.rlc_fw;
764                 header = (const struct common_firmware_header *)info->fw->data;
765                 adev->firmware.fw_size +=
766                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
767
768                 if (adev->gfx.rlc.is_rlc_v2_1 &&
769                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
770                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
771                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
772                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
773                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
774                         info->fw = adev->gfx.rlc_fw;
775                         adev->firmware.fw_size +=
776                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
777
778                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
779                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
780                         info->fw = adev->gfx.rlc_fw;
781                         adev->firmware.fw_size +=
782                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
783
784                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
785                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
786                         info->fw = adev->gfx.rlc_fw;
787                         adev->firmware.fw_size +=
788                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
789                 }
790
791                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
792                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
793                 info->fw = adev->gfx.mec_fw;
794                 header = (const struct common_firmware_header *)info->fw->data;
795                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
796                 adev->firmware.fw_size +=
797                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
798                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
799
800                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
801                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
802                 info->fw = adev->gfx.mec_fw;
803                 adev->firmware.fw_size +=
804                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
805
806                 if (adev->gfx.mec2_fw) {
807                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
808                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
809                         info->fw = adev->gfx.mec2_fw;
810                         header = (const struct common_firmware_header *)info->fw->data;
811                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
812                         adev->firmware.fw_size +=
813                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
814                                       le32_to_cpu(cp_hdr->jt_size) * 4,
815                                       PAGE_SIZE);
816                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
817                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
818                         info->fw = adev->gfx.mec2_fw;
819                         adev->firmware.fw_size +=
820                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
821                                       PAGE_SIZE);
822                 }
823         }
824
825 out:
826         if (err) {
827                 dev_err(adev->dev,
828                         "gfx10: Failed to load firmware \"%s\"\n",
829                         fw_name);
830                 release_firmware(adev->gfx.pfp_fw);
831                 adev->gfx.pfp_fw = NULL;
832                 release_firmware(adev->gfx.me_fw);
833                 adev->gfx.me_fw = NULL;
834                 release_firmware(adev->gfx.ce_fw);
835                 adev->gfx.ce_fw = NULL;
836                 release_firmware(adev->gfx.rlc_fw);
837                 adev->gfx.rlc_fw = NULL;
838                 release_firmware(adev->gfx.mec_fw);
839                 adev->gfx.mec_fw = NULL;
840                 release_firmware(adev->gfx.mec2_fw);
841                 adev->gfx.mec2_fw = NULL;
842         }
843
844         gfx_v10_0_check_gfxoff_flag(adev);
845
846         return err;
847 }
848
849 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
850 {
851         u32 count = 0;
852         const struct cs_section_def *sect = NULL;
853         const struct cs_extent_def *ext = NULL;
854
855         /* begin clear state */
856         count += 2;
857         /* context control state */
858         count += 3;
859
860         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
861                 for (ext = sect->section; ext->extent != NULL; ++ext) {
862                         if (sect->id == SECT_CONTEXT)
863                                 count += 2 + ext->reg_count;
864                         else
865                                 return 0;
866                 }
867         }
868
869         /* set PA_SC_TILE_STEERING_OVERRIDE */
870         count += 3;
871         /* end clear state */
872         count += 2;
873         /* clear state */
874         count += 2;
875
876         return count;
877 }
878
879 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
880                                     volatile u32 *buffer)
881 {
882         u32 count = 0, i;
883         const struct cs_section_def *sect = NULL;
884         const struct cs_extent_def *ext = NULL;
885         int ctx_reg_offset;
886
887         if (adev->gfx.rlc.cs_data == NULL)
888                 return;
889         if (buffer == NULL)
890                 return;
891
892         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
893         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
894
895         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
896         buffer[count++] = cpu_to_le32(0x80000000);
897         buffer[count++] = cpu_to_le32(0x80000000);
898
899         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
900                 for (ext = sect->section; ext->extent != NULL; ++ext) {
901                         if (sect->id == SECT_CONTEXT) {
902                                 buffer[count++] =
903                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
904                                 buffer[count++] = cpu_to_le32(ext->reg_index -
905                                                 PACKET3_SET_CONTEXT_REG_START);
906                                 for (i = 0; i < ext->reg_count; i++)
907                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
908                         } else {
909                                 return;
910                         }
911                 }
912         }
913
914         ctx_reg_offset =
915                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
916         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
917         buffer[count++] = cpu_to_le32(ctx_reg_offset);
918         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
919
920         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
921         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
922
923         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
924         buffer[count++] = cpu_to_le32(0);
925 }
926
927 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
928 {
929         /* clear state block */
930         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
931                         &adev->gfx.rlc.clear_state_gpu_addr,
932                         (void **)&adev->gfx.rlc.cs_ptr);
933
934         /* jump table block */
935         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
936                         &adev->gfx.rlc.cp_table_gpu_addr,
937                         (void **)&adev->gfx.rlc.cp_table_ptr);
938 }
939
940 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
941 {
942         const struct cs_section_def *cs_data;
943         int r;
944
945         adev->gfx.rlc.cs_data = gfx10_cs_data;
946
947         cs_data = adev->gfx.rlc.cs_data;
948
949         if (cs_data) {
950                 /* init clear state block */
951                 r = amdgpu_gfx_rlc_init_csb(adev);
952                 if (r)
953                         return r;
954         }
955
956         return 0;
957 }
958
959 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev)
960 {
961         int r;
962
963         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
964         if (unlikely(r != 0))
965                 return r;
966
967         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
968                         AMDGPU_GEM_DOMAIN_VRAM);
969         if (!r)
970                 adev->gfx.rlc.clear_state_gpu_addr =
971                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
972
973         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
974
975         return r;
976 }
977
978 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev)
979 {
980         int r;
981
982         if (!adev->gfx.rlc.clear_state_obj)
983                 return;
984
985         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
986         if (likely(r == 0)) {
987                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
988                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
989         }
990 }
991
992 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
993 {
994         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
995         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
996 }
997
998 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
999 {
1000         int r;
1001
1002         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1003
1004         amdgpu_gfx_graphics_queue_acquire(adev);
1005
1006         r = gfx_v10_0_init_microcode(adev);
1007         if (r)
1008                 DRM_ERROR("Failed to load gfx firmware!\n");
1009
1010         return r;
1011 }
1012
1013 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1014 {
1015         int r;
1016         u32 *hpd;
1017         const __le32 *fw_data = NULL;
1018         unsigned fw_size;
1019         u32 *fw = NULL;
1020         size_t mec_hpd_size;
1021
1022         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1023
1024         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1025
1026         /* take ownership of the relevant compute queues */
1027         amdgpu_gfx_compute_queue_acquire(adev);
1028         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1029
1030         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1031                                       AMDGPU_GEM_DOMAIN_GTT,
1032                                       &adev->gfx.mec.hpd_eop_obj,
1033                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1034                                       (void **)&hpd);
1035         if (r) {
1036                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1037                 gfx_v10_0_mec_fini(adev);
1038                 return r;
1039         }
1040
1041         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1042
1043         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1044         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1045
1046         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1047                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1048
1049                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1050                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1051                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1052
1053                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1054                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1055                                               &adev->gfx.mec.mec_fw_obj,
1056                                               &adev->gfx.mec.mec_fw_gpu_addr,
1057                                               (void **)&fw);
1058                 if (r) {
1059                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1060                         gfx_v10_0_mec_fini(adev);
1061                         return r;
1062                 }
1063
1064                 memcpy(fw, fw_data, fw_size);
1065
1066                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1067                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1068         }
1069
1070         return 0;
1071 }
1072
1073 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1074 {
1075         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1076                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1077                 (address << SQ_IND_INDEX__INDEX__SHIFT));
1078         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1079 }
1080
1081 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1082                            uint32_t thread, uint32_t regno,
1083                            uint32_t num, uint32_t *out)
1084 {
1085         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1086                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1087                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1088                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1089                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1090         while (num--)
1091                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1092 }
1093
1094 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1095 {
1096         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
1097          * field when performing a select_se_sh so it should be
1098          * zero here */
1099         WARN_ON(simd != 0);
1100
1101         /* type 2 wave data */
1102         dst[(*no_fields)++] = 2;
1103         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1104         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1105         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1106         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1107         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1108         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1109         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1110         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1111         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1112         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1113         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1114         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1115         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1116         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1117         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1118 }
1119
1120 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1121                                      uint32_t wave, uint32_t start,
1122                                      uint32_t size, uint32_t *dst)
1123 {
1124         WARN_ON(simd != 0);
1125
1126         wave_read_regs(
1127                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1128                 dst);
1129 }
1130
1131 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1132                                       uint32_t wave, uint32_t thread,
1133                                       uint32_t start, uint32_t size,
1134                                       uint32_t *dst)
1135 {
1136         wave_read_regs(
1137                 adev, wave, thread,
1138                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1139 }
1140
1141 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1142                                                                           u32 me, u32 pipe, u32 q, u32 vm)
1143  {
1144        nv_grbm_select(adev, me, pipe, q, vm);
1145  }
1146
1147
1148 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1149         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1150         .select_se_sh = &gfx_v10_0_select_se_sh,
1151         .read_wave_data = &gfx_v10_0_read_wave_data,
1152         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1153         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1154         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1155 };
1156
1157 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1158 {
1159         u32 gb_addr_config;
1160
1161         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1162
1163         switch (adev->asic_type) {
1164         case CHIP_NAVI10:
1165         case CHIP_NAVI14:
1166         case CHIP_NAVI12:
1167                 adev->gfx.config.max_hw_contexts = 8;
1168                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1169                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1170                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1171                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1172                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1173                 break;
1174         default:
1175                 BUG();
1176                 break;
1177         }
1178
1179         adev->gfx.config.gb_addr_config = gb_addr_config;
1180
1181         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1182                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1183                                       GB_ADDR_CONFIG, NUM_PIPES);
1184
1185         adev->gfx.config.max_tile_pipes =
1186                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1187
1188         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1189                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1190                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1191         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1192                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1193                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
1194         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1195                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1196                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1197         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1198                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1199                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1200 }
1201
1202 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1203                                    int me, int pipe, int queue)
1204 {
1205         int r;
1206         struct amdgpu_ring *ring;
1207         unsigned int irq_type;
1208
1209         ring = &adev->gfx.gfx_ring[ring_id];
1210
1211         ring->me = me;
1212         ring->pipe = pipe;
1213         ring->queue = queue;
1214
1215         ring->ring_obj = NULL;
1216         ring->use_doorbell = true;
1217
1218         if (!ring_id)
1219                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1220         else
1221                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1222         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1223
1224         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1225         r = amdgpu_ring_init(adev, ring, 1024,
1226                              &adev->gfx.eop_irq, irq_type);
1227         if (r)
1228                 return r;
1229         return 0;
1230 }
1231
1232 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1233                                        int mec, int pipe, int queue)
1234 {
1235         int r;
1236         unsigned irq_type;
1237         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1238
1239         ring = &adev->gfx.compute_ring[ring_id];
1240
1241         /* mec0 is me1 */
1242         ring->me = mec + 1;
1243         ring->pipe = pipe;
1244         ring->queue = queue;
1245
1246         ring->ring_obj = NULL;
1247         ring->use_doorbell = true;
1248         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1249         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1250                                 + (ring_id * GFX10_MEC_HPD_SIZE);
1251         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1252
1253         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1254                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1255                 + ring->pipe;
1256
1257         /* type-2 packets are deprecated on MEC, use type-3 instead */
1258         r = amdgpu_ring_init(adev, ring, 1024,
1259                              &adev->gfx.eop_irq, irq_type);
1260         if (r)
1261                 return r;
1262
1263         return 0;
1264 }
1265
1266 static int gfx_v10_0_sw_init(void *handle)
1267 {
1268         int i, j, k, r, ring_id = 0;
1269         struct amdgpu_kiq *kiq;
1270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271
1272         switch (adev->asic_type) {
1273         case CHIP_NAVI10:
1274         case CHIP_NAVI14:
1275         case CHIP_NAVI12:
1276                 adev->gfx.me.num_me = 1;
1277                 adev->gfx.me.num_pipe_per_me = 2;
1278                 adev->gfx.me.num_queue_per_pipe = 1;
1279                 adev->gfx.mec.num_mec = 2;
1280                 adev->gfx.mec.num_pipe_per_mec = 4;
1281                 adev->gfx.mec.num_queue_per_pipe = 8;
1282                 break;
1283         default:
1284                 adev->gfx.me.num_me = 1;
1285                 adev->gfx.me.num_pipe_per_me = 1;
1286                 adev->gfx.me.num_queue_per_pipe = 1;
1287                 adev->gfx.mec.num_mec = 1;
1288                 adev->gfx.mec.num_pipe_per_mec = 4;
1289                 adev->gfx.mec.num_queue_per_pipe = 8;
1290                 break;
1291         }
1292
1293         /* KIQ event */
1294         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1295                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1296                               &adev->gfx.kiq.irq);
1297         if (r)
1298                 return r;
1299
1300         /* EOP Event */
1301         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1302                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1303                               &adev->gfx.eop_irq);
1304         if (r)
1305                 return r;
1306
1307         /* Privileged reg */
1308         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1309                               &adev->gfx.priv_reg_irq);
1310         if (r)
1311                 return r;
1312
1313         /* Privileged inst */
1314         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1315                               &adev->gfx.priv_inst_irq);
1316         if (r)
1317                 return r;
1318
1319         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1320
1321         gfx_v10_0_scratch_init(adev);
1322
1323         r = gfx_v10_0_me_init(adev);
1324         if (r)
1325                 return r;
1326
1327         r = gfx_v10_0_rlc_init(adev);
1328         if (r) {
1329                 DRM_ERROR("Failed to init rlc BOs!\n");
1330                 return r;
1331         }
1332
1333         r = gfx_v10_0_mec_init(adev);
1334         if (r) {
1335                 DRM_ERROR("Failed to init MEC BOs!\n");
1336                 return r;
1337         }
1338
1339         /* set up the gfx ring */
1340         for (i = 0; i < adev->gfx.me.num_me; i++) {
1341                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1342                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1343                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1344                                         continue;
1345
1346                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1347                                                             i, k, j);
1348                                 if (r)
1349                                         return r;
1350                                 ring_id++;
1351                         }
1352                 }
1353         }
1354
1355         ring_id = 0;
1356         /* set up the compute queues - allocate horizontally across pipes */
1357         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1358                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1359                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1360                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1361                                                                      j))
1362                                         continue;
1363
1364                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1365                                                                 i, k, j);
1366                                 if (r)
1367                                         return r;
1368
1369                                 ring_id++;
1370                         }
1371                 }
1372         }
1373
1374         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1375         if (r) {
1376                 DRM_ERROR("Failed to init KIQ BOs!\n");
1377                 return r;
1378         }
1379
1380         kiq = &adev->gfx.kiq;
1381         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1382         if (r)
1383                 return r;
1384
1385         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1386         if (r)
1387                 return r;
1388
1389         /* allocate visible FB for rlc auto-loading fw */
1390         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1391                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1392                 if (r)
1393                         return r;
1394         }
1395
1396         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1397
1398         gfx_v10_0_gpu_early_init(adev);
1399
1400         return 0;
1401 }
1402
1403 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1404 {
1405         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1406                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1407                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1408 }
1409
1410 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1411 {
1412         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1413                               &adev->gfx.ce.ce_fw_gpu_addr,
1414                               (void **)&adev->gfx.ce.ce_fw_ptr);
1415 }
1416
1417 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1418 {
1419         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1420                               &adev->gfx.me.me_fw_gpu_addr,
1421                               (void **)&adev->gfx.me.me_fw_ptr);
1422 }
1423
1424 static int gfx_v10_0_sw_fini(void *handle)
1425 {
1426         int i;
1427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1428
1429         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1430                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1431         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1432                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1433
1434         amdgpu_gfx_mqd_sw_fini(adev);
1435         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1436         amdgpu_gfx_kiq_fini(adev);
1437
1438         gfx_v10_0_pfp_fini(adev);
1439         gfx_v10_0_ce_fini(adev);
1440         gfx_v10_0_me_fini(adev);
1441         gfx_v10_0_rlc_fini(adev);
1442         gfx_v10_0_mec_fini(adev);
1443
1444         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1445                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1446
1447         gfx_v10_0_free_microcode(adev);
1448
1449         return 0;
1450 }
1451
1452
1453 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1454 {
1455         /* TODO */
1456 }
1457
1458 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1459                                    u32 sh_num, u32 instance)
1460 {
1461         u32 data;
1462
1463         if (instance == 0xffffffff)
1464                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1465                                      INSTANCE_BROADCAST_WRITES, 1);
1466         else
1467                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1468                                      instance);
1469
1470         if (se_num == 0xffffffff)
1471                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1472                                      1);
1473         else
1474                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1475
1476         if (sh_num == 0xffffffff)
1477                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1478                                      1);
1479         else
1480                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1481
1482         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1483 }
1484
1485 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1486 {
1487         u32 data, mask;
1488
1489         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1490         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1491
1492         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1493         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1494
1495         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1496                                          adev->gfx.config.max_sh_per_se);
1497
1498         return (~data) & mask;
1499 }
1500
1501 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1502 {
1503         int i, j;
1504         u32 data;
1505         u32 active_rbs = 0;
1506         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1507                                         adev->gfx.config.max_sh_per_se;
1508
1509         mutex_lock(&adev->grbm_idx_mutex);
1510         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1511                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1512                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1513                         data = gfx_v10_0_get_rb_active_bitmap(adev);
1514                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1515                                                rb_bitmap_width_per_sh);
1516                 }
1517         }
1518         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1519         mutex_unlock(&adev->grbm_idx_mutex);
1520
1521         adev->gfx.config.backend_enable_mask = active_rbs;
1522         adev->gfx.config.num_rbs = hweight32(active_rbs);
1523 }
1524
1525 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1526 {
1527         uint32_t num_sc;
1528         uint32_t enabled_rb_per_sh;
1529         uint32_t active_rb_bitmap;
1530         uint32_t num_rb_per_sc;
1531         uint32_t num_packer_per_sc;
1532         uint32_t pa_sc_tile_steering_override;
1533
1534         /* init num_sc */
1535         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1536                         adev->gfx.config.num_sc_per_sh;
1537         /* init num_rb_per_sc */
1538         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1539         enabled_rb_per_sh = hweight32(active_rb_bitmap);
1540         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1541         /* init num_packer_per_sc */
1542         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1543
1544         pa_sc_tile_steering_override = 0;
1545         pa_sc_tile_steering_override |=
1546                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1547                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1548         pa_sc_tile_steering_override |=
1549                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1550                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1551         pa_sc_tile_steering_override |=
1552                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1553                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1554
1555         return pa_sc_tile_steering_override;
1556 }
1557
1558 #define DEFAULT_SH_MEM_BASES    (0x6000)
1559 #define FIRST_COMPUTE_VMID      (8)
1560 #define LAST_COMPUTE_VMID       (16)
1561
1562 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1563 {
1564         int i;
1565         uint32_t sh_mem_bases;
1566
1567         /*
1568          * Configure apertures:
1569          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1570          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1571          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1572          */
1573         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1574
1575         mutex_lock(&adev->srbm_mutex);
1576         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1577                 nv_grbm_select(adev, 0, 0, 0, i);
1578                 /* CP and shaders */
1579                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1580                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1581         }
1582         nv_grbm_select(adev, 0, 0, 0, 0);
1583         mutex_unlock(&adev->srbm_mutex);
1584 }
1585
1586 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1587 {
1588         int vmid;
1589
1590         /*
1591          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1592          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1593          * the driver can enable them for graphics. VMID0 should maintain
1594          * access so that HWS firmware can save/restore entries.
1595          */
1596         for (vmid = 1; vmid < 16; vmid++) {
1597                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1598                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1599                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1600                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1601         }
1602 }
1603
1604
1605 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1606 {
1607         int i, j, k;
1608         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1609         u32 tmp, wgp_active_bitmap = 0;
1610         u32 gcrd_targets_disable_tcp = 0;
1611         u32 utcl_invreq_disable = 0;
1612         /*
1613          * GCRD_TARGETS_DISABLE field contains
1614          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
1615          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
1616          */
1617         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1618                 2 * max_wgp_per_sh + /* TCP */
1619                 max_wgp_per_sh + /* SQC */
1620                 4); /* GL1C */
1621         /*
1622          * UTCL1_UTCL0_INVREQ_DISABLE field contains
1623          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
1624          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
1625          */
1626         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1627                 2 * max_wgp_per_sh + /* TCP */
1628                 2 * max_wgp_per_sh + /* SQC */
1629                 4 + /* RMI */
1630                 1); /* SQG */
1631
1632         if (adev->asic_type == CHIP_NAVI10 ||
1633             adev->asic_type == CHIP_NAVI14 ||
1634             adev->asic_type == CHIP_NAVI12) {
1635                 mutex_lock(&adev->grbm_idx_mutex);
1636                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1637                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1638                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1639                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1640                                 /*
1641                                  * Set corresponding TCP bits for the inactive WGPs in
1642                                  * GCRD_SA_TARGETS_DISABLE
1643                                  */
1644                                 gcrd_targets_disable_tcp = 0;
1645                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
1646                                 utcl_invreq_disable = 0;
1647
1648                                 for (k = 0; k < max_wgp_per_sh; k++) {
1649                                         if (!(wgp_active_bitmap & (1 << k))) {
1650                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
1651                                                 utcl_invreq_disable |= (3 << (2 * k)) |
1652                                                         (3 << (2 * (max_wgp_per_sh + k)));
1653                                         }
1654                                 }
1655
1656                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1657                                 /* only override TCP & SQC bits */
1658                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1659                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1660                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1661
1662                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1663                                 /* only override TCP bits */
1664                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1665                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1666                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1667                         }
1668                 }
1669
1670                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1671                 mutex_unlock(&adev->grbm_idx_mutex);
1672         }
1673 }
1674
1675 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1676 {
1677         u32 tmp;
1678         int i;
1679
1680         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1681
1682         gfx_v10_0_tiling_mode_table_init(adev);
1683
1684         gfx_v10_0_setup_rb(adev);
1685         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1686         adev->gfx.config.pa_sc_tile_steering_override =
1687                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1688
1689         /* XXX SH_MEM regs */
1690         /* where to put LDS, scratch, GPUVM in FSA64 space */
1691         mutex_lock(&adev->srbm_mutex);
1692         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1693                 nv_grbm_select(adev, 0, 0, 0, i);
1694                 /* CP and shaders */
1695                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1696                 if (i != 0) {
1697                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1698                                 (adev->gmc.private_aperture_start >> 48));
1699                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1700                                 (adev->gmc.shared_aperture_start >> 48));
1701                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1702                 }
1703         }
1704         nv_grbm_select(adev, 0, 0, 0, 0);
1705
1706         mutex_unlock(&adev->srbm_mutex);
1707
1708         gfx_v10_0_init_compute_vmid(adev);
1709         gfx_v10_0_init_gds_vmid(adev);
1710
1711 }
1712
1713 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1714                                                bool enable)
1715 {
1716         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1717
1718         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1719                             enable ? 1 : 0);
1720         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1721                             enable ? 1 : 0);
1722         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1723                             enable ? 1 : 0);
1724         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1725                             enable ? 1 : 0);
1726
1727         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1728 }
1729
1730 static void gfx_v10_0_init_csb(struct amdgpu_device *adev)
1731 {
1732         /* csib */
1733         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1734                      adev->gfx.rlc.clear_state_gpu_addr >> 32);
1735         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1736                      adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1737         WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1738 }
1739
1740 static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
1741 {
1742         gfx_v10_0_init_csb(adev);
1743
1744         amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
1745
1746         /* TODO: init power gating */
1747         return;
1748 }
1749
1750 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1751 {
1752         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1753
1754         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1755         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1756 }
1757
1758 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1759 {
1760         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1761         udelay(50);
1762         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1763         udelay(50);
1764 }
1765
1766 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1767                                              bool enable)
1768 {
1769         uint32_t rlc_pg_cntl;
1770
1771         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1772
1773         if (!enable) {
1774                 /* RLC_PG_CNTL[23] = 0 (default)
1775                  * RLC will wait for handshake acks with SMU
1776                  * GFXOFF will be enabled
1777                  * RLC_PG_CNTL[23] = 1
1778                  * RLC will not issue any message to SMU
1779                  * hence no handshake between SMU & RLC
1780                  * GFXOFF will be disabled
1781                  */
1782                 rlc_pg_cntl |= 0x800000;
1783         } else
1784                 rlc_pg_cntl &= ~0x800000;
1785         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1786 }
1787
1788 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1789 {
1790         /* TODO: enable rlc & smu handshake until smu
1791          * and gfxoff feature works as expected */
1792         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1793                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1794
1795         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1796         udelay(50);
1797 }
1798
1799 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1800 {
1801         uint32_t tmp;
1802
1803         /* enable Save Restore Machine */
1804         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1805         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1806         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1807         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1808 }
1809
1810 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1811 {
1812         const struct rlc_firmware_header_v2_0 *hdr;
1813         const __le32 *fw_data;
1814         unsigned i, fw_size;
1815
1816         if (!adev->gfx.rlc_fw)
1817                 return -EINVAL;
1818
1819         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1820         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1821
1822         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1823                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1824         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1825
1826         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1827                      RLCG_UCODE_LOADING_START_ADDRESS);
1828
1829         for (i = 0; i < fw_size; i++)
1830                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1831                              le32_to_cpup(fw_data++));
1832
1833         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1834
1835         return 0;
1836 }
1837
1838 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1839 {
1840         int r;
1841
1842         if (amdgpu_sriov_vf(adev))
1843                 return 0;
1844
1845         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1846                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1847                 if (r)
1848                         return r;
1849                 gfx_v10_0_init_pg(adev);
1850
1851                 /* enable RLC SRM */
1852                 gfx_v10_0_rlc_enable_srm(adev);
1853
1854         } else {
1855                 adev->gfx.rlc.funcs->stop(adev);
1856
1857                 /* disable CG */
1858                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1859
1860                 /* disable PG */
1861                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1862
1863                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1864                         /* legacy rlc firmware loading */
1865                         r = gfx_v10_0_rlc_load_microcode(adev);
1866                         if (r)
1867                                 return r;
1868                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1869                         /* rlc backdoor autoload firmware */
1870                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1871                         if (r)
1872                                 return r;
1873                 }
1874
1875                 gfx_v10_0_init_pg(adev);
1876                 adev->gfx.rlc.funcs->start(adev);
1877
1878                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1879                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1880                         if (r)
1881                                 return r;
1882                 }
1883         }
1884         return 0;
1885 }
1886
1887 static struct {
1888         FIRMWARE_ID     id;
1889         unsigned int    offset;
1890         unsigned int    size;
1891 } rlc_autoload_info[FIRMWARE_ID_MAX];
1892
1893 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1894 {
1895         int ret;
1896         RLC_TABLE_OF_CONTENT *rlc_toc;
1897
1898         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1899                                         AMDGPU_GEM_DOMAIN_GTT,
1900                                         &adev->gfx.rlc.rlc_toc_bo,
1901                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
1902                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
1903         if (ret) {
1904                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1905                 return ret;
1906         }
1907
1908         /* Copy toc from psp sos fw to rlc toc buffer */
1909         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1910
1911         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1912         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1913                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1914                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1915                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1916                         /* Offset needs 4KB alignment */
1917                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1918                 }
1919
1920                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1921                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1922                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1923
1924                 rlc_toc++;
1925         };
1926
1927         return 0;
1928 }
1929
1930 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1931 {
1932         uint32_t total_size = 0;
1933         FIRMWARE_ID id;
1934         int ret;
1935
1936         ret = gfx_v10_0_parse_rlc_toc(adev);
1937         if (ret) {
1938                 dev_err(adev->dev, "failed to parse rlc toc\n");
1939                 return 0;
1940         }
1941
1942         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1943                 total_size += rlc_autoload_info[id].size;
1944
1945         /* In case the offset in rlc toc ucode is aligned */
1946         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1947                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1948                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1949
1950         return total_size;
1951 }
1952
1953 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
1954 {
1955         int r;
1956         uint32_t total_size;
1957
1958         total_size = gfx_v10_0_calc_toc_total_size(adev);
1959
1960         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
1961                                       AMDGPU_GEM_DOMAIN_GTT,
1962                                       &adev->gfx.rlc.rlc_autoload_bo,
1963                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1964                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1965         if (r) {
1966                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1967                 return r;
1968         }
1969
1970         return 0;
1971 }
1972
1973 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
1974 {
1975         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
1976                               &adev->gfx.rlc.rlc_toc_gpu_addr,
1977                               (void **)&adev->gfx.rlc.rlc_toc_buf);
1978         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1979                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
1980                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1981 }
1982
1983 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1984                                                        FIRMWARE_ID id,
1985                                                        const void *fw_data,
1986                                                        uint32_t fw_size)
1987 {
1988         uint32_t toc_offset;
1989         uint32_t toc_fw_size;
1990         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1991
1992         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
1993                 return;
1994
1995         toc_offset = rlc_autoload_info[id].offset;
1996         toc_fw_size = rlc_autoload_info[id].size;
1997
1998         if (fw_size == 0)
1999                 fw_size = toc_fw_size;
2000
2001         if (fw_size > toc_fw_size)
2002                 fw_size = toc_fw_size;
2003
2004         memcpy(ptr + toc_offset, fw_data, fw_size);
2005
2006         if (fw_size < toc_fw_size)
2007                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2008 }
2009
2010 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2011 {
2012         void *data;
2013         uint32_t size;
2014
2015         data = adev->gfx.rlc.rlc_toc_buf;
2016         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2017
2018         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2019                                                    FIRMWARE_ID_RLC_TOC,
2020                                                    data, size);
2021 }
2022
2023 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2024 {
2025         const __le32 *fw_data;
2026         uint32_t fw_size;
2027         const struct gfx_firmware_header_v1_0 *cp_hdr;
2028         const struct rlc_firmware_header_v2_0 *rlc_hdr;
2029
2030         /* pfp ucode */
2031         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2032                 adev->gfx.pfp_fw->data;
2033         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2034                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2035         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2036         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2037                                                    FIRMWARE_ID_CP_PFP,
2038                                                    fw_data, fw_size);
2039
2040         /* ce ucode */
2041         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2042                 adev->gfx.ce_fw->data;
2043         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2044                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2045         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2046         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2047                                                    FIRMWARE_ID_CP_CE,
2048                                                    fw_data, fw_size);
2049
2050         /* me ucode */
2051         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2052                 adev->gfx.me_fw->data;
2053         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2054                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2055         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2056         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2057                                                    FIRMWARE_ID_CP_ME,
2058                                                    fw_data, fw_size);
2059
2060         /* rlc ucode */
2061         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2062                 adev->gfx.rlc_fw->data;
2063         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2064                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2065         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2066         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2067                                                    FIRMWARE_ID_RLC_G_UCODE,
2068                                                    fw_data, fw_size);
2069
2070         /* mec1 ucode */
2071         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2072                 adev->gfx.mec_fw->data;
2073         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2074                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2075         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2076                 cp_hdr->jt_size * 4;
2077         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2078                                                    FIRMWARE_ID_CP_MEC,
2079                                                    fw_data, fw_size);
2080         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
2081 }
2082
2083 /* Temporarily put sdma part here */
2084 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2085 {
2086         const __le32 *fw_data;
2087         uint32_t fw_size;
2088         const struct sdma_firmware_header_v1_0 *sdma_hdr;
2089         int i;
2090
2091         for (i = 0; i < adev->sdma.num_instances; i++) {
2092                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2093                         adev->sdma.instance[i].fw->data;
2094                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2095                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2096                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2097
2098                 if (i == 0) {
2099                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2100                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2101                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2102                                 FIRMWARE_ID_SDMA0_JT,
2103                                 (uint32_t *)fw_data +
2104                                 sdma_hdr->jt_offset,
2105                                 sdma_hdr->jt_size * 4);
2106                 } else if (i == 1) {
2107                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2108                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2109                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2110                                 FIRMWARE_ID_SDMA1_JT,
2111                                 (uint32_t *)fw_data +
2112                                 sdma_hdr->jt_offset,
2113                                 sdma_hdr->jt_size * 4);
2114                 }
2115         }
2116 }
2117
2118 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2119 {
2120         uint32_t rlc_g_offset, rlc_g_size, tmp;
2121         uint64_t gpu_addr;
2122
2123         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2124         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2125         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2126
2127         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2128         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2129         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2130
2131         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2132         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2133         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2134
2135         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2136         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2137                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2138                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2139                 return -EINVAL;
2140         }
2141
2142         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2143         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2144                 DRM_ERROR("RLC ROM should halt itself\n");
2145                 return -EINVAL;
2146         }
2147
2148         return 0;
2149 }
2150
2151 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2152 {
2153         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2154         uint32_t tmp;
2155         int i;
2156         uint64_t addr;
2157
2158         /* Trigger an invalidation of the L1 instruction caches */
2159         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2160         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2161         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2162
2163         /* Wait for invalidation complete */
2164         for (i = 0; i < usec_timeout; i++) {
2165                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2166                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2167                         INVALIDATE_CACHE_COMPLETE))
2168                         break;
2169                 udelay(1);
2170         }
2171
2172         if (i >= usec_timeout) {
2173                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2174                 return -EINVAL;
2175         }
2176
2177         /* Program me ucode address into intruction cache address register */
2178         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2179                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2180         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2181                         lower_32_bits(addr) & 0xFFFFF000);
2182         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2183                         upper_32_bits(addr));
2184
2185         return 0;
2186 }
2187
2188 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2189 {
2190         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2191         uint32_t tmp;
2192         int i;
2193         uint64_t addr;
2194
2195         /* Trigger an invalidation of the L1 instruction caches */
2196         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2197         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2198         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2199
2200         /* Wait for invalidation complete */
2201         for (i = 0; i < usec_timeout; i++) {
2202                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2203                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2204                         INVALIDATE_CACHE_COMPLETE))
2205                         break;
2206                 udelay(1);
2207         }
2208
2209         if (i >= usec_timeout) {
2210                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2211                 return -EINVAL;
2212         }
2213
2214         /* Program ce ucode address into intruction cache address register */
2215         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2216                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2217         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2218                         lower_32_bits(addr) & 0xFFFFF000);
2219         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2220                         upper_32_bits(addr));
2221
2222         return 0;
2223 }
2224
2225 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2226 {
2227         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2228         uint32_t tmp;
2229         int i;
2230         uint64_t addr;
2231
2232         /* Trigger an invalidation of the L1 instruction caches */
2233         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2234         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2235         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2236
2237         /* Wait for invalidation complete */
2238         for (i = 0; i < usec_timeout; i++) {
2239                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2240                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2241                         INVALIDATE_CACHE_COMPLETE))
2242                         break;
2243                 udelay(1);
2244         }
2245
2246         if (i >= usec_timeout) {
2247                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2248                 return -EINVAL;
2249         }
2250
2251         /* Program pfp ucode address into intruction cache address register */
2252         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2253                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2254         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2255                         lower_32_bits(addr) & 0xFFFFF000);
2256         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2257                         upper_32_bits(addr));
2258
2259         return 0;
2260 }
2261
2262 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2263 {
2264         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2265         uint32_t tmp;
2266         int i;
2267         uint64_t addr;
2268
2269         /* Trigger an invalidation of the L1 instruction caches */
2270         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2271         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2272         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2273
2274         /* Wait for invalidation complete */
2275         for (i = 0; i < usec_timeout; i++) {
2276                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2277                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2278                         INVALIDATE_CACHE_COMPLETE))
2279                         break;
2280                 udelay(1);
2281         }
2282
2283         if (i >= usec_timeout) {
2284                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2285                 return -EINVAL;
2286         }
2287
2288         /* Program mec1 ucode address into intruction cache address register */
2289         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2290                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2291         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2292                         lower_32_bits(addr) & 0xFFFFF000);
2293         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2294                         upper_32_bits(addr));
2295
2296         return 0;
2297 }
2298
2299 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2300 {
2301         uint32_t cp_status;
2302         uint32_t bootload_status;
2303         int i, r;
2304
2305         for (i = 0; i < adev->usec_timeout; i++) {
2306                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2307                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2308                 if ((cp_status == 0) &&
2309                     (REG_GET_FIELD(bootload_status,
2310                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2311                         break;
2312                 }
2313                 udelay(1);
2314         }
2315
2316         if (i >= adev->usec_timeout) {
2317                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2318                 return -ETIMEDOUT;
2319         }
2320
2321         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2322                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2323                 if (r)
2324                         return r;
2325
2326                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2327                 if (r)
2328                         return r;
2329
2330                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2331                 if (r)
2332                         return r;
2333
2334                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2335                 if (r)
2336                         return r;
2337         }
2338
2339         return 0;
2340 }
2341
2342 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2343 {
2344         int i;
2345         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2346
2347         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2348         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2349         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2350         if (!enable) {
2351                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2352                         adev->gfx.gfx_ring[i].sched.ready = false;
2353         }
2354         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2355         udelay(50);
2356 }
2357
2358 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2359 {
2360         int r;
2361         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2362         const __le32 *fw_data;
2363         unsigned i, fw_size;
2364         uint32_t tmp;
2365         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2366
2367         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2368                 adev->gfx.pfp_fw->data;
2369
2370         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2371
2372         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2373                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2374         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2375
2376         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2377                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2378                                       &adev->gfx.pfp.pfp_fw_obj,
2379                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2380                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2381         if (r) {
2382                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2383                 gfx_v10_0_pfp_fini(adev);
2384                 return r;
2385         }
2386
2387         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2388
2389         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2390         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2391
2392         /* Trigger an invalidation of the L1 instruction caches */
2393         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2394         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2395         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2396
2397         /* Wait for invalidation complete */
2398         for (i = 0; i < usec_timeout; i++) {
2399                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2400                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2401                         INVALIDATE_CACHE_COMPLETE))
2402                         break;
2403                 udelay(1);
2404         }
2405
2406         if (i >= usec_timeout) {
2407                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2408                 return -EINVAL;
2409         }
2410
2411         if (amdgpu_emu_mode == 1)
2412                 adev->nbio_funcs->hdp_flush(adev, NULL);
2413
2414         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2415         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2416         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2417         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2418         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2419         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2420         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2421                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2422         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2423                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2424
2425         return 0;
2426 }
2427
2428 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2429 {
2430         int r;
2431         const struct gfx_firmware_header_v1_0 *ce_hdr;
2432         const __le32 *fw_data;
2433         unsigned i, fw_size;
2434         uint32_t tmp;
2435         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2436
2437         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2438                 adev->gfx.ce_fw->data;
2439
2440         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2441
2442         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2443                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2444         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2445
2446         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2447                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2448                                       &adev->gfx.ce.ce_fw_obj,
2449                                       &adev->gfx.ce.ce_fw_gpu_addr,
2450                                       (void **)&adev->gfx.ce.ce_fw_ptr);
2451         if (r) {
2452                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2453                 gfx_v10_0_ce_fini(adev);
2454                 return r;
2455         }
2456
2457         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2458
2459         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2460         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2461
2462         /* Trigger an invalidation of the L1 instruction caches */
2463         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2464         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2465         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2466
2467         /* Wait for invalidation complete */
2468         for (i = 0; i < usec_timeout; i++) {
2469                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2470                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2471                         INVALIDATE_CACHE_COMPLETE))
2472                         break;
2473                 udelay(1);
2474         }
2475
2476         if (i >= usec_timeout) {
2477                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2478                 return -EINVAL;
2479         }
2480
2481         if (amdgpu_emu_mode == 1)
2482                 adev->nbio_funcs->hdp_flush(adev, NULL);
2483
2484         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2485         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2486         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2487         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2488         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2489         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2490                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2491         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2492                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2493
2494         return 0;
2495 }
2496
2497 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2498 {
2499         int r;
2500         const struct gfx_firmware_header_v1_0 *me_hdr;
2501         const __le32 *fw_data;
2502         unsigned i, fw_size;
2503         uint32_t tmp;
2504         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2505
2506         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2507                 adev->gfx.me_fw->data;
2508
2509         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2510
2511         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2512                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2513         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2514
2515         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2516                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2517                                       &adev->gfx.me.me_fw_obj,
2518                                       &adev->gfx.me.me_fw_gpu_addr,
2519                                       (void **)&adev->gfx.me.me_fw_ptr);
2520         if (r) {
2521                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2522                 gfx_v10_0_me_fini(adev);
2523                 return r;
2524         }
2525
2526         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2527
2528         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2529         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2530
2531         /* Trigger an invalidation of the L1 instruction caches */
2532         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2533         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2534         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2535
2536         /* Wait for invalidation complete */
2537         for (i = 0; i < usec_timeout; i++) {
2538                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2539                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2540                         INVALIDATE_CACHE_COMPLETE))
2541                         break;
2542                 udelay(1);
2543         }
2544
2545         if (i >= usec_timeout) {
2546                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2547                 return -EINVAL;
2548         }
2549
2550         if (amdgpu_emu_mode == 1)
2551                 adev->nbio_funcs->hdp_flush(adev, NULL);
2552
2553         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2554         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2555         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2556         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2557         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2558         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2559                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2560         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2561                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2562
2563         return 0;
2564 }
2565
2566 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2567 {
2568         int r;
2569
2570         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2571                 return -EINVAL;
2572
2573         gfx_v10_0_cp_gfx_enable(adev, false);
2574
2575         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2576         if (r) {
2577                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2578                 return r;
2579         }
2580
2581         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2582         if (r) {
2583                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2584                 return r;
2585         }
2586
2587         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2588         if (r) {
2589                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2590                 return r;
2591         }
2592
2593         return 0;
2594 }
2595
2596 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2597 {
2598         struct amdgpu_ring *ring;
2599         const struct cs_section_def *sect = NULL;
2600         const struct cs_extent_def *ext = NULL;
2601         int r, i;
2602         int ctx_reg_offset;
2603
2604         /* init the CP */
2605         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2606                      adev->gfx.config.max_hw_contexts - 1);
2607         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2608
2609         gfx_v10_0_cp_gfx_enable(adev, true);
2610
2611         ring = &adev->gfx.gfx_ring[0];
2612         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2613         if (r) {
2614                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2615                 return r;
2616         }
2617
2618         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2619         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2620
2621         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2622         amdgpu_ring_write(ring, 0x80000000);
2623         amdgpu_ring_write(ring, 0x80000000);
2624
2625         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2626                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2627                         if (sect->id == SECT_CONTEXT) {
2628                                 amdgpu_ring_write(ring,
2629                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
2630                                                           ext->reg_count));
2631                                 amdgpu_ring_write(ring, ext->reg_index -
2632                                                   PACKET3_SET_CONTEXT_REG_START);
2633                                 for (i = 0; i < ext->reg_count; i++)
2634                                         amdgpu_ring_write(ring, ext->extent[i]);
2635                         }
2636                 }
2637         }
2638
2639         ctx_reg_offset =
2640                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2641         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2642         amdgpu_ring_write(ring, ctx_reg_offset);
2643         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2644
2645         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2646         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2647
2648         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2649         amdgpu_ring_write(ring, 0);
2650
2651         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2652         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2653         amdgpu_ring_write(ring, 0x8000);
2654         amdgpu_ring_write(ring, 0x8000);
2655
2656         amdgpu_ring_commit(ring);
2657
2658         /* submit cs packet to copy state 0 to next available state */
2659         ring = &adev->gfx.gfx_ring[1];
2660         r = amdgpu_ring_alloc(ring, 2);
2661         if (r) {
2662                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2663                 return r;
2664         }
2665
2666         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2667         amdgpu_ring_write(ring, 0);
2668
2669         amdgpu_ring_commit(ring);
2670
2671         return 0;
2672 }
2673
2674 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2675                                          CP_PIPE_ID pipe)
2676 {
2677         u32 tmp;
2678
2679         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2680         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2681
2682         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2683 }
2684
2685 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2686                                           struct amdgpu_ring *ring)
2687 {
2688         u32 tmp;
2689
2690         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2691         if (ring->use_doorbell) {
2692                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2693                                     DOORBELL_OFFSET, ring->doorbell_index);
2694                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2695                                     DOORBELL_EN, 1);
2696         } else {
2697                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2698                                     DOORBELL_EN, 0);
2699         }
2700         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2701         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2702                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
2703         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2704
2705         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2706                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2707 }
2708
2709 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2710 {
2711         struct amdgpu_ring *ring;
2712         u32 tmp;
2713         u32 rb_bufsz;
2714         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2715         u32 i;
2716
2717         /* Set the write pointer delay */
2718         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2719
2720         /* set the RB to use vmid 0 */
2721         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2722
2723         /* Init gfx ring 0 for pipe 0 */
2724         mutex_lock(&adev->srbm_mutex);
2725         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2726         mutex_unlock(&adev->srbm_mutex);
2727         /* Set ring buffer size */
2728         ring = &adev->gfx.gfx_ring[0];
2729         rb_bufsz = order_base_2(ring->ring_size / 8);
2730         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2731         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2732 #ifdef __BIG_ENDIAN
2733         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2734 #endif
2735         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2736
2737         /* Initialize the ring buffer's write pointers */
2738         ring->wptr = 0;
2739         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2740         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2741
2742         /* set the wb address wether it's enabled or not */
2743         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2744         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2745         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2746                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2747
2748         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2749         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2750                      lower_32_bits(wptr_gpu_addr));
2751         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2752                      upper_32_bits(wptr_gpu_addr));
2753
2754         mdelay(1);
2755         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2756
2757         rb_addr = ring->gpu_addr >> 8;
2758         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2759         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2760
2761         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2762
2763         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2764
2765         /* Init gfx ring 1 for pipe 1 */
2766         mutex_lock(&adev->srbm_mutex);
2767         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2768         mutex_unlock(&adev->srbm_mutex);
2769         ring = &adev->gfx.gfx_ring[1];
2770         rb_bufsz = order_base_2(ring->ring_size / 8);
2771         tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2772         tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2773         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2774         /* Initialize the ring buffer's write pointers */
2775         ring->wptr = 0;
2776         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2777         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2778         /* Set the wb address wether it's enabled or not */
2779         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2780         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2781         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2782                 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2783         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2784         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2785                 lower_32_bits(wptr_gpu_addr));
2786         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2787                 upper_32_bits(wptr_gpu_addr));
2788
2789         mdelay(1);
2790         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2791
2792         rb_addr = ring->gpu_addr >> 8;
2793         WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2794         WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2795         WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2796
2797         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2798
2799         /* Switch to pipe 0 */
2800         mutex_lock(&adev->srbm_mutex);
2801         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2802         mutex_unlock(&adev->srbm_mutex);
2803
2804         /* start the ring */
2805         gfx_v10_0_cp_gfx_start(adev);
2806
2807         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2808                 ring = &adev->gfx.gfx_ring[i];
2809                 ring->sched.ready = true;
2810         }
2811
2812         return 0;
2813 }
2814
2815 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2816 {
2817         int i;
2818
2819         if (enable) {
2820                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2821         } else {
2822                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2823                              (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2824                               CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2825                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2826                         adev->gfx.compute_ring[i].sched.ready = false;
2827                 adev->gfx.kiq.ring.sched.ready = false;
2828         }
2829         udelay(50);
2830 }
2831
2832 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2833 {
2834         const struct gfx_firmware_header_v1_0 *mec_hdr;
2835         const __le32 *fw_data;
2836         unsigned i;
2837         u32 tmp;
2838         u32 usec_timeout = 50000; /* Wait for 50 ms */
2839
2840         if (!adev->gfx.mec_fw)
2841                 return -EINVAL;
2842
2843         gfx_v10_0_cp_compute_enable(adev, false);
2844
2845         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2846         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2847
2848         fw_data = (const __le32 *)
2849                 (adev->gfx.mec_fw->data +
2850                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2851
2852         /* Trigger an invalidation of the L1 instruction caches */
2853         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2854         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2855         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2856
2857         /* Wait for invalidation complete */
2858         for (i = 0; i < usec_timeout; i++) {
2859                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2860                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2861                                        INVALIDATE_CACHE_COMPLETE))
2862                         break;
2863                 udelay(1);
2864         }
2865
2866         if (i >= usec_timeout) {
2867                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2868                 return -EINVAL;
2869         }
2870
2871         if (amdgpu_emu_mode == 1)
2872                 adev->nbio_funcs->hdp_flush(adev, NULL);
2873
2874         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2875         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2876         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2877         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2878         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2879
2880         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2881                      0xFFFFF000);
2882         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2883                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2884
2885         /* MEC1 */
2886         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2887
2888         for (i = 0; i < mec_hdr->jt_size; i++)
2889                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2890                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2891
2892         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2893
2894         /*
2895          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
2896          * different microcode than MEC1.
2897          */
2898
2899         return 0;
2900 }
2901
2902 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2903 {
2904         uint32_t tmp;
2905         struct amdgpu_device *adev = ring->adev;
2906
2907         /* tell RLC which is KIQ queue */
2908         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2909         tmp &= 0xffffff00;
2910         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2911         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2912         tmp |= 0x80;
2913         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2914 }
2915
2916 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2917 {
2918         struct amdgpu_device *adev = ring->adev;
2919         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2920         uint64_t hqd_gpu_addr, wb_gpu_addr;
2921         uint32_t tmp;
2922         uint32_t rb_bufsz;
2923
2924         /* set up gfx hqd wptr */
2925         mqd->cp_gfx_hqd_wptr = 0;
2926         mqd->cp_gfx_hqd_wptr_hi = 0;
2927
2928         /* set the pointer to the MQD */
2929         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2930         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2931
2932         /* set up mqd control */
2933         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2934         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2935         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2936         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2937         mqd->cp_gfx_mqd_control = tmp;
2938
2939         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2940         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
2941         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2942         mqd->cp_gfx_hqd_vmid = 0;
2943
2944         /* set up default queue priority level
2945          * 0x0 = low priority, 0x1 = high priority */
2946         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
2947         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2948         mqd->cp_gfx_hqd_queue_priority = tmp;
2949
2950         /* set up time quantum */
2951         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
2952         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
2953         mqd->cp_gfx_hqd_quantum = tmp;
2954
2955         /* set up gfx hqd base. this is similar as CP_RB_BASE */
2956         hqd_gpu_addr = ring->gpu_addr >> 8;
2957         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
2958         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
2959
2960         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
2961         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2962         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
2963         mqd->cp_gfx_hqd_rptr_addr_hi =
2964                 upper_32_bits(wb_gpu_addr) & 0xffff;
2965
2966         /* set up rb_wptr_poll addr */
2967         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2968         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2969         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2970
2971         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
2972         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
2973         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
2974         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
2975         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
2976 #ifdef __BIG_ENDIAN
2977         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
2978 #endif
2979         mqd->cp_gfx_hqd_cntl = tmp;
2980
2981         /* set up cp_doorbell_control */
2982         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2983         if (ring->use_doorbell) {
2984                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2985                                     DOORBELL_OFFSET, ring->doorbell_index);
2986                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2987                                     DOORBELL_EN, 1);
2988         } else
2989                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2990                                     DOORBELL_EN, 0);
2991         mqd->cp_rb_doorbell_control = tmp;
2992
2993         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2994         ring->wptr = 0;
2995         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
2996
2997         /* active the queue */
2998         mqd->cp_gfx_hqd_active = 1;
2999
3000         return 0;
3001 }
3002
3003 #ifdef BRING_UP_DEBUG
3004 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3005 {
3006         struct amdgpu_device *adev = ring->adev;
3007         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3008
3009         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3010         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3011         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3012
3013         /* set GFX_MQD_BASE */
3014         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3015         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);