2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <drm/drm_vblank.h>
27 #include "amdgpu_pm.h"
28 #include "amdgpu_i2c.h"
30 #include "amdgpu_pll.h"
31 #include "amdgpu_connectors.h"
32 #ifdef CONFIG_DRM_AMDGPU_SI
35 #ifdef CONFIG_DRM_AMDGPU_CIK
38 #include "dce_v10_0.h"
39 #include "dce_v11_0.h"
40 #include "dce_virtual.h"
41 #include "ivsrcid/ivsrcid_vislands30.h"
43 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
46 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
47 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
48 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
50 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
52 enum amdgpu_interrupt_state state);
54 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
59 static void dce_virtual_page_flip(struct amdgpu_device *adev,
60 int crtc_id, u64 crtc_base, bool async)
65 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
66 u32 *vbl, u32 *position)
74 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
75 enum amdgpu_hpd_id hpd)
80 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
81 enum amdgpu_hpd_id hpd)
86 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
92 * dce_virtual_bandwidth_update - program display watermarks
94 * @adev: amdgpu_device pointer
96 * Calculate and program the display watermarks and line
97 * buffer allocation (CIK).
99 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
104 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
105 u16 *green, u16 *blue, uint32_t size,
106 struct drm_modeset_acquire_ctx *ctx)
111 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
113 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
115 drm_crtc_cleanup(crtc);
119 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
122 .gamma_set = dce_virtual_crtc_gamma_set,
123 .set_config = amdgpu_display_crtc_set_config,
124 .destroy = dce_virtual_crtc_destroy,
125 .page_flip_target = amdgpu_display_crtc_page_flip_target,
128 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
130 struct drm_device *dev = crtc->dev;
131 struct amdgpu_device *adev = dev->dev_private;
132 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
135 if (amdgpu_sriov_vf(adev))
139 case DRM_MODE_DPMS_ON:
140 amdgpu_crtc->enabled = true;
141 /* Make sure VBLANK interrupts are still enabled */
142 type = amdgpu_display_crtc_idx_to_irq_type(adev,
143 amdgpu_crtc->crtc_id);
144 amdgpu_irq_update(adev, &adev->crtc_irq, type);
145 drm_crtc_vblank_on(crtc);
147 case DRM_MODE_DPMS_STANDBY:
148 case DRM_MODE_DPMS_SUSPEND:
149 case DRM_MODE_DPMS_OFF:
150 drm_crtc_vblank_off(crtc);
151 amdgpu_crtc->enabled = false;
157 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
159 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
162 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
164 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
167 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
169 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
171 dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
173 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
174 amdgpu_crtc->encoder = NULL;
175 amdgpu_crtc->connector = NULL;
178 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
179 struct drm_display_mode *mode,
180 struct drm_display_mode *adjusted_mode,
181 int x, int y, struct drm_framebuffer *old_fb)
183 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
185 /* update the hw version fpr dpm */
186 amdgpu_crtc->hw_mode = *adjusted_mode;
191 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
192 const struct drm_display_mode *mode,
193 struct drm_display_mode *adjusted_mode)
199 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
200 struct drm_framebuffer *old_fb)
205 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
206 struct drm_framebuffer *fb,
207 int x, int y, enum mode_set_atomic state)
212 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
213 .dpms = dce_virtual_crtc_dpms,
214 .mode_fixup = dce_virtual_crtc_mode_fixup,
215 .mode_set = dce_virtual_crtc_mode_set,
216 .mode_set_base = dce_virtual_crtc_set_base,
217 .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
218 .prepare = dce_virtual_crtc_prepare,
219 .commit = dce_virtual_crtc_commit,
220 .disable = dce_virtual_crtc_disable,
223 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
225 struct amdgpu_crtc *amdgpu_crtc;
227 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
228 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
229 if (amdgpu_crtc == NULL)
232 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
234 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
235 amdgpu_crtc->crtc_id = index;
236 adev->mode_info.crtcs[index] = amdgpu_crtc;
238 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
239 amdgpu_crtc->encoder = NULL;
240 amdgpu_crtc->connector = NULL;
241 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
242 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
247 static int dce_virtual_early_init(void *handle)
249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
251 dce_virtual_set_display_funcs(adev);
252 dce_virtual_set_irq_funcs(adev);
254 adev->mode_info.num_hpd = 1;
255 adev->mode_info.num_dig = 1;
259 static struct drm_encoder *
260 dce_virtual_encoder(struct drm_connector *connector)
262 struct drm_encoder *encoder;
265 drm_connector_for_each_possible_encoder(connector, encoder, i) {
266 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
270 /* pick the first one */
271 drm_connector_for_each_possible_encoder(connector, encoder, i)
277 static int dce_virtual_get_modes(struct drm_connector *connector)
279 struct drm_device *dev = connector->dev;
280 struct drm_display_mode *mode = NULL;
282 static const struct mode_size {
285 } common_modes[17] = {
305 for (i = 0; i < 17; i++) {
306 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
307 drm_mode_probed_add(connector, mode);
313 static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
314 struct drm_display_mode *mode)
320 dce_virtual_dpms(struct drm_connector *connector, int mode)
326 dce_virtual_set_property(struct drm_connector *connector,
327 struct drm_property *property,
333 static void dce_virtual_destroy(struct drm_connector *connector)
335 drm_connector_unregister(connector);
336 drm_connector_cleanup(connector);
340 static void dce_virtual_force(struct drm_connector *connector)
345 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
346 .get_modes = dce_virtual_get_modes,
347 .mode_valid = dce_virtual_mode_valid,
348 .best_encoder = dce_virtual_encoder,
351 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
352 .dpms = dce_virtual_dpms,
353 .fill_modes = drm_helper_probe_single_connector_modes,
354 .set_property = dce_virtual_set_property,
355 .destroy = dce_virtual_destroy,
356 .force = dce_virtual_force,
359 static int dce_virtual_sw_init(void *handle)
362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
364 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
368 adev->ddev->max_vblank_count = 0;
370 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
372 adev->ddev->mode_config.max_width = 16384;
373 adev->ddev->mode_config.max_height = 16384;
375 adev->ddev->mode_config.preferred_depth = 24;
376 adev->ddev->mode_config.prefer_shadow = 1;
378 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
380 r = amdgpu_display_modeset_create_props(adev);
384 adev->ddev->mode_config.max_width = 16384;
385 adev->ddev->mode_config.max_height = 16384;
387 /* allocate crtcs, encoders, connectors */
388 for (i = 0; i < adev->mode_info.num_crtc; i++) {
389 r = dce_virtual_crtc_init(adev, i);
392 r = dce_virtual_connector_encoder_init(adev, i);
397 drm_kms_helper_poll_init(adev->ddev);
399 adev->mode_info.mode_config_initialized = true;
403 static int dce_virtual_sw_fini(void *handle)
405 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
407 kfree(adev->mode_info.bios_hardcoded_edid);
409 drm_kms_helper_poll_fini(adev->ddev);
411 drm_mode_config_cleanup(adev->ddev);
412 /* clear crtcs pointer to avoid dce irq finish routine access freed data */
413 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
414 adev->mode_info.mode_config_initialized = false;
418 static int dce_virtual_hw_init(void *handle)
420 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
422 switch (adev->asic_type) {
423 #ifdef CONFIG_DRM_AMDGPU_SI
428 dce_v6_0_disable_dce(adev);
431 #ifdef CONFIG_DRM_AMDGPU_CIK
437 dce_v8_0_disable_dce(adev);
442 dce_v10_0_disable_dce(adev);
449 dce_v11_0_disable_dce(adev);
452 #ifdef CONFIG_DRM_AMDGPU_SI
462 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
467 static int dce_virtual_hw_fini(void *handle)
469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
472 for (i = 0; i<adev->mode_info.num_crtc; i++)
473 if (adev->mode_info.crtcs[i])
474 dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
479 static int dce_virtual_suspend(void *handle)
481 return dce_virtual_hw_fini(handle);
484 static int dce_virtual_resume(void *handle)
486 return dce_virtual_hw_init(handle);
489 static bool dce_virtual_is_idle(void *handle)
494 static int dce_virtual_wait_for_idle(void *handle)
499 static int dce_virtual_soft_reset(void *handle)
504 static int dce_virtual_set_clockgating_state(void *handle,
505 enum amd_clockgating_state state)
510 static int dce_virtual_set_powergating_state(void *handle,
511 enum amd_powergating_state state)
516 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
517 .name = "dce_virtual",
518 .early_init = dce_virtual_early_init,
520 .sw_init = dce_virtual_sw_init,
521 .sw_fini = dce_virtual_sw_fini,
522 .hw_init = dce_virtual_hw_init,
523 .hw_fini = dce_virtual_hw_fini,
524 .suspend = dce_virtual_suspend,
525 .resume = dce_virtual_resume,
526 .is_idle = dce_virtual_is_idle,
527 .wait_for_idle = dce_virtual_wait_for_idle,
528 .soft_reset = dce_virtual_soft_reset,
529 .set_clockgating_state = dce_virtual_set_clockgating_state,
530 .set_powergating_state = dce_virtual_set_powergating_state,
533 /* these are handled by the primary encoders */
534 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
539 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
545 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
546 struct drm_display_mode *mode,
547 struct drm_display_mode *adjusted_mode)
552 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
558 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
563 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
564 const struct drm_display_mode *mode,
565 struct drm_display_mode *adjusted_mode)
570 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
571 .dpms = dce_virtual_encoder_dpms,
572 .mode_fixup = dce_virtual_encoder_mode_fixup,
573 .prepare = dce_virtual_encoder_prepare,
574 .mode_set = dce_virtual_encoder_mode_set,
575 .commit = dce_virtual_encoder_commit,
576 .disable = dce_virtual_encoder_disable,
579 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
581 drm_encoder_cleanup(encoder);
585 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
586 .destroy = dce_virtual_encoder_destroy,
589 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
592 struct drm_encoder *encoder;
593 struct drm_connector *connector;
595 /* add a new encoder */
596 encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
599 encoder->possible_crtcs = 1 << index;
600 drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
601 DRM_MODE_ENCODER_VIRTUAL, NULL);
602 drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
604 connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
610 /* add a new connector */
611 drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
612 DRM_MODE_CONNECTOR_VIRTUAL);
613 drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
614 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
615 connector->interlace_allowed = false;
616 connector->doublescan_allowed = false;
617 drm_connector_register(connector);
620 drm_connector_attach_encoder(connector, encoder);
625 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
626 .bandwidth_update = &dce_virtual_bandwidth_update,
627 .vblank_get_counter = &dce_virtual_vblank_get_counter,
628 .backlight_set_level = NULL,
629 .backlight_get_level = NULL,
630 .hpd_sense = &dce_virtual_hpd_sense,
631 .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
632 .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
633 .page_flip = &dce_virtual_page_flip,
634 .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
636 .add_connector = NULL,
639 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
641 adev->mode_info.funcs = &dce_virtual_display_funcs;
644 static int dce_virtual_pageflip(struct amdgpu_device *adev,
648 struct amdgpu_crtc *amdgpu_crtc;
649 struct amdgpu_flip_work *works;
651 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
653 if (crtc_id >= adev->mode_info.num_crtc) {
654 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
658 /* IRQ could occur when in initial stage */
659 if (amdgpu_crtc == NULL)
662 spin_lock_irqsave(&adev->ddev->event_lock, flags);
663 works = amdgpu_crtc->pflip_works;
664 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
665 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
666 "AMDGPU_FLIP_SUBMITTED(%d)\n",
667 amdgpu_crtc->pflip_status,
668 AMDGPU_FLIP_SUBMITTED);
669 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
673 /* page flip completed. clean up */
674 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
675 amdgpu_crtc->pflip_works = NULL;
677 /* wakeup usersapce */
679 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
681 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
683 drm_crtc_vblank_put(&amdgpu_crtc->base);
684 amdgpu_bo_unref(&works->old_abo);
685 kfree(works->shared);
691 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
693 struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
694 struct amdgpu_crtc, vblank_timer);
695 struct drm_device *ddev = amdgpu_crtc->base.dev;
696 struct amdgpu_device *adev = ddev->dev_private;
698 drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
699 dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
700 hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
703 return HRTIMER_NORESTART;
706 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
708 enum amdgpu_interrupt_state state)
710 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
711 DRM_DEBUG("invalid crtc %d\n", crtc);
715 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
716 DRM_DEBUG("Enable software vsync timer\n");
717 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
718 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
719 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
720 DCE_VIRTUAL_VBLANK_PERIOD);
721 adev->mode_info.crtcs[crtc]->vblank_timer.function =
722 dce_virtual_vblank_timer_handle;
723 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
724 DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
725 } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
726 DRM_DEBUG("Disable software vsync timer\n");
727 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
730 adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
731 DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
735 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
736 struct amdgpu_irq_src *source,
738 enum amdgpu_interrupt_state state)
740 if (type > AMDGPU_CRTC_IRQ_VBLANK6)
743 dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
748 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
749 .set = dce_virtual_set_crtc_irq_state,
753 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
755 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
756 adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
759 const struct amdgpu_ip_block_version dce_virtual_ip_block =
761 .type = AMD_IP_BLOCK_TYPE_DCE,
765 .funcs = &dce_virtual_ip_funcs,