Merge remote-tracking branch 'airlied/drm-next' into drm-misc-next
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / dce_v10_0.c
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <drm/drmP.h>
24 #include "amdgpu.h"
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
27 #include "vid.h"
28 #include "atom.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
34 #include "dce_v10_0.h"
35
36 #include "dce/dce_10_0_d.h"
37 #include "dce/dce_10_0_sh_mask.h"
38 #include "dce/dce_10_0_enum.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
41 #include "gmc/gmc_8_1_d.h"
42 #include "gmc/gmc_8_1_sh_mask.h"
43
44 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
45 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
46
47 static const u32 crtc_offsets[] =
48 {
49         CRTC0_REGISTER_OFFSET,
50         CRTC1_REGISTER_OFFSET,
51         CRTC2_REGISTER_OFFSET,
52         CRTC3_REGISTER_OFFSET,
53         CRTC4_REGISTER_OFFSET,
54         CRTC5_REGISTER_OFFSET,
55         CRTC6_REGISTER_OFFSET
56 };
57
58 static const u32 hpd_offsets[] =
59 {
60         HPD0_REGISTER_OFFSET,
61         HPD1_REGISTER_OFFSET,
62         HPD2_REGISTER_OFFSET,
63         HPD3_REGISTER_OFFSET,
64         HPD4_REGISTER_OFFSET,
65         HPD5_REGISTER_OFFSET
66 };
67
68 static const uint32_t dig_offsets[] = {
69         DIG0_REGISTER_OFFSET,
70         DIG1_REGISTER_OFFSET,
71         DIG2_REGISTER_OFFSET,
72         DIG3_REGISTER_OFFSET,
73         DIG4_REGISTER_OFFSET,
74         DIG5_REGISTER_OFFSET,
75         DIG6_REGISTER_OFFSET
76 };
77
78 static const struct {
79         uint32_t        reg;
80         uint32_t        vblank;
81         uint32_t        vline;
82         uint32_t        hpd;
83
84 } interrupt_status_offsets[] = { {
85         .reg = mmDISP_INTERRUPT_STATUS,
86         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
87         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
88         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
89 }, {
90         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
91         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
92         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
93         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
94 }, {
95         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
96         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
97         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
98         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99 }, {
100         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
101         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
102         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
103         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
104 }, {
105         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
106         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
107         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
108         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
109 }, {
110         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
111         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
112         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
113         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
114 } };
115
116 static const u32 golden_settings_tonga_a11[] =
117 {
118         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
119         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
120         mmFBC_MISC, 0x1f311fff, 0x12300000,
121         mmHDMI_CONTROL, 0x31000111, 0x00000011,
122 };
123
124 static const u32 tonga_mgcg_cgcg_init[] =
125 {
126         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128 };
129
130 static const u32 golden_settings_fiji_a10[] =
131 {
132         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
133         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
134         mmFBC_MISC, 0x1f311fff, 0x12300000,
135         mmHDMI_CONTROL, 0x31000111, 0x00000011,
136 };
137
138 static const u32 fiji_mgcg_cgcg_init[] =
139 {
140         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
141         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
142 };
143
144 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
145 {
146         switch (adev->asic_type) {
147         case CHIP_FIJI:
148                 amdgpu_program_register_sequence(adev,
149                                                  fiji_mgcg_cgcg_init,
150                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
151                 amdgpu_program_register_sequence(adev,
152                                                  golden_settings_fiji_a10,
153                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
154                 break;
155         case CHIP_TONGA:
156                 amdgpu_program_register_sequence(adev,
157                                                  tonga_mgcg_cgcg_init,
158                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
159                 amdgpu_program_register_sequence(adev,
160                                                  golden_settings_tonga_a11,
161                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
162                 break;
163         default:
164                 break;
165         }
166 }
167
168 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
169                                      u32 block_offset, u32 reg)
170 {
171         unsigned long flags;
172         u32 r;
173
174         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
175         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
176         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
177         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
178
179         return r;
180 }
181
182 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
183                                       u32 block_offset, u32 reg, u32 v)
184 {
185         unsigned long flags;
186
187         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
188         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
189         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
190         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
191 }
192
193 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
194 {
195         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
196                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
197                 return true;
198         else
199                 return false;
200 }
201
202 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
203 {
204         u32 pos1, pos2;
205
206         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
207         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
208
209         if (pos1 != pos2)
210                 return true;
211         else
212                 return false;
213 }
214
215 /**
216  * dce_v10_0_vblank_wait - vblank wait asic callback.
217  *
218  * @adev: amdgpu_device pointer
219  * @crtc: crtc to wait for vblank on
220  *
221  * Wait for vblank on the requested crtc (evergreen+).
222  */
223 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
224 {
225         unsigned i = 100;
226
227         if (crtc >= adev->mode_info.num_crtc)
228                 return;
229
230         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
231                 return;
232
233         /* depending on when we hit vblank, we may be close to active; if so,
234          * wait for another frame.
235          */
236         while (dce_v10_0_is_in_vblank(adev, crtc)) {
237                 if (i++ == 100) {
238                         i = 0;
239                         if (!dce_v10_0_is_counter_moving(adev, crtc))
240                                 break;
241                 }
242         }
243
244         while (!dce_v10_0_is_in_vblank(adev, crtc)) {
245                 if (i++ == 100) {
246                         i = 0;
247                         if (!dce_v10_0_is_counter_moving(adev, crtc))
248                                 break;
249                 }
250         }
251 }
252
253 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
254 {
255         if (crtc >= adev->mode_info.num_crtc)
256                 return 0;
257         else
258                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
259 }
260
261 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
262 {
263         unsigned i;
264
265         /* Enable pflip interrupts */
266         for (i = 0; i < adev->mode_info.num_crtc; i++)
267                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
268 }
269
270 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
271 {
272         unsigned i;
273
274         /* Disable pflip interrupts */
275         for (i = 0; i < adev->mode_info.num_crtc; i++)
276                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
277 }
278
279 /**
280  * dce_v10_0_page_flip - pageflip callback.
281  *
282  * @adev: amdgpu_device pointer
283  * @crtc_id: crtc to cleanup pageflip on
284  * @crtc_base: new address of the crtc (GPU MC address)
285  *
286  * Triggers the actual pageflip by updating the primary
287  * surface base address.
288  */
289 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
290                                 int crtc_id, u64 crtc_base, bool async)
291 {
292         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
293         u32 tmp;
294
295         /* flip at hsync for async, default is vsync */
296         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
297         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
298                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
299         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
300         /* update the primary scanout address */
301         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
302                upper_32_bits(crtc_base));
303         /* writing to the low address triggers the update */
304         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
305                lower_32_bits(crtc_base));
306         /* post the write */
307         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
308 }
309
310 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
311                                         u32 *vbl, u32 *position)
312 {
313         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
314                 return -EINVAL;
315
316         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
317         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
318
319         return 0;
320 }
321
322 /**
323  * dce_v10_0_hpd_sense - hpd sense callback.
324  *
325  * @adev: amdgpu_device pointer
326  * @hpd: hpd (hotplug detect) pin
327  *
328  * Checks if a digital monitor is connected (evergreen+).
329  * Returns true if connected, false if not connected.
330  */
331 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
332                                enum amdgpu_hpd_id hpd)
333 {
334         bool connected = false;
335
336         if (hpd >= adev->mode_info.num_hpd)
337                 return connected;
338
339         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
340             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
341                 connected = true;
342
343         return connected;
344 }
345
346 /**
347  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
348  *
349  * @adev: amdgpu_device pointer
350  * @hpd: hpd (hotplug detect) pin
351  *
352  * Set the polarity of the hpd pin (evergreen+).
353  */
354 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
355                                       enum amdgpu_hpd_id hpd)
356 {
357         u32 tmp;
358         bool connected = dce_v10_0_hpd_sense(adev, hpd);
359
360         if (hpd >= adev->mode_info.num_hpd)
361                 return;
362
363         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
364         if (connected)
365                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
366         else
367                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
368         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
369 }
370
371 /**
372  * dce_v10_0_hpd_init - hpd setup callback.
373  *
374  * @adev: amdgpu_device pointer
375  *
376  * Setup the hpd pins used by the card (evergreen+).
377  * Enable the pin, set the polarity, and enable the hpd interrupts.
378  */
379 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
380 {
381         struct drm_device *dev = adev->ddev;
382         struct drm_connector *connector;
383         u32 tmp;
384
385         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
386                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
387
388                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
389                         continue;
390
391                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
392                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
393                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
394                          * aux dp channel on imac and help (but not completely fix)
395                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
396                          * also avoid interrupt storms during dpms.
397                          */
398                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
400                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401                         continue;
402                 }
403
404                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
405                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
406                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
407
408                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
409                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
410                                     DC_HPD_CONNECT_INT_DELAY,
411                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
412                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
413                                     DC_HPD_DISCONNECT_INT_DELAY,
414                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
415                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
416
417                 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
418                 amdgpu_irq_get(adev, &adev->hpd_irq,
419                                amdgpu_connector->hpd.hpd);
420         }
421 }
422
423 /**
424  * dce_v10_0_hpd_fini - hpd tear down callback.
425  *
426  * @adev: amdgpu_device pointer
427  *
428  * Tear down the hpd pins used by the card (evergreen+).
429  * Disable the hpd interrupts.
430  */
431 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
432 {
433         struct drm_device *dev = adev->ddev;
434         struct drm_connector *connector;
435         u32 tmp;
436
437         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
438                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
439
440                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
441                         continue;
442
443                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
444                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
445                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
446
447                 amdgpu_irq_put(adev, &adev->hpd_irq,
448                                amdgpu_connector->hpd.hpd);
449         }
450 }
451
452 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
453 {
454         return mmDC_GPIO_HPD_A;
455 }
456
457 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
458 {
459         u32 crtc_hung = 0;
460         u32 crtc_status[6];
461         u32 i, j, tmp;
462
463         for (i = 0; i < adev->mode_info.num_crtc; i++) {
464                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
465                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
466                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
467                         crtc_hung |= (1 << i);
468                 }
469         }
470
471         for (j = 0; j < 10; j++) {
472                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
473                         if (crtc_hung & (1 << i)) {
474                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
475                                 if (tmp != crtc_status[i])
476                                         crtc_hung &= ~(1 << i);
477                         }
478                 }
479                 if (crtc_hung == 0)
480                         return false;
481                 udelay(100);
482         }
483
484         return true;
485 }
486
487 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
488                                      struct amdgpu_mode_mc_save *save)
489 {
490         u32 crtc_enabled, tmp;
491         int i;
492
493         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
494         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
495
496         /* disable VGA render */
497         tmp = RREG32(mmVGA_RENDER_CONTROL);
498         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
499         WREG32(mmVGA_RENDER_CONTROL, tmp);
500
501         /* blank the display controllers */
502         for (i = 0; i < adev->mode_info.num_crtc; i++) {
503                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
504                                              CRTC_CONTROL, CRTC_MASTER_EN);
505                 if (crtc_enabled) {
506 #if 0
507                         u32 frame_count;
508                         int j;
509
510                         save->crtc_enabled[i] = true;
511                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
512                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
513                                 amdgpu_display_vblank_wait(adev, i);
514                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
515                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
516                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
517                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
518                         }
519                         /* wait for the next frame */
520                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
521                         for (j = 0; j < adev->usec_timeout; j++) {
522                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
523                                         break;
524                                 udelay(1);
525                         }
526                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
527                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
528                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
529                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
530                         }
531                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
532                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
533                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
534                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
535                         }
536 #else
537                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
538                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
539                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
540                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
541                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
542                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
543                         save->crtc_enabled[i] = false;
544                         /* ***** */
545 #endif
546                 } else {
547                         save->crtc_enabled[i] = false;
548                 }
549         }
550 }
551
552 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
553                                        struct amdgpu_mode_mc_save *save)
554 {
555         u32 tmp, frame_count;
556         int i, j;
557
558         /* update crtc base addresses */
559         for (i = 0; i < adev->mode_info.num_crtc; i++) {
560                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
561                        upper_32_bits(adev->mc.vram_start));
562                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
563                        upper_32_bits(adev->mc.vram_start));
564                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
565                        (u32)adev->mc.vram_start);
566                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
567                        (u32)adev->mc.vram_start);
568
569                 if (save->crtc_enabled[i]) {
570                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
571                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
572                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
573                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
574                         }
575                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
576                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
577                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
578                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
579                         }
580                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
581                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
582                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
583                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
584                         }
585                         for (j = 0; j < adev->usec_timeout; j++) {
586                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
587                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
588                                         break;
589                                 udelay(1);
590                         }
591                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
592                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
593                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
594                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
595                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
596                         /* wait for the next frame */
597                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
598                         for (j = 0; j < adev->usec_timeout; j++) {
599                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
600                                         break;
601                                 udelay(1);
602                         }
603                 }
604         }
605
606         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
607         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
608
609         /* Unlock vga access */
610         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
611         mdelay(1);
612         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
613 }
614
615 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
616                                            bool render)
617 {
618         u32 tmp;
619
620         /* Lockout access through VGA aperture*/
621         tmp = RREG32(mmVGA_HDP_CONTROL);
622         if (render)
623                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
624         else
625                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
626         WREG32(mmVGA_HDP_CONTROL, tmp);
627
628         /* disable VGA render */
629         tmp = RREG32(mmVGA_RENDER_CONTROL);
630         if (render)
631                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
632         else
633                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
634         WREG32(mmVGA_RENDER_CONTROL, tmp);
635 }
636
637 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
638 {
639         int num_crtc = 0;
640
641         switch (adev->asic_type) {
642         case CHIP_FIJI:
643         case CHIP_TONGA:
644                 num_crtc = 6;
645                 break;
646         default:
647                 num_crtc = 0;
648         }
649         return num_crtc;
650 }
651
652 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
653 {
654         /*Disable VGA render and enabled crtc, if has DCE engine*/
655         if (amdgpu_atombios_has_dce_engine_info(adev)) {
656                 u32 tmp;
657                 int crtc_enabled, i;
658
659                 dce_v10_0_set_vga_render_state(adev, false);
660
661                 /*Disable crtc*/
662                 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
663                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
664                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
665                         if (crtc_enabled) {
666                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
667                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
668                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
669                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
670                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
671                         }
672                 }
673         }
674 }
675
676 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
677 {
678         struct drm_device *dev = encoder->dev;
679         struct amdgpu_device *adev = dev->dev_private;
680         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
681         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
682         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
683         int bpc = 0;
684         u32 tmp = 0;
685         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
686
687         if (connector) {
688                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
689                 bpc = amdgpu_connector_get_monitor_bpc(connector);
690                 dither = amdgpu_connector->dither;
691         }
692
693         /* LVDS/eDP FMT is set up by atom */
694         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
695                 return;
696
697         /* not needed for analog */
698         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
699             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
700                 return;
701
702         if (bpc == 0)
703                 return;
704
705         switch (bpc) {
706         case 6:
707                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
708                         /* XXX sort out optimal dither settings */
709                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
710                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
711                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
712                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
713                 } else {
714                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
715                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
716                 }
717                 break;
718         case 8:
719                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
720                         /* XXX sort out optimal dither settings */
721                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
722                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
723                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
724                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
725                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
726                 } else {
727                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
728                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
729                 }
730                 break;
731         case 10:
732                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
733                         /* XXX sort out optimal dither settings */
734                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
735                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
737                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
739                 } else {
740                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
741                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
742                 }
743                 break;
744         default:
745                 /* not needed */
746                 break;
747         }
748
749         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
750 }
751
752
753 /* display watermark setup */
754 /**
755  * dce_v10_0_line_buffer_adjust - Set up the line buffer
756  *
757  * @adev: amdgpu_device pointer
758  * @amdgpu_crtc: the selected display controller
759  * @mode: the current display mode on the selected display
760  * controller
761  *
762  * Setup up the line buffer allocation for
763  * the selected display controller (CIK).
764  * Returns the line buffer size in pixels.
765  */
766 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
767                                        struct amdgpu_crtc *amdgpu_crtc,
768                                        struct drm_display_mode *mode)
769 {
770         u32 tmp, buffer_alloc, i, mem_cfg;
771         u32 pipe_offset = amdgpu_crtc->crtc_id;
772         /*
773          * Line Buffer Setup
774          * There are 6 line buffers, one for each display controllers.
775          * There are 3 partitions per LB. Select the number of partitions
776          * to enable based on the display width.  For display widths larger
777          * than 4096, you need use to use 2 display controllers and combine
778          * them using the stereo blender.
779          */
780         if (amdgpu_crtc->base.enabled && mode) {
781                 if (mode->crtc_hdisplay < 1920) {
782                         mem_cfg = 1;
783                         buffer_alloc = 2;
784                 } else if (mode->crtc_hdisplay < 2560) {
785                         mem_cfg = 2;
786                         buffer_alloc = 2;
787                 } else if (mode->crtc_hdisplay < 4096) {
788                         mem_cfg = 0;
789                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
790                 } else {
791                         DRM_DEBUG_KMS("Mode too big for LB!\n");
792                         mem_cfg = 0;
793                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
794                 }
795         } else {
796                 mem_cfg = 1;
797                 buffer_alloc = 0;
798         }
799
800         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
801         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
802         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
803
804         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
805         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
806         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
807
808         for (i = 0; i < adev->usec_timeout; i++) {
809                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
810                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
811                         break;
812                 udelay(1);
813         }
814
815         if (amdgpu_crtc->base.enabled && mode) {
816                 switch (mem_cfg) {
817                 case 0:
818                 default:
819                         return 4096 * 2;
820                 case 1:
821                         return 1920 * 2;
822                 case 2:
823                         return 2560 * 2;
824                 }
825         }
826
827         /* controller not enabled, so no lb used */
828         return 0;
829 }
830
831 /**
832  * cik_get_number_of_dram_channels - get the number of dram channels
833  *
834  * @adev: amdgpu_device pointer
835  *
836  * Look up the number of video ram channels (CIK).
837  * Used for display watermark bandwidth calculations
838  * Returns the number of dram channels
839  */
840 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
841 {
842         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
843
844         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
845         case 0:
846         default:
847                 return 1;
848         case 1:
849                 return 2;
850         case 2:
851                 return 4;
852         case 3:
853                 return 8;
854         case 4:
855                 return 3;
856         case 5:
857                 return 6;
858         case 6:
859                 return 10;
860         case 7:
861                 return 12;
862         case 8:
863                 return 16;
864         }
865 }
866
867 struct dce10_wm_params {
868         u32 dram_channels; /* number of dram channels */
869         u32 yclk;          /* bandwidth per dram data pin in kHz */
870         u32 sclk;          /* engine clock in kHz */
871         u32 disp_clk;      /* display clock in kHz */
872         u32 src_width;     /* viewport width */
873         u32 active_time;   /* active display time in ns */
874         u32 blank_time;    /* blank time in ns */
875         bool interlaced;    /* mode is interlaced */
876         fixed20_12 vsc;    /* vertical scale ratio */
877         u32 num_heads;     /* number of active crtcs */
878         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
879         u32 lb_size;       /* line buffer allocated to pipe */
880         u32 vtaps;         /* vertical scaler taps */
881 };
882
883 /**
884  * dce_v10_0_dram_bandwidth - get the dram bandwidth
885  *
886  * @wm: watermark calculation data
887  *
888  * Calculate the raw dram bandwidth (CIK).
889  * Used for display watermark bandwidth calculations
890  * Returns the dram bandwidth in MBytes/s
891  */
892 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
893 {
894         /* Calculate raw DRAM Bandwidth */
895         fixed20_12 dram_efficiency; /* 0.7 */
896         fixed20_12 yclk, dram_channels, bandwidth;
897         fixed20_12 a;
898
899         a.full = dfixed_const(1000);
900         yclk.full = dfixed_const(wm->yclk);
901         yclk.full = dfixed_div(yclk, a);
902         dram_channels.full = dfixed_const(wm->dram_channels * 4);
903         a.full = dfixed_const(10);
904         dram_efficiency.full = dfixed_const(7);
905         dram_efficiency.full = dfixed_div(dram_efficiency, a);
906         bandwidth.full = dfixed_mul(dram_channels, yclk);
907         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
908
909         return dfixed_trunc(bandwidth);
910 }
911
912 /**
913  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
914  *
915  * @wm: watermark calculation data
916  *
917  * Calculate the dram bandwidth used for display (CIK).
918  * Used for display watermark bandwidth calculations
919  * Returns the dram bandwidth for display in MBytes/s
920  */
921 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
922 {
923         /* Calculate DRAM Bandwidth and the part allocated to display. */
924         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
925         fixed20_12 yclk, dram_channels, bandwidth;
926         fixed20_12 a;
927
928         a.full = dfixed_const(1000);
929         yclk.full = dfixed_const(wm->yclk);
930         yclk.full = dfixed_div(yclk, a);
931         dram_channels.full = dfixed_const(wm->dram_channels * 4);
932         a.full = dfixed_const(10);
933         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
934         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
935         bandwidth.full = dfixed_mul(dram_channels, yclk);
936         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
937
938         return dfixed_trunc(bandwidth);
939 }
940
941 /**
942  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
943  *
944  * @wm: watermark calculation data
945  *
946  * Calculate the data return bandwidth used for display (CIK).
947  * Used for display watermark bandwidth calculations
948  * Returns the data return bandwidth in MBytes/s
949  */
950 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
951 {
952         /* Calculate the display Data return Bandwidth */
953         fixed20_12 return_efficiency; /* 0.8 */
954         fixed20_12 sclk, bandwidth;
955         fixed20_12 a;
956
957         a.full = dfixed_const(1000);
958         sclk.full = dfixed_const(wm->sclk);
959         sclk.full = dfixed_div(sclk, a);
960         a.full = dfixed_const(10);
961         return_efficiency.full = dfixed_const(8);
962         return_efficiency.full = dfixed_div(return_efficiency, a);
963         a.full = dfixed_const(32);
964         bandwidth.full = dfixed_mul(a, sclk);
965         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
966
967         return dfixed_trunc(bandwidth);
968 }
969
970 /**
971  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
972  *
973  * @wm: watermark calculation data
974  *
975  * Calculate the dmif bandwidth used for display (CIK).
976  * Used for display watermark bandwidth calculations
977  * Returns the dmif bandwidth in MBytes/s
978  */
979 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
980 {
981         /* Calculate the DMIF Request Bandwidth */
982         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
983         fixed20_12 disp_clk, bandwidth;
984         fixed20_12 a, b;
985
986         a.full = dfixed_const(1000);
987         disp_clk.full = dfixed_const(wm->disp_clk);
988         disp_clk.full = dfixed_div(disp_clk, a);
989         a.full = dfixed_const(32);
990         b.full = dfixed_mul(a, disp_clk);
991
992         a.full = dfixed_const(10);
993         disp_clk_request_efficiency.full = dfixed_const(8);
994         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
995
996         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
997
998         return dfixed_trunc(bandwidth);
999 }
1000
1001 /**
1002  * dce_v10_0_available_bandwidth - get the min available bandwidth
1003  *
1004  * @wm: watermark calculation data
1005  *
1006  * Calculate the min available bandwidth used for display (CIK).
1007  * Used for display watermark bandwidth calculations
1008  * Returns the min available bandwidth in MBytes/s
1009  */
1010 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1011 {
1012         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1013         u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1014         u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1015         u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1016
1017         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1018 }
1019
1020 /**
1021  * dce_v10_0_average_bandwidth - get the average available bandwidth
1022  *
1023  * @wm: watermark calculation data
1024  *
1025  * Calculate the average available bandwidth used for display (CIK).
1026  * Used for display watermark bandwidth calculations
1027  * Returns the average available bandwidth in MBytes/s
1028  */
1029 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1030 {
1031         /* Calculate the display mode Average Bandwidth
1032          * DisplayMode should contain the source and destination dimensions,
1033          * timing, etc.
1034          */
1035         fixed20_12 bpp;
1036         fixed20_12 line_time;
1037         fixed20_12 src_width;
1038         fixed20_12 bandwidth;
1039         fixed20_12 a;
1040
1041         a.full = dfixed_const(1000);
1042         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1043         line_time.full = dfixed_div(line_time, a);
1044         bpp.full = dfixed_const(wm->bytes_per_pixel);
1045         src_width.full = dfixed_const(wm->src_width);
1046         bandwidth.full = dfixed_mul(src_width, bpp);
1047         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1048         bandwidth.full = dfixed_div(bandwidth, line_time);
1049
1050         return dfixed_trunc(bandwidth);
1051 }
1052
1053 /**
1054  * dce_v10_0_latency_watermark - get the latency watermark
1055  *
1056  * @wm: watermark calculation data
1057  *
1058  * Calculate the latency watermark (CIK).
1059  * Used for display watermark bandwidth calculations
1060  * Returns the latency watermark in ns
1061  */
1062 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1063 {
1064         /* First calculate the latency in ns */
1065         u32 mc_latency = 2000; /* 2000 ns. */
1066         u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1067         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1068         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1069         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1070         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1071                 (wm->num_heads * cursor_line_pair_return_time);
1072         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1073         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1074         u32 tmp, dmif_size = 12288;
1075         fixed20_12 a, b, c;
1076
1077         if (wm->num_heads == 0)
1078                 return 0;
1079
1080         a.full = dfixed_const(2);
1081         b.full = dfixed_const(1);
1082         if ((wm->vsc.full > a.full) ||
1083             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1084             (wm->vtaps >= 5) ||
1085             ((wm->vsc.full >= a.full) && wm->interlaced))
1086                 max_src_lines_per_dst_line = 4;
1087         else
1088                 max_src_lines_per_dst_line = 2;
1089
1090         a.full = dfixed_const(available_bandwidth);
1091         b.full = dfixed_const(wm->num_heads);
1092         a.full = dfixed_div(a, b);
1093         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
1094         tmp = min(dfixed_trunc(a), tmp);
1095
1096         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
1097
1098         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1099         b.full = dfixed_const(1000);
1100         c.full = dfixed_const(lb_fill_bw);
1101         b.full = dfixed_div(c, b);
1102         a.full = dfixed_div(a, b);
1103         line_fill_time = dfixed_trunc(a);
1104
1105         if (line_fill_time < wm->active_time)
1106                 return latency;
1107         else
1108                 return latency + (line_fill_time - wm->active_time);
1109
1110 }
1111
1112 /**
1113  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1114  * average and available dram bandwidth
1115  *
1116  * @wm: watermark calculation data
1117  *
1118  * Check if the display average bandwidth fits in the display
1119  * dram bandwidth (CIK).
1120  * Used for display watermark bandwidth calculations
1121  * Returns true if the display fits, false if not.
1122  */
1123 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1124 {
1125         if (dce_v10_0_average_bandwidth(wm) <=
1126             (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1127                 return true;
1128         else
1129                 return false;
1130 }
1131
1132 /**
1133  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1134  * average and available bandwidth
1135  *
1136  * @wm: watermark calculation data
1137  *
1138  * Check if the display average bandwidth fits in the display
1139  * available bandwidth (CIK).
1140  * Used for display watermark bandwidth calculations
1141  * Returns true if the display fits, false if not.
1142  */
1143 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1144 {
1145         if (dce_v10_0_average_bandwidth(wm) <=
1146             (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1147                 return true;
1148         else
1149                 return false;
1150 }
1151
1152 /**
1153  * dce_v10_0_check_latency_hiding - check latency hiding
1154  *
1155  * @wm: watermark calculation data
1156  *
1157  * Check latency hiding (CIK).
1158  * Used for display watermark bandwidth calculations
1159  * Returns true if the display fits, false if not.
1160  */
1161 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1162 {
1163         u32 lb_partitions = wm->lb_size / wm->src_width;
1164         u32 line_time = wm->active_time + wm->blank_time;
1165         u32 latency_tolerant_lines;
1166         u32 latency_hiding;
1167         fixed20_12 a;
1168
1169         a.full = dfixed_const(1);
1170         if (wm->vsc.full > a.full)
1171                 latency_tolerant_lines = 1;
1172         else {
1173                 if (lb_partitions <= (wm->vtaps + 1))
1174                         latency_tolerant_lines = 1;
1175                 else
1176                         latency_tolerant_lines = 2;
1177         }
1178
1179         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1180
1181         if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1182                 return true;
1183         else
1184                 return false;
1185 }
1186
1187 /**
1188  * dce_v10_0_program_watermarks - program display watermarks
1189  *
1190  * @adev: amdgpu_device pointer
1191  * @amdgpu_crtc: the selected display controller
1192  * @lb_size: line buffer size
1193  * @num_heads: number of display controllers in use
1194  *
1195  * Calculate and program the display watermarks for the
1196  * selected display controller (CIK).
1197  */
1198 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1199                                         struct amdgpu_crtc *amdgpu_crtc,
1200                                         u32 lb_size, u32 num_heads)
1201 {
1202         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1203         struct dce10_wm_params wm_low, wm_high;
1204         u32 active_time;
1205         u32 line_time = 0;
1206         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1207         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1208
1209         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1210                 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
1211                 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
1212
1213                 /* watermark for high clocks */
1214                 if (adev->pm.dpm_enabled) {
1215                         wm_high.yclk =
1216                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1217                         wm_high.sclk =
1218                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1219                 } else {
1220                         wm_high.yclk = adev->pm.current_mclk * 10;
1221                         wm_high.sclk = adev->pm.current_sclk * 10;
1222                 }
1223
1224                 wm_high.disp_clk = mode->clock;
1225                 wm_high.src_width = mode->crtc_hdisplay;
1226                 wm_high.active_time = active_time;
1227                 wm_high.blank_time = line_time - wm_high.active_time;
1228                 wm_high.interlaced = false;
1229                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1230                         wm_high.interlaced = true;
1231                 wm_high.vsc = amdgpu_crtc->vsc;
1232                 wm_high.vtaps = 1;
1233                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1234                         wm_high.vtaps = 2;
1235                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1236                 wm_high.lb_size = lb_size;
1237                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1238                 wm_high.num_heads = num_heads;
1239
1240                 /* set for high clocks */
1241                 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1242
1243                 /* possibly force display priority to high */
1244                 /* should really do this at mode validation time... */
1245                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1246                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1247                     !dce_v10_0_check_latency_hiding(&wm_high) ||
1248                     (adev->mode_info.disp_priority == 2)) {
1249                         DRM_DEBUG_KMS("force priority to high\n");
1250                 }
1251
1252                 /* watermark for low clocks */
1253                 if (adev->pm.dpm_enabled) {
1254                         wm_low.yclk =
1255                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1256                         wm_low.sclk =
1257                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1258                 } else {
1259                         wm_low.yclk = adev->pm.current_mclk * 10;
1260                         wm_low.sclk = adev->pm.current_sclk * 10;
1261                 }
1262
1263                 wm_low.disp_clk = mode->clock;
1264                 wm_low.src_width = mode->crtc_hdisplay;
1265                 wm_low.active_time = active_time;
1266                 wm_low.blank_time = line_time - wm_low.active_time;
1267                 wm_low.interlaced = false;
1268                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1269                         wm_low.interlaced = true;
1270                 wm_low.vsc = amdgpu_crtc->vsc;
1271                 wm_low.vtaps = 1;
1272                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1273                         wm_low.vtaps = 2;
1274                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1275                 wm_low.lb_size = lb_size;
1276                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1277                 wm_low.num_heads = num_heads;
1278
1279                 /* set for low clocks */
1280                 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1281
1282                 /* possibly force display priority to high */
1283                 /* should really do this at mode validation time... */
1284                 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1285                     !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1286                     !dce_v10_0_check_latency_hiding(&wm_low) ||
1287                     (adev->mode_info.disp_priority == 2)) {
1288                         DRM_DEBUG_KMS("force priority to high\n");
1289                 }
1290                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1291         }
1292
1293         /* select wm A */
1294         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1295         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1296         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1297         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1298         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1299         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1300         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1301         /* select wm B */
1302         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1303         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1304         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1305         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1306         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1307         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1308         /* restore original selection */
1309         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1310
1311         /* save values for DPM */
1312         amdgpu_crtc->line_time = line_time;
1313         amdgpu_crtc->wm_high = latency_watermark_a;
1314         amdgpu_crtc->wm_low = latency_watermark_b;
1315         /* Save number of lines the linebuffer leads before the scanout */
1316         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1317 }
1318
1319 /**
1320  * dce_v10_0_bandwidth_update - program display watermarks
1321  *
1322  * @adev: amdgpu_device pointer
1323  *
1324  * Calculate and program the display watermarks and line
1325  * buffer allocation (CIK).
1326  */
1327 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1328 {
1329         struct drm_display_mode *mode = NULL;
1330         u32 num_heads = 0, lb_size;
1331         int i;
1332
1333         amdgpu_update_display_priority(adev);
1334
1335         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1336                 if (adev->mode_info.crtcs[i]->base.enabled)
1337                         num_heads++;
1338         }
1339         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1340                 mode = &adev->mode_info.crtcs[i]->base.mode;
1341                 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1342                 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1343                                             lb_size, num_heads);
1344         }
1345 }
1346
1347 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1348 {
1349         int i;
1350         u32 offset, tmp;
1351
1352         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1353                 offset = adev->mode_info.audio.pin[i].offset;
1354                 tmp = RREG32_AUDIO_ENDPT(offset,
1355                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1356                 if (((tmp &
1357                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1358                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1359                         adev->mode_info.audio.pin[i].connected = false;
1360                 else
1361                         adev->mode_info.audio.pin[i].connected = true;
1362         }
1363 }
1364
1365 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1366 {
1367         int i;
1368
1369         dce_v10_0_audio_get_connected_pins(adev);
1370
1371         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1372                 if (adev->mode_info.audio.pin[i].connected)
1373                         return &adev->mode_info.audio.pin[i];
1374         }
1375         DRM_ERROR("No connected audio pins found!\n");
1376         return NULL;
1377 }
1378
1379 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1380 {
1381         struct amdgpu_device *adev = encoder->dev->dev_private;
1382         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1383         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1384         u32 tmp;
1385
1386         if (!dig || !dig->afmt || !dig->afmt->pin)
1387                 return;
1388
1389         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1390         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1391         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1392 }
1393
1394 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1395                                                 struct drm_display_mode *mode)
1396 {
1397         struct amdgpu_device *adev = encoder->dev->dev_private;
1398         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1399         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1400         struct drm_connector *connector;
1401         struct amdgpu_connector *amdgpu_connector = NULL;
1402         u32 tmp;
1403         int interlace = 0;
1404
1405         if (!dig || !dig->afmt || !dig->afmt->pin)
1406                 return;
1407
1408         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1409                 if (connector->encoder == encoder) {
1410                         amdgpu_connector = to_amdgpu_connector(connector);
1411                         break;
1412                 }
1413         }
1414
1415         if (!amdgpu_connector) {
1416                 DRM_ERROR("Couldn't find encoder's connector\n");
1417                 return;
1418         }
1419
1420         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1421                 interlace = 1;
1422         if (connector->latency_present[interlace]) {
1423                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1424                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1425                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1426                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1427         } else {
1428                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1429                                     VIDEO_LIPSYNC, 0);
1430                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1431                                     AUDIO_LIPSYNC, 0);
1432         }
1433         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1434                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1435 }
1436
1437 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1438 {
1439         struct amdgpu_device *adev = encoder->dev->dev_private;
1440         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1441         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1442         struct drm_connector *connector;
1443         struct amdgpu_connector *amdgpu_connector = NULL;
1444         u32 tmp;
1445         u8 *sadb = NULL;
1446         int sad_count;
1447
1448         if (!dig || !dig->afmt || !dig->afmt->pin)
1449                 return;
1450
1451         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1452                 if (connector->encoder == encoder) {
1453                         amdgpu_connector = to_amdgpu_connector(connector);
1454                         break;
1455                 }
1456         }
1457
1458         if (!amdgpu_connector) {
1459                 DRM_ERROR("Couldn't find encoder's connector\n");
1460                 return;
1461         }
1462
1463         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1464         if (sad_count < 0) {
1465                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1466                 sad_count = 0;
1467         }
1468
1469         /* program the speaker allocation */
1470         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1471                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1472         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1473                             DP_CONNECTION, 0);
1474         /* set HDMI mode */
1475         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1476                             HDMI_CONNECTION, 1);
1477         if (sad_count)
1478                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1479                                     SPEAKER_ALLOCATION, sadb[0]);
1480         else
1481                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1482                                     SPEAKER_ALLOCATION, 5); /* stereo */
1483         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1484                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1485
1486         kfree(sadb);
1487 }
1488
1489 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1490 {
1491         struct amdgpu_device *adev = encoder->dev->dev_private;
1492         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1493         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1494         struct drm_connector *connector;
1495         struct amdgpu_connector *amdgpu_connector = NULL;
1496         struct cea_sad *sads;
1497         int i, sad_count;
1498
1499         static const u16 eld_reg_to_type[][2] = {
1500                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1501                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1502                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1503                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1504                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1505                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1506                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1507                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1508                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1509                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1510                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1511                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1512         };
1513
1514         if (!dig || !dig->afmt || !dig->afmt->pin)
1515                 return;
1516
1517         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1518                 if (connector->encoder == encoder) {
1519                         amdgpu_connector = to_amdgpu_connector(connector);
1520                         break;
1521                 }
1522         }
1523
1524         if (!amdgpu_connector) {
1525                 DRM_ERROR("Couldn't find encoder's connector\n");
1526                 return;
1527         }
1528
1529         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1530         if (sad_count <= 0) {
1531                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1532                 return;
1533         }
1534         BUG_ON(!sads);
1535
1536         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1537                 u32 tmp = 0;
1538                 u8 stereo_freqs = 0;
1539                 int max_channels = -1;
1540                 int j;
1541
1542                 for (j = 0; j < sad_count; j++) {
1543                         struct cea_sad *sad = &sads[j];
1544
1545                         if (sad->format == eld_reg_to_type[i][1]) {
1546                                 if (sad->channels > max_channels) {
1547                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1548                                                             MAX_CHANNELS, sad->channels);
1549                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1550                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1551                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1552                                                             SUPPORTED_FREQUENCIES, sad->freq);
1553                                         max_channels = sad->channels;
1554                                 }
1555
1556                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1557                                         stereo_freqs |= sad->freq;
1558                                 else
1559                                         break;
1560                         }
1561                 }
1562
1563                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1564                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1565                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1566         }
1567
1568         kfree(sads);
1569 }
1570
1571 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1572                                   struct amdgpu_audio_pin *pin,
1573                                   bool enable)
1574 {
1575         if (!pin)
1576                 return;
1577
1578         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1579                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1580 }
1581
1582 static const u32 pin_offsets[] =
1583 {
1584         AUD0_REGISTER_OFFSET,
1585         AUD1_REGISTER_OFFSET,
1586         AUD2_REGISTER_OFFSET,
1587         AUD3_REGISTER_OFFSET,
1588         AUD4_REGISTER_OFFSET,
1589         AUD5_REGISTER_OFFSET,
1590         AUD6_REGISTER_OFFSET,
1591 };
1592
1593 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1594 {
1595         int i;
1596
1597         if (!amdgpu_audio)
1598                 return 0;
1599
1600         adev->mode_info.audio.enabled = true;
1601
1602         adev->mode_info.audio.num_pins = 7;
1603
1604         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1605                 adev->mode_info.audio.pin[i].channels = -1;
1606                 adev->mode_info.audio.pin[i].rate = -1;
1607                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1608                 adev->mode_info.audio.pin[i].status_bits = 0;
1609                 adev->mode_info.audio.pin[i].category_code = 0;
1610                 adev->mode_info.audio.pin[i].connected = false;
1611                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1612                 adev->mode_info.audio.pin[i].id = i;
1613                 /* disable audio.  it will be set up later */
1614                 /* XXX remove once we switch to ip funcs */
1615                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1616         }
1617
1618         return 0;
1619 }
1620
1621 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1622 {
1623         int i;
1624
1625         if (!amdgpu_audio)
1626                 return;
1627
1628         if (!adev->mode_info.audio.enabled)
1629                 return;
1630
1631         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1632                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1633
1634         adev->mode_info.audio.enabled = false;
1635 }
1636
1637 /*
1638  * update the N and CTS parameters for a given pixel clock rate
1639  */
1640 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1641 {
1642         struct drm_device *dev = encoder->dev;
1643         struct amdgpu_device *adev = dev->dev_private;
1644         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1645         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1646         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1647         u32 tmp;
1648
1649         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1650         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1651         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1652         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1653         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1654         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1655
1656         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1657         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1658         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1659         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1660         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1661         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1662
1663         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1664         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1665         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1666         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1667         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1668         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1669
1670 }
1671
1672 /*
1673  * build a HDMI Video Info Frame
1674  */
1675 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1676                                                void *buffer, size_t size)
1677 {
1678         struct drm_device *dev = encoder->dev;
1679         struct amdgpu_device *adev = dev->dev_private;
1680         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1681         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1682         uint8_t *frame = buffer + 3;
1683         uint8_t *header = buffer;
1684
1685         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1686                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1687         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1688                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1689         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1690                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1691         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1692                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1693 }
1694
1695 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1696 {
1697         struct drm_device *dev = encoder->dev;
1698         struct amdgpu_device *adev = dev->dev_private;
1699         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1700         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1701         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1702         u32 dto_phase = 24 * 1000;
1703         u32 dto_modulo = clock;
1704         u32 tmp;
1705
1706         if (!dig || !dig->afmt)
1707                 return;
1708
1709         /* XXX two dtos; generally use dto0 for hdmi */
1710         /* Express [24MHz / target pixel clock] as an exact rational
1711          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1712          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1713          */
1714         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1715         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1716                             amdgpu_crtc->crtc_id);
1717         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1718         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1719         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1720 }
1721
1722 /*
1723  * update the info frames with the data from the current display mode
1724  */
1725 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1726                                   struct drm_display_mode *mode)
1727 {
1728         struct drm_device *dev = encoder->dev;
1729         struct amdgpu_device *adev = dev->dev_private;
1730         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1731         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1732         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1733         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1734         struct hdmi_avi_infoframe frame;
1735         ssize_t err;
1736         u32 tmp;
1737         int bpc = 8;
1738
1739         if (!dig || !dig->afmt)
1740                 return;
1741
1742         /* Silent, r600_hdmi_enable will raise WARN for us */
1743         if (!dig->afmt->enabled)
1744                 return;
1745
1746         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1747         if (encoder->crtc) {
1748                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1749                 bpc = amdgpu_crtc->bpc;
1750         }
1751
1752         /* disable audio prior to setting up hw */
1753         dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1754         dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1755
1756         dce_v10_0_audio_set_dto(encoder, mode->clock);
1757
1758         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1759         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1760         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1761
1762         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1763
1764         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1765         switch (bpc) {
1766         case 0:
1767         case 6:
1768         case 8:
1769         case 16:
1770         default:
1771                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1772                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1773                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1774                           connector->name, bpc);
1775                 break;
1776         case 10:
1777                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1778                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1779                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1780                           connector->name);
1781                 break;
1782         case 12:
1783                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1784                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1785                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1786                           connector->name);
1787                 break;
1788         }
1789         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1790
1791         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1792         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1793         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1794         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1795         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1796
1797         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1798         /* enable audio info frames (frames won't be set until audio is enabled) */
1799         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1800         /* required for audio info values to be updated */
1801         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1802         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1803
1804         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1805         /* required for audio info values to be updated */
1806         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1807         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1808
1809         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1810         /* anything other than 0 */
1811         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1812         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1813
1814         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1815
1816         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1817         /* set the default audio delay */
1818         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1819         /* should be suffient for all audio modes and small enough for all hblanks */
1820         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1821         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1822
1823         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1824         /* allow 60958 channel status fields to be updated */
1825         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1826         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1827
1828         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1829         if (bpc > 8)
1830                 /* clear SW CTS value */
1831                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1832         else
1833                 /* select SW CTS value */
1834                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1835         /* allow hw to sent ACR packets when required */
1836         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1837         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1838
1839         dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1840
1841         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1842         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1843         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1844
1845         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1846         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1847         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1848
1849         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1850         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1851         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1852         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1853         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1854         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1855         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1856         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1857
1858         dce_v10_0_audio_write_speaker_allocation(encoder);
1859
1860         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1861                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1862
1863         dce_v10_0_afmt_audio_select_pin(encoder);
1864         dce_v10_0_audio_write_sad_regs(encoder);
1865         dce_v10_0_audio_write_latency_fields(encoder, mode);
1866
1867         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1868         if (err < 0) {
1869                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1870                 return;
1871         }
1872
1873         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1874         if (err < 0) {
1875                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1876                 return;
1877         }
1878
1879         dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1880
1881         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1882         /* enable AVI info frames */
1883         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1884         /* required for audio info values to be updated */
1885         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1886         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1887
1888         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1889         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1890         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1891
1892         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1893         /* send audio packets */
1894         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1895         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1896
1897         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1898         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1899         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1900         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1901
1902         /* enable audio after to setting up hw */
1903         dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1904 }
1905
1906 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1907 {
1908         struct drm_device *dev = encoder->dev;
1909         struct amdgpu_device *adev = dev->dev_private;
1910         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1911         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1912
1913         if (!dig || !dig->afmt)
1914                 return;
1915
1916         /* Silent, r600_hdmi_enable will raise WARN for us */
1917         if (enable && dig->afmt->enabled)
1918                 return;
1919         if (!enable && !dig->afmt->enabled)
1920                 return;
1921
1922         if (!enable && dig->afmt->pin) {
1923                 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1924                 dig->afmt->pin = NULL;
1925         }
1926
1927         dig->afmt->enabled = enable;
1928
1929         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1930                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1931 }
1932
1933 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1934 {
1935         int i;
1936
1937         for (i = 0; i < adev->mode_info.num_dig; i++)
1938                 adev->mode_info.afmt[i] = NULL;
1939
1940         /* DCE10 has audio blocks tied to DIG encoders */
1941         for (i = 0; i < adev->mode_info.num_dig; i++) {
1942                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1943                 if (adev->mode_info.afmt[i]) {
1944                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1945                         adev->mode_info.afmt[i]->id = i;
1946                 } else {
1947                         int j;
1948                         for (j = 0; j < i; j++) {
1949                                 kfree(adev->mode_info.afmt[j]);
1950                                 adev->mode_info.afmt[j] = NULL;
1951                         }
1952                         return -ENOMEM;
1953                 }
1954         }
1955         return 0;
1956 }
1957
1958 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1959 {
1960         int i;
1961
1962         for (i = 0; i < adev->mode_info.num_dig; i++) {
1963                 kfree(adev->mode_info.afmt[i]);
1964                 adev->mode_info.afmt[i] = NULL;
1965         }
1966 }
1967
1968 static const u32 vga_control_regs[6] =
1969 {
1970         mmD1VGA_CONTROL,
1971         mmD2VGA_CONTROL,
1972         mmD3VGA_CONTROL,
1973         mmD4VGA_CONTROL,
1974         mmD5VGA_CONTROL,
1975         mmD6VGA_CONTROL,
1976 };
1977
1978 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1979 {
1980         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1981         struct drm_device *dev = crtc->dev;
1982         struct amdgpu_device *adev = dev->dev_private;
1983         u32 vga_control;
1984
1985         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1986         if (enable)
1987                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1988         else
1989                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1990 }
1991
1992 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1993 {
1994         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1995         struct drm_device *dev = crtc->dev;
1996         struct amdgpu_device *adev = dev->dev_private;
1997
1998         if (enable)
1999                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2000         else
2001                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2002 }
2003
2004 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2005                                      struct drm_framebuffer *fb,
2006                                      int x, int y, int atomic)
2007 {
2008         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2009         struct drm_device *dev = crtc->dev;
2010         struct amdgpu_device *adev = dev->dev_private;
2011         struct amdgpu_framebuffer *amdgpu_fb;
2012         struct drm_framebuffer *target_fb;
2013         struct drm_gem_object *obj;
2014         struct amdgpu_bo *abo;
2015         uint64_t fb_location, tiling_flags;
2016         uint32_t fb_format, fb_pitch_pixels;
2017         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2018         u32 pipe_config;
2019         u32 tmp, viewport_w, viewport_h;
2020         int r;
2021         bool bypass_lut = false;
2022         struct drm_format_name_buf format_name;
2023
2024         /* no fb bound */
2025         if (!atomic && !crtc->primary->fb) {
2026                 DRM_DEBUG_KMS("No FB bound\n");
2027                 return 0;
2028         }
2029
2030         if (atomic) {
2031                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2032                 target_fb = fb;
2033         } else {
2034                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2035                 target_fb = crtc->primary->fb;
2036         }
2037
2038         /* If atomic, assume fb object is pinned & idle & fenced and
2039          * just update base pointers
2040          */
2041         obj = amdgpu_fb->obj;
2042         abo = gem_to_amdgpu_bo(obj);
2043         r = amdgpu_bo_reserve(abo, false);
2044         if (unlikely(r != 0))
2045                 return r;
2046
2047         if (atomic) {
2048                 fb_location = amdgpu_bo_gpu_offset(abo);
2049         } else {
2050                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2051                 if (unlikely(r != 0)) {
2052                         amdgpu_bo_unreserve(abo);
2053                         return -EINVAL;
2054                 }
2055         }
2056
2057         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2058         amdgpu_bo_unreserve(abo);
2059
2060         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2061
2062         switch (target_fb->format->format) {
2063         case DRM_FORMAT_C8:
2064                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2065                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2066                 break;
2067         case DRM_FORMAT_XRGB4444:
2068         case DRM_FORMAT_ARGB4444:
2069                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2070                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2071 #ifdef __BIG_ENDIAN
2072                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2073                                         ENDIAN_8IN16);
2074 #endif
2075                 break;
2076         case DRM_FORMAT_XRGB1555:
2077         case DRM_FORMAT_ARGB1555:
2078                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2079                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2080 #ifdef __BIG_ENDIAN
2081                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2082                                         ENDIAN_8IN16);
2083 #endif
2084                 break;
2085         case DRM_FORMAT_BGRX5551:
2086         case DRM_FORMAT_BGRA5551:
2087                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2088                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2089 #ifdef __BIG_ENDIAN
2090                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2091                                         ENDIAN_8IN16);
2092 #endif
2093                 break;
2094         case DRM_FORMAT_RGB565:
2095                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2096                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2097 #ifdef __BIG_ENDIAN
2098                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2099                                         ENDIAN_8IN16);
2100 #endif
2101                 break;
2102         case DRM_FORMAT_XRGB8888:
2103         case DRM_FORMAT_ARGB8888:
2104                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2105                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2106 #ifdef __BIG_ENDIAN
2107                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108                                         ENDIAN_8IN32);
2109 #endif
2110                 break;
2111         case DRM_FORMAT_XRGB2101010:
2112         case DRM_FORMAT_ARGB2101010:
2113                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2114                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2115 #ifdef __BIG_ENDIAN
2116                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2117                                         ENDIAN_8IN32);
2118 #endif
2119                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2120                 bypass_lut = true;
2121                 break;
2122         case DRM_FORMAT_BGRX1010102:
2123         case DRM_FORMAT_BGRA1010102:
2124                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2125                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2126 #ifdef __BIG_ENDIAN
2127                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2128                                         ENDIAN_8IN32);
2129 #endif
2130                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2131                 bypass_lut = true;
2132                 break;
2133         default:
2134                 DRM_ERROR("Unsupported screen format %s\n",
2135                           drm_get_format_name(target_fb->format->format, &format_name));
2136                 return -EINVAL;
2137         }
2138
2139         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2140                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2141
2142                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2143                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2144                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2145                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2146                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2147
2148                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2149                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2150                                           ARRAY_2D_TILED_THIN1);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2152                                           tile_split);
2153                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2154                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2155                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2156                                           mtaspect);
2157                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2158                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2159         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2160                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2161                                           ARRAY_1D_TILED_THIN1);
2162         }
2163
2164         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2165                                   pipe_config);
2166
2167         dce_v10_0_vga_enable(crtc, false);
2168
2169         /* Make sure surface address is updated at vertical blank rather than
2170          * horizontal blank
2171          */
2172         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2173         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2174                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2175         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2176
2177         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2178                upper_32_bits(fb_location));
2179         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2180                upper_32_bits(fb_location));
2181         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2182                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2183         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2184                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2185         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2186         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2187
2188         /*
2189          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2190          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2191          * retain the full precision throughout the pipeline.
2192          */
2193         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2194         if (bypass_lut)
2195                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2196         else
2197                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2198         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2199
2200         if (bypass_lut)
2201                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2202
2203         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2204         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2205         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2206         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2207         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2208         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2209
2210         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2211         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2212
2213         dce_v10_0_grph_enable(crtc, true);
2214
2215         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2216                target_fb->height);
2217
2218         x &= ~3;
2219         y &= ~1;
2220         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2221                (x << 16) | y);
2222         viewport_w = crtc->mode.hdisplay;
2223         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2224         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2225                (viewport_w << 16) | viewport_h);
2226
2227         /* set pageflip to happen anywhere in vblank interval */
2228         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2229
2230         if (!atomic && fb && fb != crtc->primary->fb) {
2231                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2232                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2233                 r = amdgpu_bo_reserve(abo, true);
2234                 if (unlikely(r != 0))
2235                         return r;
2236                 amdgpu_bo_unpin(abo);
2237                 amdgpu_bo_unreserve(abo);
2238         }
2239
2240         /* Bytes per pixel may have changed */
2241         dce_v10_0_bandwidth_update(adev);
2242
2243         return 0;
2244 }
2245
2246 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2247                                      struct drm_display_mode *mode)
2248 {
2249         struct drm_device *dev = crtc->dev;
2250         struct amdgpu_device *adev = dev->dev_private;
2251         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2252         u32 tmp;
2253
2254         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2255         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2256                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2257         else
2258                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2259         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2260 }
2261
2262 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2263 {
2264         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2265         struct drm_device *dev = crtc->dev;
2266         struct amdgpu_device *adev = dev->dev_private;
2267         int i;
2268         u32 tmp;
2269
2270         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2271
2272         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2273         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2274         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2275         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2276
2277         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2278         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2279         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2280
2281         tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2282         tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2283         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2284
2285         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2286         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2287         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2288         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2289
2290         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2291
2292         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2293         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2294         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2295
2296         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2297         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2298         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2299
2300         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2301         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2302
2303         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2304         for (i = 0; i < 256; i++) {
2305                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2306                        (amdgpu_crtc->lut_r[i] << 20) |
2307                        (amdgpu_crtc->lut_g[i] << 10) |
2308                        (amdgpu_crtc->lut_b[i] << 0));
2309         }
2310
2311         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2312         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2313         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2314         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2315         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2316
2317         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2318         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2319         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2320         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2321
2322         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2323         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2324         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2325         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2326
2327         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2328         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2329         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2330         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2331
2332         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2333         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2334         /* XXX this only needs to be programmed once per crtc at startup,
2335          * not sure where the best place for it is
2336          */
2337         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2338         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2339         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2340 }
2341
2342 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2343 {
2344         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2345         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2346
2347         switch (amdgpu_encoder->encoder_id) {
2348         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2349                 if (dig->linkb)
2350                         return 1;
2351                 else
2352                         return 0;
2353                 break;
2354         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2355                 if (dig->linkb)
2356                         return 3;
2357                 else
2358                         return 2;
2359                 break;
2360         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2361                 if (dig->linkb)
2362                         return 5;
2363                 else
2364                         return 4;
2365                 break;
2366         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2367                 return 6;
2368                 break;
2369         default:
2370                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2371                 return 0;
2372         }
2373 }
2374
2375 /**
2376  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2377  *
2378  * @crtc: drm crtc
2379  *
2380  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2381  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2382  * monitors a dedicated PPLL must be used.  If a particular board has
2383  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2384  * as there is no need to program the PLL itself.  If we are not able to
2385  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2386  * avoid messing up an existing monitor.
2387  *
2388  * Asic specific PLL information
2389  *
2390  * DCE 10.x
2391  * Tonga
2392  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2393  * CI
2394  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2395  *
2396  */
2397 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2398 {
2399         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2400         struct drm_device *dev = crtc->dev;
2401         struct amdgpu_device *adev = dev->dev_private;
2402         u32 pll_in_use;
2403         int pll;
2404
2405         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2406                 if (adev->clock.dp_extclk)
2407                         /* skip PPLL programming if using ext clock */
2408                         return ATOM_PPLL_INVALID;
2409                 else {
2410                         /* use the same PPLL for all DP monitors */
2411                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2412                         if (pll != ATOM_PPLL_INVALID)
2413                                 return pll;
2414                 }
2415         } else {
2416                 /* use the same PPLL for all monitors with the same clock */
2417                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2418                 if (pll != ATOM_PPLL_INVALID)
2419                         return pll;
2420         }
2421
2422         /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2423         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2424         if (!(pll_in_use & (1 << ATOM_PPLL2)))
2425                 return ATOM_PPLL2;
2426         if (!(pll_in_use & (1 << ATOM_PPLL1)))
2427                 return ATOM_PPLL1;
2428         if (!(pll_in_use & (1 << ATOM_PPLL0)))
2429                 return ATOM_PPLL0;
2430         DRM_ERROR("unable to allocate a PPLL\n");
2431         return ATOM_PPLL_INVALID;
2432 }
2433
2434 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2435 {
2436         struct amdgpu_device *adev = crtc->dev->dev_private;
2437         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2438         uint32_t cur_lock;
2439
2440         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2441         if (lock)
2442                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2443         else
2444                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2445         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2446 }
2447
2448 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2449 {
2450         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2451         struct amdgpu_device *adev = crtc->dev->dev_private;
2452         u32 tmp;
2453
2454         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2455         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2456         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2457 }
2458
2459 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2460 {
2461         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2462         struct amdgpu_device *adev = crtc->dev->dev_private;
2463         u32 tmp;
2464
2465         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2466                upper_32_bits(amdgpu_crtc->cursor_addr));
2467         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2468                lower_32_bits(amdgpu_crtc->cursor_addr));
2469
2470         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2471         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2472         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2473         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2474 }
2475
2476 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2477                                         int x, int y)
2478 {
2479         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2480         struct amdgpu_device *adev = crtc->dev->dev_private;
2481         int xorigin = 0, yorigin = 0;
2482
2483         amdgpu_crtc->cursor_x = x;
2484         amdgpu_crtc->cursor_y = y;
2485
2486         /* avivo cursor are offset into the total surface */
2487         x += crtc->x;
2488         y += crtc->y;
2489         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2490
2491         if (x < 0) {
2492                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2493                 x = 0;
2494         }
2495         if (y < 0) {
2496                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2497                 y = 0;
2498         }
2499
2500         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2501         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2502         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2503                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2504
2505         return 0;
2506 }
2507
2508 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2509                                       int x, int y)
2510 {
2511         int ret;
2512
2513         dce_v10_0_lock_cursor(crtc, true);
2514         ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2515         dce_v10_0_lock_cursor(crtc, false);
2516
2517         return ret;
2518 }
2519
2520 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2521                                       struct drm_file *file_priv,
2522                                       uint32_t handle,
2523                                       uint32_t width,
2524                                       uint32_t height,
2525                                       int32_t hot_x,
2526                                       int32_t hot_y)
2527 {
2528         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2529         struct drm_gem_object *obj;
2530         struct amdgpu_bo *aobj;
2531         int ret;
2532
2533         if (!handle) {
2534                 /* turn off cursor */
2535                 dce_v10_0_hide_cursor(crtc);
2536                 obj = NULL;
2537                 goto unpin;
2538         }
2539
2540         if ((width > amdgpu_crtc->max_cursor_width) ||
2541             (height > amdgpu_crtc->max_cursor_height)) {
2542                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2543                 return -EINVAL;
2544         }
2545
2546         obj = drm_gem_object_lookup(file_priv, handle);
2547         if (!obj) {
2548                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2549                 return -ENOENT;
2550         }
2551
2552         aobj = gem_to_amdgpu_bo(obj);
2553         ret = amdgpu_bo_reserve(aobj, false);
2554         if (ret != 0) {
2555                 drm_gem_object_unreference_unlocked(obj);
2556                 return ret;
2557         }
2558
2559         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2560         amdgpu_bo_unreserve(aobj);
2561         if (ret) {
2562                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2563                 drm_gem_object_unreference_unlocked(obj);
2564                 return ret;
2565         }
2566
2567         dce_v10_0_lock_cursor(crtc, true);
2568
2569         if (width != amdgpu_crtc->cursor_width ||
2570             height != amdgpu_crtc->cursor_height ||
2571             hot_x != amdgpu_crtc->cursor_hot_x ||
2572             hot_y != amdgpu_crtc->cursor_hot_y) {
2573                 int x, y;
2574
2575                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2576                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2577
2578                 dce_v10_0_cursor_move_locked(crtc, x, y);
2579
2580                 amdgpu_crtc->cursor_width = width;
2581                 amdgpu_crtc->cursor_height = height;
2582                 amdgpu_crtc->cursor_hot_x = hot_x;
2583                 amdgpu_crtc->cursor_hot_y = hot_y;
2584         }
2585
2586         dce_v10_0_show_cursor(crtc);
2587         dce_v10_0_lock_cursor(crtc, false);
2588
2589 unpin:
2590         if (amdgpu_crtc->cursor_bo) {
2591                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2592                 ret = amdgpu_bo_reserve(aobj, true);
2593                 if (likely(ret == 0)) {
2594                         amdgpu_bo_unpin(aobj);
2595                         amdgpu_bo_unreserve(aobj);
2596                 }
2597                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2598         }
2599
2600         amdgpu_crtc->cursor_bo = obj;
2601         return 0;
2602 }
2603
2604 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2605 {
2606         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2607
2608         if (amdgpu_crtc->cursor_bo) {
2609                 dce_v10_0_lock_cursor(crtc, true);
2610
2611                 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2612                                              amdgpu_crtc->cursor_y);
2613
2614                 dce_v10_0_show_cursor(crtc);
2615
2616                 dce_v10_0_lock_cursor(crtc, false);
2617         }
2618 }
2619
2620 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2621                                     u16 *blue, uint32_t size,
2622                                     struct drm_modeset_acquire_ctx *ctx)
2623 {
2624         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2625         int i;
2626
2627         /* userspace palettes are always correct as is */
2628         for (i = 0; i < size; i++) {
2629                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2630                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2631                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2632         }
2633         dce_v10_0_crtc_load_lut(crtc);
2634
2635         return 0;
2636 }
2637
2638 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2639 {
2640         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2641
2642         drm_crtc_cleanup(crtc);
2643         kfree(amdgpu_crtc);
2644 }
2645
2646 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2647         .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2648         .cursor_move = dce_v10_0_crtc_cursor_move,
2649         .gamma_set = dce_v10_0_crtc_gamma_set,
2650         .set_config = amdgpu_crtc_set_config,
2651         .destroy = dce_v10_0_crtc_destroy,
2652         .page_flip_target = amdgpu_crtc_page_flip_target,
2653 };
2654
2655 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2656 {
2657         struct drm_device *dev = crtc->dev;
2658         struct amdgpu_device *adev = dev->dev_private;
2659         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2660         unsigned type;
2661
2662         switch (mode) {
2663         case DRM_MODE_DPMS_ON:
2664                 amdgpu_crtc->enabled = true;
2665                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2666                 dce_v10_0_vga_enable(crtc, true);
2667                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2668                 dce_v10_0_vga_enable(crtc, false);
2669                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2670                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2671                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2672                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2673                 drm_crtc_vblank_on(crtc);
2674                 dce_v10_0_crtc_load_lut(crtc);
2675                 break;
2676         case DRM_MODE_DPMS_STANDBY:
2677         case DRM_MODE_DPMS_SUSPEND:
2678         case DRM_MODE_DPMS_OFF:
2679                 drm_crtc_vblank_off(crtc);
2680                 if (amdgpu_crtc->enabled) {
2681                         dce_v10_0_vga_enable(crtc, true);
2682                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2683                         dce_v10_0_vga_enable(crtc, false);
2684                 }
2685                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2686                 amdgpu_crtc->enabled = false;
2687                 break;
2688         }
2689         /* adjust pm to dpms */
2690         amdgpu_pm_compute_clocks(adev);
2691 }
2692
2693 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2694 {
2695         /* disable crtc pair power gating before programming */
2696         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2697         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2698         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2699 }
2700
2701 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2702 {
2703         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2704         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2705 }
2706
2707 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2708 {
2709         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2710         struct drm_device *dev = crtc->dev;
2711         struct amdgpu_device *adev = dev->dev_private;
2712         struct amdgpu_atom_ss ss;
2713         int i;
2714
2715         dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2716         if (crtc->primary->fb) {
2717                 int r;
2718                 struct amdgpu_framebuffer *amdgpu_fb;
2719                 struct amdgpu_bo *abo;
2720
2721                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2722                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2723                 r = amdgpu_bo_reserve(abo, true);
2724                 if (unlikely(r))
2725                         DRM_ERROR("failed to reserve abo before unpin\n");
2726                 else {
2727                         amdgpu_bo_unpin(abo);
2728                         amdgpu_bo_unreserve(abo);
2729                 }
2730         }
2731         /* disable the GRPH */
2732         dce_v10_0_grph_enable(crtc, false);
2733
2734         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2735
2736         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2737                 if (adev->mode_info.crtcs[i] &&
2738                     adev->mode_info.crtcs[i]->enabled &&
2739                     i != amdgpu_crtc->crtc_id &&
2740                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2741                         /* one other crtc is using this pll don't turn
2742                          * off the pll
2743                          */
2744                         goto done;
2745                 }
2746         }
2747
2748         switch (amdgpu_crtc->pll_id) {
2749         case ATOM_PPLL0:
2750         case ATOM_PPLL1:
2751         case ATOM_PPLL2:
2752                 /* disable the ppll */
2753                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2754                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2755                 break;
2756         default:
2757                 break;
2758         }
2759 done:
2760         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2761         amdgpu_crtc->adjusted_clock = 0;
2762         amdgpu_crtc->encoder = NULL;
2763         amdgpu_crtc->connector = NULL;
2764 }
2765
2766 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2767                                   struct drm_display_mode *mode,
2768                                   struct drm_display_mode *adjusted_mode,
2769                                   int x, int y, struct drm_framebuffer *old_fb)
2770 {
2771         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2772
2773         if (!amdgpu_crtc->adjusted_clock)
2774                 return -EINVAL;
2775
2776         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2777         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2778         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2779         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2780         amdgpu_atombios_crtc_scaler_setup(crtc);
2781         dce_v10_0_cursor_reset(crtc);
2782         /* update the hw version fpr dpm */
2783         amdgpu_crtc->hw_mode = *adjusted_mode;
2784
2785         return 0;
2786 }
2787
2788 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2789                                      const struct drm_display_mode *mode,
2790                                      struct drm_display_mode *adjusted_mode)
2791 {
2792         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2793         struct drm_device *dev = crtc->dev;
2794         struct drm_encoder *encoder;
2795
2796         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2797         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2798                 if (encoder->crtc == crtc) {
2799                         amdgpu_crtc->encoder = encoder;
2800                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2801                         break;
2802                 }
2803         }
2804         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2805                 amdgpu_crtc->encoder = NULL;
2806                 amdgpu_crtc->connector = NULL;
2807                 return false;
2808         }
2809         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2810                 return false;
2811         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2812                 return false;
2813         /* pick pll */
2814         amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2815         /* if we can't get a PPLL for a non-DP encoder, fail */
2816         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2817             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2818                 return false;
2819
2820         return true;
2821 }
2822
2823 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2824                                   struct drm_framebuffer *old_fb)
2825 {
2826         return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2827 }
2828
2829 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2830                                          struct drm_framebuffer *fb,
2831                                          int x, int y, enum mode_set_atomic state)
2832 {
2833        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2834 }
2835
2836 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2837         .dpms = dce_v10_0_crtc_dpms,
2838         .mode_fixup = dce_v10_0_crtc_mode_fixup,
2839         .mode_set = dce_v10_0_crtc_mode_set,
2840         .mode_set_base = dce_v10_0_crtc_set_base,
2841         .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2842         .prepare = dce_v10_0_crtc_prepare,
2843         .commit = dce_v10_0_crtc_commit,
2844         .load_lut = dce_v10_0_crtc_load_lut,
2845         .disable = dce_v10_0_crtc_disable,
2846 };
2847
2848 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2849 {
2850         struct amdgpu_crtc *amdgpu_crtc;
2851         int i;
2852
2853         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2854                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2855         if (amdgpu_crtc == NULL)
2856                 return -ENOMEM;
2857
2858         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2859
2860         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2861         amdgpu_crtc->crtc_id = index;
2862         adev->mode_info.crtcs[index] = amdgpu_crtc;
2863
2864         amdgpu_crtc->max_cursor_width = 128;
2865         amdgpu_crtc->max_cursor_height = 128;
2866         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2867         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2868
2869         for (i = 0; i < 256; i++) {
2870                 amdgpu_crtc->lut_r[i] = i << 2;
2871                 amdgpu_crtc->lut_g[i] = i << 2;
2872                 amdgpu_crtc->lut_b[i] = i << 2;
2873         }
2874
2875         switch (amdgpu_crtc->crtc_id) {
2876         case 0:
2877         default:
2878                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2879                 break;
2880         case 1:
2881                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2882                 break;
2883         case 2:
2884                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2885                 break;
2886         case 3:
2887                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2888                 break;
2889         case 4:
2890                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2891                 break;
2892         case 5:
2893                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2894                 break;
2895         }
2896
2897         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2898         amdgpu_crtc->adjusted_clock = 0;
2899         amdgpu_crtc->encoder = NULL;
2900         amdgpu_crtc->connector = NULL;
2901         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2902
2903         return 0;
2904 }
2905
2906 static int dce_v10_0_early_init(void *handle)
2907 {
2908         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2909
2910         adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2911         adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2912
2913         dce_v10_0_set_display_funcs(adev);
2914         dce_v10_0_set_irq_funcs(adev);
2915
2916         adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2917
2918         switch (adev->asic_type) {
2919         case CHIP_FIJI:
2920         case CHIP_TONGA:
2921                 adev->mode_info.num_hpd = 6;
2922                 adev->mode_info.num_dig = 7;
2923                 break;
2924         default:
2925                 /* FIXME: not supported yet */
2926                 return -EINVAL;
2927         }
2928
2929         return 0;
2930 }
2931
2932 static int dce_v10_0_sw_init(void *handle)
2933 {
2934         int r, i;
2935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2936
2937         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2938                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2939                 if (r)
2940                         return r;
2941         }
2942
2943         for (i = 8; i < 20; i += 2) {
2944                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2945                 if (r)
2946                         return r;
2947         }
2948
2949         /* HPD hotplug */
2950         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2951         if (r)
2952                 return r;
2953
2954         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2955
2956         adev->ddev->mode_config.async_page_flip = true;
2957
2958         adev->ddev->mode_config.max_width = 16384;
2959         adev->ddev->mode_config.max_height = 16384;
2960
2961         adev->ddev->mode_config.preferred_depth = 24;
2962         adev->ddev->mode_config.prefer_shadow = 1;
2963
2964         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2965
2966         r = amdgpu_modeset_create_props(adev);
2967         if (r)
2968                 return r;
2969
2970         adev->ddev->mode_config.max_width = 16384;
2971         adev->ddev->mode_config.max_height = 16384;
2972
2973         /* allocate crtcs */
2974         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2975                 r = dce_v10_0_crtc_init(adev, i);
2976                 if (r)
2977                         return r;
2978         }
2979
2980         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2981                 amdgpu_print_display_setup(adev->ddev);
2982         else
2983                 return -EINVAL;
2984
2985         /* setup afmt */
2986         r = dce_v10_0_afmt_init(adev);
2987         if (r)
2988                 return r;
2989
2990         r = dce_v10_0_audio_init(adev);
2991         if (r)
2992                 return r;
2993
2994         drm_kms_helper_poll_init(adev->ddev);
2995
2996         adev->mode_info.mode_config_initialized = true;
2997         return 0;
2998 }
2999
3000 static int dce_v10_0_sw_fini(void *handle)
3001 {
3002         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3003
3004         kfree(adev->mode_info.bios_hardcoded_edid);
3005
3006         drm_kms_helper_poll_fini(adev->ddev);
3007
3008         dce_v10_0_audio_fini(adev);
3009
3010         dce_v10_0_afmt_fini(adev);
3011
3012         drm_mode_config_cleanup(adev->ddev);
3013         adev->mode_info.mode_config_initialized = false;
3014
3015         return 0;
3016 }
3017
3018 static int dce_v10_0_hw_init(void *handle)
3019 {
3020         int i;
3021         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3022
3023         dce_v10_0_init_golden_registers(adev);
3024
3025         /* init dig PHYs, disp eng pll */
3026         amdgpu_atombios_encoder_init_dig(adev);
3027         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3028
3029         /* initialize hpd */
3030         dce_v10_0_hpd_init(adev);
3031
3032         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3033                 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3034         }
3035
3036         dce_v10_0_pageflip_interrupt_init(adev);
3037
3038         return 0;
3039 }
3040
3041 static int dce_v10_0_hw_fini(void *handle)
3042 {
3043