a6dda3470003fe2d130695e8d434a92a90359c0b
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / ci_dpm.c
1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23
24 #include <linux/firmware.h>
25 #include "drmP.h"
26 #include "amdgpu.h"
27 #include "amdgpu_pm.h"
28 #include "amdgpu_ucode.h"
29 #include "cikd.h"
30 #include "amdgpu_dpm.h"
31 #include "ci_dpm.h"
32 #include "gfx_v7_0.h"
33 #include "atom.h"
34 #include "amd_pcie.h"
35 #include <linux/seq_file.h>
36
37 #include "smu/smu_7_0_1_d.h"
38 #include "smu/smu_7_0_1_sh_mask.h"
39
40 #include "dce/dce_8_0_d.h"
41 #include "dce/dce_8_0_sh_mask.h"
42
43 #include "bif/bif_4_1_d.h"
44 #include "bif/bif_4_1_sh_mask.h"
45
46 #include "gca/gfx_7_2_d.h"
47 #include "gca/gfx_7_2_sh_mask.h"
48
49 #include "gmc/gmc_7_1_d.h"
50 #include "gmc/gmc_7_1_sh_mask.h"
51
52 MODULE_FIRMWARE("radeon/bonaire_smc.bin");
53 MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
54 MODULE_FIRMWARE("radeon/hawaii_smc.bin");
55 MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
56
57 #define MC_CG_ARB_FREQ_F0           0x0a
58 #define MC_CG_ARB_FREQ_F1           0x0b
59 #define MC_CG_ARB_FREQ_F2           0x0c
60 #define MC_CG_ARB_FREQ_F3           0x0d
61
62 #define SMC_RAM_END 0x40000
63
64 #define VOLTAGE_SCALE               4
65 #define VOLTAGE_VID_OFFSET_SCALE1    625
66 #define VOLTAGE_VID_OFFSET_SCALE2    100
67
68 static const struct ci_pt_defaults defaults_hawaii_xt =
69 {
70         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
71         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
72         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
73 };
74
75 static const struct ci_pt_defaults defaults_hawaii_pro =
76 {
77         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
78         { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
79         { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
80 };
81
82 static const struct ci_pt_defaults defaults_bonaire_xt =
83 {
84         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
85         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
86         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
87 };
88
89 #if 0
90 static const struct ci_pt_defaults defaults_bonaire_pro =
91 {
92         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
93         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
94         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
95 };
96 #endif
97
98 static const struct ci_pt_defaults defaults_saturn_xt =
99 {
100         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
101         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
102         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
103 };
104
105 #if 0
106 static const struct ci_pt_defaults defaults_saturn_pro =
107 {
108         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
109         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
110         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
111 };
112 #endif
113
114 static const struct ci_pt_config_reg didt_config_ci[] =
115 {
116         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
121         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
122         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
123         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
129         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
130         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
131         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
132         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
133         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
139         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
140         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
141         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
147         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
148         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
149         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
150         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
151         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
157         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
158         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
159         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
160         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
161         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
163         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
164         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
165         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
166         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
167         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
168         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
169         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
170         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
171         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
172         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
173         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
174         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
175         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
176         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
177         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
178         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
179         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
180         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
181         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
182         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
183         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
184         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
185         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
186         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
187         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
188         { 0xFFFFFFFF }
189 };
190
191 static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
192 {
193         return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
194 }
195
196 #define MC_CG_ARB_FREQ_F0           0x0a
197 #define MC_CG_ARB_FREQ_F1           0x0b
198 #define MC_CG_ARB_FREQ_F2           0x0c
199 #define MC_CG_ARB_FREQ_F3           0x0d
200
201 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
202                                        u32 arb_freq_src, u32 arb_freq_dest)
203 {
204         u32 mc_arb_dram_timing;
205         u32 mc_arb_dram_timing2;
206         u32 burst_time;
207         u32 mc_cg_config;
208
209         switch (arb_freq_src) {
210         case MC_CG_ARB_FREQ_F0:
211                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
212                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
213                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
214                          MC_ARB_BURST_TIME__STATE0__SHIFT;
215                 break;
216         case MC_CG_ARB_FREQ_F1:
217                 mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
218                 mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
219                 burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
220                          MC_ARB_BURST_TIME__STATE1__SHIFT;
221                 break;
222         default:
223                 return -EINVAL;
224         }
225
226         switch (arb_freq_dest) {
227         case MC_CG_ARB_FREQ_F0:
228                 WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
229                 WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
230                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
231                         ~MC_ARB_BURST_TIME__STATE0_MASK);
232                 break;
233         case MC_CG_ARB_FREQ_F1:
234                 WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
235                 WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
236                 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
237                         ~MC_ARB_BURST_TIME__STATE1_MASK);
238                 break;
239         default:
240                 return -EINVAL;
241         }
242
243         mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
244         WREG32(mmMC_CG_CONFIG, mc_cg_config);
245         WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
246                 ~MC_ARB_CG__CG_ARB_REQ_MASK);
247
248         return 0;
249 }
250
251 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
252 {
253         u8 mc_para_index;
254
255         if (memory_clock < 10000)
256                 mc_para_index = 0;
257         else if (memory_clock >= 80000)
258                 mc_para_index = 0x0f;
259         else
260                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
261         return mc_para_index;
262 }
263
264 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
265 {
266         u8 mc_para_index;
267
268         if (strobe_mode) {
269                 if (memory_clock < 12500)
270                         mc_para_index = 0x00;
271                 else if (memory_clock > 47500)
272                         mc_para_index = 0x0f;
273                 else
274                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
275         } else {
276                 if (memory_clock < 65000)
277                         mc_para_index = 0x00;
278                 else if (memory_clock > 135000)
279                         mc_para_index = 0x0f;
280                 else
281                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
282         }
283         return mc_para_index;
284 }
285
286 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
287                                                      u32 max_voltage_steps,
288                                                      struct atom_voltage_table *voltage_table)
289 {
290         unsigned int i, diff;
291
292         if (voltage_table->count <= max_voltage_steps)
293                 return;
294
295         diff = voltage_table->count - max_voltage_steps;
296
297         for (i = 0; i < max_voltage_steps; i++)
298                 voltage_table->entries[i] = voltage_table->entries[i + diff];
299
300         voltage_table->count = max_voltage_steps;
301 }
302
303 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
304                                          struct atom_voltage_table_entry *voltage_table,
305                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
306 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
307 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
308                                        u32 target_tdp);
309 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
310 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
311 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
312
313 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
314                                                              PPSMC_Msg msg, u32 parameter);
315 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
316 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
317
318 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
319 {
320         struct ci_power_info *pi = adev->pm.dpm.priv;
321
322         return pi;
323 }
324
325 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
326 {
327         struct ci_ps *ps = rps->ps_priv;
328
329         return ps;
330 }
331
332 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
333 {
334         struct ci_power_info *pi = ci_get_pi(adev);
335
336         switch (adev->pdev->device) {
337         case 0x6649:
338         case 0x6650:
339         case 0x6651:
340         case 0x6658:
341         case 0x665C:
342         case 0x665D:
343         default:
344                 pi->powertune_defaults = &defaults_bonaire_xt;
345                 break;
346         case 0x6640:
347         case 0x6641:
348         case 0x6646:
349         case 0x6647:
350                 pi->powertune_defaults = &defaults_saturn_xt;
351                 break;
352         case 0x67B8:
353         case 0x67B0:
354                 pi->powertune_defaults = &defaults_hawaii_xt;
355                 break;
356         case 0x67BA:
357         case 0x67B1:
358                 pi->powertune_defaults = &defaults_hawaii_pro;
359                 break;
360         case 0x67A0:
361         case 0x67A1:
362         case 0x67A2:
363         case 0x67A8:
364         case 0x67A9:
365         case 0x67AA:
366         case 0x67B9:
367         case 0x67BE:
368                 pi->powertune_defaults = &defaults_bonaire_xt;
369                 break;
370         }
371
372         pi->dte_tj_offset = 0;
373
374         pi->caps_power_containment = true;
375         pi->caps_cac = false;
376         pi->caps_sq_ramping = false;
377         pi->caps_db_ramping = false;
378         pi->caps_td_ramping = false;
379         pi->caps_tcp_ramping = false;
380
381         if (pi->caps_power_containment) {
382                 pi->caps_cac = true;
383                 if (adev->asic_type == CHIP_HAWAII)
384                         pi->enable_bapm_feature = false;
385                 else
386                         pi->enable_bapm_feature = true;
387                 pi->enable_tdc_limit_feature = true;
388                 pi->enable_pkg_pwr_tracking_feature = true;
389         }
390 }
391
392 static u8 ci_convert_to_vid(u16 vddc)
393 {
394         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
395 }
396
397 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
398 {
399         struct ci_power_info *pi = ci_get_pi(adev);
400         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
401         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
402         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
403         u32 i;
404
405         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
406                 return -EINVAL;
407         if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
408                 return -EINVAL;
409         if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
410             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
411                 return -EINVAL;
412
413         for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
414                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
415                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
416                         hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
417                         hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
418                 } else {
419                         lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
420                         hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
421                 }
422         }
423         return 0;
424 }
425
426 static int ci_populate_vddc_vid(struct amdgpu_device *adev)
427 {
428         struct ci_power_info *pi = ci_get_pi(adev);
429         u8 *vid = pi->smc_powertune_table.VddCVid;
430         u32 i;
431
432         if (pi->vddc_voltage_table.count > 8)
433                 return -EINVAL;
434
435         for (i = 0; i < pi->vddc_voltage_table.count; i++)
436                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
437
438         return 0;
439 }
440
441 static int ci_populate_svi_load_line(struct amdgpu_device *adev)
442 {
443         struct ci_power_info *pi = ci_get_pi(adev);
444         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
445
446         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
447         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
448         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
449         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
450
451         return 0;
452 }
453
454 static int ci_populate_tdc_limit(struct amdgpu_device *adev)
455 {
456         struct ci_power_info *pi = ci_get_pi(adev);
457         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
458         u16 tdc_limit;
459
460         tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
461         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
462         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
463                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
464         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
465
466         return 0;
467 }
468
469 static int ci_populate_dw8(struct amdgpu_device *adev)
470 {
471         struct ci_power_info *pi = ci_get_pi(adev);
472         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
473         int ret;
474
475         ret = amdgpu_ci_read_smc_sram_dword(adev,
476                                      SMU7_FIRMWARE_HEADER_LOCATION +
477                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
478                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
479                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
480                                      pi->sram_end);
481         if (ret)
482                 return -EINVAL;
483         else
484                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
485
486         return 0;
487 }
488
489 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
490 {
491         struct ci_power_info *pi = ci_get_pi(adev);
492
493         if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
494             (adev->pm.dpm.fan.fan_output_sensitivity == 0))
495                 adev->pm.dpm.fan.fan_output_sensitivity =
496                         adev->pm.dpm.fan.default_fan_output_sensitivity;
497
498         pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
499                 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
500
501         return 0;
502 }
503
504 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
505 {
506         struct ci_power_info *pi = ci_get_pi(adev);
507         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
508         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
509         int i, min, max;
510
511         min = max = hi_vid[0];
512         for (i = 0; i < 8; i++) {
513                 if (0 != hi_vid[i]) {
514                         if (min > hi_vid[i])
515                                 min = hi_vid[i];
516                         if (max < hi_vid[i])
517                                 max = hi_vid[i];
518                 }
519
520                 if (0 != lo_vid[i]) {
521                         if (min > lo_vid[i])
522                                 min = lo_vid[i];
523                         if (max < lo_vid[i])
524                                 max = lo_vid[i];
525                 }
526         }
527
528         if ((min == 0) || (max == 0))
529                 return -EINVAL;
530         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
531         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
532
533         return 0;
534 }
535
536 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
537 {
538         struct ci_power_info *pi = ci_get_pi(adev);
539         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
540         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
541         struct amdgpu_cac_tdp_table *cac_tdp_table =
542                 adev->pm.dpm.dyn_state.cac_tdp_table;
543
544         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
545         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
546
547         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
548         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
549
550         return 0;
551 }
552
553 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
554 {
555         struct ci_power_info *pi = ci_get_pi(adev);
556         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
557         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
558         struct amdgpu_cac_tdp_table *cac_tdp_table =
559                 adev->pm.dpm.dyn_state.cac_tdp_table;
560         struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
561         int i, j, k;
562         const u16 *def1;
563         const u16 *def2;
564
565         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
566         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
567
568         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
569         dpm_table->GpuTjMax =
570                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
571         dpm_table->GpuTjHyst = 8;
572
573         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
574
575         if (ppm) {
576                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
577                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
578         } else {
579                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
580                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
581         }
582
583         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
584         def1 = pt_defaults->bapmti_r;
585         def2 = pt_defaults->bapmti_rc;
586
587         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
588                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
589                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
590                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
591                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
592                                 def1++;
593                                 def2++;
594                         }
595                 }
596         }
597
598         return 0;
599 }
600
601 static int ci_populate_pm_base(struct amdgpu_device *adev)
602 {
603         struct ci_power_info *pi = ci_get_pi(adev);
604         u32 pm_fuse_table_offset;
605         int ret;
606
607         if (pi->caps_power_containment) {
608                 ret = amdgpu_ci_read_smc_sram_dword(adev,
609                                              SMU7_FIRMWARE_HEADER_LOCATION +
610                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
611                                              &pm_fuse_table_offset, pi->sram_end);
612                 if (ret)
613                         return ret;
614                 ret = ci_populate_bapm_vddc_vid_sidd(adev);
615                 if (ret)
616                         return ret;
617                 ret = ci_populate_vddc_vid(adev);
618                 if (ret)
619                         return ret;
620                 ret = ci_populate_svi_load_line(adev);
621                 if (ret)
622                         return ret;
623                 ret = ci_populate_tdc_limit(adev);
624                 if (ret)
625                         return ret;
626                 ret = ci_populate_dw8(adev);
627                 if (ret)
628                         return ret;
629                 ret = ci_populate_fuzzy_fan(adev);
630                 if (ret)
631                         return ret;
632                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
633                 if (ret)
634                         return ret;
635                 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
636                 if (ret)
637                         return ret;
638                 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
639                                            (u8 *)&pi->smc_powertune_table,
640                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
641                 if (ret)
642                         return ret;
643         }
644
645         return 0;
646 }
647
648 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
649 {
650         struct ci_power_info *pi = ci_get_pi(adev);
651         u32 data;
652
653         if (pi->caps_sq_ramping) {
654                 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
655                 if (enable)
656                         data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
657                 else
658                         data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
659                 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
660         }
661
662         if (pi->caps_db_ramping) {
663                 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
664                 if (enable)
665                         data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
666                 else
667                         data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
668                 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
669         }
670
671         if (pi->caps_td_ramping) {
672                 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
673                 if (enable)
674                         data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
675                 else
676                         data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
677                 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
678         }
679
680         if (pi->caps_tcp_ramping) {
681                 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
682                 if (enable)
683                         data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
684                 else
685                         data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
686                 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
687         }
688 }
689
690 static int ci_program_pt_config_registers(struct amdgpu_device *adev,
691                                           const struct ci_pt_config_reg *cac_config_regs)
692 {
693         const struct ci_pt_config_reg *config_regs = cac_config_regs;
694         u32 data;
695         u32 cache = 0;
696
697         if (config_regs == NULL)
698                 return -EINVAL;
699
700         while (config_regs->offset != 0xFFFFFFFF) {
701                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
702                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
703                 } else {
704                         switch (config_regs->type) {
705                         case CISLANDS_CONFIGREG_SMC_IND:
706                                 data = RREG32_SMC(config_regs->offset);
707                                 break;
708                         case CISLANDS_CONFIGREG_DIDT_IND:
709                                 data = RREG32_DIDT(config_regs->offset);
710                                 break;
711                         default:
712                                 data = RREG32(config_regs->offset);
713                                 break;
714                         }
715
716                         data &= ~config_regs->mask;
717                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
718                         data |= cache;
719
720                         switch (config_regs->type) {
721                         case CISLANDS_CONFIGREG_SMC_IND:
722                                 WREG32_SMC(config_regs->offset, data);
723                                 break;
724                         case CISLANDS_CONFIGREG_DIDT_IND:
725                                 WREG32_DIDT(config_regs->offset, data);
726                                 break;
727                         default:
728                                 WREG32(config_regs->offset, data);
729                                 break;
730                         }
731                         cache = 0;
732                 }
733                 config_regs++;
734         }
735         return 0;
736 }
737
738 static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
739 {
740         struct ci_power_info *pi = ci_get_pi(adev);
741         int ret;
742
743         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
744             pi->caps_td_ramping || pi->caps_tcp_ramping) {
745                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
746
747                 if (enable) {
748                         ret = ci_program_pt_config_registers(adev, didt_config_ci);
749                         if (ret) {
750                                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
751                                 return ret;
752                         }
753                 }
754
755                 ci_do_enable_didt(adev, enable);
756
757                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
758         }
759
760         return 0;
761 }
762
763 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
764 {
765         struct ci_power_info *pi = ci_get_pi(adev);
766         PPSMC_Result smc_result;
767         int ret = 0;
768
769         if (enable) {
770                 pi->power_containment_features = 0;
771                 if (pi->caps_power_containment) {
772                         if (pi->enable_bapm_feature) {
773                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
774                                 if (smc_result != PPSMC_Result_OK)
775                                         ret = -EINVAL;
776                                 else
777                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
778                         }
779
780                         if (pi->enable_tdc_limit_feature) {
781                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
782                                 if (smc_result != PPSMC_Result_OK)
783                                         ret = -EINVAL;
784                                 else
785                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
786                         }
787
788                         if (pi->enable_pkg_pwr_tracking_feature) {
789                                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
790                                 if (smc_result != PPSMC_Result_OK) {
791                                         ret = -EINVAL;
792                                 } else {
793                                         struct amdgpu_cac_tdp_table *cac_tdp_table =
794                                                 adev->pm.dpm.dyn_state.cac_tdp_table;
795                                         u32 default_pwr_limit =
796                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
797
798                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
799
800                                         ci_set_power_limit(adev, default_pwr_limit);
801                                 }
802                         }
803                 }
804         } else {
805                 if (pi->caps_power_containment && pi->power_containment_features) {
806                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
807                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
808
809                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
810                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
811
812                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
813                                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
814                         pi->power_containment_features = 0;
815                 }
816         }
817
818         return ret;
819 }
820
821 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
822 {
823         struct ci_power_info *pi = ci_get_pi(adev);
824         PPSMC_Result smc_result;
825         int ret = 0;
826
827         if (pi->caps_cac) {
828                 if (enable) {
829                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
830                         if (smc_result != PPSMC_Result_OK) {
831                                 ret = -EINVAL;
832                                 pi->cac_enabled = false;
833                         } else {
834                                 pi->cac_enabled = true;
835                         }
836                 } else if (pi->cac_enabled) {
837                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
838                         pi->cac_enabled = false;
839                 }
840         }
841
842         return ret;
843 }
844
845 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
846                                             bool enable)
847 {
848         struct ci_power_info *pi = ci_get_pi(adev);
849         PPSMC_Result smc_result = PPSMC_Result_OK;
850
851         if (pi->thermal_sclk_dpm_enabled) {
852                 if (enable)
853                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
854                 else
855                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
856         }
857
858         if (smc_result == PPSMC_Result_OK)
859                 return 0;
860         else
861                 return -EINVAL;
862 }
863
864 static int ci_power_control_set_level(struct amdgpu_device *adev)
865 {
866         struct ci_power_info *pi = ci_get_pi(adev);
867         struct amdgpu_cac_tdp_table *cac_tdp_table =
868                 adev->pm.dpm.dyn_state.cac_tdp_table;
869         s32 adjust_percent;
870         s32 target_tdp;
871         int ret = 0;
872         bool adjust_polarity = false; /* ??? */
873
874         if (pi->caps_power_containment) {
875                 adjust_percent = adjust_polarity ?
876                         adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
877                 target_tdp = ((100 + adjust_percent) *
878                               (s32)cac_tdp_table->configurable_tdp) / 100;
879
880                 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
881         }
882
883         return ret;
884 }
885
886 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
887 {
888         struct ci_power_info *pi = ci_get_pi(adev);
889
890         pi->uvd_power_gated = gate;
891
892         if (gate) {
893                 /* stop the UVD block */
894                 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
895                                                         AMD_PG_STATE_GATE);
896                 ci_update_uvd_dpm(adev, gate);
897         } else {
898                 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
899                                                         AMD_PG_STATE_UNGATE);
900                 ci_update_uvd_dpm(adev, gate);
901         }
902 }
903
904 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
905 {
906         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
907         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
908
909         if (vblank_time < switch_limit)
910                 return true;
911         else
912                 return false;
913
914 }
915
916 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
917                                         struct amdgpu_ps *rps)
918 {
919         struct ci_ps *ps = ci_get_ps(rps);
920         struct ci_power_info *pi = ci_get_pi(adev);
921         struct amdgpu_clock_and_voltage_limits *max_limits;
922         bool disable_mclk_switching;
923         u32 sclk, mclk;
924         int i;
925
926         if (rps->vce_active) {
927                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
928                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
929         } else {
930                 rps->evclk = 0;
931                 rps->ecclk = 0;
932         }
933
934         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
935             ci_dpm_vblank_too_short(adev))
936                 disable_mclk_switching = true;
937         else
938                 disable_mclk_switching = false;
939
940         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
941                 pi->battery_state = true;
942         else
943                 pi->battery_state = false;
944
945         if (adev->pm.dpm.ac_power)
946                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
947         else
948                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
949
950         if (adev->pm.dpm.ac_power == false) {
951                 for (i = 0; i < ps->performance_level_count; i++) {
952                         if (ps->performance_levels[i].mclk > max_limits->mclk)
953                                 ps->performance_levels[i].mclk = max_limits->mclk;
954                         if (ps->performance_levels[i].sclk > max_limits->sclk)
955                                 ps->performance_levels[i].sclk = max_limits->sclk;
956                 }
957         }
958
959         /* XXX validate the min clocks required for display */
960
961         if (disable_mclk_switching) {
962                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
963                 sclk = ps->performance_levels[0].sclk;
964         } else {
965                 mclk = ps->performance_levels[0].mclk;
966                 sclk = ps->performance_levels[0].sclk;
967         }
968
969         if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
970                 sclk = adev->pm.pm_display_cfg.min_core_set_clock;
971
972         if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
973                 mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
974
975         if (rps->vce_active) {
976                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
977                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
978                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
979                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
980         }
981
982         ps->performance_levels[0].sclk = sclk;
983         ps->performance_levels[0].mclk = mclk;
984
985         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
986                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
987
988         if (disable_mclk_switching) {
989                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
990                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
991         } else {
992                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
993                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
994         }
995 }
996
997 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
998                                             int min_temp, int max_temp)
999 {
1000         int low_temp = 0 * 1000;
1001         int high_temp = 255 * 1000;
1002         u32 tmp;
1003
1004         if (low_temp < min_temp)
1005                 low_temp = min_temp;
1006         if (high_temp > max_temp)
1007                 high_temp = max_temp;
1008         if (high_temp < low_temp) {
1009                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1010                 return -EINVAL;
1011         }
1012
1013         tmp = RREG32_SMC(ixCG_THERMAL_INT);
1014         tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
1015         tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
1016                 ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
1017         WREG32_SMC(ixCG_THERMAL_INT, tmp);
1018
1019 #if 0
1020         /* XXX: need to figure out how to handle this properly */
1021         tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1022         tmp &= DIG_THERM_DPM_MASK;
1023         tmp |= DIG_THERM_DPM(high_temp / 1000);
1024         WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1025 #endif
1026
1027         adev->pm.dpm.thermal.min_temp = low_temp;
1028         adev->pm.dpm.thermal.max_temp = high_temp;
1029         return 0;
1030 }
1031
1032 static int ci_thermal_enable_alert(struct amdgpu_device *adev,
1033                                    bool enable)
1034 {
1035         u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
1036         PPSMC_Result result;
1037
1038         if (enable) {
1039                 thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1040                                  CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
1041                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1042                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
1043                 if (result != PPSMC_Result_OK) {
1044                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1045                         return -EINVAL;
1046                 }
1047         } else {
1048                 thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
1049                         CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
1050                 WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
1051                 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
1052                 if (result != PPSMC_Result_OK) {
1053                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
1054                         return -EINVAL;
1055                 }
1056         }
1057
1058         return 0;
1059 }
1060
1061 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
1062 {
1063         struct ci_power_info *pi = ci_get_pi(adev);
1064         u32 tmp;
1065
1066         if (pi->fan_ctrl_is_in_default_mode) {
1067                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
1068                         >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1069                 pi->fan_ctrl_default_mode = tmp;
1070                 tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
1071                         >> CG_FDO_CTRL2__TMIN__SHIFT;
1072                 pi->t_min = tmp;
1073                 pi->fan_ctrl_is_in_default_mode = false;
1074         }
1075
1076         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1077         tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
1078         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1079
1080         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1081         tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1082         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1083 }
1084
1085 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
1086 {
1087         struct ci_power_info *pi = ci_get_pi(adev);
1088         SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
1089         u32 duty100;
1090         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
1091         u16 fdo_min, slope1, slope2;
1092         u32 reference_clock, tmp;
1093         int ret;
1094         u64 tmp64;
1095
1096         if (!pi->fan_table_start) {
1097                 adev->pm.dpm.fan.ucode_fan_control = false;
1098                 return 0;
1099         }
1100
1101         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1102                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1103
1104         if (duty100 == 0) {
1105                 adev->pm.dpm.fan.ucode_fan_control = false;
1106                 return 0;
1107         }
1108
1109         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
1110         do_div(tmp64, 10000);
1111         fdo_min = (u16)tmp64;
1112
1113         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
1114         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
1115
1116         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
1117         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
1118
1119         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
1120         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
1121
1122         fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
1123         fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
1124         fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
1125
1126         fan_table.Slope1 = cpu_to_be16(slope1);
1127         fan_table.Slope2 = cpu_to_be16(slope2);
1128
1129         fan_table.FdoMin = cpu_to_be16(fdo_min);
1130
1131         fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
1132
1133         fan_table.HystUp = cpu_to_be16(1);
1134
1135         fan_table.HystSlope = cpu_to_be16(1);
1136
1137         fan_table.TempRespLim = cpu_to_be16(5);
1138
1139         reference_clock = amdgpu_asic_get_xclk(adev);
1140
1141         fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
1142                                                reference_clock) / 1600);
1143
1144         fan_table.FdoMax = cpu_to_be16((u16)duty100);
1145
1146         tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
1147                 >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
1148         fan_table.TempSrc = (uint8_t)tmp;
1149
1150         ret = amdgpu_ci_copy_bytes_to_smc(adev,
1151                                           pi->fan_table_start,
1152                                           (u8 *)(&fan_table),
1153                                           sizeof(fan_table),
1154                                           pi->sram_end);
1155
1156         if (ret) {
1157                 DRM_ERROR("Failed to load fan table to the SMC.");
1158                 adev->pm.dpm.fan.ucode_fan_control = false;
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
1165 {
1166         struct ci_power_info *pi = ci_get_pi(adev);
1167         PPSMC_Result ret;
1168
1169         if (pi->caps_od_fuzzy_fan_control_support) {
1170                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1171                                                                PPSMC_StartFanControl,
1172                                                                FAN_CONTROL_FUZZY);
1173                 if (ret != PPSMC_Result_OK)
1174                         return -EINVAL;
1175                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1176                                                                PPSMC_MSG_SetFanPwmMax,
1177                                                                adev->pm.dpm.fan.default_max_fan_pwm);
1178                 if (ret != PPSMC_Result_OK)
1179                         return -EINVAL;
1180         } else {
1181                 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
1182                                                                PPSMC_StartFanControl,
1183                                                                FAN_CONTROL_TABLE);
1184                 if (ret != PPSMC_Result_OK)
1185                         return -EINVAL;
1186         }
1187
1188         pi->fan_is_controlled_by_smc = true;
1189         return 0;
1190 }
1191
1192
1193 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
1194 {
1195         PPSMC_Result ret;
1196         struct ci_power_info *pi = ci_get_pi(adev);
1197
1198         ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
1199         if (ret == PPSMC_Result_OK) {
1200                 pi->fan_is_controlled_by_smc = false;
1201                 return 0;
1202         } else {
1203                 return -EINVAL;
1204         }
1205 }
1206
1207 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
1208                                         u32 *speed)
1209 {
1210         u32 duty, duty100;
1211         u64 tmp64;
1212
1213         if (adev->pm.no_fan)
1214                 return -ENOENT;
1215
1216         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1217                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1218         duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
1219                 >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
1220
1221         if (duty100 == 0)
1222                 return -EINVAL;
1223
1224         tmp64 = (u64)duty * 100;
1225         do_div(tmp64, duty100);
1226         *speed = (u32)tmp64;
1227
1228         if (*speed > 100)
1229                 *speed = 100;
1230
1231         return 0;
1232 }
1233
1234 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
1235                                         u32 speed)
1236 {
1237         u32 tmp;
1238         u32 duty, duty100;
1239         u64 tmp64;
1240         struct ci_power_info *pi = ci_get_pi(adev);
1241
1242         if (adev->pm.no_fan)
1243                 return -ENOENT;
1244
1245         if (pi->fan_is_controlled_by_smc)
1246                 return -EINVAL;
1247
1248         if (speed > 100)
1249                 return -EINVAL;
1250
1251         duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
1252                 >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
1253
1254         if (duty100 == 0)
1255                 return -EINVAL;
1256
1257         tmp64 = (u64)speed * duty100;
1258         do_div(tmp64, 100);
1259         duty = (u32)tmp64;
1260
1261         tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
1262         tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
1263         WREG32_SMC(ixCG_FDO_CTRL0, tmp);
1264
1265         return 0;
1266 }
1267
1268 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
1269 {
1270         if (mode) {
1271                 /* stop auto-manage */
1272                 if (adev->pm.dpm.fan.ucode_fan_control)
1273                         ci_fan_ctrl_stop_smc_fan_control(adev);
1274                 ci_fan_ctrl_set_static_mode(adev, mode);
1275         } else {
1276                 /* restart auto-manage */
1277                 if (adev->pm.dpm.fan.ucode_fan_control)
1278                         ci_thermal_start_smc_fan_control(adev);
1279                 else
1280                         ci_fan_ctrl_set_default_mode(adev);
1281         }
1282 }
1283
1284 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
1285 {
1286         struct ci_power_info *pi = ci_get_pi(adev);
1287         u32 tmp;
1288
1289         if (pi->fan_is_controlled_by_smc)
1290                 return 0;
1291
1292         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1293         return (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
1294 }
1295
1296 #if 0
1297 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1298                                          u32 *speed)
1299 {
1300         u32 tach_period;
1301         u32 xclk = amdgpu_asic_get_xclk(adev);
1302
1303         if (adev->pm.no_fan)
1304                 return -ENOENT;
1305
1306         if (adev->pm.fan_pulses_per_revolution == 0)
1307                 return -ENOENT;
1308
1309         tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
1310                 >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
1311         if (tach_period == 0)
1312                 return -ENOENT;
1313
1314         *speed = 60 * xclk * 10000 / tach_period;
1315
1316         return 0;
1317 }
1318
1319 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1320                                          u32 speed)
1321 {
1322         u32 tach_period, tmp;
1323         u32 xclk = amdgpu_asic_get_xclk(adev);
1324
1325         if (adev->pm.no_fan)
1326                 return -ENOENT;
1327
1328         if (adev->pm.fan_pulses_per_revolution == 0)
1329                 return -ENOENT;
1330
1331         if ((speed < adev->pm.fan_min_rpm) ||
1332             (speed > adev->pm.fan_max_rpm))
1333                 return -EINVAL;
1334
1335         if (adev->pm.dpm.fan.ucode_fan_control)
1336                 ci_fan_ctrl_stop_smc_fan_control(adev);
1337
1338         tach_period = 60 * xclk * 10000 / (8 * speed);
1339         tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
1340         tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
1341         WREG32_SMC(CG_TACH_CTRL, tmp);
1342
1343         ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1344
1345         return 0;
1346 }
1347 #endif
1348
1349 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
1350 {
1351         struct ci_power_info *pi = ci_get_pi(adev);
1352         u32 tmp;
1353
1354         if (!pi->fan_ctrl_is_in_default_mode) {
1355                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
1356                 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
1357                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1358
1359                 tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
1360                 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
1361                 WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1362                 pi->fan_ctrl_is_in_default_mode = true;
1363         }
1364 }
1365
1366 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
1367 {
1368         if (adev->pm.dpm.fan.ucode_fan_control) {
1369                 ci_fan_ctrl_start_smc_fan_control(adev);
1370                 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
1371         }
1372 }
1373
1374 static void ci_thermal_initialize(struct amdgpu_device *adev)
1375 {
1376         u32 tmp;
1377
1378         if (adev->pm.fan_pulses_per_revolution) {
1379                 tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
1380                 tmp |= (adev->pm.fan_pulses_per_revolution - 1)
1381                         << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
1382                 WREG32_SMC(ixCG_TACH_CTRL, tmp);
1383         }
1384
1385         tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
1386         tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
1387         WREG32_SMC(ixCG_FDO_CTRL2, tmp);
1388 }
1389
1390 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
1391 {
1392         int ret;
1393
1394         ci_thermal_initialize(adev);
1395         ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
1396         if (ret)
1397                 return ret;
1398         ret = ci_thermal_enable_alert(adev, true);
1399         if (ret)
1400                 return ret;
1401         if (adev->pm.dpm.fan.ucode_fan_control) {
1402                 ret = ci_thermal_setup_fan_table(adev);
1403                 if (ret)
1404                         return ret;
1405                 ci_thermal_start_smc_fan_control(adev);
1406         }
1407
1408         return 0;
1409 }
1410
1411 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
1412 {
1413         if (!adev->pm.no_fan)
1414                 ci_fan_ctrl_set_default_mode(adev);
1415 }
1416
1417 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1418                                      u16 reg_offset, u32 *value)
1419 {
1420         struct ci_power_info *pi = ci_get_pi(adev);
1421
1422         return amdgpu_ci_read_smc_sram_dword(adev,
1423                                       pi->soft_regs_start + reg_offset,
1424                                       value, pi->sram_end);
1425 }
1426
1427 static int ci_write_smc_soft_register(struct amdgpu_device *adev,
1428                                       u16 reg_offset, u32 value)
1429 {
1430         struct ci_power_info *pi = ci_get_pi(adev);
1431
1432         return amdgpu_ci_write_smc_sram_dword(adev,
1433                                        pi->soft_regs_start + reg_offset,
1434                                        value, pi->sram_end);
1435 }
1436
1437 static void ci_init_fps_limits(struct amdgpu_device *adev)
1438 {
1439         struct ci_power_info *pi = ci_get_pi(adev);
1440         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1441
1442         if (pi->caps_fps) {
1443                 u16 tmp;
1444
1445                 tmp = 45;
1446                 table->FpsHighT = cpu_to_be16(tmp);
1447
1448                 tmp = 30;
1449                 table->FpsLowT = cpu_to_be16(tmp);
1450         }
1451 }
1452
1453 static int ci_update_sclk_t(struct amdgpu_device *adev)
1454 {
1455         struct ci_power_info *pi = ci_get_pi(adev);
1456         int ret = 0;
1457         u32 low_sclk_interrupt_t = 0;
1458
1459         if (pi->caps_sclk_throttle_low_notification) {
1460                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1461
1462                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
1463                                            pi->dpm_table_start +
1464                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1465                                            (u8 *)&low_sclk_interrupt_t,
1466                                            sizeof(u32), pi->sram_end);
1467
1468         }
1469
1470         return ret;
1471 }
1472
1473 static void ci_get_leakage_voltages(struct amdgpu_device *adev)
1474 {
1475         struct ci_power_info *pi = ci_get_pi(adev);
1476         u16 leakage_id, virtual_voltage_id;
1477         u16 vddc, vddci;
1478         int i;
1479
1480         pi->vddc_leakage.count = 0;
1481         pi->vddci_leakage.count = 0;
1482
1483         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1484                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1485                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1486                         if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
1487                                 continue;
1488                         if (vddc != 0 && vddc != virtual_voltage_id) {
1489                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1490                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1491                                 pi->vddc_leakage.count++;
1492                         }
1493                 }
1494         } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
1495                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1496                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1497                         if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
1498                                                                                      virtual_voltage_id,
1499                                                                                      leakage_id) == 0) {
1500                                 if (vddc != 0 && vddc != virtual_voltage_id) {
1501                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1502                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1503                                         pi->vddc_leakage.count++;
1504                                 }
1505                                 if (vddci != 0 && vddci != virtual_voltage_id) {
1506                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1507                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1508                                         pi->vddci_leakage.count++;
1509                                 }
1510                         }
1511                 }
1512         }
1513 }
1514
1515 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
1516 {
1517         struct ci_power_info *pi = ci_get_pi(adev);
1518         bool want_thermal_protection;
1519         enum amdgpu_dpm_event_src dpm_event_src;
1520         u32 tmp;
1521
1522         switch (sources) {
1523         case 0:
1524         default:
1525                 want_thermal_protection = false;
1526                 break;
1527         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
1528                 want_thermal_protection = true;
1529                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
1530                 break;
1531         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1532                 want_thermal_protection = true;
1533                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
1534                 break;
1535         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1536               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1537                 want_thermal_protection = true;
1538                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1539                 break;
1540         }
1541
1542         if (want_thermal_protection) {
1543 #if 0
1544                 /* XXX: need to figure out how to handle this properly */
1545                 tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
1546                 tmp &= DPM_EVENT_SRC_MASK;
1547                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1548                 WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
1549 #endif
1550
1551                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1552                 if (pi->thermal_protection)
1553                         tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1554                 else
1555                         tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1556                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1557         } else {
1558                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1559                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
1560                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1561         }
1562 }
1563
1564 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
1565                                            enum amdgpu_dpm_auto_throttle_src source,
1566                                            bool enable)
1567 {
1568         struct ci_power_info *pi = ci_get_pi(adev);
1569
1570         if (enable) {
1571                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1572                         pi->active_auto_throttle_sources |= 1 << source;
1573                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1574                 }
1575         } else {
1576                 if (pi->active_auto_throttle_sources & (1 << source)) {
1577                         pi->active_auto_throttle_sources &= ~(1 << source);
1578                         ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
1579                 }
1580         }
1581 }
1582
1583 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
1584 {
1585         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1586                 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1587 }
1588
1589 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1590 {
1591         struct ci_power_info *pi = ci_get_pi(adev);
1592         PPSMC_Result smc_result;
1593
1594         if (!pi->need_update_smu7_dpm_table)
1595                 return 0;
1596
1597         if ((!pi->sclk_dpm_key_disabled) &&
1598             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1599                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1600                 if (smc_result != PPSMC_Result_OK)
1601                         return -EINVAL;
1602         }
1603
1604         if ((!pi->mclk_dpm_key_disabled) &&
1605             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1606                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1607                 if (smc_result != PPSMC_Result_OK)
1608                         return -EINVAL;
1609         }
1610
1611         pi->need_update_smu7_dpm_table = 0;
1612         return 0;
1613 }
1614
1615 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
1616 {
1617         struct ci_power_info *pi = ci_get_pi(adev);
1618         PPSMC_Result smc_result;
1619
1620         if (enable) {
1621                 if (!pi->sclk_dpm_key_disabled) {
1622                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
1623                         if (smc_result != PPSMC_Result_OK)
1624                                 return -EINVAL;
1625                 }
1626
1627                 if (!pi->mclk_dpm_key_disabled) {
1628                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
1629                         if (smc_result != PPSMC_Result_OK)
1630                                 return -EINVAL;
1631
1632                         WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
1633                                         ~MC_SEQ_CNTL_3__CAC_EN_MASK);
1634
1635                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
1636                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
1637                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
1638
1639                         udelay(10);
1640
1641                         WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
1642                         WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
1643                         WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
1644                 }
1645         } else {
1646                 if (!pi->sclk_dpm_key_disabled) {
1647                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
1648                         if (smc_result != PPSMC_Result_OK)
1649                                 return -EINVAL;
1650                 }
1651
1652                 if (!pi->mclk_dpm_key_disabled) {
1653                         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
1654                         if (smc_result != PPSMC_Result_OK)
1655                                 return -EINVAL;
1656                 }
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int ci_start_dpm(struct amdgpu_device *adev)
1663 {
1664         struct ci_power_info *pi = ci_get_pi(adev);
1665         PPSMC_Result smc_result;
1666         int ret;
1667         u32 tmp;
1668
1669         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1670         tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1671         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1672
1673         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1674         tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1675         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1676
1677         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1678
1679         WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
1680
1681         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
1682         if (smc_result != PPSMC_Result_OK)
1683                 return -EINVAL;
1684
1685         ret = ci_enable_sclk_mclk_dpm(adev, true);
1686         if (ret)
1687                 return ret;
1688
1689         if (!pi->pcie_dpm_key_disabled) {
1690                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
1691                 if (smc_result != PPSMC_Result_OK)
1692                         return -EINVAL;
1693         }
1694
1695         return 0;
1696 }
1697
1698 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
1699 {
1700         struct ci_power_info *pi = ci_get_pi(adev);
1701         PPSMC_Result smc_result;
1702
1703         if (!pi->need_update_smu7_dpm_table)
1704                 return 0;
1705
1706         if ((!pi->sclk_dpm_key_disabled) &&
1707             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1708                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1709                 if (smc_result != PPSMC_Result_OK)
1710                         return -EINVAL;
1711         }
1712
1713         if ((!pi->mclk_dpm_key_disabled) &&
1714             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1715                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1716                 if (smc_result != PPSMC_Result_OK)
1717                         return -EINVAL;
1718         }
1719
1720         return 0;
1721 }
1722
1723 static int ci_stop_dpm(struct amdgpu_device *adev)
1724 {
1725         struct ci_power_info *pi = ci_get_pi(adev);
1726         PPSMC_Result smc_result;
1727         int ret;
1728         u32 tmp;
1729
1730         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
1731         tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
1732         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
1733
1734         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1735         tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
1736         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1737
1738         if (!pi->pcie_dpm_key_disabled) {
1739                 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
1740                 if (smc_result != PPSMC_Result_OK)
1741                         return -EINVAL;
1742         }
1743
1744         ret = ci_enable_sclk_mclk_dpm(adev, false);
1745         if (ret)
1746                 return ret;
1747
1748         smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
1749         if (smc_result != PPSMC_Result_OK)
1750                 return -EINVAL;
1751
1752         return 0;
1753 }
1754
1755 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
1756 {
1757         u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
1758
1759         if (enable)
1760                 tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1761         else
1762                 tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
1763         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
1764 }
1765
1766 #if 0
1767 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1768                                         bool ac_power)
1769 {
1770         struct ci_power_info *pi = ci_get_pi(adev);
1771         struct amdgpu_cac_tdp_table *cac_tdp_table =
1772                 adev->pm.dpm.dyn_state.cac_tdp_table;
1773         u32 power_limit;
1774
1775         if (ac_power)
1776                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1777         else
1778                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1779
1780         ci_set_power_limit(adev, power_limit);
1781
1782         if (pi->caps_automatic_dc_transition) {
1783                 if (ac_power)
1784                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1785                 else
1786                         amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1787         }
1788
1789         return 0;
1790 }
1791 #endif
1792
1793 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
1794                                                       PPSMC_Msg msg, u32 parameter)
1795 {
1796         WREG32(mmSMC_MSG_ARG_0, parameter);
1797         return amdgpu_ci_send_msg_to_smc(adev, msg);
1798 }
1799
1800 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
1801                                                         PPSMC_Msg msg, u32 *parameter)
1802 {
1803         PPSMC_Result smc_result;
1804
1805         smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
1806
1807         if ((smc_result == PPSMC_Result_OK) && parameter)
1808                 *parameter = RREG32(mmSMC_MSG_ARG_0);
1809
1810         return smc_result;
1811 }
1812
1813 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
1814 {
1815         struct ci_power_info *pi = ci_get_pi(adev);
1816
1817         if (!pi->sclk_dpm_key_disabled) {
1818                 PPSMC_Result smc_result =
1819                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1820                 if (smc_result != PPSMC_Result_OK)
1821                         return -EINVAL;
1822         }
1823
1824         return 0;
1825 }
1826
1827 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
1828 {
1829         struct ci_power_info *pi = ci_get_pi(adev);
1830
1831         if (!pi->mclk_dpm_key_disabled) {
1832                 PPSMC_Result smc_result =
1833                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1834                 if (smc_result != PPSMC_Result_OK)
1835                         return -EINVAL;
1836         }
1837
1838         return 0;
1839 }
1840
1841 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
1842 {
1843         struct ci_power_info *pi = ci_get_pi(adev);
1844
1845         if (!pi->pcie_dpm_key_disabled) {
1846                 PPSMC_Result smc_result =
1847                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1848                 if (smc_result != PPSMC_Result_OK)
1849                         return -EINVAL;
1850         }
1851
1852         return 0;
1853 }
1854
1855 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
1856 {
1857         struct ci_power_info *pi = ci_get_pi(adev);
1858
1859         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1860                 PPSMC_Result smc_result =
1861                         amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
1862                 if (smc_result != PPSMC_Result_OK)
1863                         return -EINVAL;
1864         }
1865
1866         return 0;
1867 }
1868
1869 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
1870                                        u32 target_tdp)
1871 {
1872         PPSMC_Result smc_result =
1873                 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1874         if (smc_result != PPSMC_Result_OK)
1875                 return -EINVAL;
1876         return 0;
1877 }
1878
1879 #if 0
1880 static int ci_set_boot_state(struct amdgpu_device *adev)
1881 {
1882         return ci_enable_sclk_mclk_dpm(adev, false);
1883 }
1884 #endif
1885
1886 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
1887 {
1888         u32 sclk_freq;
1889         PPSMC_Result smc_result =
1890                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1891                                                     PPSMC_MSG_API_GetSclkFrequency,
1892                                                     &sclk_freq);
1893         if (smc_result != PPSMC_Result_OK)
1894                 sclk_freq = 0;
1895
1896         return sclk_freq;
1897 }
1898
1899 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
1900 {
1901         u32 mclk_freq;
1902         PPSMC_Result smc_result =
1903                 amdgpu_ci_send_msg_to_smc_return_parameter(adev,
1904                                                     PPSMC_MSG_API_GetMclkFrequency,
1905                                                     &mclk_freq);
1906         if (smc_result != PPSMC_Result_OK)
1907                 mclk_freq = 0;
1908
1909         return mclk_freq;
1910 }
1911
1912 static void ci_dpm_start_smc(struct amdgpu_device *adev)
1913 {
1914         int i;
1915
1916         amdgpu_ci_program_jump_on_start(adev);
1917         amdgpu_ci_start_smc_clock(adev);
1918         amdgpu_ci_start_smc(adev);
1919         for (i = 0; i < adev->usec_timeout; i++) {
1920                 if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
1921                         break;
1922         }
1923 }
1924
1925 static void ci_dpm_stop_smc(struct amdgpu_device *adev)
1926 {
1927         amdgpu_ci_reset_smc(adev);
1928         amdgpu_ci_stop_smc_clock(adev);
1929 }
1930
1931 static int ci_process_firmware_header(struct amdgpu_device *adev)
1932 {
1933         struct ci_power_info *pi = ci_get_pi(adev);
1934         u32 tmp;
1935         int ret;
1936
1937         ret = amdgpu_ci_read_smc_sram_dword(adev,
1938                                      SMU7_FIRMWARE_HEADER_LOCATION +
1939                                      offsetof(SMU7_Firmware_Header, DpmTable),
1940                                      &tmp, pi->sram_end);
1941         if (ret)
1942                 return ret;
1943
1944         pi->dpm_table_start = tmp;
1945
1946         ret = amdgpu_ci_read_smc_sram_dword(adev,
1947                                      SMU7_FIRMWARE_HEADER_LOCATION +
1948                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1949                                      &tmp, pi->sram_end);
1950         if (ret)
1951                 return ret;
1952
1953         pi->soft_regs_start = tmp;
1954
1955         ret = amdgpu_ci_read_smc_sram_dword(adev,
1956                                      SMU7_FIRMWARE_HEADER_LOCATION +
1957                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1958                                      &tmp, pi->sram_end);
1959         if (ret)
1960                 return ret;
1961
1962         pi->mc_reg_table_start = tmp;
1963
1964         ret = amdgpu_ci_read_smc_sram_dword(adev,
1965                                      SMU7_FIRMWARE_HEADER_LOCATION +
1966                                      offsetof(SMU7_Firmware_Header, FanTable),
1967                                      &tmp, pi->sram_end);
1968         if (ret)
1969                 return ret;
1970
1971         pi->fan_table_start = tmp;
1972
1973         ret = amdgpu_ci_read_smc_sram_dword(adev,
1974                                      SMU7_FIRMWARE_HEADER_LOCATION +
1975                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1976                                      &tmp, pi->sram_end);
1977         if (ret)
1978                 return ret;
1979
1980         pi->arb_table_start = tmp;
1981
1982         return 0;
1983 }
1984
1985 static void ci_read_clock_registers(struct amdgpu_device *adev)
1986 {
1987         struct ci_power_info *pi = ci_get_pi(adev);
1988
1989         pi->clock_registers.cg_spll_func_cntl =
1990                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
1991         pi->clock_registers.cg_spll_func_cntl_2 =
1992                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
1993         pi->clock_registers.cg_spll_func_cntl_3 =
1994                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
1995         pi->clock_registers.cg_spll_func_cntl_4 =
1996                 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
1997         pi->clock_registers.cg_spll_spread_spectrum =
1998                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
1999         pi->clock_registers.cg_spll_spread_spectrum_2 =
2000                 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
2001         pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
2002         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
2003         pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
2004         pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
2005         pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
2006         pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
2007         pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
2008         pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
2009         pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
2010 }
2011
2012 static void ci_init_sclk_t(struct amdgpu_device *adev)
2013 {
2014         struct ci_power_info *pi = ci_get_pi(adev);
2015
2016         pi->low_sclk_interrupt_t = 0;
2017 }
2018
2019 static void ci_enable_thermal_protection(struct amdgpu_device *adev,
2020                                          bool enable)
2021 {
2022         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2023
2024         if (enable)
2025                 tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2026         else
2027                 tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
2028         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2029 }
2030
2031 static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
2032 {
2033         u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2034
2035         tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
2036
2037         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2038 }
2039
2040 #if 0
2041 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2042 {
2043
2044         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2045
2046         udelay(25000);
2047
2048         return 0;
2049 }
2050
2051 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2052 {
2053         int i;
2054
2055         WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
2056
2057         udelay(7000);
2058
2059         for (i = 0; i < adev->usec_timeout; i++) {
2060                 if (RREG32(mmSMC_RESP_0) == 1)
2061                         break;
2062                 udelay(1000);
2063         }
2064
2065         return 0;
2066 }
2067 #endif
2068
2069 static int ci_notify_smc_display_change(struct amdgpu_device *adev,
2070                                         bool has_display)
2071 {
2072         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
2073
2074         return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
2075 }
2076
2077 static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
2078                                       bool enable)
2079 {
2080         struct ci_power_info *pi = ci_get_pi(adev);
2081
2082         if (enable) {
2083                 if (pi->caps_sclk_ds) {
2084                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
2085                                 return -EINVAL;
2086                 } else {
2087                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2088                                 return -EINVAL;
2089                 }
2090         } else {
2091                 if (pi->caps_sclk_ds) {
2092                         if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
2093                                 return -EINVAL;
2094                 }
2095         }
2096
2097         return 0;
2098 }
2099
2100 static void ci_program_display_gap(struct amdgpu_device *adev)
2101 {
2102         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2103         u32 pre_vbi_time_in_us;
2104         u32 frame_time_in_us;
2105         u32 ref_clock = adev->clock.spll.reference_freq;
2106         u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
2107         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
2108
2109         tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
2110         if (adev->pm.dpm.new_active_crtc_count > 0)
2111                 tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2112         else
2113                 tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
2114         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2115
2116         if (refresh_rate == 0)
2117                 refresh_rate = 60;
2118         if (vblank_time == 0xffffffff)
2119                 vblank_time = 500;
2120         frame_time_in_us = 1000000 / refresh_rate;
2121         pre_vbi_time_in_us =
2122                 frame_time_in_us - 200 - vblank_time;
2123         tmp = pre_vbi_time_in_us * (ref_clock / 100);
2124
2125         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
2126         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2127         ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2128
2129
2130         ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
2131
2132 }
2133
2134 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
2135 {
2136         struct ci_power_info *pi = ci_get_pi(adev);
2137         u32 tmp;
2138
2139         if (enable) {
2140                 if (pi->caps_sclk_ss_support) {
2141                         tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2142                         tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2143                         WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2144                 }
2145         } else {
2146                 tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
2147                 tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
2148                 WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
2149
2150                 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
2151                 tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
2152                 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
2153         }
2154 }
2155
2156 static void ci_program_sstp(struct amdgpu_device *adev)
2157 {
2158         WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
2159         ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
2160          (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
2161 }
2162
2163 static void ci_enable_display_gap(struct amdgpu_device *adev)
2164 {
2165         u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
2166
2167         tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
2168                         CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
2169         tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
2170                 (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
2171
2172         WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
2173 }
2174
2175 static void ci_program_vc(struct amdgpu_device *adev)
2176 {
2177         u32 tmp;
2178
2179         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2180         tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2181         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2182
2183         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
2184         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
2185         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
2186         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
2187         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
2188         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
2189         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
2190         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
2191 }
2192
2193 static void ci_clear_vc(struct amdgpu_device *adev)
2194 {
2195         u32 tmp;
2196
2197         tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2198         tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
2199         WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
2200
2201         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
2202         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
2203         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
2204         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
2205         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
2206         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
2207         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
2208         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
2209 }
2210
2211 static int ci_upload_firmware(struct amdgpu_device *adev)
2212 {
2213         int i, ret;
2214
2215         if (amdgpu_ci_is_smc_running(adev)) {
2216                 DRM_INFO("smc is running, no need to load smc firmware\n");
2217                 return 0;
2218         }
2219
2220         for (i = 0; i < adev->usec_timeout; i++) {
2221                 if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
2222                         break;
2223         }
2224         WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
2225
2226         amdgpu_ci_stop_smc_clock(adev);
2227         amdgpu_ci_reset_smc(adev);
2228
2229         ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
2230
2231         return ret;
2232
2233 }
2234
2235 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
2236                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
2237                                      struct atom_voltage_table *voltage_table)
2238 {
2239         u32 i;
2240
2241         if (voltage_dependency_table == NULL)
2242                 return -EINVAL;
2243
2244         voltage_table->mask_low = 0;
2245         voltage_table->phase_delay = 0;
2246
2247         voltage_table->count = voltage_dependency_table->count;
2248         for (i = 0; i < voltage_table->count; i++) {
2249                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2250                 voltage_table->entries[i].smio_low = 0;
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int ci_construct_voltage_tables(struct amdgpu_device *adev)
2257 {
2258         struct ci_power_info *pi = ci_get_pi(adev);
2259         int ret;
2260
2261         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2262                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
2263                                                         VOLTAGE_OBJ_GPIO_LUT,
2264                                                         &pi->vddc_voltage_table);
2265                 if (ret)
2266                         return ret;
2267         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2268                 ret = ci_get_svi2_voltage_table(adev,
2269                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2270                                                 &pi->vddc_voltage_table);
2271                 if (ret)
2272                         return ret;
2273         }
2274
2275         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2276                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
2277                                                          &pi->vddc_voltage_table);
2278
2279         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2280                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
2281                                                         VOLTAGE_OBJ_GPIO_LUT,
2282                                                         &pi->vddci_voltage_table);
2283                 if (ret)
2284                         return ret;
2285         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2286                 ret = ci_get_svi2_voltage_table(adev,
2287                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2288                                                 &pi->vddci_voltage_table);
2289                 if (ret)
2290                         return ret;
2291         }
2292
2293         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2294                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
2295                                                          &pi->vddci_voltage_table);
2296
2297         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2298                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
2299                                                         VOLTAGE_OBJ_GPIO_LUT,
2300                                                         &pi->mvdd_voltage_table);
2301                 if (ret)
2302                         return ret;
2303         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2304                 ret = ci_get_svi2_voltage_table(adev,
2305                                                 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2306                                                 &pi->mvdd_voltage_table);
2307                 if (ret)
2308                         return ret;
2309         }
2310
2311         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2312                 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
2313                                                          &pi->mvdd_voltage_table);
2314
2315         return 0;
2316 }
2317
2318 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
2319                                           struct atom_voltage_table_entry *voltage_table,
2320                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
2321 {
2322         int ret;
2323
2324         ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
2325                                             &smc_voltage_table->StdVoltageHiSidd,
2326                                             &smc_voltage_table->StdVoltageLoSidd);
2327
2328         if (ret) {
2329                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2330                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2331         }
2332
2333         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2334         smc_voltage_table->StdVoltageHiSidd =
2335                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2336         smc_voltage_table->StdVoltageLoSidd =
2337                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2338 }
2339
2340 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
2341                                       SMU7_Discrete_DpmTable *table)
2342 {
2343         struct ci_power_info *pi = ci_get_pi(adev);
2344         unsigned int count;
2345
2346         table->VddcLevelCount = pi->vddc_voltage_table.count;
2347         for (count = 0; count < table->VddcLevelCount; count++) {
2348                 ci_populate_smc_voltage_table(adev,
2349                                               &pi->vddc_voltage_table.entries[count],
2350                                               &table->VddcLevel[count]);
2351
2352                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2353                         table->VddcLevel[count].Smio |=
2354                                 pi->vddc_voltage_table.entries[count].smio_low;
2355                 else
2356                         table->VddcLevel[count].Smio = 0;
2357         }
2358         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2359
2360         return 0;
2361 }
2362
2363 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
2364                                        SMU7_Discrete_DpmTable *table)
2365 {
2366         unsigned int count;
2367         struct ci_power_info *pi = ci_get_pi(adev);
2368
2369         table->VddciLevelCount = pi->vddci_voltage_table.count;
2370         for (count = 0; count < table->VddciLevelCount; count++) {
2371                 ci_populate_smc_voltage_table(adev,
2372                                               &pi->vddci_voltage_table.entries[count],
2373                                               &table->VddciLevel[count]);
2374
2375                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2376                         table->VddciLevel[count].Smio |=
2377                                 pi->vddci_voltage_table.entries[count].smio_low;
2378                 else
2379                         table->VddciLevel[count].Smio = 0;
2380         }
2381         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2382
2383         return 0;
2384 }
2385
2386 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
2387                                       SMU7_Discrete_DpmTable *table)
2388 {
2389         struct ci_power_info *pi = ci_get_pi(adev);
2390         unsigned int count;
2391
2392         table->MvddLevelCount = pi->mvdd_voltage_table.count;
2393         for (count = 0; count < table->MvddLevelCount; count++) {
2394                 ci_populate_smc_voltage_table(adev,
2395                                               &pi->mvdd_voltage_table.entries[count],
2396                                               &table->MvddLevel[count]);
2397
2398                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2399                         table->MvddLevel[count].Smio |=
2400                                 pi->mvdd_voltage_table.entries[count].smio_low;
2401                 else
2402                         table->MvddLevel[count].Smio = 0;
2403         }
2404         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2405
2406         return 0;
2407 }
2408
2409 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
2410                                           SMU7_Discrete_DpmTable *table)
2411 {
2412         int ret;
2413
2414         ret = ci_populate_smc_vddc_table(adev, table);
2415         if (ret)
2416                 return ret;
2417
2418         ret = ci_populate_smc_vddci_table(adev, table);
2419         if (ret)
2420                 return ret;
2421
2422         ret = ci_populate_smc_mvdd_table(adev, table);
2423         if (ret)
2424                 return ret;
2425
2426         return 0;
2427 }
2428
2429 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
2430                                   SMU7_Discrete_VoltageLevel *voltage)
2431 {
2432         struct ci_power_info *pi = ci_get_pi(adev);
2433         u32 i = 0;
2434
2435         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2436                 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2437                         if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2438                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2439                                 break;
2440                         }
2441                 }
2442
2443                 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2444                         return -EINVAL;
2445         }
2446
2447         return -EINVAL;
2448 }
2449
2450 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
2451                                          struct atom_voltage_table_entry *voltage_table,
2452                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2453 {
2454         u16 v_index, idx;
2455         bool voltage_found = false;
2456         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2457         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2458
2459         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2460                 return -EINVAL;
2461
2462         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2463                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2464                         if (voltage_table->value ==
2465                             adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2466                                 voltage_found = true;
2467                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2468                                         idx = v_index;
2469                                 else
2470                                         idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2471                                 *std_voltage_lo_sidd =
2472                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2473                                 *std_voltage_hi_sidd =
2474                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2475                                 break;
2476                         }
2477                 }
2478
2479                 if (!voltage_found) {
2480                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2481                                 if (voltage_table->value <=
2482                                     adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2483                                         voltage_found = true;
2484                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
2485                                                 idx = v_index;
2486                                         else
2487                                                 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2488                                         *std_voltage_lo_sidd =
2489                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2490                                         *std_voltage_hi_sidd =
2491                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2492                                         break;
2493                                 }
2494                         }
2495                 }
2496         }
2497
2498         return 0;
2499 }
2500
2501 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
2502                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2503                                                   u32 sclk,
2504                                                   u32 *phase_shedding)
2505 {
2506         unsigned int i;
2507
2508         *phase_shedding = 1;
2509
2510         for (i = 0; i < limits->count; i++) {
2511                 if (sclk < limits->entries[i].sclk) {
2512                         *phase_shedding = i;
2513                         break;
2514                 }
2515         }
2516 }
2517
2518 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
2519                                                   const struct amdgpu_phase_shedding_limits_table *limits,
2520                                                   u32 mclk,
2521                                                   u32 *phase_shedding)
2522 {
2523         unsigned int i;
2524
2525         *phase_shedding = 1;
2526
2527         for (i = 0; i < limits->count; i++) {
2528                 if (mclk < limits->entries[i].mclk) {
2529                         *phase_shedding = i;
2530                         break;
2531                 }
2532         }
2533 }
2534
2535 static int ci_init_arb_table_index(struct amdgpu_device *adev)
2536 {
2537         struct ci_power_info *pi = ci_get_pi(adev);
2538         u32 tmp;
2539         int ret;
2540
2541         ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
2542                                      &tmp, pi->sram_end);
2543         if (ret)
2544                 return ret;
2545
2546         tmp &= 0x00FFFFFF;
2547         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2548
2549         return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
2550                                        tmp, pi->sram_end);
2551 }
2552
2553 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
2554                                          struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
2555                                          u32 clock, u32 *voltage)
2556 {
2557         u32 i = 0;
2558
2559         if (allowed_clock_voltage_table->count == 0)
2560                 return -EINVAL;
2561
2562         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2563                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2564                         *voltage = allowed_clock_voltage_table->entries[i].v;
2565                         return 0;
2566                 }
2567         }
2568
2569         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2570
2571         return 0;
2572 }
2573
2574 static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
2575 {
2576         u32 i;
2577         u32 tmp;
2578         u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
2579
2580         if (sclk < min)
2581                 return 0;
2582
2583         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2584                 tmp = sclk >> i;
2585                 if (tmp >= min || i == 0)
2586                         break;
2587         }
2588
2589         return (u8)i;
2590 }
2591
2592 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
2593 {
2594         return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2595 }
2596
2597 static int ci_reset_to_default(struct amdgpu_device *adev)
2598 {
2599         return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2600                 0 : -EINVAL;
2601 }
2602
2603 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
2604 {
2605         u32 tmp;
2606
2607         tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
2608
2609         if (tmp == MC_CG_ARB_FREQ_F0)
2610                 return 0;
2611
2612         return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
2613 }
2614
2615 static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
2616                                         const u32 engine_clock,
2617                                         const u32 memory_clock,
2618                                         u32 *dram_timimg2)
2619 {
2620         bool patch;
2621         u32 tmp, tmp2;
2622
2623         tmp = RREG32(mmMC_SEQ_MISC0);
2624         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2625
2626         if (patch &&
2627             ((adev->pdev->device == 0x67B0) ||
2628              (adev->pdev->device == 0x67B1))) {
2629                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2630                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2631                         *dram_timimg2 &= ~0x00ff0000;
2632                         *dram_timimg2 |= tmp2 << 16;
2633                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2634                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2635                         *dram_timimg2 &= ~0x00ff0000;
2636                         *dram_timimg2 |= tmp2 << 16;
2637                 }
2638         }
2639 }
2640
2641 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
2642                                                 u32 sclk,
2643                                                 u32 mclk,
2644                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2645 {
2646         u32 dram_timing;
2647         u32 dram_timing2;
2648         u32 burst_time;
2649
2650         amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
2651
2652         dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
2653         dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
2654         burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
2655
2656         ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
2657
2658         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2659         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2660         arb_regs->McArbBurstTime = (u8)burst_time;
2661
2662         return 0;
2663 }
2664
2665 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
2666 {
2667         struct ci_power_info *pi = ci_get_pi(adev);
2668         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2669         u32 i, j;
2670         int ret =  0;
2671
2672         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2673
2674         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2675                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2676                         ret = ci_populate_memory_timing_parameters(adev,
2677                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2678                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2679                                                                    &arb_regs.entries[i][j]);
2680                         if (ret)
2681                                 break;
2682                 }
2683         }
2684
2685         if (ret == 0)
2686                 ret = amdgpu_ci_copy_bytes_to_smc(adev,
2687                                            pi->arb_table_start,
2688                                            (u8 *)&arb_regs,
2689                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2690                                            pi->sram_end);
2691
2692         return ret;
2693 }
2694
2695 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
2696 {
2697         struct ci_power_info *pi = ci_get_pi(adev);
2698
2699         if (pi->need_update_smu7_dpm_table == 0)
2700                 return 0;
2701
2702         return ci_do_program_memory_timing_parameters(adev);
2703 }
2704
2705 static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
2706                                           struct amdgpu_ps *amdgpu_boot_state)
2707 {
2708         struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
2709         struct ci_power_info *pi = ci_get_pi(adev);
2710         u32 level = 0;
2711
2712         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2713                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2714                     boot_state->performance_levels[0].sclk) {
2715                         pi->smc_state_table.GraphicsBootLevel = level;
2716                         break;
2717                 }
2718         }
2719
2720         for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2721                 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2722                     boot_state->performance_levels[0].mclk) {
2723                         pi->smc_state_table.MemoryBootLevel = level;
2724                         break;
2725                 }
2726         }
2727 }
2728
2729 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2730 {
2731         u32 i;
2732         u32 mask_value = 0;
2733
2734         for (i = dpm_table->count; i > 0; i--) {
2735                 mask_value = mask_value << 1;
2736                 if (dpm_table->dpm_levels[i-1].enabled)
2737                         mask_value |= 0x1;
2738                 else
2739                         mask_value &= 0xFFFFFFFE;
2740         }
2741
2742         return mask_value;
2743 }
2744
2745 static void ci_populate_smc_link_level(struct amdgpu_device *adev,
2746                                        SMU7_Discrete_DpmTable *table)
2747 {
2748         struct ci_power_info *pi = ci_get_pi(adev);
2749         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2750         u32 i;
2751
2752         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2753                 table->LinkLevel[i].PcieGenSpeed =
2754                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2755                 table->LinkLevel[i].PcieLaneCount =
2756                         amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2757                 table->LinkLevel[i].EnabledForActivity = 1;
2758                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2759                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2760         }
2761
2762         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2763         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2764                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2765 }
2766
2767 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
2768                                      SMU7_Discrete_DpmTable *table)
2769 {
2770         u32 count;
2771         struct atom_clock_dividers dividers;
2772         int ret = -EINVAL;
2773
2774         table->UvdLevelCount =
2775                 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2776
2777         for (count = 0; count < table->UvdLevelCount; count++) {
2778                 table->UvdLevel[count].VclkFrequency =
2779                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2780                 table->UvdLevel[count].DclkFrequency =
2781                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2782                 table->UvdLevel[count].MinVddc =
2783                         adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2784                 table->UvdLevel[count].MinVddcPhases = 1;
2785
2786                 ret = amdgpu_atombios_get_clock_dividers(adev,
2787                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2788                                                          table->UvdLevel[count].VclkFrequency, false, &dividers);
2789                 if (ret)
2790                         return ret;
2791
2792                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2793
2794                 ret = amdgpu_atombios_get_clock_dividers(adev,
2795                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2796                                                          table->UvdLevel[count].DclkFrequency, false, &dividers);
2797                 if (ret)
2798                         return ret;
2799
2800                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2801
2802                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2803                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2804                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2805         }
2806
2807         return ret;
2808 }
2809
2810 static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
2811                                      SMU7_Discrete_DpmTable *table)
2812 {
2813         u32 count;
2814         struct atom_clock_dividers dividers;
2815         int ret = -EINVAL;
2816
2817         table->VceLevelCount =
2818                 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2819
2820         for (count = 0; count < table->VceLevelCount; count++) {
2821                 table->VceLevel[count].Frequency =
2822                         adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2823                 table->VceLevel[count].MinVoltage =
2824                         (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2825                 table->VceLevel[count].MinPhases = 1;
2826
2827                 ret = amdgpu_atombios_get_clock_dividers(adev,
2828                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2829                                                          table->VceLevel[count].Frequency, false, &dividers);
2830                 if (ret)
2831                         return ret;
2832
2833                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2834
2835                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2836                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2837         }
2838
2839         return ret;
2840
2841 }
2842
2843 static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
2844                                      SMU7_Discrete_DpmTable *table)
2845 {
2846         u32 count;
2847         struct atom_clock_dividers dividers;
2848         int ret = -EINVAL;
2849
2850         table->AcpLevelCount = (u8)
2851                 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2852
2853         for (count = 0; count < table->AcpLevelCount; count++) {
2854                 table->AcpLevel[count].Frequency =
2855                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2856                 table->AcpLevel[count].MinVoltage =
2857                         adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2858                 table->AcpLevel[count].MinPhases = 1;
2859
2860                 ret = amdgpu_atombios_get_clock_dividers(adev,
2861                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2862                                                          table->AcpLevel[count].Frequency, false, &dividers);
2863                 if (ret)
2864                         return ret;
2865
2866                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2867
2868                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2869                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2870         }
2871
2872         return ret;
2873 }
2874
2875 static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
2876                                       SMU7_Discrete_DpmTable *table)
2877 {
2878         u32 count;
2879         struct atom_clock_dividers dividers;
2880         int ret = -EINVAL;
2881
2882         table->SamuLevelCount =
2883                 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2884
2885         for (count = 0; count < table->SamuLevelCount; count++) {
2886                 table->SamuLevel[count].Frequency =
2887                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2888                 table->SamuLevel[count].MinVoltage =
2889                         adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2890                 table->SamuLevel[count].MinPhases = 1;
2891
2892                 ret = amdgpu_atombios_get_clock_dividers(adev,
2893                                                          COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2894                                                          table->SamuLevel[count].Frequency, false, &dividers);
2895                 if (ret)
2896                         return ret;
2897
2898                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2899
2900                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2901                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2902         }
2903
2904         return ret;
2905 }
2906
2907 static int ci_calculate_mclk_params(struct amdgpu_device *adev,
2908                                     u32 memory_clock,
2909                                     SMU7_Discrete_MemoryLevel *mclk,
2910                                     bool strobe_mode,
2911                                     bool dll_state_on)
2912 {
2913         struct ci_power_info *pi = ci_get_pi(adev);
2914         u32  dll_cntl = pi->clock_registers.dll_cntl;
2915         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2916         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2917         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2918         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2919         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2920         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2921         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2922         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2923         struct atom_mpll_param mpll_param;
2924         int ret;
2925
2926         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
2927         if (ret)
2928                 return ret;
2929
2930         mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
2931         mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
2932
2933         mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
2934                         MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
2935         mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
2936                 (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
2937                 (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
2938
2939         mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
2940         mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2941
2942         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
2943                 mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
2944                                 MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
2945                 mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
2946                                 (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
2947         }
2948
2949         if (pi->caps_mclk_ss_support) {
2950                 struct amdgpu_atom_ss ss;
2951                 u32 freq_nom;
2952                 u32 tmp;
2953                 u32 reference_clock = adev->clock.mpll.reference_freq;
2954
2955                 if (mpll_param.qdr == 1)
2956                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2957                 else
2958                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2959
2960                 tmp = (freq_nom / reference_clock);
2961                 tmp = tmp * tmp;
2962                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
2963                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2964                         u32 clks = reference_clock * 5 / ss.rate;
2965                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2966
2967                         mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
2968                         mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
2969
2970                         mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
2971                         mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
2972                 }
2973         }
2974
2975         mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
2976         mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
2977
2978         if (dll_state_on)
2979                 mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2980                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
2981         else
2982                 mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
2983                         MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
2984
2985         mclk->MclkFrequency = memory_clock;
2986         mclk->MpllFuncCntl = mpll_func_cntl;
2987         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2988         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2989         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2990         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2991         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2992         mclk->DllCntl = dll_cntl;
2993         mclk->MpllSs1 = mpll_ss1;
2994         mclk->MpllSs2 = mpll_ss2;
2995
2996         return 0;
2997 }
2998
2999 static int ci_populate_single_memory_level(struct amdgpu_device *adev,
3000                                            u32 memory_clock,
3001                                            SMU7_Discrete_MemoryLevel *memory_level)
3002 {
3003         struct ci_power_info *pi = ci_get_pi(adev);
3004         int ret;
3005         bool dll_state_on;
3006
3007         if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
3008                 ret = ci_get_dependency_volt_by_clk(adev,
3009                                                     &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3010                                                     memory_clock, &memory_level->MinVddc);
3011                 if (ret)
3012                         return ret;
3013         }
3014
3015         if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
3016                 ret = ci_get_dependency_volt_by_clk(adev,
3017                                                     &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3018                                                     memory_clock, &memory_level->MinVddci);
3019                 if (ret)
3020                         return ret;
3021         }
3022
3023         if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
3024                 ret = ci_get_dependency_volt_by_clk(adev,
3025                                                     &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
3026                                                     memory_clock, &memory_level->MinMvdd);
3027                 if (ret)
3028                         return ret;
3029         }
3030
3031         memory_level->MinVddcPhases = 1;
3032
3033         if (pi->vddc_phase_shed_control)
3034                 ci_populate_phase_value_based_on_mclk(adev,