drivers/gpu/drm/amd/amdgpu/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/amdgpu_drm.h>
  29 #include "amdgpu.h"
  30
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_atombios.h"
  37 #include <drm/drm_dp_helper.h>
  38
  39 /* move these to drm_dp_helper.c/h */
  40 #define DP_LINK_CONFIGURATION_SIZE 9
  41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  42
  43 static char *voltage_names[] = {
  44         "0.4V", "0.6V", "0.8V", "1.2V"
  45 };
  46 static char *pre_emph_names[] = {
  47         "0dB", "3.5dB", "6dB", "9.5dB"
  48 };
  49
  50 /***** amdgpu AUX functions *****/
  51
  52 union aux_channel_transaction {
  53         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  54         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  55 };
  56
  57 static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
  58                                       u8 *send, int send_bytes,
  59                                       u8 *recv, int recv_size,
  60                                       u8 delay, u8 *ack)
  61 {
  62         struct drm_device *dev = chan->dev;
  63         struct amdgpu_device *adev = dev->dev_private;
  64         union aux_channel_transaction args;
  65         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  66         unsigned char *base;
  67         int recv_bytes;
  68         int r = 0;
  69
  70         memset(&args, 0, sizeof(args));
  71
  72         mutex_lock(&chan->mutex);
  73
  74         base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
  75
  76         amdgpu_atombios_copy_swap(base, send, send_bytes, true);
  77
  78         args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
  79         args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
  80         args.v2.ucDataOutLen = 0;
  81         args.v2.ucChannelID = chan->rec.i2c_id;
  82         args.v2.ucDelay = delay / 10;
  83         args.v2.ucHPD_ID = chan->rec.hpd;
  84
  85         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
  86
  87         *ack = args.v2.ucReplyStatus;
  88
  89         /* timeout */
  90         if (args.v2.ucReplyStatus == 1) {
  91                 r = -ETIMEDOUT;
  92                 goto done;
  93         }
  94
  95         /* flags not zero */
  96         if (args.v2.ucReplyStatus == 2) {
  97                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  98                 r = -EIO;
  99                 goto done;
 100         }
 101
 102         /* error */
 103         if (args.v2.ucReplyStatus == 3) {
 104                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 105                 r = -EIO;
 106                 goto done;
 107         }
 108
 109         recv_bytes = args.v1.ucDataOutLen;
 110         if (recv_bytes > recv_size)
 111                 recv_bytes = recv_size;
 112
 113         if (recv && recv_size)
 114                 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
 115
 116         r = recv_bytes;
 117 done:
 118         mutex_unlock(&chan->mutex);
 119
 120         return r;
 121 }
 122
 123 #define BARE_ADDRESS_SIZE 3
 124 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
 125
 126 static ssize_t
 127 amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 128 {
 129         struct amdgpu_i2c_chan *chan =
 130                 container_of(aux, struct amdgpu_i2c_chan, aux);
 131         int ret;
 132         u8 tx_buf[20];
 133         size_t tx_size;
 134         u8 ack, delay = 0;
 135
 136         if (WARN_ON(msg->size > 16))
 137                 return -E2BIG;
 138
 139         tx_buf[0] = msg->address & 0xff;
 140         tx_buf[1] = msg->address >> 8;
 141         tx_buf[2] = (msg->request << 4) |
 142                 ((msg->address >> 16) & 0xf);
 143         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
 144
 145         switch (msg->request & ~DP_AUX_I2C_MOT) {
 146         case DP_AUX_NATIVE_WRITE:
 147         case DP_AUX_I2C_WRITE:
 148                 /* tx_size needs to be 4 even for bare address packets since the atom
 149                  * table needs the info in tx_buf[3].
 150                  */
 151                 tx_size = HEADER_SIZE + msg->size;
 152                 if (msg->size == 0)
 153                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 154                 else
 155                         tx_buf[3] |= tx_size << 4;
 156                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
 157                 ret = amdgpu_atombios_dp_process_aux_ch(chan,
 158                                                  tx_buf, tx_size, NULL, 0, delay, &ack);
 159                 if (ret >= 0)
 160                         /* Return payload size. */
 161                         ret = msg->size;
 162                 break;
 163         case DP_AUX_NATIVE_READ:
 164         case DP_AUX_I2C_READ:
 165                 /* tx_size needs to be 4 even for bare address packets since the atom
 166                  * table needs the info in tx_buf[3].
 167                  */
 168                 tx_size = HEADER_SIZE;
 169                 if (msg->size == 0)
 170                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
 171                 else
 172                         tx_buf[3] |= tx_size << 4;
 173                 ret = amdgpu_atombios_dp_process_aux_ch(chan,
 174                                                  tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
 175                 break;
 176         default:
 177                 ret = -EINVAL;
 178                 break;
 179         }
 180
 181         if (ret >= 0)
 182                 msg->reply = ack >> 4;
 183
 184         return ret;
 185 }
 186
 187 void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
 188 {
 189         int ret;
 190
 191         amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
 192         amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
 193         amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
 194         ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
 195         if (!ret)
 196                 amdgpu_connector->ddc_bus->has_aux = true;
 197
 198         WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
 199 }
 200
 201 /***** general DP utility functions *****/
 202
 203 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
 204 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
 205
 206 static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
 207                                                 int lane_count,
 208                                                 u8 train_set[4])
 209 {
 210         u8 v = 0;
 211         u8 p = 0;
 212         int lane;
 213
 214         for (lane = 0; lane < lane_count; lane++) {
 215                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 216                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 217
 218                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 219                           lane,
 220                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 221                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 222
 223                 if (this_v > v)
 224                         v = this_v;
 225                 if (this_p > p)
 226                         p = this_p;
 227         }
 228
 229         if (v >= DP_VOLTAGE_MAX)
 230                 v |= DP_TRAIN_MAX_SWING_REACHED;
 231
 232         if (p >= DP_PRE_EMPHASIS_MAX)
 233                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 234
 235         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 236                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 237                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 238
 239         for (lane = 0; lane < 4; lane++)
 240                 train_set[lane] = v | p;
 241 }
 242
 243 /* convert bits per color to bits per pixel */
 244 /* get bpc from the EDID */
 245 static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
 246 {
 247         if (bpc == 0)
 248                 return 24;
 249         else
 250                 return bpc * 3;
 251 }
 252
 253 /***** amdgpu specific DP functions *****/
 254
 255 static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector,
 256                                                  const u8 dpcd[DP_DPCD_SIZE],
 257                                                  unsigned pix_clock,
 258                                                  unsigned *dp_lanes, unsigned *dp_rate)
 259 {
 260         unsigned bpp =
 261                 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
 262         static const unsigned link_rates[3] = { 162000, 270000, 540000 };
 263         unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
 264         unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
 265         unsigned lane_num, i, max_pix_clock;
 266
 267         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 268             ENCODER_OBJECT_ID_NUTMEG) {
 269                 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 270                         max_pix_clock = (lane_num * 270000 * 8) / bpp;
 271                         if (max_pix_clock >= pix_clock) {
 272                                 *dp_lanes = lane_num;
 273                                 *dp_rate = 270000;
 274                                 return 0;
 275                         }
 276                 }
 277         } else {
 278                 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
 279                         for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
 280                                 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
 281                                 if (max_pix_clock >= pix_clock) {
 282                                         *dp_lanes = lane_num;
 283                                         *dp_rate = link_rates[i];
 284                                         return 0;
 285                                 }
 286                         }
 287                 }
 288         }
 289
 290         return -EINVAL;
 291 }
 292
 293 static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
 294                                       int action, int dp_clock,
 295                                       u8 ucconfig, u8 lane_num)
 296 {
 297         DP_ENCODER_SERVICE_PARAMETERS args;
 298         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 299
 300         memset(&args, 0, sizeof(args));
 301         args.ucLinkClock = dp_clock / 10;
 302         args.ucConfig = ucconfig;
 303         args.ucAction = action;
 304         args.ucLaneNum = lane_num;
 305         args.ucStatus = 0;
 306
 307         amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
 308         return args.ucStatus;
 309 }
 310
 311 u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
 312 {
 313         struct drm_device *dev = amdgpu_connector->base.dev;
 314         struct amdgpu_device *adev = dev->dev_private;
 315
 316         return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 317                                            amdgpu_connector->ddc_bus->rec.i2c_id, 0);
 318 }
 319
 320 static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
 321 {
 322         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 323         u8 buf[3];
 324
 325         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 326                 return;
 327
 328         if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
 329                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
 330                               buf[0], buf[1], buf[2]);
 331
 332         if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
 333                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
 334                               buf[0], buf[1], buf[2]);
 335 }
 336
 337 int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
 338 {
 339         struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
 340         u8 msg[DP_DPCD_SIZE];
 341         int ret;
 342
 343         ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
 344                                msg, DP_DPCD_SIZE);
 345         if (ret == DP_DPCD_SIZE) {
 346                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 347
 348                 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
 349                               dig_connector->dpcd);
 350
 351                 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
 352
 353                 return 0;
 354         }
 355
 356         dig_connector->dpcd[0] = 0;
 357         return -EINVAL;
 358 }
 359
 360 int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
 361                                struct drm_connector *connector)
 362 {
 363         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 364         struct amdgpu_connector_atom_dig *dig_connector;
 365         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 366         u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
 367         u8 tmp;
 368
 369         if (!amdgpu_connector->con_priv)
 370                 return panel_mode;
 371
 372         dig_connector = amdgpu_connector->con_priv;
 373
 374         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 375                 /* DP bridge chips */
 376                 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
 377                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 378                         if (tmp & 1)
 379                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 380                         else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 381                                  (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 382                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 383                         else
 384                                 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 385                 }
 386         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 387                 /* eDP */
 388                 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
 389                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
 390                         if (tmp & 1)
 391                                 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 392                 }
 393         }
 394
 395         return panel_mode;
 396 }
 397
 398 void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
 399                                  const struct drm_display_mode *mode)
 400 {
 401         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 402         struct amdgpu_connector_atom_dig *dig_connector;
 403         int ret;
 404
 405         if (!amdgpu_connector->con_priv)
 406                 return;
 407         dig_connector = amdgpu_connector->con_priv;
 408
 409         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 410             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 411                 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
 412                                                             mode->clock,
 413                                                             &dig_connector->dp_lane_count,
 414                                                             &dig_connector->dp_clock);
 415                 if (ret) {
 416                         dig_connector->dp_clock = 0;
 417                         dig_connector->dp_lane_count = 0;
 418                 }
 419         }
 420 }
 421
 422 int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
 423                                   struct drm_display_mode *mode)
 424 {
 425         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 426         struct amdgpu_connector_atom_dig *dig_connector;
 427         unsigned dp_lanes, dp_clock;
 428         int ret;
 429
 430         if (!amdgpu_connector->con_priv)
 431                 return MODE_CLOCK_HIGH;
 432         dig_connector = amdgpu_connector->con_priv;
 433
 434         ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
 435                                                     mode->clock, &dp_lanes, &dp_clock);
 436         if (ret)
 437                 return MODE_CLOCK_HIGH;
 438
 439         if ((dp_clock == 540000) &&
 440             (!amdgpu_connector_is_dp12_capable(connector)))
 441                 return MODE_CLOCK_HIGH;
 442
 443         return MODE_OK;
 444 }
 445
 446 bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
 447 {
 448         u8 link_status[DP_LINK_STATUS_SIZE];
 449         struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 450
 451         if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
 452             <= 0)
 453                 return false;
 454         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 455                 return false;
 456         return true;
 457 }
 458
 459 void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
 460                                     u8 power_state)
 461 {
 462         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 463         struct amdgpu_connector_atom_dig *dig_connector;
 464
 465         if (!amdgpu_connector->con_priv)
 466                 return;
 467
 468         dig_connector = amdgpu_connector->con_priv;
 469
 470         /* power up/down the sink */
 471         if (dig_connector->dpcd[0] >= 0x11) {
 472                 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
 473                                    DP_SET_POWER, power_state);
 474                 usleep_range(1000, 2000);
 475         }
 476 }
 477
 478 struct amdgpu_atombios_dp_link_train_info {
 479         struct amdgpu_device *adev;
 480         struct drm_encoder *encoder;
 481         struct drm_connector *connector;
 482         int dp_clock;
 483         int dp_lane_count;
 484         bool tp3_supported;
 485         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 486         u8 train_set[4];
 487         u8 link_status[DP_LINK_STATUS_SIZE];
 488         u8 tries;
 489         struct drm_dp_aux *aux;
 490 };
 491
 492 static void
 493 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
 494 {
 495         /* set the initial vs/emph on the source */
 496         amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
 497                                                ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 498                                                0, dp_info->train_set[0]); /* sets all lanes at once */
 499
 500         /* set the vs/emph on the sink */
 501         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
 502                           dp_info->train_set, dp_info->dp_lane_count);
 503 }
 504
 505 static void
 506 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
 507 {
 508         int rtp = 0;
 509
 510         /* set training pattern on the source */
 511         switch (tp) {
 512         case DP_TRAINING_PATTERN_1:
 513                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 514                 break;
 515         case DP_TRAINING_PATTERN_2:
 516                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 517                 break;
 518         case DP_TRAINING_PATTERN_3:
 519                 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 520                         break;
 521         }
 522         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
 523
 524         /* enable training pattern on the sink */
 525         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
 526 }
 527
 528 static int
 529 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
 530 {
 531         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
 532         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 533         u8 tmp;
 534
 535         /* power up the sink */
 536         amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
 537
 538         /* possibly enable downspread on the sink */
 539         if (dp_info->dpcd[3] & 0x1)
 540                 drm_dp_dpcd_writeb(dp_info->aux,
 541                                    DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 542         else
 543                 drm_dp_dpcd_writeb(dp_info->aux,
 544                                    DP_DOWNSPREAD_CTRL, 0);
 545
 546         if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
 547                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
 548
 549         /* set the lane count on the sink */
 550         tmp = dp_info->dp_lane_count;
 551         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
 552                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 553         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
 554
 555         /* set the link rate on the sink */
 556         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 557         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
 558
 559         /* start training on the source */
 560         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
 561                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 562
 563         /* disable the training pattern on the sink */
 564         drm_dp_dpcd_writeb(dp_info->aux,
 565                            DP_TRAINING_PATTERN_SET,
 566                            DP_TRAINING_PATTERN_DISABLE);
 567
 568         return 0;
 569 }
 570
 571 static int
 572 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
 573 {
 574         udelay(400);
 575
 576         /* disable the training pattern on the sink */
 577         drm_dp_dpcd_writeb(dp_info->aux,
 578                            DP_TRAINING_PATTERN_SET,
 579                            DP_TRAINING_PATTERN_DISABLE);
 580
 581         /* disable the training pattern on the source */
 582         amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
 583                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 584
 585         return 0;
 586 }
 587
 588 static int
 589 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
 590 {
 591         bool clock_recovery;
 592         u8 voltage;
 593         int i;
 594
 595         amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 596         memset(dp_info->train_set, 0, 4);
 597         amdgpu_atombios_dp_update_vs_emph(dp_info);
 598
 599         udelay(400);
 600
 601         /* clock recovery loop */
 602         clock_recovery = false;
 603         dp_info->tries = 0;
 604         voltage = 0xff;
 605         while (1) {
 606                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 607
 608                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 609                                                  dp_info->link_status) <= 0) {
 610                         DRM_ERROR("displayport link status failed\n");
 611                         break;
 612                 }
 613
 614                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 615                         clock_recovery = true;
 616                         break;
 617                 }
 618
 619                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 620                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 621                                 break;
 622                 }
 623                 if (i == dp_info->dp_lane_count) {
 624                         DRM_ERROR("clock recovery reached max voltage\n");
 625                         break;
 626                 }
 627
 628                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 629                         ++dp_info->tries;
 630                         if (dp_info->tries == 5) {
 631                                 DRM_ERROR("clock recovery tried 5 times\n");
 632                                 break;
 633                         }
 634                 } else
 635                         dp_info->tries = 0;
 636
 637                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 638
 639                 /* Compute new train_set as requested by sink */
 640                 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
 641                                              dp_info->train_set);
 642
 643                 amdgpu_atombios_dp_update_vs_emph(dp_info);
 644         }
 645         if (!clock_recovery) {
 646                 DRM_ERROR("clock recovery failed\n");
 647                 return -1;
 648         } else {
 649                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 650                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 651                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 652                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 653                 return 0;
 654         }
 655 }
 656
 657 static int
 658 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
 659 {
 660         bool channel_eq;
 661
 662         if (dp_info->tp3_supported)
 663                 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 664         else
 665                 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 666
 667         /* channel equalization loop */
 668         dp_info->tries = 0;
 669         channel_eq = false;
 670         while (1) {
 671                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 672
 673                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
 674                                                  dp_info->link_status) <= 0) {
 675                         DRM_ERROR("displayport link status failed\n");
 676                         break;
 677                 }
 678
 679                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 680                         channel_eq = true;
 681                         break;
 682                 }
 683
 684                 /* Try 5 times */
 685                 if (dp_info->tries > 5) {
 686                         DRM_ERROR("channel eq failed: 5 tries\n");
 687                         break;
 688                 }
 689
 690                 /* Compute new train_set as requested by sink */
 691                 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
 692                                              dp_info->train_set);
 693
 694                 amdgpu_atombios_dp_update_vs_emph(dp_info);
 695                 dp_info->tries++;
 696         }
 697
 698         if (!channel_eq) {
 699                 DRM_ERROR("channel eq failed\n");
 700                 return -1;
 701         } else {
 702                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 703                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 704                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 705                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 706                 return 0;
 707         }
 708 }
 709
 710 void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
 711                             struct drm_connector *connector)
 712 {
 713         struct drm_device *dev = encoder->dev;
 714         struct amdgpu_device *adev = dev->dev_private;
 715         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 716         struct amdgpu_encoder_atom_dig *dig;
 717         struct amdgpu_connector *amdgpu_connector;
 718         struct amdgpu_connector_atom_dig *dig_connector;
 719         struct amdgpu_atombios_dp_link_train_info dp_info;
 720         u8 tmp;
 721
 722         if (!amdgpu_encoder->enc_priv)
 723                 return;
 724         dig = amdgpu_encoder->enc_priv;
 725
 726         amdgpu_connector = to_amdgpu_connector(connector);
 727         if (!amdgpu_connector->con_priv)
 728                 return;
 729         dig_connector = amdgpu_connector->con_priv;
 730
 731         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 732             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 733                 return;
 734
 735         if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
 736             == 1) {
 737                 if (tmp & DP_TPS3_SUPPORTED)
 738                         dp_info.tp3_supported = true;
 739                 else
 740                         dp_info.tp3_supported = false;
 741         } else {
 742                 dp_info.tp3_supported = false;
 743         }
 744
 745         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 746         dp_info.adev = adev;
 747         dp_info.encoder = encoder;
 748         dp_info.connector = connector;
 749         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 750         dp_info.dp_clock = dig_connector->dp_clock;
 751         dp_info.aux = &amdgpu_connector->ddc_bus->aux;
 752
 753         if (amdgpu_atombios_dp_link_train_init(&dp_info))
 754                 goto done;
 755         if (amdgpu_atombios_dp_link_train_cr(&dp_info))
 756                 goto done;
 757         if (amdgpu_atombios_dp_link_train_ce(&dp_info))
 758                 goto done;
 759 done:
 760         if (amdgpu_atombios_dp_link_train_finish(&dp_info))
 761                 return;
 762 }