2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
27 #include <linux/rbtree.h>
29 #include "gpu_scheduler.h"
30 #include "amdgpu_sync.h"
31 #include "amdgpu_ring.h"
35 struct amdgpu_bo_list_entry;
41 /* maximum number of VMIDs */
42 #define AMDGPU_NUM_VM 16
44 /* Maximum number of PTEs the hardware can write with one command */
45 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
47 /* number of entries in page table */
48 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
50 /* PTBs (Page Table Blocks) need to be aligned to 32K */
51 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
53 /* LOG2 number of continuous pages for the fragment field */
54 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
56 #define AMDGPU_PTE_VALID (1ULL << 0)
57 #define AMDGPU_PTE_SYSTEM (1ULL << 1)
58 #define AMDGPU_PTE_SNOOPED (1ULL << 2)
61 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
63 #define AMDGPU_PTE_READABLE (1ULL << 5)
64 #define AMDGPU_PTE_WRITEABLE (1ULL << 6)
66 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
68 #define AMDGPU_PTE_PRT (1ULL << 63)
71 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
72 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL)
74 /* How to programm VM fault handling */
75 #define AMDGPU_VM_FAULT_STOP_NEVER 0
76 #define AMDGPU_VM_FAULT_STOP_FIRST 1
77 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
79 /* max number of VMHUB */
80 #define AMDGPU_MAX_VMHUBS 2
81 #define AMDGPU_GFXHUB 0
82 #define AMDGPU_MMHUB 1
84 /* hardcode that limit for now */
85 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
91 /* array of page tables, one for each directory entry */
92 struct amdgpu_vm_pt *entries;
93 unsigned last_entry_used;
97 /* tree of virtual addresses mapped */
100 /* protecting invalidated */
101 spinlock_t status_lock;
103 /* BOs moved, but not yet updated in the PT */
104 struct list_head invalidated;
106 /* BOs cleared in the PT because of a move */
107 struct list_head cleared;
109 /* BO mappings freed, but not yet updated in the PT */
110 struct list_head freed;
112 /* contains the page directory */
113 struct amdgpu_vm_pt root;
114 struct dma_fence *last_dir_update;
115 uint64_t last_eviction_counter;
117 /* for id and flush management per ring */
118 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
120 /* protecting freed */
121 spinlock_t freed_lock;
123 /* Scheduler entity for page table updates */
124 struct amd_sched_entity entity;
128 /* each VM will map on CSA */
129 struct amdgpu_bo_va *csa_bo_va;
132 struct amdgpu_vm_id {
133 struct list_head list;
134 struct amdgpu_sync active;
135 struct dma_fence *last_flush;
138 uint64_t pd_gpu_addr;
139 /* last flushed PD/PT update */
140 struct dma_fence *flushed_updates;
142 uint32_t current_gpu_reset_count;
152 struct amdgpu_vm_manager {
153 /* Handling of VMIDs */
156 struct list_head ids_lru;
157 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
159 /* Handling of VM fences */
161 unsigned seqno[AMDGPU_MAX_RINGS];
167 /* vram base address for page table entry */
168 u64 vram_base_offset;
171 /* vm pte handling */
172 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
173 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
174 unsigned vm_pte_num_rings;
175 atomic_t vm_pte_next_ring;
176 /* client id counter */
177 atomic64_t client_counter;
179 /* partial resident texture handling */
181 atomic_t num_prt_users;
184 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
185 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
186 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
187 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
188 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
189 struct list_head *validated,
190 struct amdgpu_bo_list_entry *entry);
191 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
192 int (*callback)(void *p, struct amdgpu_bo *bo),
194 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
195 struct amdgpu_vm *vm);
196 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
197 struct amdgpu_vm *vm,
198 uint64_t saddr, uint64_t size);
199 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
200 struct amdgpu_sync *sync, struct dma_fence *fence,
201 struct amdgpu_job *job);
202 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
203 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
204 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
205 struct amdgpu_vm *vm);
206 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
207 struct amdgpu_vm *vm,
208 struct dma_fence **fence);
209 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
210 struct amdgpu_sync *sync);
211 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
212 struct amdgpu_bo_va *bo_va,
214 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
215 struct amdgpu_bo *bo);
216 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
217 struct amdgpu_bo *bo);
218 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
219 struct amdgpu_vm *vm,
220 struct amdgpu_bo *bo);
221 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
222 struct amdgpu_bo_va *bo_va,
223 uint64_t addr, uint64_t offset,
224 uint64_t size, uint64_t flags);
225 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
226 struct amdgpu_bo_va *bo_va,
227 uint64_t addr, uint64_t offset,
228 uint64_t size, uint64_t flags);
229 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
230 struct amdgpu_bo_va *bo_va,
232 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
233 struct amdgpu_vm *vm,
234 uint64_t saddr, uint64_t size);
235 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
236 struct amdgpu_bo_va *bo_va);
237 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);