2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
39 * PASIDs are global address space identifiers that can be shared
40 * between the GPU, an IOMMU and the driver. VMs on different devices
41 * may use the same PASID if they share the same address
42 * space. Therefore PASIDs are allocated using a global IDA. VMs are
43 * looked up from the PASID per amdgpu_device.
45 static DEFINE_IDA(amdgpu_vm_pasid_ida);
48 * amdgpu_vm_alloc_pasid - Allocate a PASID
49 * @bits: Maximum width of the PASID in bits, must be at least 1
51 * Allocates a PASID of the given width while keeping smaller PASIDs
52 * available if possible.
54 * Returns a positive integer on success. Returns %-EINVAL if bits==0.
55 * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
56 * memory allocation failure.
58 int amdgpu_vm_alloc_pasid(unsigned int bits)
62 for (bits = min(bits, 31U); bits > 0; bits--) {
63 pasid = ida_simple_get(&amdgpu_vm_pasid_ida,
64 1U << (bits - 1), 1U << bits,
74 * amdgpu_vm_free_pasid - Free a PASID
75 * @pasid: PASID to free
77 void amdgpu_vm_free_pasid(unsigned int pasid)
79 ida_simple_remove(&amdgpu_vm_pasid_ida, pasid);
84 * GPUVM is similar to the legacy gart on older asics, however
85 * rather than there being a single global gart table
86 * for the entire GPU, there are multiple VM page tables active
87 * at any given time. The VM page tables can contain a mix
88 * vram pages and system memory pages and system memory pages
89 * can be mapped as snooped (cached system pages) or unsnooped
90 * (uncached system pages).
91 * Each VM has an ID associated with it and there is a page table
92 * associated with each VMID. When execting a command buffer,
93 * the kernel tells the the ring what VMID to use for that command
94 * buffer. VMIDs are allocated dynamically as commands are submitted.
95 * The userspace drivers maintain their own address space and the kernel
96 * sets up their pages tables accordingly when they submit their
97 * command buffers and a VMID is assigned.
98 * Cayman/Trinity support up to 8 active VMs at any given time;
102 #define START(node) ((node)->start)
103 #define LAST(node) ((node)->last)
105 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
106 START, LAST, static, amdgpu_vm_it)
111 /* Local structure. Encapsulate some VM table update parameters to reduce
112 * the number of function parameters
114 struct amdgpu_pte_update_params {
115 /* amdgpu device we do this update for */
116 struct amdgpu_device *adev;
117 /* optional amdgpu_vm we do this update for */
118 struct amdgpu_vm *vm;
119 /* address where to copy page table entries from */
121 /* indirect buffer to fill with commands */
122 struct amdgpu_ib *ib;
123 /* Function which actually does the update */
124 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
125 uint64_t addr, unsigned count, uint32_t incr,
127 /* The next two are used during VM update by CPU
128 * DMA addresses to use for mapping
129 * Kernel pointer of PD/PT BO that needs to be updated
131 dma_addr_t *pages_addr;
135 /* Helper to disable partial resident texture feature from a fence callback */
136 struct amdgpu_prt_cb {
137 struct amdgpu_device *adev;
138 struct dma_fence_cb cb;
142 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
144 * @adev: amdgpu_device pointer
146 * Calculate the number of entries in a page directory or page table.
148 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
152 /* For the root directory */
153 return adev->vm_manager.max_pfn >>
154 (adev->vm_manager.block_size *
155 adev->vm_manager.num_level);
156 else if (level == adev->vm_manager.num_level)
157 /* For the page tables on the leaves */
158 return AMDGPU_VM_PTE_COUNT(adev);
160 /* Everything in between */
161 return 1 << adev->vm_manager.block_size;
165 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
167 * @adev: amdgpu_device pointer
169 * Calculate the size of the BO for a page directory or page table in bytes.
171 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
173 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
177 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
179 * @vm: vm providing the BOs
180 * @validated: head of validation list
181 * @entry: entry to add
183 * Add the page directory to the list of BOs to
184 * validate for command submission.
186 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
187 struct list_head *validated,
188 struct amdgpu_bo_list_entry *entry)
190 entry->robj = vm->root.base.bo;
192 entry->tv.bo = &entry->robj->tbo;
193 entry->tv.shared = true;
194 entry->user_pages = NULL;
195 list_add(&entry->tv.head, validated);
199 * amdgpu_vm_validate_pt_bos - validate the page table BOs
201 * @adev: amdgpu device pointer
202 * @vm: vm providing the BOs
203 * @validate: callback to do the validation
204 * @param: parameter for the validation callback
206 * Validate the page table BOs on command submission if neccessary.
208 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
209 int (*validate)(void *p, struct amdgpu_bo *bo),
212 struct ttm_bo_global *glob = adev->mman.bdev.glob;
215 spin_lock(&vm->status_lock);
216 while (!list_empty(&vm->evicted)) {
217 struct amdgpu_vm_bo_base *bo_base;
218 struct amdgpu_bo *bo;
220 bo_base = list_first_entry(&vm->evicted,
221 struct amdgpu_vm_bo_base,
223 spin_unlock(&vm->status_lock);
228 r = validate(param, bo);
232 spin_lock(&glob->lru_lock);
233 ttm_bo_move_to_lru_tail(&bo->tbo);
235 ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
236 spin_unlock(&glob->lru_lock);
239 if (bo->tbo.type == ttm_bo_type_kernel &&
240 vm->use_cpu_for_update) {
241 r = amdgpu_bo_kmap(bo, NULL);
246 spin_lock(&vm->status_lock);
247 if (bo->tbo.type != ttm_bo_type_kernel)
248 list_move(&bo_base->vm_status, &vm->moved);
250 list_move(&bo_base->vm_status, &vm->relocated);
252 spin_unlock(&vm->status_lock);
258 * amdgpu_vm_ready - check VM is ready for updates
262 * Check if all VM PDs/PTs are ready for updates
264 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
268 spin_lock(&vm->status_lock);
269 ready = list_empty(&vm->evicted);
270 spin_unlock(&vm->status_lock);
276 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
278 * @adev: amdgpu_device pointer
280 * @saddr: start of the address range
281 * @eaddr: end of the address range
283 * Make sure the page directories and page tables are allocated
285 static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
286 struct amdgpu_vm *vm,
287 struct amdgpu_vm_pt *parent,
288 uint64_t saddr, uint64_t eaddr,
291 unsigned shift = (adev->vm_manager.num_level - level) *
292 adev->vm_manager.block_size;
293 unsigned pt_idx, from, to;
296 uint64_t init_value = 0;
298 if (!parent->entries) {
299 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
301 parent->entries = kvmalloc_array(num_entries,
302 sizeof(struct amdgpu_vm_pt),
303 GFP_KERNEL | __GFP_ZERO);
304 if (!parent->entries)
306 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
309 from = saddr >> shift;
311 if (from >= amdgpu_vm_num_entries(adev, level) ||
312 to >= amdgpu_vm_num_entries(adev, level))
315 if (to > parent->last_entry_used)
316 parent->last_entry_used = to;
319 saddr = saddr & ((1 << shift) - 1);
320 eaddr = eaddr & ((1 << shift) - 1);
322 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
323 AMDGPU_GEM_CREATE_VRAM_CLEARED;
324 if (vm->use_cpu_for_update)
325 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
327 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
328 AMDGPU_GEM_CREATE_SHADOW);
330 if (vm->pte_support_ats) {
331 init_value = AMDGPU_PTE_DEFAULT_ATC;
332 if (level != adev->vm_manager.num_level - 1)
333 init_value |= AMDGPU_PDE_PTE;
337 /* walk over the address space and allocate the page tables */
338 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
339 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
340 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
341 struct amdgpu_bo *pt;
343 if (!entry->base.bo) {
344 r = amdgpu_bo_create(adev,
345 amdgpu_vm_bo_size(adev, level),
346 AMDGPU_GPU_PAGE_SIZE, true,
347 AMDGPU_GEM_DOMAIN_VRAM,
349 NULL, resv, init_value, &pt);
353 if (vm->use_cpu_for_update) {
354 r = amdgpu_bo_kmap(pt, NULL);
356 amdgpu_bo_unref(&pt);
361 /* Keep a reference to the root directory to avoid
362 * freeing them up in the wrong order.
364 pt->parent = amdgpu_bo_ref(parent->base.bo);
368 list_add_tail(&entry->base.bo_list, &pt->va);
369 spin_lock(&vm->status_lock);
370 list_add(&entry->base.vm_status, &vm->relocated);
371 spin_unlock(&vm->status_lock);
375 if (level < adev->vm_manager.num_level) {
376 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
377 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
379 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
390 * amdgpu_vm_alloc_pts - Allocate page tables.
392 * @adev: amdgpu_device pointer
393 * @vm: VM to allocate page tables for
394 * @saddr: Start address which needs to be allocated
395 * @size: Size from start address we need.
397 * Make sure the page tables are allocated.
399 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
400 struct amdgpu_vm *vm,
401 uint64_t saddr, uint64_t size)
406 /* validate the parameters */
407 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
410 eaddr = saddr + size - 1;
411 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
412 if (last_pfn >= adev->vm_manager.max_pfn) {
413 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
414 last_pfn, adev->vm_manager.max_pfn);
418 saddr /= AMDGPU_GPU_PAGE_SIZE;
419 eaddr /= AMDGPU_GPU_PAGE_SIZE;
421 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0);
425 * amdgpu_vm_had_gpu_reset - check if reset occured since last use
427 * @adev: amdgpu_device pointer
428 * @id: VMID structure
430 * Check if GPU reset occured since last use of the VMID.
432 static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
433 struct amdgpu_vm_id *id)
435 return id->current_gpu_reset_count !=
436 atomic_read(&adev->gpu_reset_counter);
439 static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub)
441 return !!vm->reserved_vmid[vmhub];
444 /* idr_mgr->lock must be held */
445 static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm,
446 struct amdgpu_ring *ring,
447 struct amdgpu_sync *sync,
448 struct dma_fence *fence,
449 struct amdgpu_job *job)
451 struct amdgpu_device *adev = ring->adev;
452 unsigned vmhub = ring->funcs->vmhub;
453 uint64_t fence_context = adev->fence_context + ring->idx;
454 struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub];
455 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
456 struct dma_fence *updates = sync->last_vm_update;
458 struct dma_fence *flushed, *tmp;
459 bool needs_flush = vm->use_cpu_for_update;
461 flushed = id->flushed_updates;
462 if ((amdgpu_vm_had_gpu_reset(adev, id)) ||
463 (atomic64_read(&id->owner) != vm->client_id) ||
464 (job->vm_pd_addr != id->pd_gpu_addr) ||
465 (updates && (!flushed || updates->context != flushed->context ||
466 dma_fence_is_later(updates, flushed))) ||
467 (!id->last_flush || (id->last_flush->context != fence_context &&
468 !dma_fence_is_signaled(id->last_flush)))) {
470 /* to prevent one context starved by another context */
472 tmp = amdgpu_sync_peek_fence(&id->active, ring);
474 r = amdgpu_sync_fence(adev, sync, tmp);
479 /* Good we can use this VMID. Remember this submission as
482 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
486 if (updates && (!flushed || updates->context != flushed->context ||
487 dma_fence_is_later(updates, flushed))) {
488 dma_fence_put(id->flushed_updates);
489 id->flushed_updates = dma_fence_get(updates);
491 id->pd_gpu_addr = job->vm_pd_addr;
492 atomic64_set(&id->owner, vm->client_id);
493 job->vm_needs_flush = needs_flush;
495 dma_fence_put(id->last_flush);
496 id->last_flush = NULL;
498 job->vm_id = id - id_mgr->ids;
499 trace_amdgpu_vm_grab_id(vm, ring, job);
505 * amdgpu_vm_grab_id - allocate the next free VMID
507 * @vm: vm to allocate id for
508 * @ring: ring we want to submit job to
509 * @sync: sync object where we add dependencies
510 * @fence: fence protecting ID from reuse
512 * Allocate an id for the vm, adding fences to the sync obj as necessary.
514 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
515 struct amdgpu_sync *sync, struct dma_fence *fence,
516 struct amdgpu_job *job)
518 struct amdgpu_device *adev = ring->adev;
519 unsigned vmhub = ring->funcs->vmhub;
520 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
521 uint64_t fence_context = adev->fence_context + ring->idx;
522 struct dma_fence *updates = sync->last_vm_update;
523 struct amdgpu_vm_id *id, *idle;
524 struct dma_fence **fences;
528 mutex_lock(&id_mgr->lock);
529 if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) {
530 r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job);
531 mutex_unlock(&id_mgr->lock);
534 fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
536 mutex_unlock(&id_mgr->lock);
539 /* Check if we have an idle VMID */
541 list_for_each_entry(idle, &id_mgr->ids_lru, list) {
542 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
548 /* If we can't find a idle VMID to use, wait till one becomes available */
549 if (&idle->list == &id_mgr->ids_lru) {
550 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
551 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
552 struct dma_fence_array *array;
555 for (j = 0; j < i; ++j)
556 dma_fence_get(fences[j]);
558 array = dma_fence_array_create(i, fences, fence_context,
561 for (j = 0; j < i; ++j)
562 dma_fence_put(fences[j]);
569 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
570 dma_fence_put(&array->base);
574 mutex_unlock(&id_mgr->lock);
580 job->vm_needs_flush = vm->use_cpu_for_update;
581 /* Check if we can use a VMID already assigned to this VM */
582 list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
583 struct dma_fence *flushed;
584 bool needs_flush = vm->use_cpu_for_update;
586 /* Check all the prerequisites to using this VMID */
587 if (amdgpu_vm_had_gpu_reset(adev, id))
590 if (atomic64_read(&id->owner) != vm->client_id)
593 if (job->vm_pd_addr != id->pd_gpu_addr)
596 if (!id->last_flush ||
597 (id->last_flush->context != fence_context &&
598 !dma_fence_is_signaled(id->last_flush)))
601 flushed = id->flushed_updates;
602 if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
605 /* Concurrent flushes are only possible starting with Vega10 */
606 if (adev->asic_type < CHIP_VEGA10 && needs_flush)
609 /* Good we can use this VMID. Remember this submission as
612 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
616 if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
617 dma_fence_put(id->flushed_updates);
618 id->flushed_updates = dma_fence_get(updates);
624 goto no_flush_needed;
628 /* Still no ID to use? Then use the idle one found earlier */
631 /* Remember this submission as user of the VMID */
632 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
636 id->pd_gpu_addr = job->vm_pd_addr;
637 dma_fence_put(id->flushed_updates);
638 id->flushed_updates = dma_fence_get(updates);
639 atomic64_set(&id->owner, vm->client_id);
642 job->vm_needs_flush = true;
643 dma_fence_put(id->last_flush);
644 id->last_flush = NULL;
647 list_move_tail(&id->list, &id_mgr->ids_lru);
649 job->vm_id = id - id_mgr->ids;
650 trace_amdgpu_vm_grab_id(vm, ring, job);
653 mutex_unlock(&id_mgr->lock);
657 static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev,
658 struct amdgpu_vm *vm,
661 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
663 mutex_lock(&id_mgr->lock);
664 if (vm->reserved_vmid[vmhub]) {
665 list_add(&vm->reserved_vmid[vmhub]->list,
667 vm->reserved_vmid[vmhub] = NULL;
668 atomic_dec(&id_mgr->reserved_vmid_num);
670 mutex_unlock(&id_mgr->lock);
673 static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev,
674 struct amdgpu_vm *vm,
677 struct amdgpu_vm_id_manager *id_mgr;
678 struct amdgpu_vm_id *idle;
681 id_mgr = &adev->vm_manager.id_mgr[vmhub];
682 mutex_lock(&id_mgr->lock);
683 if (vm->reserved_vmid[vmhub])
685 if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
686 AMDGPU_VM_MAX_RESERVED_VMID) {
687 DRM_ERROR("Over limitation of reserved vmid\n");
688 atomic_dec(&id_mgr->reserved_vmid_num);
692 /* Select the first entry VMID */
693 idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list);
694 list_del_init(&idle->list);
695 vm->reserved_vmid[vmhub] = idle;
696 mutex_unlock(&id_mgr->lock);
700 mutex_unlock(&id_mgr->lock);
705 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
707 * @adev: amdgpu_device pointer
709 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
711 const struct amdgpu_ip_block *ip_block;
712 bool has_compute_vm_bug;
713 struct amdgpu_ring *ring;
716 has_compute_vm_bug = false;
718 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
720 /* Compute has a VM bug for GFX version < 7.
721 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
722 if (ip_block->version->major <= 7)
723 has_compute_vm_bug = true;
724 else if (ip_block->version->major == 8)
725 if (adev->gfx.mec_fw_version < 673)
726 has_compute_vm_bug = true;
729 for (i = 0; i < adev->num_rings; i++) {
730 ring = adev->rings[i];
731 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
732 /* only compute rings */
733 ring->has_compute_vm_bug = has_compute_vm_bug;
735 ring->has_compute_vm_bug = false;
739 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
740 struct amdgpu_job *job)
742 struct amdgpu_device *adev = ring->adev;
743 unsigned vmhub = ring->funcs->vmhub;
744 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
745 struct amdgpu_vm_id *id;
746 bool gds_switch_needed;
747 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
751 id = &id_mgr->ids[job->vm_id];
752 gds_switch_needed = ring->funcs->emit_gds_switch && (
753 id->gds_base != job->gds_base ||
754 id->gds_size != job->gds_size ||
755 id->gws_base != job->gws_base ||
756 id->gws_size != job->gws_size ||
757 id->oa_base != job->oa_base ||
758 id->oa_size != job->oa_size);
760 if (amdgpu_vm_had_gpu_reset(adev, id))
763 return vm_flush_needed || gds_switch_needed;
766 static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
768 return (adev->mc.real_vram_size == adev->mc.visible_vram_size);
772 * amdgpu_vm_flush - hardware flush the vm
774 * @ring: ring to use for flush
775 * @vm_id: vmid number to use
776 * @pd_addr: address of the page directory
778 * Emit a VM flush when it is necessary.
780 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
782 struct amdgpu_device *adev = ring->adev;
783 unsigned vmhub = ring->funcs->vmhub;
784 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
785 struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
786 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
787 id->gds_base != job->gds_base ||
788 id->gds_size != job->gds_size ||
789 id->gws_base != job->gws_base ||
790 id->gws_size != job->gws_size ||
791 id->oa_base != job->oa_base ||
792 id->oa_size != job->oa_size);
793 bool vm_flush_needed = job->vm_needs_flush;
794 unsigned patch_offset = 0;
797 if (amdgpu_vm_had_gpu_reset(adev, id)) {
798 gds_switch_needed = true;
799 vm_flush_needed = true;
802 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
805 if (ring->funcs->init_cond_exec)
806 patch_offset = amdgpu_ring_init_cond_exec(ring);
809 amdgpu_ring_emit_pipeline_sync(ring);
811 if (ring->funcs->emit_vm_flush && vm_flush_needed) {
812 struct dma_fence *fence;
814 trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr);
815 amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
817 r = amdgpu_fence_emit(ring, &fence);
821 mutex_lock(&id_mgr->lock);
822 dma_fence_put(id->last_flush);
823 id->last_flush = fence;
824 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
825 mutex_unlock(&id_mgr->lock);
828 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
829 id->gds_base = job->gds_base;
830 id->gds_size = job->gds_size;
831 id->gws_base = job->gws_base;
832 id->gws_size = job->gws_size;
833 id->oa_base = job->oa_base;
834 id->oa_size = job->oa_size;
835 amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
836 job->gds_size, job->gws_base,
837 job->gws_size, job->oa_base,
841 if (ring->funcs->patch_cond_exec)
842 amdgpu_ring_patch_cond_exec(ring, patch_offset);
844 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
845 if (ring->funcs->emit_switch_buffer) {
846 amdgpu_ring_emit_switch_buffer(ring);
847 amdgpu_ring_emit_switch_buffer(ring);
853 * amdgpu_vm_reset_id - reset VMID to zero
855 * @adev: amdgpu device structure
856 * @vm_id: vmid number to use
858 * Reset saved GDW, GWS and OA to force switch on next flush.
860 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
863 struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
864 struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
866 atomic64_set(&id->owner, 0);
876 * amdgpu_vm_reset_all_id - reset VMID to zero
878 * @adev: amdgpu device structure
880 * Reset VMID to force flush on next use
882 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
886 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
887 struct amdgpu_vm_id_manager *id_mgr =
888 &adev->vm_manager.id_mgr[i];
890 for (j = 1; j < id_mgr->num_ids; ++j)
891 amdgpu_vm_reset_id(adev, i, j);
896 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
899 * @bo: requested buffer object
901 * Find @bo inside the requested vm.
902 * Search inside the @bos vm list for the requested vm
903 * Returns the found bo_va or NULL if none is found
905 * Object has to be reserved!
907 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
908 struct amdgpu_bo *bo)
910 struct amdgpu_bo_va *bo_va;
912 list_for_each_entry(bo_va, &bo->va, base.bo_list) {
913 if (bo_va->base.vm == vm) {
921 * amdgpu_vm_do_set_ptes - helper to call the right asic function
923 * @params: see amdgpu_pte_update_params definition
924 * @pe: addr of the page entry
925 * @addr: dst addr to write into pe
926 * @count: number of page entries to update
927 * @incr: increase next addr by incr bytes
928 * @flags: hw access flags
930 * Traces the parameters and calls the right asic functions
931 * to setup the page table using the DMA.
933 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
934 uint64_t pe, uint64_t addr,
935 unsigned count, uint32_t incr,
938 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
941 amdgpu_vm_write_pte(params->adev, params->ib, pe,
942 addr | flags, count, incr);
945 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
951 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
953 * @params: see amdgpu_pte_update_params definition
954 * @pe: addr of the page entry
955 * @addr: dst addr to write into pe
956 * @count: number of page entries to update
957 * @incr: increase next addr by incr bytes
958 * @flags: hw access flags
960 * Traces the parameters and calls the DMA function to copy the PTEs.
962 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
963 uint64_t pe, uint64_t addr,
964 unsigned count, uint32_t incr,
967 uint64_t src = (params->src + (addr >> 12) * 8);
970 trace_amdgpu_vm_copy_ptes(pe, src, count);
972 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
976 * amdgpu_vm_map_gart - Resolve gart mapping of addr
978 * @pages_addr: optional DMA address to use for lookup
979 * @addr: the unmapped addr
981 * Look up the physical address of the page that the pte resolves
982 * to and return the pointer for the page table entry.
984 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
988 /* page table offset */
989 result = pages_addr[addr >> PAGE_SHIFT];
991 /* in case cpu page size != gpu page size*/
992 result |= addr & (~PAGE_MASK);
994 result &= 0xFFFFFFFFFFFFF000ULL;
1000 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
1002 * @params: see amdgpu_pte_update_params definition
1003 * @pe: kmap addr of the page entry
1004 * @addr: dst addr to write into pe
1005 * @count: number of page entries to update
1006 * @incr: increase next addr by incr bytes
1007 * @flags: hw access flags
1009 * Write count number of PT/PD entries directly.
1011 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
1012 uint64_t pe, uint64_t addr,
1013 unsigned count, uint32_t incr,
1019 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
1021 for (i = 0; i < count; i++) {
1022 value = params->pages_addr ?
1023 amdgpu_vm_map_gart(params->pages_addr, addr) :
1025 amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
1031 static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1034 struct amdgpu_sync sync;
1037 amdgpu_sync_create(&sync);
1038 amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
1039 r = amdgpu_sync_wait(&sync, true);
1040 amdgpu_sync_free(&sync);
1046 * amdgpu_vm_update_level - update a single level in the hierarchy
1048 * @adev: amdgpu_device pointer
1050 * @parent: parent directory
1052 * Makes sure all entries in @parent are up to date.
1053 * Returns 0 for success, error for failure.
1055 static int amdgpu_vm_update_level(struct amdgpu_device *adev,
1056 struct amdgpu_vm *vm,
1057 struct amdgpu_vm_pt *parent)
1059 struct amdgpu_bo *shadow;
1060 struct amdgpu_ring *ring = NULL;
1061 uint64_t pd_addr, shadow_addr = 0;
1062 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
1063 unsigned count = 0, pt_idx, ndw = 0;
1064 struct amdgpu_job *job;
1065 struct amdgpu_pte_update_params params;
1066 struct dma_fence *fence = NULL;
1071 if (!parent->entries)
1074 memset(¶ms, 0, sizeof(params));
1076 shadow = parent->base.bo->shadow;
1078 if (vm->use_cpu_for_update) {
1079 pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
1080 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
1084 params.func = amdgpu_vm_cpu_set_ptes;
1086 ring = container_of(vm->entity.sched, struct amdgpu_ring,
1092 /* assume the worst case */
1093 ndw += parent->last_entry_used * 6;
1095 pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
1098 shadow_addr = amdgpu_bo_gpu_offset(shadow);
1104 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1108 params.ib = &job->ibs[0];
1109 params.func = amdgpu_vm_do_set_ptes;
1113 /* walk over the address space and update the directory */
1114 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1115 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1116 struct amdgpu_bo *bo = entry->base.bo;
1122 spin_lock(&vm->status_lock);
1123 list_del_init(&entry->base.vm_status);
1124 spin_unlock(&vm->status_lock);
1126 pt = amdgpu_bo_gpu_offset(bo);
1127 pt = amdgpu_gart_get_vm_pde(adev, pt);
1128 /* Don't update huge pages here */
1129 if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) ||
1130 parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID))
1133 parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID;
1135 pde = pd_addr + pt_idx * 8;
1136 incr = amdgpu_bo_size(bo);
1137 if (((last_pde + 8 * count) != pde) ||
1138 ((last_pt + incr * count) != pt) ||
1139 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
1143 params.func(¶ms,
1149 params.func(¶ms, last_pde,
1150 last_pt, count, incr,
1156 last_shadow = shadow_addr + pt_idx * 8;
1164 if (vm->root.base.bo->shadow)
1165 params.func(¶ms, last_shadow, last_pt,
1166 count, incr, AMDGPU_PTE_VALID);
1168 params.func(¶ms, last_pde, last_pt,
1169 count, incr, AMDGPU_PTE_VALID);
1172 if (!vm->use_cpu_for_update) {
1173 if (params.ib->length_dw == 0) {
1174 amdgpu_job_free(job);
1176 amdgpu_ring_pad_ib(ring, params.ib);
1177 amdgpu_sync_resv(adev, &job->sync,
1178 parent->base.bo->tbo.resv,
1179 AMDGPU_FENCE_OWNER_VM, false);
1181 amdgpu_sync_resv(adev, &job->sync,
1183 AMDGPU_FENCE_OWNER_VM, false);
1185 WARN_ON(params.ib->length_dw > ndw);
1186 r = amdgpu_job_submit(job, ring, &vm->entity,
1187 AMDGPU_FENCE_OWNER_VM, &fence);
1191 amdgpu_bo_fence(parent->base.bo, fence, true);
1192 dma_fence_put(vm->last_update);
1193 vm->last_update = fence;
1200 amdgpu_job_free(job);
1205 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
1207 * @parent: parent PD
1209 * Mark all PD level as invalid after an error.
1211 static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm,
1212 struct amdgpu_vm_pt *parent)
1217 * Recurse into the subdirectories. This recursion is harmless because
1218 * we only have a maximum of 5 layers.
1220 for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) {
1221 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1223 if (!entry->base.bo)
1226 entry->addr = ~0ULL;
1227 spin_lock(&vm->status_lock);
1228 if (list_empty(&entry->base.vm_status))
1229 list_add(&entry->base.vm_status, &vm->relocated);
1230 spin_unlock(&vm->status_lock);
1231 amdgpu_vm_invalidate_level(vm, entry);
1236 * amdgpu_vm_update_directories - make sure that all directories are valid
1238 * @adev: amdgpu_device pointer
1241 * Makes sure all directories are up to date.
1242 * Returns 0 for success, error for failure.
1244 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1245 struct amdgpu_vm *vm)
1249 spin_lock(&vm->status_lock);
1250 while (!list_empty(&vm->relocated)) {
1251 struct amdgpu_vm_bo_base *bo_base;
1252 struct amdgpu_bo *bo;
1254 bo_base = list_first_entry(&vm->relocated,
1255 struct amdgpu_vm_bo_base,
1257 spin_unlock(&vm->status_lock);
1259 bo = bo_base->bo->parent;
1261 struct amdgpu_vm_bo_base *parent;
1262 struct amdgpu_vm_pt *pt;
1264 parent = list_first_entry(&bo->va,
1265 struct amdgpu_vm_bo_base,
1267 pt = container_of(parent, struct amdgpu_vm_pt, base);
1269 r = amdgpu_vm_update_level(adev, vm, pt);
1271 amdgpu_vm_invalidate_level(vm, &vm->root);
1274 spin_lock(&vm->status_lock);
1276 spin_lock(&vm->status_lock);
1277 list_del_init(&bo_base->vm_status);
1280 spin_unlock(&vm->status_lock);
1282 if (vm->use_cpu_for_update) {
1285 amdgpu_gart_flush_gpu_tlb(adev, 0);
1292 * amdgpu_vm_find_entry - find the entry for an address
1294 * @p: see amdgpu_pte_update_params definition
1295 * @addr: virtual address in question
1296 * @entry: resulting entry or NULL
1297 * @parent: parent entry
1299 * Find the vm_pt entry and it's parent for the given address.
1301 void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
1302 struct amdgpu_vm_pt **entry,
1303 struct amdgpu_vm_pt **parent)
1305 unsigned idx, level = p->adev->vm_manager.num_level;
1308 *entry = &p->vm->root;
1309 while ((*entry)->entries) {
1310 idx = addr >> (p->adev->vm_manager.block_size * level--);
1311 idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
1313 *entry = &(*entry)->entries[idx];
1321 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
1323 * @p: see amdgpu_pte_update_params definition
1324 * @entry: vm_pt entry to check
1325 * @parent: parent entry
1326 * @nptes: number of PTEs updated with this operation
1327 * @dst: destination address where the PTEs should point to
1328 * @flags: access flags fro the PTEs
1330 * Check if we can update the PD with a huge page.
1332 static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
1333 struct amdgpu_vm_pt *entry,
1334 struct amdgpu_vm_pt *parent,
1335 unsigned nptes, uint64_t dst,
1338 bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes);
1339 uint64_t pd_addr, pde;
1341 /* In the case of a mixed PT the PDE must point to it*/
1342 if (p->adev->asic_type < CHIP_VEGA10 ||
1343 nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
1345 !(flags & AMDGPU_PTE_VALID)) {
1347 dst = amdgpu_bo_gpu_offset(entry->base.bo);
1348 dst = amdgpu_gart_get_vm_pde(p->adev, dst);
1349 flags = AMDGPU_PTE_VALID;
1351 /* Set the huge page flag to stop scanning at this PDE */
1352 flags |= AMDGPU_PDE_PTE;
1355 if (entry->addr == (dst | flags))
1358 entry->addr = (dst | flags);
1360 if (use_cpu_update) {
1361 /* In case a huge page is replaced with a system
1362 * memory mapping, p->pages_addr != NULL and
1363 * amdgpu_vm_cpu_set_ptes would try to translate dst
1364 * through amdgpu_vm_map_gart. But dst is already a
1365 * GPU address (of the page table). Disable
1366 * amdgpu_vm_map_gart temporarily.
1370 tmp = p->pages_addr;
1371 p->pages_addr = NULL;
1373 pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo);
1374 pde = pd_addr + (entry - parent->entries) * 8;
1375 amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
1377 p->pages_addr = tmp;
1379 if (parent->base.bo->shadow) {
1380 pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow);
1381 pde = pd_addr + (entry - parent->entries) * 8;
1382 amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
1384 pd_addr = amdgpu_bo_gpu_offset(parent->base.bo);
1385 pde = pd_addr + (entry - parent->entries) * 8;
1386 amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags);
1391 * amdgpu_vm_update_ptes - make sure that page tables are valid
1393 * @params: see amdgpu_pte_update_params definition
1395 * @start: start of GPU address range
1396 * @end: end of GPU address range
1397 * @dst: destination address to map to, the next dst inside the function
1398 * @flags: mapping flags
1400 * Update the page tables in the range @start - @end.
1401 * Returns 0 for success, -EINVAL for failure.
1403 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1404 uint64_t start, uint64_t end,
1405 uint64_t dst, uint64_t flags)
1407 struct amdgpu_device *adev = params->adev;
1408 const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1410 uint64_t addr, pe_start;
1411 struct amdgpu_bo *pt;
1413 bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes);
1415 /* walk over the address space and update the page tables */
1416 for (addr = start; addr < end; addr += nptes,
1417 dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
1418 struct amdgpu_vm_pt *entry, *parent;
1420 amdgpu_vm_get_entry(params, addr, &entry, &parent);
1424 if ((addr & ~mask) == (end & ~mask))
1427 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1429 amdgpu_vm_handle_huge_pages(params, entry, parent,
1431 /* We don't need to update PTEs for huge pages */
1432 if (entry->addr & AMDGPU_PDE_PTE)
1435 pt = entry->base.bo;
1436 if (use_cpu_update) {
1437 pe_start = (unsigned long)amdgpu_bo_kptr(pt);
1440 pe_start = amdgpu_bo_gpu_offset(pt->shadow);
1441 pe_start += (addr & mask) * 8;
1442 params->func(params, pe_start, dst, nptes,
1443 AMDGPU_GPU_PAGE_SIZE, flags);
1445 pe_start = amdgpu_bo_gpu_offset(pt);
1448 pe_start += (addr & mask) * 8;
1449 params->func(params, pe_start, dst, nptes,
1450 AMDGPU_GPU_PAGE_SIZE, flags);
1457 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1459 * @params: see amdgpu_pte_update_params definition
1461 * @start: first PTE to handle
1462 * @end: last PTE to handle
1463 * @dst: addr those PTEs should point to
1464 * @flags: hw mapping flags
1465 * Returns 0 for success, -EINVAL for failure.
1467 static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1468 uint64_t start, uint64_t end,
1469 uint64_t dst, uint64_t flags)
1472 * The MC L1 TLB supports variable sized pages, based on a fragment
1473 * field in the PTE. When this field is set to a non-zero value, page
1474 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1475 * flags are considered valid for all PTEs within the fragment range
1476 * and corresponding mappings are assumed to be physically contiguous.
1478 * The L1 TLB can store a single PTE for the whole fragment,
1479 * significantly increasing the space available for translation
1480 * caching. This leads to large improvements in throughput when the
1481 * TLB is under pressure.
1483 * The L2 TLB distributes small and large fragments into two
1484 * asymmetric partitions. The large fragment cache is significantly
1485 * larger. Thus, we try to use large fragments wherever possible.
1486 * Userspace can support this by aligning virtual base address and
1487 * allocation size to the fragment size.
1489 unsigned max_frag = params->adev->vm_manager.fragment_size;
1492 /* system pages are non continuously */
1493 if (params->src || !(flags & AMDGPU_PTE_VALID))
1494 return amdgpu_vm_update_ptes(params, start, end, dst, flags);
1496 while (start != end) {
1497 uint64_t frag_flags, frag_end;
1500 /* This intentionally wraps around if no bit is set */
1501 frag = min((unsigned)ffs(start) - 1,
1502 (unsigned)fls64(end - start) - 1);
1503 if (frag >= max_frag) {
1504 frag_flags = AMDGPU_PTE_FRAG(max_frag);
1505 frag_end = end & ~((1ULL << max_frag) - 1);
1507 frag_flags = AMDGPU_PTE_FRAG(frag);
1508 frag_end = start + (1 << frag);
1511 r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
1512 flags | frag_flags);
1516 dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
1524 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1526 * @adev: amdgpu_device pointer
1527 * @exclusive: fence we need to sync to
1528 * @pages_addr: DMA addresses to use for mapping
1530 * @start: start of mapped range
1531 * @last: last mapped entry
1532 * @flags: flags for the entries
1533 * @addr: addr to set the area to
1534 * @fence: optional resulting fence
1536 * Fill in the page table entries between @start and @last.
1537 * Returns 0 for success, -EINVAL for failure.
1539 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1540 struct dma_fence *exclusive,
1541 dma_addr_t *pages_addr,
1542 struct amdgpu_vm *vm,
1543 uint64_t start, uint64_t last,
1544 uint64_t flags, uint64_t addr,
1545 struct dma_fence **fence)
1547 struct amdgpu_ring *ring;
1548 void *owner = AMDGPU_FENCE_OWNER_VM;
1549 unsigned nptes, ncmds, ndw;
1550 struct amdgpu_job *job;
1551 struct amdgpu_pte_update_params params;
1552 struct dma_fence *f = NULL;
1555 memset(¶ms, 0, sizeof(params));
1559 /* sync to everything on unmapping */
1560 if (!(flags & AMDGPU_PTE_VALID))
1561 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1563 if (vm->use_cpu_for_update) {
1564 /* params.src is used as flag to indicate system Memory */
1568 /* Wait for PT BOs to be free. PTs share the same resv. object
1571 r = amdgpu_vm_wait_pd(adev, vm, owner);
1575 params.func = amdgpu_vm_cpu_set_ptes;
1576 params.pages_addr = pages_addr;
1577 return amdgpu_vm_frag_ptes(¶ms, start, last + 1,
1581 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1583 nptes = last - start + 1;
1586 * reserve space for two commands every (1 << BLOCK_SIZE)
1587 * entries or 2k dwords (whatever is smaller)
1589 * The second command is for the shadow pagetables.
1591 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1596 /* one PDE write for each huge page */
1597 ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6;
1600 /* copy commands needed */
1601 ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
1606 params.func = amdgpu_vm_do_copy_ptes;
1609 /* set page commands needed */
1610 ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
1612 /* extra commands for begin/end fragments */
1613 ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw
1614 * adev->vm_manager.fragment_size;
1616 params.func = amdgpu_vm_do_set_ptes;
1619 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1623 params.ib = &job->ibs[0];
1629 /* Put the PTEs at the end of the IB. */
1630 i = ndw - nptes * 2;
1631 pte= (uint64_t *)&(job->ibs->ptr[i]);
1632 params.src = job->ibs->gpu_addr + i * 4;
1634 for (i = 0; i < nptes; ++i) {
1635 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1636 AMDGPU_GPU_PAGE_SIZE);
1642 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1646 r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1651 r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
1655 r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1659 amdgpu_ring_pad_ib(ring, params.ib);
1660 WARN_ON(params.ib->length_dw > ndw);
1661 r = amdgpu_job_submit(job, ring, &vm->entity,
1662 AMDGPU_FENCE_OWNER_VM, &f);
1666 amdgpu_bo_fence(vm->root.base.bo, f, true);
1667 dma_fence_put(*fence);
1672 amdgpu_job_free(job);
1673 amdgpu_vm_invalidate_level(vm, &vm->root);
1678 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1680 * @adev: amdgpu_device pointer
1681 * @exclusive: fence we need to sync to
1682 * @pages_addr: DMA addresses to use for mapping
1684 * @mapping: mapped range and flags to use for the update
1685 * @flags: HW flags for the mapping
1686 * @nodes: array of drm_mm_nodes with the MC addresses
1687 * @fence: optional resulting fence
1689 * Split the mapping into smaller chunks so that each update fits
1691 * Returns 0 for success, -EINVAL for failure.
1693 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1694 struct dma_fence *exclusive,
1695 dma_addr_t *pages_addr,
1696 struct amdgpu_vm *vm,
1697 struct amdgpu_bo_va_mapping *mapping,
1699 struct drm_mm_node *nodes,
1700 struct dma_fence **fence)
1702 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1703 uint64_t pfn, start = mapping->start;
1706 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1707 * but in case of something, we filter the flags in first place
1709 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1710 flags &= ~AMDGPU_PTE_READABLE;
1711 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1712 flags &= ~AMDGPU_PTE_WRITEABLE;
1714 flags &= ~AMDGPU_PTE_EXECUTABLE;
1715 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1717 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1718 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1720 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1721 (adev->asic_type >= CHIP_VEGA10)) {
1722 flags |= AMDGPU_PTE_PRT;
1723 flags &= ~AMDGPU_PTE_VALID;
1726 trace_amdgpu_vm_bo_update(mapping);
1728 pfn = mapping->offset >> PAGE_SHIFT;
1730 while (pfn >= nodes->size) {
1737 dma_addr_t *dma_addr = NULL;
1738 uint64_t max_entries;
1739 uint64_t addr, last;
1742 addr = nodes->start << PAGE_SHIFT;
1743 max_entries = (nodes->size - pfn) *
1744 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1747 max_entries = S64_MAX;
1753 max_entries = min(max_entries, 16ull * 1024ull);
1754 for (count = 1; count < max_entries; ++count) {
1755 uint64_t idx = pfn + count;
1757 if (pages_addr[idx] !=
1758 (pages_addr[idx - 1] + PAGE_SIZE))
1762 if (count < min_linear_pages) {
1763 addr = pfn << PAGE_SHIFT;
1764 dma_addr = pages_addr;
1766 addr = pages_addr[pfn];
1767 max_entries = count;
1770 } else if (flags & AMDGPU_PTE_VALID) {
1771 addr += adev->vm_manager.vram_base_offset;
1772 addr += pfn << PAGE_SHIFT;
1775 last = min((uint64_t)mapping->last, start + max_entries - 1);
1776 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1777 start, last, flags, addr,
1782 pfn += last - start + 1;
1783 if (nodes && nodes->size == pfn) {
1789 } while (unlikely(start != mapping->last + 1));
1795 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1797 * @adev: amdgpu_device pointer
1798 * @bo_va: requested BO and VM object
1799 * @clear: if true clear the entries
1801 * Fill in the page table entries for @bo_va.
1802 * Returns 0 for success, -EINVAL for failure.
1804 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1805 struct amdgpu_bo_va *bo_va,
1808 struct amdgpu_bo *bo = bo_va->base.bo;
1809 struct amdgpu_vm *vm = bo_va->base.vm;
1810 struct amdgpu_bo_va_mapping *mapping;
1811 dma_addr_t *pages_addr = NULL;
1812 struct ttm_mem_reg *mem;
1813 struct drm_mm_node *nodes;
1814 struct dma_fence *exclusive, **last_update;
1818 if (clear || !bo_va->base.bo) {
1823 struct ttm_dma_tt *ttm;
1825 mem = &bo_va->base.bo->tbo.mem;
1826 nodes = mem->mm_node;
1827 if (mem->mem_type == TTM_PL_TT) {
1828 ttm = container_of(bo_va->base.bo->tbo.ttm,
1829 struct ttm_dma_tt, ttm);
1830 pages_addr = ttm->dma_address;
1832 exclusive = reservation_object_get_excl(bo->tbo.resv);
1836 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1840 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
1841 last_update = &vm->last_update;
1843 last_update = &bo_va->last_pt_update;
1845 if (!clear && bo_va->base.moved) {
1846 bo_va->base.moved = false;
1847 list_splice_init(&bo_va->valids, &bo_va->invalids);
1849 } else if (bo_va->cleared != clear) {
1850 list_splice_init(&bo_va->valids, &bo_va->invalids);
1853 list_for_each_entry(mapping, &bo_va->invalids, list) {
1854 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1855 mapping, flags, nodes,
1861 if (vm->use_cpu_for_update) {
1864 amdgpu_gart_flush_gpu_tlb(adev, 0);
1867 spin_lock(&vm->status_lock);
1868 list_del_init(&bo_va->base.vm_status);
1869 spin_unlock(&vm->status_lock);
1871 list_splice_init(&bo_va->invalids, &bo_va->valids);
1872 bo_va->cleared = clear;
1874 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1875 list_for_each_entry(mapping, &bo_va->valids, list)
1876 trace_amdgpu_vm_bo_mapping(mapping);
1883 * amdgpu_vm_update_prt_state - update the global PRT state
1885 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1887 unsigned long flags;
1890 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1891 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1892 adev->gart.gart_funcs->set_prt(adev, enable);
1893 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1897 * amdgpu_vm_prt_get - add a PRT user
1899 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1901 if (!adev->gart.gart_funcs->set_prt)
1904 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1905 amdgpu_vm_update_prt_state(adev);
1909 * amdgpu_vm_prt_put - drop a PRT user
1911 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1913 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1914 amdgpu_vm_update_prt_state(adev);
1918 * amdgpu_vm_prt_cb - callback for updating the PRT status
1920 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1922 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1924 amdgpu_vm_prt_put(cb->adev);
1929 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1931 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1932 struct dma_fence *fence)
1934 struct amdgpu_prt_cb *cb;
1936 if (!adev->gart.gart_funcs->set_prt)
1939 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1941 /* Last resort when we are OOM */
1943 dma_fence_wait(fence, false);
1945 amdgpu_vm_prt_put(adev);
1948 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1950 amdgpu_vm_prt_cb(fence, &cb->cb);
1955 * amdgpu_vm_free_mapping - free a mapping
1957 * @adev: amdgpu_device pointer
1959 * @mapping: mapping to be freed
1960 * @fence: fence of the unmap operation
1962 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1964 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1965 struct amdgpu_vm *vm,
1966 struct amdgpu_bo_va_mapping *mapping,
1967 struct dma_fence *fence)
1969 if (mapping->flags & AMDGPU_PTE_PRT)
1970 amdgpu_vm_add_prt_cb(adev, fence);
1975 * amdgpu_vm_prt_fini - finish all prt mappings
1977 * @adev: amdgpu_device pointer
1980 * Register a cleanup callback to disable PRT support after VM dies.
1982 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1984 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1985 struct dma_fence *excl, **shared;
1986 unsigned i, shared_count;
1989 r = reservation_object_get_fences_rcu(resv, &excl,
1990 &shared_count, &shared);
1992 /* Not enough memory to grab the fence list, as last resort
1993 * block for all the fences to complete.
1995 reservation_object_wait_timeout_rcu(resv, true, false,
1996 MAX_SCHEDULE_TIMEOUT);
2000 /* Add a callback for each fence in the reservation object */
2001 amdgpu_vm_prt_get(adev);
2002 amdgpu_vm_add_prt_cb(adev, excl);
2004 for (i = 0; i < shared_count; ++i) {
2005 amdgpu_vm_prt_get(adev);
2006 amdgpu_vm_add_prt_cb(adev, shared[i]);
2013 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2015 * @adev: amdgpu_device pointer
2017 * @fence: optional resulting fence (unchanged if no work needed to be done
2018 * or if an error occurred)
2020 * Make sure all freed BOs are cleared in the PT.
2021 * Returns 0 for success.
2023 * PTs have to be reserved and mutex must be locked!
2025 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2026 struct amdgpu_vm *vm,
2027 struct dma_fence **fence)
2029 struct amdgpu_bo_va_mapping *mapping;
2030 struct dma_fence *f = NULL;
2032 uint64_t init_pte_value = 0;
2034 while (!list_empty(&vm->freed)) {
2035 mapping = list_first_entry(&vm->freed,
2036 struct amdgpu_bo_va_mapping, list);
2037 list_del(&mapping->list);
2039 if (vm->pte_support_ats)
2040 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2042 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
2043 mapping->start, mapping->last,
2044 init_pte_value, 0, &f);
2045 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2053 dma_fence_put(*fence);
2064 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2066 * @adev: amdgpu_device pointer
2068 * @sync: sync object to add fences to
2070 * Make sure all BOs which are moved are updated in the PTs.
2071 * Returns 0 for success.
2073 * PTs have to be reserved!
2075 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2076 struct amdgpu_vm *vm)
2081 spin_lock(&vm->status_lock);
2082 while (!list_empty(&vm->moved)) {
2083 struct amdgpu_bo_va *bo_va;
2085 bo_va = list_first_entry(&vm->moved,
2086 struct amdgpu_bo_va, base.vm_status);
2087 spin_unlock(&vm->status_lock);
2089 /* Per VM BOs never need to bo cleared in the page tables */
2090 clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv;
2092 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2096 spin_lock(&vm->status_lock);
2098 spin_unlock(&vm->status_lock);
2104 * amdgpu_vm_bo_add - add a bo to a specific vm
2106 * @adev: amdgpu_device pointer
2108 * @bo: amdgpu buffer object
2110 * Add @bo into the requested vm.
2111 * Add @bo to the list of bos associated with the vm
2112 * Returns newly added bo_va or NULL for failure
2114 * Object has to be reserved!
2116 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2117 struct amdgpu_vm *vm,
2118 struct amdgpu_bo *bo)
2120 struct amdgpu_bo_va *bo_va;
2122 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2123 if (bo_va == NULL) {
2126 bo_va->base.vm = vm;
2127 bo_va->base.bo = bo;
2128 INIT_LIST_HEAD(&bo_va->base.bo_list);
2129 INIT_LIST_HEAD(&bo_va->base.vm_status);
2131 bo_va->ref_count = 1;
2132 INIT_LIST_HEAD(&bo_va->valids);
2133 INIT_LIST_HEAD(&bo_va->invalids);
2136 list_add_tail(&bo_va->base.bo_list, &bo->va);
2143 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2145 * @adev: amdgpu_device pointer
2146 * @bo_va: bo_va to store the address
2147 * @mapping: the mapping to insert
2149 * Insert a new mapping into all structures.
2151 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2152 struct amdgpu_bo_va *bo_va,
2153 struct amdgpu_bo_va_mapping *mapping)
2155 struct amdgpu_vm *vm = bo_va->base.vm;
2156 struct amdgpu_bo *bo = bo_va->base.bo;
2158 mapping->bo_va = bo_va;
2159 list_add(&mapping->list, &bo_va->invalids);
2160 amdgpu_vm_it_insert(mapping, &vm->va);
2162 if (mapping->flags & AMDGPU_PTE_PRT)
2163 amdgpu_vm_prt_get(adev);
2165 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2166 spin_lock(&vm->status_lock);
2167 if (list_empty(&bo_va->base.vm_status))
2168 list_add(&bo_va->base.vm_status, &vm->moved);
2169 spin_unlock(&vm->status_lock);
2171 trace_amdgpu_vm_bo_map(bo_va, mapping);
2175 * amdgpu_vm_bo_map - map bo inside a vm
2177 * @adev: amdgpu_device pointer
2178 * @bo_va: bo_va to store the address
2179 * @saddr: where to map the BO
2180 * @offset: requested offset in the BO
2181 * @flags: attributes of pages (read/write/valid/etc.)
2183 * Add a mapping of the BO at the specefied addr into the VM.
2184 * Returns 0 for success, error for failure.
2186 * Object has to be reserved and unreserved outside!
2188 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2189 struct amdgpu_bo_va *bo_va,
2190 uint64_t saddr, uint64_t offset,
2191 uint64_t size, uint64_t flags)
2193 struct amdgpu_bo_va_mapping *mapping, *tmp;
2194 struct amdgpu_bo *bo = bo_va->base.bo;
2195 struct amdgpu_vm *vm = bo_va->base.vm;
2198 /* validate the parameters */
2199 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2200 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2203 /* make sure object fit at this offset */
2204 eaddr = saddr + size - 1;
2205 if (saddr >= eaddr ||
2206 (bo && offset + size > amdgpu_bo_size(bo)))
2209 saddr /= AMDGPU_GPU_PAGE_SIZE;
2210 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2212 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2214 /* bo and tmp overlap, invalid addr */
2215 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2216 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2217 tmp->start, tmp->last + 1);
2221 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2225 mapping->start = saddr;
2226 mapping->last = eaddr;
2227 mapping->offset = offset;
2228 mapping->flags = flags;
2230 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2236 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2238 * @adev: amdgpu_device pointer
2239 * @bo_va: bo_va to store the address
2240 * @saddr: where to map the BO
2241 * @offset: requested offset in the BO
2242 * @flags: attributes of pages (read/write/valid/etc.)
2244 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2245 * mappings as we do so.
2246 * Returns 0 for success, error for failure.
2248 * Object has to be reserved and unreserved outside!
2250 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2251 struct amdgpu_bo_va *bo_va,
2252 uint64_t saddr, uint64_t offset,
2253 uint64_t size, uint64_t flags)
2255 struct amdgpu_bo_va_mapping *mapping;
2256 struct amdgpu_bo *bo = bo_va->base.bo;
2260 /* validate the parameters */
2261 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2262 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2265 /* make sure object fit at this offset */
2266 eaddr = saddr + size - 1;
2267 if (saddr >= eaddr ||
2268 (bo && offset + size > amdgpu_bo_size(bo)))
2271 /* Allocate all the needed memory */
2272 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2276 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2282 saddr /= AMDGPU_GPU_PAGE_SIZE;
2283 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2285 mapping->start = saddr;
2286 mapping->last = eaddr;
2287 mapping->offset = offset;
2288 mapping->flags = flags;
2290 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2296 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2298 * @adev: amdgpu_device pointer
2299 * @bo_va: bo_va to remove the address from
2300 * @saddr: where to the BO is mapped
2302 * Remove a mapping of the BO at the specefied addr from the VM.
2303 * Returns 0 for success, error for failure.
2305 * Object has to be reserved and unreserved outside!
2307 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2308 struct amdgpu_bo_va *bo_va,
2311 struct amdgpu_bo_va_mapping *mapping;
2312 struct amdgpu_vm *vm = bo_va->base.vm;
2315 saddr /= AMDGPU_GPU_PAGE_SIZE;
2317 list_for_each_entry(mapping, &bo_va->valids, list) {
2318 if (mapping->start == saddr)
2322 if (&mapping->list == &bo_va->valids) {
2325 list_for_each_entry(mapping, &bo_va->invalids, list) {
2326 if (mapping->start == saddr)
2330 if (&mapping->list == &bo_va->invalids)
2334 list_del(&mapping->list);
2335 amdgpu_vm_it_remove(mapping, &vm->va);
2336 mapping->bo_va = NULL;
2337 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2340 list_add(&mapping->list, &vm->freed);
2342 amdgpu_vm_free_mapping(adev, vm, mapping,
2343 bo_va->last_pt_update);
2349 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2351 * @adev: amdgpu_device pointer
2352 * @vm: VM structure to use
2353 * @saddr: start of the range
2354 * @size: size of the range
2356 * Remove all mappings in a range, split them as appropriate.
2357 * Returns 0 for success, error for failure.
2359 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2360 struct amdgpu_vm *vm,
2361 uint64_t saddr, uint64_t size)
2363 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2367 eaddr = saddr + size - 1;
2368 saddr /= AMDGPU_GPU_PAGE_SIZE;
2369 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2371 /* Allocate all the needed memory */
2372 before = kzalloc(sizeof(*before), GFP_KERNEL);
2375 INIT_LIST_HEAD(&before->list);
2377 after = kzalloc(sizeof(*after), GFP_KERNEL);
2382 INIT_LIST_HEAD(&after->list);
2384 /* Now gather all removed mappings */
2385 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2387 /* Remember mapping split at the start */
2388 if (tmp->start < saddr) {
2389 before->start = tmp->start;
2390 before->last = saddr - 1;
2391 before->offset = tmp->offset;
2392 before->flags = tmp->flags;
2393 list_add(&before->list, &tmp->list);
2396 /* Remember mapping split at the end */
2397 if (tmp->last > eaddr) {
2398 after->start = eaddr + 1;
2399 after->last = tmp->last;
2400 after->offset = tmp->offset;
2401 after->offset += after->start - tmp->start;
2402 after->flags = tmp->flags;
2403 list_add(&after->list, &tmp->list);
2406 list_del(&tmp->list);
2407 list_add(&tmp->list, &removed);
2409 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2412 /* And free them up */
2413 list_for_each_entry_safe(tmp, next, &removed, list) {
2414 amdgpu_vm_it_remove(tmp, &vm->va);
2415 list_del(&tmp->list);
2417 if (tmp->start < saddr)
2419 if (tmp->last > eaddr)
2423 list_add(&tmp->list, &vm->freed);
2424 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2427 /* Insert partial mapping before the range */
2428 if (!list_empty(&before->list)) {
2429 amdgpu_vm_it_insert(before, &vm->va);
2430 if (before->flags & AMDGPU_PTE_PRT)
2431 amdgpu_vm_prt_get(adev);
2436 /* Insert partial mapping after the range */
2437 if (!list_empty(&after->list)) {
2438 amdgpu_vm_it_insert(after, &vm->va);
2439 if (after->flags & AMDGPU_PTE_PRT)
2440 amdgpu_vm_prt_get(adev);
2449 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2451 * @vm: the requested VM
2453 * Find a mapping by it's address.
2455 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2458 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2462 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2464 * @adev: amdgpu_device pointer
2465 * @bo_va: requested bo_va
2467 * Remove @bo_va->bo from the requested vm.
2469 * Object have to be reserved!
2471 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2472 struct amdgpu_bo_va *bo_va)
2474 struct amdgpu_bo_va_mapping *mapping, *next;
2475 struct amdgpu_vm *vm = bo_va->base.vm;
2477 list_del(&bo_va->base.bo_list);
2479 spin_lock(&vm->status_lock);
2480 list_del(&bo_va->base.vm_status);
2481 spin_unlock(&vm->status_lock);
2483 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2484 list_del(&mapping->list);
2485 amdgpu_vm_it_remove(mapping, &vm->va);
2486 mapping->bo_va = NULL;
2487 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2488 list_add(&mapping->list, &vm->freed);
2490 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2491 list_del(&mapping->list);
2492 amdgpu_vm_it_remove(mapping, &vm->va);
2493 amdgpu_vm_free_mapping(adev, vm, mapping,
2494 bo_va->last_pt_update);
2497 dma_fence_put(bo_va->last_pt_update);
2502 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2504 * @adev: amdgpu_device pointer
2506 * @bo: amdgpu buffer object
2508 * Mark @bo as invalid.
2510 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2511 struct amdgpu_bo *bo, bool evicted)
2513 struct amdgpu_vm_bo_base *bo_base;
2515 list_for_each_entry(bo_base, &bo->va, bo_list) {
2516 struct amdgpu_vm *vm = bo_base->vm;
2518 bo_base->moved = true;
2519 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2520 spin_lock(&bo_base->vm->status_lock);
2521 if (bo->tbo.type == ttm_bo_type_kernel)
2522 list_move(&bo_base->vm_status, &vm->evicted);
2524 list_move_tail(&bo_base->vm_status,
2526 spin_unlock(&bo_base->vm->status_lock);
2530 if (bo->tbo.type == ttm_bo_type_kernel) {
2531 spin_lock(&bo_base->vm->status_lock);
2532 if (list_empty(&bo_base->vm_status))
2533 list_add(&bo_base->vm_status, &vm->relocated);
2534 spin_unlock(&bo_base->vm->status_lock);
2538 spin_lock(&bo_base->vm->status_lock);
2539 if (list_empty(&bo_base->vm_status))
2540 list_add(&bo_base->vm_status, &vm->moved);
2541 spin_unlock(&bo_base->vm->status_lock);
2545 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2547 /* Total bits covered by PD + PTs */
2548 unsigned bits = ilog2(vm_size) + 18;
2550 /* Make sure the PD is 4K in size up to 8GB address space.
2551 Above that split equal between PD and PTs */
2555 return ((bits + 3) / 2);
2559 * amdgpu_vm_set_fragment_size - adjust fragment size in PTE
2561 * @adev: amdgpu_device pointer
2562 * @fragment_size_default: the default fragment size if it's set auto
2564 void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
2565 uint32_t fragment_size_default)
2567 if (amdgpu_vm_fragment_size == -1)
2568 adev->vm_manager.fragment_size = fragment_size_default;
2570 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2574 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2576 * @adev: amdgpu_device pointer
2577 * @vm_size: the default vm size if it's set auto
2579 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
2580 uint32_t fragment_size_default)
2582 /* adjust vm size firstly */
2583 if (amdgpu_vm_size == -1)
2584 adev->vm_manager.vm_size = vm_size;
2586 adev->vm_manager.vm_size = amdgpu_vm_size;
2588 /* block size depends on vm size */
2589 if (amdgpu_vm_block_size == -1)
2590 adev->vm_manager.block_size =
2591 amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
2593 adev->vm_manager.block_size = amdgpu_vm_block_size;
2595 amdgpu_vm_set_fragment_size(adev, fragment_size_default);
2597 DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
2598 adev->vm_manager.vm_size, adev->vm_manager.block_size,
2599 adev->vm_manager.fragment_size);
2603 * amdgpu_vm_init - initialize a vm instance
2605 * @adev: amdgpu_device pointer
2607 * @vm_context: Indicates if it GFX or Compute context
2611 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2612 int vm_context, unsigned int pasid)
2614 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2615 AMDGPU_VM_PTE_COUNT(adev) * 8);
2616 unsigned ring_instance;
2617 struct amdgpu_ring *ring;
2618 struct amd_sched_rq *rq;
2621 uint64_t init_pde_value = 0;
2623 vm->va = RB_ROOT_CACHED;
2624 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
2625 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2626 vm->reserved_vmid[i] = NULL;
2627 spin_lock_init(&vm->status_lock);
2628 INIT_LIST_HEAD(&vm->evicted);
2629 INIT_LIST_HEAD(&vm->relocated);
2630 INIT_LIST_HEAD(&vm->moved);
2631 INIT_LIST_HEAD(&vm->freed);
2633 /* create scheduler entity for page table updates */
2635 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2636 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2637 ring = adev->vm_manager.vm_pte_rings[ring_instance];
2638 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
2639 r = amd_sched_entity_init(&ring->sched, &vm->entity,
2640 rq, amdgpu_sched_jobs);
2644 vm->pte_support_ats = false;
2646 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2647 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2648 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2650 if (adev->asic_type == CHIP_RAVEN) {
2651 vm->pte_support_ats = true;
2652 init_pde_value = AMDGPU_PTE_DEFAULT_ATC
2657 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2658 AMDGPU_VM_USE_CPU_FOR_GFX);
2659 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2660 vm->use_cpu_for_update ? "CPU" : "SDMA");
2661 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2662 "CPU update of VM recommended only for large BAR system\n");
2663 vm->last_update = NULL;
2665 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
2666 AMDGPU_GEM_CREATE_VRAM_CLEARED;
2667 if (vm->use_cpu_for_update)
2668 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
2670 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
2671 AMDGPU_GEM_CREATE_SHADOW);
2673 r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true,
2674 AMDGPU_GEM_DOMAIN_VRAM,
2676 NULL, NULL, init_pde_value, &vm->root.base.bo);
2678 goto error_free_sched_entity;
2680 vm->root.base.vm = vm;
2681 list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
2682 INIT_LIST_HEAD(&vm->root.base.vm_status);
2684 if (vm->use_cpu_for_update) {
2685 r = amdgpu_bo_reserve(vm->root.base.bo, false);
2687 goto error_free_root;
2689 r = amdgpu_bo_kmap(vm->root.base.bo, NULL);
2690 amdgpu_bo_unreserve(vm->root.base.bo);
2692 goto error_free_root;
2696 unsigned long flags;
2698 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2699 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2701 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2703 goto error_free_root;
2708 INIT_KFIFO(vm->faults);
2709 vm->fault_credit = 16;
2714 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2715 amdgpu_bo_unref(&vm->root.base.bo);
2716 vm->root.base.bo = NULL;
2718 error_free_sched_entity:
2719 amd_sched_entity_fini(&ring->sched, &vm->entity);
2725 * amdgpu_vm_free_levels - free PD/PT levels
2727 * @level: PD/PT starting level to free
2729 * Free the page directory or page table level and all sub levels.
2731 static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level)
2735 if (level->base.bo) {
2736 list_del(&level->base.bo_list);
2737 list_del(&level->base.vm_status);
2738 amdgpu_bo_unref(&level->base.bo->shadow);
2739 amdgpu_bo_unref(&level->base.bo);
2743 for (i = 0; i <= level->last_entry_used; i++)
2744 amdgpu_vm_free_levels(&level->entries[i]);
2746 kvfree(level->entries);
2750 * amdgpu_vm_fini - tear down a vm instance
2752 * @adev: amdgpu_device pointer
2756 * Unbind the VM and remove all bos from the vm bo list
2758 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2760 struct amdgpu_bo_va_mapping *mapping, *tmp;
2761 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
2762 struct amdgpu_bo *root;
2766 /* Clear pending page faults from IH when the VM is destroyed */
2767 while (kfifo_get(&vm->faults, &fault))
2768 amdgpu_ih_clear_fault(adev, fault);
2771 unsigned long flags;
2773 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2774 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2775 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2778 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
2780 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2781 dev_err(adev->dev, "still active bo inside vm\n");
2783 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2784 &vm->va.rb_root, rb) {
2785 list_del(&mapping->list);
2786 amdgpu_vm_it_remove(mapping, &vm->va);
2789 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2790 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2791 amdgpu_vm_prt_fini(adev, vm);
2792 prt_fini_needed = false;
2795 list_del(&mapping->list);
2796 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2799 root = amdgpu_bo_ref(vm->root.base.bo);
2800 r = amdgpu_bo_reserve(root, true);
2802 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2804 amdgpu_vm_free_levels(&vm->root);
2805 amdgpu_bo_unreserve(root);
2807 amdgpu_bo_unref(&root);
2808 dma_fence_put(vm->last_update);
2809 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2810 amdgpu_vm_free_reserved_vmid(adev, vm, i);
2814 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
2816 * @adev: amdgpu_device pointer
2817 * @pasid: PASID do identify the VM
2819 * This function is expected to be called in interrupt context. Returns
2820 * true if there was fault credit, false otherwise
2822 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
2825 struct amdgpu_vm *vm;
2827 spin_lock(&adev->vm_manager.pasid_lock);
2828 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
2829 spin_unlock(&adev->vm_manager.pasid_lock);
2831 /* VM not found, can't track fault credit */
2834 /* No lock needed. only accessed by IRQ handler */
2835 if (!vm->fault_credit)
2836 /* Too many faults in this VM */
2844 * amdgpu_vm_manager_init - init the VM manager
2846 * @adev: amdgpu_device pointer
2848 * Initialize the VM manager structures
2850 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2854 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2855 struct amdgpu_vm_id_manager *id_mgr =
2856 &adev->vm_manager.id_mgr[i];
2858 mutex_init(&id_mgr->lock);
2859 INIT_LIST_HEAD(&id_mgr->ids_lru);
2860 atomic_set(&id_mgr->reserved_vmid_num, 0);
2862 /* skip over VMID 0, since it is the system VM */
2863 for (j = 1; j < id_mgr->num_ids; ++j) {
2864 amdgpu_vm_reset_id(adev, i, j);
2865 amdgpu_sync_create(&id_mgr->ids[i].active);
2866 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
2870 adev->vm_manager.fence_context =
2871 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2872 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2873 adev->vm_manager.seqno[i] = 0;
2875 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2876 atomic64_set(&adev->vm_manager.client_counter, 0);
2877 spin_lock_init(&adev->vm_manager.prt_lock);
2878 atomic_set(&adev->vm_manager.num_prt_users, 0);
2880 /* If not overridden by the user, by default, only in large BAR systems
2881 * Compute VM tables will be updated by CPU
2883 #ifdef CONFIG_X86_64
2884 if (amdgpu_vm_update_mode == -1) {
2885 if (amdgpu_vm_is_large_bar(adev))
2886 adev->vm_manager.vm_update_mode =
2887 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2889 adev->vm_manager.vm_update_mode = 0;
2891 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2893 adev->vm_manager.vm_update_mode = 0;
2896 idr_init(&adev->vm_manager.pasid_idr);
2897 spin_lock_init(&adev->vm_manager.pasid_lock);
2901 * amdgpu_vm_manager_fini - cleanup VM manager
2903 * @adev: amdgpu_device pointer
2905 * Cleanup the VM manager and free resources.
2907 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2911 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
2912 idr_destroy(&adev->vm_manager.pasid_idr);
2914 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
2915 struct amdgpu_vm_id_manager *id_mgr =
2916 &adev->vm_manager.id_mgr[i];
2918 mutex_destroy(&id_mgr->lock);
2919 for (j = 0; j < AMDGPU_NUM_VM; ++j) {
2920 struct amdgpu_vm_id *id = &id_mgr->ids[j];
2922 amdgpu_sync_free(&id->active);
2923 dma_fence_put(id->flushed_updates);
2924 dma_fence_put(id->last_flush);
2929 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2931 union drm_amdgpu_vm *args = data;
2932 struct amdgpu_device *adev = dev->dev_private;
2933 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2936 switch (args->in.op) {
2937 case AMDGPU_VM_OP_RESERVE_VMID:
2938 /* current, we only have requirement to reserve vmid from gfxhub */
2939 r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm,
2944 case AMDGPU_VM_OP_UNRESERVE_VMID:
2945 amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB);