drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <drm/drmP.h>
  30 #include <drm/drm.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_pm.h"
  34 #include "amdgpu_vcn.h"
  35 #include "soc15d.h"
  36 #include "soc15_common.h"
  37
  38 #include "vcn/vcn_1_0_offset.h"
  39
  40 /* 1 second timeout */
  41 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  42
  43 /* Firmware Names */
  44 #define FIRMWARE_RAVEN          "amdgpu/raven_vcn.bin"
  45
  46 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  47
  48 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  49
  50 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  51 {
  52         unsigned long bo_size;
  53         const char *fw_name;
  54         const struct common_firmware_header *hdr;
  55         unsigned char fw_check;
  56         int r;
  57
  58         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  59
  60         switch (adev->asic_type) {
  61         case CHIP_RAVEN:
  62                 fw_name = FIRMWARE_RAVEN;
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
  69         if (r) {
  70                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
  71                         fw_name);
  72                 return r;
  73         }
  74
  75         r = amdgpu_ucode_validate(adev->vcn.fw);
  76         if (r) {
  77                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
  78                         fw_name);
  79                 release_firmware(adev->vcn.fw);
  80                 adev->vcn.fw = NULL;
  81                 return r;
  82         }
  83
  84         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
  85         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
  86
  87         /* Bit 20-23, it is encode major and non-zero for new naming convention.
  88          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
  89          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
  90          * is zero in old naming convention, this field is always zero so far.
  91          * These four bits are used to tell which naming convention is present.
  92          */
  93         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
  94         if (fw_check) {
  95                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
  96
  97                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
  98                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
  99                 enc_major = fw_check;
 100                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 101                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 102                 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
 103                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 104         } else {
 105                 unsigned int version_major, version_minor, family_id;
 106
 107                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 108                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 109                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 110                 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
 111                         version_major, version_minor, family_id);
 112         }
 113
 114         bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 115                   +  AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
 116                   +  AMDGPU_VCN_SESSION_SIZE * 40;
 117         r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 118                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
 119                                     &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
 120         if (r) {
 121                 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 122                 return r;
 123         }
 124
 125         return 0;
 126 }
 127
 128 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 129 {
 130         int i;
 131
 132         kfree(adev->vcn.saved_bo);
 133
 134         amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
 135                               &adev->vcn.gpu_addr,
 136                               (void **)&adev->vcn.cpu_addr);
 137
 138         amdgpu_ring_fini(&adev->vcn.ring_dec);
 139
 140         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 141                 amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
 142
 143         amdgpu_ring_fini(&adev->vcn.ring_jpeg);
 144
 145         release_firmware(adev->vcn.fw);
 146
 147         return 0;
 148 }
 149
 150 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 151 {
 152         unsigned size;
 153         void *ptr;
 154
 155         if (adev->vcn.vcpu_bo == NULL)
 156                 return 0;
 157
 158         cancel_delayed_work_sync(&adev->vcn.idle_work);
 159
 160         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 161         ptr = adev->vcn.cpu_addr;
 162
 163         adev->vcn.saved_bo = kmalloc(size, GFP_KERNEL);
 164         if (!adev->vcn.saved_bo)
 165                 return -ENOMEM;
 166
 167         memcpy_fromio(adev->vcn.saved_bo, ptr, size);
 168
 169         return 0;
 170 }
 171
 172 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 173 {
 174         unsigned size;
 175         void *ptr;
 176
 177         if (adev->vcn.vcpu_bo == NULL)
 178                 return -EINVAL;
 179
 180         size = amdgpu_bo_size(adev->vcn.vcpu_bo);
 181         ptr = adev->vcn.cpu_addr;
 182
 183         if (adev->vcn.saved_bo != NULL) {
 184                 memcpy_toio(ptr, adev->vcn.saved_bo, size);
 185                 kfree(adev->vcn.saved_bo);
 186                 adev->vcn.saved_bo = NULL;
 187         } else {
 188                 const struct common_firmware_header *hdr;
 189                 unsigned offset;
 190
 191                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 192                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 193                 memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
 194                             le32_to_cpu(hdr->ucode_size_bytes));
 195                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 196                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 197                 memset_io(ptr, 0, size);
 198         }
 199
 200         return 0;
 201 }
 202
 203 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 204 {
 205         struct amdgpu_device *adev =
 206                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 207         unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
 208         unsigned i;
 209
 210         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 211                 fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
 212         }
 213
 214         fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
 215
 216         if (fences == 0) {
 217                 if (adev->pm.dpm_enabled)
 218                         amdgpu_dpm_enable_uvd(adev, false);
 219                 else
 220                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 221                                                                AMD_PG_STATE_GATE);
 222         } else {
 223                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 224         }
 225 }
 226
 227 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 228 {
 229         struct amdgpu_device *adev = ring->adev;
 230         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 231
 232         if (set_clocks) {
 233                 if (adev->pm.dpm_enabled)
 234                         amdgpu_dpm_enable_uvd(adev, true);
 235                 else
 236                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 237                                                                AMD_PG_STATE_UNGATE);
 238         }
 239 }
 240
 241 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 242 {
 243         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 244 }
 245
 246 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 247 {
 248         struct amdgpu_device *adev = ring->adev;
 249         uint32_t tmp = 0;
 250         unsigned i;
 251         int r;
 252
 253         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
 254         r = amdgpu_ring_alloc(ring, 3);
 255         if (r) {
 256                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 257                           ring->idx, r);
 258                 return r;
 259         }
 260         amdgpu_ring_write(ring,
 261                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
 262         amdgpu_ring_write(ring, 0xDEADBEEF);
 263         amdgpu_ring_commit(ring);
 264         for (i = 0; i < adev->usec_timeout; i++) {
 265                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
 266                 if (tmp == 0xDEADBEEF)
 267                         break;
 268                 DRM_UDELAY(1);
 269         }
 270
 271         if (i < adev->usec_timeout) {
 272                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 273                          ring->idx, i);
 274         } else {
 275                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 276                           ring->idx, tmp);
 277                 r = -EINVAL;
 278         }
 279         return r;
 280 }
 281
 282 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 283                                    struct amdgpu_bo *bo,
 284                                    struct dma_fence **fence)
 285 {
 286         struct amdgpu_device *adev = ring->adev;
 287         struct dma_fence *f = NULL;
 288         struct amdgpu_job *job;
 289         struct amdgpu_ib *ib;
 290         uint64_t addr;
 291         int i, r;
 292
 293         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 294         if (r)
 295                 goto err;
 296
 297         ib = &job->ibs[0];
 298         addr = amdgpu_bo_gpu_offset(bo);
 299         ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
 300         ib->ptr[1] = addr;
 301         ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
 302         ib->ptr[3] = addr >> 32;
 303         ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
 304         ib->ptr[5] = 0;
 305         for (i = 6; i < 16; i += 2) {
 306                 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
 307                 ib->ptr[i+1] = 0;
 308         }
 309         ib->length_dw = 16;
 310
 311         r = amdgpu_job_submit_direct(job, ring, &f);
 312         if (r)
 313                 goto err_free;
 314
 315         amdgpu_bo_fence(bo, f, false);
 316         amdgpu_bo_unreserve(bo);
 317         amdgpu_bo_unref(&bo);
 318
 319         if (fence)
 320                 *fence = dma_fence_get(f);
 321         dma_fence_put(f);
 322
 323         return 0;
 324
 325 err_free:
 326         amdgpu_job_free(job);
 327
 328 err:
 329         amdgpu_bo_unreserve(bo);
 330         amdgpu_bo_unref(&bo);
 331         return r;
 332 }
 333
 334 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 335                               struct dma_fence **fence)
 336 {
 337         struct amdgpu_device *adev = ring->adev;
 338         struct amdgpu_bo *bo = NULL;
 339         uint32_t *msg;
 340         int r, i;
 341
 342         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 343                                       AMDGPU_GEM_DOMAIN_VRAM,
 344                                       &bo, NULL, (void **)&msg);
 345         if (r)
 346                 return r;
 347
 348         msg[0] = cpu_to_le32(0x00000028);
 349         msg[1] = cpu_to_le32(0x00000038);
 350         msg[2] = cpu_to_le32(0x00000001);
 351         msg[3] = cpu_to_le32(0x00000000);
 352         msg[4] = cpu_to_le32(handle);
 353         msg[5] = cpu_to_le32(0x00000000);
 354         msg[6] = cpu_to_le32(0x00000001);
 355         msg[7] = cpu_to_le32(0x00000028);
 356         msg[8] = cpu_to_le32(0x00000010);
 357         msg[9] = cpu_to_le32(0x00000000);
 358         msg[10] = cpu_to_le32(0x00000007);
 359         msg[11] = cpu_to_le32(0x00000000);
 360         msg[12] = cpu_to_le32(0x00000780);
 361         msg[13] = cpu_to_le32(0x00000440);
 362         for (i = 14; i < 1024; ++i)
 363                 msg[i] = cpu_to_le32(0x0);
 364
 365         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 366 }
 367
 368 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 369                                struct dma_fence **fence)
 370 {
 371         struct amdgpu_device *adev = ring->adev;
 372         struct amdgpu_bo *bo = NULL;
 373         uint32_t *msg;
 374         int r, i;
 375
 376         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 377                                       AMDGPU_GEM_DOMAIN_VRAM,
 378                                       &bo, NULL, (void **)&msg);
 379         if (r)
 380                 return r;
 381
 382         msg[0] = cpu_to_le32(0x00000028);
 383         msg[1] = cpu_to_le32(0x00000018);
 384         msg[2] = cpu_to_le32(0x00000000);
 385         msg[3] = cpu_to_le32(0x00000002);
 386         msg[4] = cpu_to_le32(handle);
 387         msg[5] = cpu_to_le32(0x00000000);
 388         for (i = 6; i < 1024; ++i)
 389                 msg[i] = cpu_to_le32(0x0);
 390
 391         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 392 }
 393
 394 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 395 {
 396         struct dma_fence *fence;
 397         long r;
 398
 399         r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
 400         if (r) {
 401                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 402                 goto error;
 403         }
 404
 405         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
 406         if (r) {
 407                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 408                 goto error;
 409         }
 410
 411         r = dma_fence_wait_timeout(fence, false, timeout);
 412         if (r == 0) {
 413                 DRM_ERROR("amdgpu: IB test timed out.\n");
 414                 r = -ETIMEDOUT;
 415         } else if (r < 0) {
 416                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 417         } else {
 418                 DRM_DEBUG("ib test on ring %d succeeded\n",  ring->idx);
 419                 r = 0;
 420         }
 421
 422         dma_fence_put(fence);
 423
 424 error:
 425         return r;
 426 }
 427
 428 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 432         unsigned i;
 433         int r;
 434
 435         r = amdgpu_ring_alloc(ring, 16);
 436         if (r) {
 437                 DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
 438                           ring->idx, r);
 439                 return r;
 440         }
 441         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 442         amdgpu_ring_commit(ring);
 443
 444         for (i = 0; i < adev->usec_timeout; i++) {
 445                 if (amdgpu_ring_get_rptr(ring) != rptr)
 446                         break;
 447                 DRM_UDELAY(1);
 448         }
 449
 450         if (i < adev->usec_timeout) {
 451                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 452                          ring->idx, i);
 453         } else {
 454                 DRM_ERROR("amdgpu: ring %d test failed\n",
 455                           ring->idx);
 456                 r = -ETIMEDOUT;
 457         }
 458
 459         return r;
 460 }
 461
 462 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 463                               struct dma_fence **fence)
 464 {
 465         const unsigned ib_size_dw = 16;
 466         struct amdgpu_job *job;
 467         struct amdgpu_ib *ib;
 468         struct dma_fence *f = NULL;
 469         uint64_t dummy;
 470         int i, r;
 471
 472         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 473         if (r)
 474                 return r;
 475
 476         ib = &job->ibs[0];
 477         dummy = ib->gpu_addr + 1024;
 478
 479         ib->length_dw = 0;
 480         ib->ptr[ib->length_dw++] = 0x00000018;
 481         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 482         ib->ptr[ib->length_dw++] = handle;
 483         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 484         ib->ptr[ib->length_dw++] = dummy;
 485         ib->ptr[ib->length_dw++] = 0x0000000b;
 486
 487         ib->ptr[ib->length_dw++] = 0x00000014;
 488         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 489         ib->ptr[ib->length_dw++] = 0x0000001c;
 490         ib->ptr[ib->length_dw++] = 0x00000000;
 491         ib->ptr[ib->length_dw++] = 0x00000000;
 492
 493         ib->ptr[ib->length_dw++] = 0x00000008;
 494         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 495
 496         for (i = ib->length_dw; i < ib_size_dw; ++i)
 497                 ib->ptr[i] = 0x0;
 498
 499         r = amdgpu_job_submit_direct(job, ring, &f);
 500         if (r)
 501                 goto err;
 502
 503         if (fence)
 504                 *fence = dma_fence_get(f);
 505         dma_fence_put(f);
 506
 507         return 0;
 508
 509 err:
 510         amdgpu_job_free(job);
 511         return r;
 512 }
 513
 514 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 515                                 struct dma_fence **fence)
 516 {
 517         const unsigned ib_size_dw = 16;
 518         struct amdgpu_job *job;
 519         struct amdgpu_ib *ib;
 520         struct dma_fence *f = NULL;
 521         uint64_t dummy;
 522         int i, r;
 523
 524         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 525         if (r)
 526                 return r;
 527
 528         ib = &job->ibs[0];
 529         dummy = ib->gpu_addr + 1024;
 530
 531         ib->length_dw = 0;
 532         ib->ptr[ib->length_dw++] = 0x00000018;
 533         ib->ptr[ib->length_dw++] = 0x00000001;
 534         ib->ptr[ib->length_dw++] = handle;
 535         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 536         ib->ptr[ib->length_dw++] = dummy;
 537         ib->ptr[ib->length_dw++] = 0x0000000b;
 538
 539         ib->ptr[ib->length_dw++] = 0x00000014;
 540         ib->ptr[ib->length_dw++] = 0x00000002;
 541         ib->ptr[ib->length_dw++] = 0x0000001c;
 542         ib->ptr[ib->length_dw++] = 0x00000000;
 543         ib->ptr[ib->length_dw++] = 0x00000000;
 544
 545         ib->ptr[ib->length_dw++] = 0x00000008;
 546         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 547
 548         for (i = ib->length_dw; i < ib_size_dw; ++i)
 549                 ib->ptr[i] = 0x0;
 550
 551         r = amdgpu_job_submit_direct(job, ring, &f);
 552         if (r)
 553                 goto err;
 554
 555         if (fence)
 556                 *fence = dma_fence_get(f);
 557         dma_fence_put(f);
 558
 559         return 0;
 560
 561 err:
 562         amdgpu_job_free(job);
 563         return r;
 564 }
 565
 566 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 567 {
 568         struct dma_fence *fence = NULL;
 569         long r;
 570
 571         r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
 572         if (r) {
 573                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 574                 goto error;
 575         }
 576
 577         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
 578         if (r) {
 579                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 580                 goto error;
 581         }
 582
 583         r = dma_fence_wait_timeout(fence, false, timeout);
 584         if (r == 0) {
 585                 DRM_ERROR("amdgpu: IB test timed out.\n");
 586                 r = -ETIMEDOUT;
 587         } else if (r < 0) {
 588                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 589         } else {
 590                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 591                 r = 0;
 592         }
 593 error:
 594         dma_fence_put(fence);
 595         return r;
 596 }
 597
 598 int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
 599 {
 600         struct amdgpu_device *adev = ring->adev;
 601         uint32_t tmp = 0;
 602         unsigned i;
 603         int r;
 604
 605         WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
 606         r = amdgpu_ring_alloc(ring, 3);
 607
 608         if (r) {
 609                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 610                                   ring->idx, r);
 611                 return r;
 612         }
 613
 614         amdgpu_ring_write(ring,
 615                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
 616         amdgpu_ring_write(ring, 0xDEADBEEF);
 617         amdgpu_ring_commit(ring);
 618
 619         for (i = 0; i < adev->usec_timeout; i++) {
 620                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
 621                 if (tmp == 0xDEADBEEF)
 622                         break;
 623                 DRM_UDELAY(1);
 624         }
 625
 626         if (i < adev->usec_timeout) {
 627                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 628                                   ring->idx, i);
 629         } else {
 630                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 631                                   ring->idx, tmp);
 632                 r = -EINVAL;
 633         }
 634
 635         return r;
 636 }
 637
 638 static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
 639                 struct dma_fence **fence)
 640 {
 641         struct amdgpu_device *adev = ring->adev;
 642         struct amdgpu_job *job;
 643         struct amdgpu_ib *ib;
 644         struct dma_fence *f = NULL;
 645         const unsigned ib_size_dw = 16;
 646         int i, r;
 647
 648         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 649         if (r)
 650                 return r;
 651
 652         ib = &job->ibs[0];
 653
 654         ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH), 0, 0, PACKETJ_TYPE0);
 655         ib->ptr[1] = 0xDEADBEEF;
 656         for (i = 2; i < 16; i += 2) {
 657                 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
 658                 ib->ptr[i+1] = 0;
 659         }
 660         ib->length_dw = 16;
 661
 662         r = amdgpu_job_submit_direct(job, ring, &f);
 663         if (r)
 664                 goto err;
 665
 666         if (fence)
 667                 *fence = dma_fence_get(f);
 668         dma_fence_put(f);
 669
 670         return 0;
 671
 672 err:
 673         amdgpu_job_free(job);
 674         return r;
 675 }
 676
 677 int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 678 {
 679         struct amdgpu_device *adev = ring->adev;
 680         uint32_t tmp = 0;
 681         unsigned i;
 682         struct dma_fence *fence = NULL;
 683         long r = 0;
 684
 685         r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
 686         if (r) {
 687                 DRM_ERROR("amdgpu: failed to set jpeg register (%ld).\n", r);
 688                 goto error;
 689         }
 690
 691         r = dma_fence_wait_timeout(fence, false, timeout);
 692         if (r == 0) {
 693                 DRM_ERROR("amdgpu: IB test timed out.\n");
 694                 r = -ETIMEDOUT;
 695                 goto error;
 696         } else if (r < 0) {
 697                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 698                 goto error;
 699         } else
 700                 r = 0;
 701
 702         for (i = 0; i < adev->usec_timeout; i++) {
 703                 tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH));
 704                 if (tmp == 0xDEADBEEF)
 705                         break;
 706                 DRM_UDELAY(1);
 707         }
 708
 709         if (i < adev->usec_timeout)
 710                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 711         else {
 712                 DRM_ERROR("ib test failed (0x%08X)\n", tmp);
 713                 r = -EINVAL;
 714         }
 715
 716         dma_fence_put(fence);
 717
 718 error:
 719         return r;
 720 }