drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "si_dpm.h"
  34 #include "cik_dpm.h"
  35 #include "vi_dpm.h"
  36
  37 static int amdgpu_create_pp_handle(struct amdgpu_device *adev)
  38 {
  39         struct amd_pp_init pp_init;
  40         struct amd_powerplay *amd_pp;
  41         int ret;
  42
  43         amd_pp = &(adev->powerplay);
  44         pp_init.chip_family = adev->family;
  45         pp_init.chip_id = adev->asic_type;
  46         pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
  47         pp_init.feature_mask = amdgpu_pp_feature_mask;
  48         pp_init.device = amdgpu_cgs_create_device(adev);
  49         ret = amd_powerplay_create(&pp_init, &(amd_pp->pp_handle));
  50         if (ret)
  51                 return -EINVAL;
  52         return 0;
  53 }
  54
  55 static int amdgpu_pp_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58         struct amd_powerplay *amd_pp;
  59         int ret = 0;
  60
  61         amd_pp = &(adev->powerplay);
  62         adev->pp_enabled = false;
  63         amd_pp->pp_handle = (void *)adev;
  64
  65         switch (adev->asic_type) {
  66         case CHIP_POLARIS11:
  67         case CHIP_POLARIS10:
  68         case CHIP_POLARIS12:
  69         case CHIP_TONGA:
  70         case CHIP_FIJI:
  71         case CHIP_TOPAZ:
  72         case CHIP_CARRIZO:
  73         case CHIP_STONEY:
  74         case CHIP_VEGA10:
  75         case CHIP_RAVEN:
  76                 adev->pp_enabled = true;
  77                 if (amdgpu_create_pp_handle(adev))
  78                         return -EINVAL;
  79                 amd_pp->ip_funcs = &pp_ip_funcs;
  80                 amd_pp->pp_funcs = &pp_dpm_funcs;
  81                 break;
  82         /* These chips don't have powerplay implemenations */
  83 #ifdef CONFIG_DRM_AMDGPU_SI
  84         case CHIP_TAHITI:
  85         case CHIP_PITCAIRN:
  86         case CHIP_VERDE:
  87         case CHIP_OLAND:
  88         case CHIP_HAINAN:
  89                 amd_pp->ip_funcs = &si_dpm_ip_funcs;
  90         break;
  91 #endif
  92 #ifdef CONFIG_DRM_AMDGPU_CIK
  93         case CHIP_BONAIRE:
  94         case CHIP_HAWAII:
  95                 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  96                 break;
  97         case CHIP_KABINI:
  98         case CHIP_MULLINS:
  99         case CHIP_KAVERI:
 100                 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
 101                 break;
 102 #endif
 103         default:
 104                 ret = -EINVAL;
 105                 break;
 106         }
 107
 108         if (adev->powerplay.ip_funcs->early_init)
 109                 ret = adev->powerplay.ip_funcs->early_init(
 110                                         adev->powerplay.pp_handle);
 111
 112         if (ret == PP_DPM_DISABLED) {
 113                 adev->pm.dpm_enabled = false;
 114                 return 0;
 115         }
 116         return ret;
 117 }
 118
 119
 120 static int amdgpu_pp_late_init(void *handle)
 121 {
 122         int ret = 0;
 123         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 124
 125         if (adev->powerplay.ip_funcs->late_init)
 126                 ret = adev->powerplay.ip_funcs->late_init(
 127                                         adev->powerplay.pp_handle);
 128
 129         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 130                 amdgpu_pm_sysfs_init(adev);
 131                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
 132         }
 133
 134         return ret;
 135 }
 136
 137 static int amdgpu_pp_sw_init(void *handle)
 138 {
 139         int ret = 0;
 140         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 141
 142         if (adev->powerplay.ip_funcs->sw_init)
 143                 ret = adev->powerplay.ip_funcs->sw_init(
 144                                         adev->powerplay.pp_handle);
 145
 146         return ret;
 147 }
 148
 149 static int amdgpu_pp_sw_fini(void *handle)
 150 {
 151         int ret = 0;
 152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 153
 154         if (adev->powerplay.ip_funcs->sw_fini)
 155                 ret = adev->powerplay.ip_funcs->sw_fini(
 156                                         adev->powerplay.pp_handle);
 157         if (ret)
 158                 return ret;
 159
 160         return ret;
 161 }
 162
 163 static int amdgpu_pp_hw_init(void *handle)
 164 {
 165         int ret = 0;
 166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 167
 168         if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 169                 amdgpu_ucode_init_bo(adev);
 170
 171         if (adev->powerplay.ip_funcs->hw_init)
 172                 ret = adev->powerplay.ip_funcs->hw_init(
 173                                         adev->powerplay.pp_handle);
 174
 175         if (ret == PP_DPM_DISABLED) {
 176                 adev->pm.dpm_enabled = false;
 177                 return 0;
 178         }
 179
 180         if ((amdgpu_dpm != 0) && !amdgpu_sriov_vf(adev))
 181                 adev->pm.dpm_enabled = true;
 182
 183         return ret;
 184 }
 185
 186 static int amdgpu_pp_hw_fini(void *handle)
 187 {
 188         int ret = 0;
 189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 190
 191         if (adev->pp_enabled && adev->pm.dpm_enabled)
 192                 amdgpu_pm_sysfs_fini(adev);
 193
 194         if (adev->powerplay.ip_funcs->hw_fini)
 195                 ret = adev->powerplay.ip_funcs->hw_fini(
 196                                         adev->powerplay.pp_handle);
 197
 198         if (adev->pp_enabled && adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
 199                 amdgpu_ucode_fini_bo(adev);
 200
 201         return ret;
 202 }
 203
 204 static void amdgpu_pp_late_fini(void *handle)
 205 {
 206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 207
 208         if (adev->powerplay.ip_funcs->late_fini)
 209                 adev->powerplay.ip_funcs->late_fini(
 210                           adev->powerplay.pp_handle);
 211
 212
 213         if (adev->pp_enabled)
 214                 amd_powerplay_destroy(adev->powerplay.pp_handle);
 215 }
 216
 217 static int amdgpu_pp_suspend(void *handle)
 218 {
 219         int ret = 0;
 220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 221
 222         if (adev->powerplay.ip_funcs->suspend)
 223                 ret = adev->powerplay.ip_funcs->suspend(
 224                                          adev->powerplay.pp_handle);
 225         return ret;
 226 }
 227
 228 static int amdgpu_pp_resume(void *handle)
 229 {
 230         int ret = 0;
 231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 232
 233         if (adev->powerplay.ip_funcs->resume)
 234                 ret = adev->powerplay.ip_funcs->resume(
 235                                         adev->powerplay.pp_handle);
 236         return ret;
 237 }
 238
 239 static int amdgpu_pp_set_clockgating_state(void *handle,
 240                                         enum amd_clockgating_state state)
 241 {
 242         int ret = 0;
 243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 244
 245         if (adev->powerplay.ip_funcs->set_clockgating_state)
 246                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 247                                 adev->powerplay.pp_handle, state);
 248         return ret;
 249 }
 250
 251 static int amdgpu_pp_set_powergating_state(void *handle,
 252                                         enum amd_powergating_state state)
 253 {
 254         int ret = 0;
 255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 256
 257         if (adev->powerplay.ip_funcs->set_powergating_state)
 258                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 259                                  adev->powerplay.pp_handle, state);
 260         return ret;
 261 }
 262
 263
 264 static bool amdgpu_pp_is_idle(void *handle)
 265 {
 266         bool ret = true;
 267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 268
 269         if (adev->powerplay.ip_funcs->is_idle)
 270                 ret = adev->powerplay.ip_funcs->is_idle(
 271                                         adev->powerplay.pp_handle);
 272         return ret;
 273 }
 274
 275 static int amdgpu_pp_wait_for_idle(void *handle)
 276 {
 277         int ret = 0;
 278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 279
 280         if (adev->powerplay.ip_funcs->wait_for_idle)
 281                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 282                                         adev->powerplay.pp_handle);
 283         return ret;
 284 }
 285
 286 static int amdgpu_pp_soft_reset(void *handle)
 287 {
 288         int ret = 0;
 289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 290
 291         if (adev->powerplay.ip_funcs->soft_reset)
 292                 ret = adev->powerplay.ip_funcs->soft_reset(
 293                                         adev->powerplay.pp_handle);
 294         return ret;
 295 }
 296
 297 static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 298         .name = "amdgpu_powerplay",
 299         .early_init = amdgpu_pp_early_init,
 300         .late_init = amdgpu_pp_late_init,
 301         .sw_init = amdgpu_pp_sw_init,
 302         .sw_fini = amdgpu_pp_sw_fini,
 303         .hw_init = amdgpu_pp_hw_init,
 304         .hw_fini = amdgpu_pp_hw_fini,
 305         .late_fini = amdgpu_pp_late_fini,
 306         .suspend = amdgpu_pp_suspend,
 307         .resume = amdgpu_pp_resume,
 308         .is_idle = amdgpu_pp_is_idle,
 309         .wait_for_idle = amdgpu_pp_wait_for_idle,
 310         .soft_reset = amdgpu_pp_soft_reset,
 311         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 312         .set_powergating_state = amdgpu_pp_set_powergating_state,
 313 };
 314
 315 const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
 316 {
 317         .type = AMD_IP_BLOCK_TYPE_SMC,
 318         .major = 1,
 319         .minor = 0,
 320         .rev = 0,
 321         .funcs = &amdgpu_pp_ip_funcs,
 322 };