drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_display.h"
  31 #include "amdgpu_smu.h"
  32 #include "atom.h"
  33 #include <linux/power_supply.h>
  34 #include <linux/hwmon.h>
  35 #include <linux/hwmon-sysfs.h>
  36 #include <linux/nospec.h>
  37 #include "hwmgr.h"
  38 #define WIDTH_4K 3840
  39
  40 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  41
  42 static const struct cg_flag_name clocks[] = {
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {0, NULL},
  68 };
  69
  70 static const struct hwmon_temp_label {
  71         enum PP_HWMON_TEMP channel;
  72         const char *label;
  73 } temp_label[] = {
  74         {PP_TEMP_EDGE, "edge"},
  75         {PP_TEMP_JUNCTION, "junction"},
  76         {PP_TEMP_MEM, "mem"},
  77 };
  78
  79 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  80 {
  81         if (adev->pm.dpm_enabled) {
  82                 mutex_lock(&adev->pm.mutex);
  83                 if (power_supply_is_system_supplied() > 0)
  84                         adev->pm.ac_power = true;
  85                 else
  86                         adev->pm.ac_power = false;
  87                 if (adev->powerplay.pp_funcs->enable_bapm)
  88                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  89                 mutex_unlock(&adev->pm.mutex);
  90         }
  91 }
  92
  93 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  94                            void *data, uint32_t *size)
  95 {
  96         int ret = 0;
  97
  98         if (!data || !size)
  99                 return -EINVAL;
 100
 101         if (is_support_sw_smu(adev))
 102                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 103         else {
 104                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 105                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 106                                                                     sensor, data, size);
 107                 else
 108                         ret = -EINVAL;
 109         }
 110
 111         return ret;
 112 }
 113
 114 /**
 115  * DOC: power_dpm_state
 116  *
 117  * The power_dpm_state file is a legacy interface and is only provided for
 118  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 119  * certain power related parameters.  The file power_dpm_state is used for this.
 120  * It accepts the following arguments:
 121  *
 122  * - battery
 123  *
 124  * - balanced
 125  *
 126  * - performance
 127  *
 128  * battery
 129  *
 130  * On older GPUs, the vbios provided a special power state for battery
 131  * operation.  Selecting battery switched to this state.  This is no
 132  * longer provided on newer GPUs so the option does nothing in that case.
 133  *
 134  * balanced
 135  *
 136  * On older GPUs, the vbios provided a special power state for balanced
 137  * operation.  Selecting balanced switched to this state.  This is no
 138  * longer provided on newer GPUs so the option does nothing in that case.
 139  *
 140  * performance
 141  *
 142  * On older GPUs, the vbios provided a special power state for performance
 143  * operation.  Selecting performance switched to this state.  This is no
 144  * longer provided on newer GPUs so the option does nothing in that case.
 145  *
 146  */
 147
 148 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 149                                     struct device_attribute *attr,
 150                                     char *buf)
 151 {
 152         struct drm_device *ddev = dev_get_drvdata(dev);
 153         struct amdgpu_device *adev = ddev->dev_private;
 154         enum amd_pm_state_type pm;
 155
 156         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 157                 pm = amdgpu_smu_get_current_power_state(adev);
 158         else if (adev->powerplay.pp_funcs->get_current_power_state)
 159                 pm = amdgpu_dpm_get_current_power_state(adev);
 160         else
 161                 pm = adev->pm.dpm.user_state;
 162
 163         return snprintf(buf, PAGE_SIZE, "%s\n",
 164                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 165                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 166 }
 167
 168 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 169                                     struct device_attribute *attr,
 170                                     const char *buf,
 171                                     size_t count)
 172 {
 173         struct drm_device *ddev = dev_get_drvdata(dev);
 174         struct amdgpu_device *adev = ddev->dev_private;
 175         enum amd_pm_state_type  state;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else {
 184                 count = -EINVAL;
 185                 goto fail;
 186         }
 187
 188         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 189                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 190         } else {
 191                 mutex_lock(&adev->pm.mutex);
 192                 adev->pm.dpm.user_state = state;
 193                 mutex_unlock(&adev->pm.mutex);
 194
 195                 /* Can't set dpm state when the card is off */
 196                 if (!(adev->flags & AMD_IS_PX) ||
 197                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 198                         amdgpu_pm_compute_clocks(adev);
 199         }
 200 fail:
 201         return count;
 202 }
 203
 204
 205 /**
 206  * DOC: power_dpm_force_performance_level
 207  *
 208  * The amdgpu driver provides a sysfs API for adjusting certain power
 209  * related parameters.  The file power_dpm_force_performance_level is
 210  * used for this.  It accepts the following arguments:
 211  *
 212  * - auto
 213  *
 214  * - low
 215  *
 216  * - high
 217  *
 218  * - manual
 219  *
 220  * - profile_standard
 221  *
 222  * - profile_min_sclk
 223  *
 224  * - profile_min_mclk
 225  *
 226  * - profile_peak
 227  *
 228  * auto
 229  *
 230  * When auto is selected, the driver will attempt to dynamically select
 231  * the optimal power profile for current conditions in the driver.
 232  *
 233  * low
 234  *
 235  * When low is selected, the clocks are forced to the lowest power state.
 236  *
 237  * high
 238  *
 239  * When high is selected, the clocks are forced to the highest power state.
 240  *
 241  * manual
 242  *
 243  * When manual is selected, the user can manually adjust which power states
 244  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 245  * and pp_dpm_pcie files and adjust the power state transition heuristics
 246  * via the pp_power_profile_mode sysfs file.
 247  *
 248  * profile_standard
 249  * profile_min_sclk
 250  * profile_min_mclk
 251  * profile_peak
 252  *
 253  * When the profiling modes are selected, clock and power gating are
 254  * disabled and the clocks are set for different profiling cases. This
 255  * mode is recommended for profiling specific work loads where you do
 256  * not want clock or power gating for clock fluctuation to interfere
 257  * with your results. profile_standard sets the clocks to a fixed clock
 258  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 259  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 260  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 261  *
 262  */
 263
 264 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 265                                                 struct device_attribute *attr,
 266                                                                 char *buf)
 267 {
 268         struct drm_device *ddev = dev_get_drvdata(dev);
 269         struct amdgpu_device *adev = ddev->dev_private;
 270         enum amd_dpm_forced_level level = 0xff;
 271
 272         if  ((adev->flags & AMD_IS_PX) &&
 273              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 274                 return snprintf(buf, PAGE_SIZE, "off\n");
 275
 276         if (is_support_sw_smu(adev))
 277                 level = smu_get_performance_level(&adev->smu);
 278         else if (adev->powerplay.pp_funcs->get_performance_level)
 279                 level = amdgpu_dpm_get_performance_level(adev);
 280         else
 281                 level = adev->pm.dpm.forced_level;
 282
 283         return snprintf(buf, PAGE_SIZE, "%s\n",
 284                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 285                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 286                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 287                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 288                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 289                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 290                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 291                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 292                         "unknown");
 293 }
 294
 295 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 296                                                        struct device_attribute *attr,
 297                                                        const char *buf,
 298                                                        size_t count)
 299 {
 300         struct drm_device *ddev = dev_get_drvdata(dev);
 301         struct amdgpu_device *adev = ddev->dev_private;
 302         enum amd_dpm_forced_level level;
 303         enum amd_dpm_forced_level current_level = 0xff;
 304         int ret = 0;
 305
 306         /* Can't force performance level when the card is off */
 307         if  ((adev->flags & AMD_IS_PX) &&
 308              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 309                 return -EINVAL;
 310
 311         if (is_support_sw_smu(adev))
 312                 current_level = smu_get_performance_level(&adev->smu);
 313         else if (adev->powerplay.pp_funcs->get_performance_level)
 314                 current_level = amdgpu_dpm_get_performance_level(adev);
 315
 316         if (strncmp("low", buf, strlen("low")) == 0) {
 317                 level = AMD_DPM_FORCED_LEVEL_LOW;
 318         } else if (strncmp("high", buf, strlen("high")) == 0) {
 319                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 320         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 321                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 322         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 323                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 324         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 325                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 326         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 327                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 328         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 329                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 330         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 331                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 332         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 333                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 334         }  else {
 335                 count = -EINVAL;
 336                 goto fail;
 337         }
 338
 339         if (amdgpu_sriov_vf(adev)) {
 340                 if (amdgim_is_hwperf(adev) &&
 341                     adev->virt.ops->force_dpm_level) {
 342                         mutex_lock(&adev->pm.mutex);
 343                         adev->virt.ops->force_dpm_level(adev, level);
 344                         mutex_unlock(&adev->pm.mutex);
 345                         return count;
 346                 } else {
 347                         return -EINVAL;
 348                 }
 349         }
 350
 351         if (current_level == level)
 352                 return count;
 353
 354         /* profile_exit setting is valid only when current mode is in profile mode */
 355         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 356             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 357             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 358             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 359             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 360                 pr_err("Currently not in any profile mode!\n");
 361                 return -EINVAL;
 362         }
 363
 364         if (is_support_sw_smu(adev)) {
 365                 mutex_lock(&adev->pm.mutex);
 366                 if (adev->pm.dpm.thermal_active) {
 367                         count = -EINVAL;
 368                         mutex_unlock(&adev->pm.mutex);
 369                         goto fail;
 370                 }
 371                 ret = smu_force_performance_level(&adev->smu, level);
 372                 if (ret)
 373                         count = -EINVAL;
 374                 else
 375                         adev->pm.dpm.forced_level = level;
 376                 mutex_unlock(&adev->pm.mutex);
 377         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 378                 mutex_lock(&adev->pm.mutex);
 379                 if (adev->pm.dpm.thermal_active) {
 380                         count = -EINVAL;
 381                         mutex_unlock(&adev->pm.mutex);
 382                         goto fail;
 383                 }
 384                 ret = amdgpu_dpm_force_performance_level(adev, level);
 385                 if (ret)
 386                         count = -EINVAL;
 387                 else
 388                         adev->pm.dpm.forced_level = level;
 389                 mutex_unlock(&adev->pm.mutex);
 390         }
 391
 392 fail:
 393         return count;
 394 }
 395
 396 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 397                 struct device_attribute *attr,
 398                 char *buf)
 399 {
 400         struct drm_device *ddev = dev_get_drvdata(dev);
 401         struct amdgpu_device *adev = ddev->dev_private;
 402         struct pp_states_info data;
 403         int i, buf_len, ret;
 404
 405         if (is_support_sw_smu(adev)) {
 406                 ret = smu_get_power_num_states(&adev->smu, &data);
 407                 if (ret)
 408                         return ret;
 409         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 410                 amdgpu_dpm_get_pp_num_states(adev, &data);
 411
 412         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 413         for (i = 0; i < data.nums; i++)
 414                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 415                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 416                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 417                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 418                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 419
 420         return buf_len;
 421 }
 422
 423 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 424                 struct device_attribute *attr,
 425                 char *buf)
 426 {
 427         struct drm_device *ddev = dev_get_drvdata(dev);
 428         struct amdgpu_device *adev = ddev->dev_private;
 429         struct pp_states_info data;
 430         struct smu_context *smu = &adev->smu;
 431         enum amd_pm_state_type pm = 0;
 432         int i = 0, ret = 0;
 433
 434         if (is_support_sw_smu(adev)) {
 435                 pm = smu_get_current_power_state(smu);
 436                 ret = smu_get_power_num_states(smu, &data);
 437                 if (ret)
 438                         return ret;
 439         } else if (adev->powerplay.pp_funcs->get_current_power_state
 440                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 441                 pm = amdgpu_dpm_get_current_power_state(adev);
 442                 amdgpu_dpm_get_pp_num_states(adev, &data);
 443         }
 444
 445         for (i = 0; i < data.nums; i++) {
 446                 if (pm == data.states[i])
 447                         break;
 448         }
 449
 450         if (i == data.nums)
 451                 i = -EINVAL;
 452
 453         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 454 }
 455
 456 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 457                 struct device_attribute *attr,
 458                 char *buf)
 459 {
 460         struct drm_device *ddev = dev_get_drvdata(dev);
 461         struct amdgpu_device *adev = ddev->dev_private;
 462
 463         if (adev->pp_force_state_enabled)
 464                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 465         else
 466                 return snprintf(buf, PAGE_SIZE, "\n");
 467 }
 468
 469 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 470                 struct device_attribute *attr,
 471                 const char *buf,
 472                 size_t count)
 473 {
 474         struct drm_device *ddev = dev_get_drvdata(dev);
 475         struct amdgpu_device *adev = ddev->dev_private;
 476         enum amd_pm_state_type state = 0;
 477         unsigned long idx;
 478         int ret;
 479
 480         if (strlen(buf) == 1)
 481                 adev->pp_force_state_enabled = false;
 482         else if (is_support_sw_smu(adev))
 483                 adev->pp_force_state_enabled = false;
 484         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 485                         adev->powerplay.pp_funcs->get_pp_num_states) {
 486                 struct pp_states_info data;
 487
 488                 ret = kstrtoul(buf, 0, &idx);
 489                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 490                         count = -EINVAL;
 491                         goto fail;
 492                 }
 493                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 494
 495                 amdgpu_dpm_get_pp_num_states(adev, &data);
 496                 state = data.states[idx];
 497                 /* only set user selected power states */
 498                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 499                     state != POWER_STATE_TYPE_DEFAULT) {
 500                         amdgpu_dpm_dispatch_task(adev,
 501                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 502                         adev->pp_force_state_enabled = true;
 503                 }
 504         }
 505 fail:
 506         return count;
 507 }
 508
 509 /**
 510  * DOC: pp_table
 511  *
 512  * The amdgpu driver provides a sysfs API for uploading new powerplay
 513  * tables.  The file pp_table is used for this.  Reading the file
 514  * will dump the current power play table.  Writing to the file
 515  * will attempt to upload a new powerplay table and re-initialize
 516  * powerplay using that new table.
 517  *
 518  */
 519
 520 static ssize_t amdgpu_get_pp_table(struct device *dev,
 521                 struct device_attribute *attr,
 522                 char *buf)
 523 {
 524         struct drm_device *ddev = dev_get_drvdata(dev);
 525         struct amdgpu_device *adev = ddev->dev_private;
 526         char *table = NULL;
 527         int size;
 528
 529         if (is_support_sw_smu(adev)) {
 530                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 531                 if (size < 0)
 532                         return size;
 533         }
 534         else if (adev->powerplay.pp_funcs->get_pp_table)
 535                 size = amdgpu_dpm_get_pp_table(adev, &table);
 536         else
 537                 return 0;
 538
 539         if (size >= PAGE_SIZE)
 540                 size = PAGE_SIZE - 1;
 541
 542         memcpy(buf, table, size);
 543
 544         return size;
 545 }
 546
 547 static ssize_t amdgpu_set_pp_table(struct device *dev,
 548                 struct device_attribute *attr,
 549                 const char *buf,
 550                 size_t count)
 551 {
 552         struct drm_device *ddev = dev_get_drvdata(dev);
 553         struct amdgpu_device *adev = ddev->dev_private;
 554         int ret = 0;
 555
 556         if (is_support_sw_smu(adev)) {
 557                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 558                 if (ret)
 559                         return ret;
 560         } else if (adev->powerplay.pp_funcs->set_pp_table)
 561                 amdgpu_dpm_set_pp_table(adev, buf, count);
 562
 563         return count;
 564 }
 565
 566 /**
 567  * DOC: pp_od_clk_voltage
 568  *
 569  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 570  * in each power level within a power state.  The pp_od_clk_voltage is used for
 571  * this.
 572  *
 573  * < For Vega10 and previous ASICs >
 574  *
 575  * Reading the file will display:
 576  *
 577  * - a list of engine clock levels and voltages labeled OD_SCLK
 578  *
 579  * - a list of memory clock levels and voltages labeled OD_MCLK
 580  *
 581  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 582  *
 583  * To manually adjust these settings, first select manual using
 584  * power_dpm_force_performance_level. Enter a new value for each
 585  * level by writing a string that contains "s/m level clock voltage" to
 586  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 587  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 588  * 810 mV.  When you have edited all of the states as needed, write
 589  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 590  * default power levels, write "r" (reset) to the file to reset them.
 591  *
 592  *
 593  * < For Vega20 >
 594  *
 595  * Reading the file will display:
 596  *
 597  * - minimum and maximum engine clock labeled OD_SCLK
 598  *
 599  * - maximum memory clock labeled OD_MCLK
 600  *
 601  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 602  *   They can be used to calibrate the sclk voltage curve.
 603  *
 604  * - a list of valid ranges for sclk, mclk, and voltage curve points
 605  *   labeled OD_RANGE
 606  *
 607  * To manually adjust these settings:
 608  *
 609  * - First select manual using power_dpm_force_performance_level
 610  *
 611  * - For clock frequency setting, enter a new value by writing a
 612  *   string that contains "s/m index clock" to the file. The index
 613  *   should be 0 if to set minimum clock. And 1 if to set maximum
 614  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 615  *   "m 1 800" will update maximum mclk to be 800Mhz.
 616  *
 617  *   For sclk voltage curve, enter the new values by writing a
 618  *   string that contains "vc point clock voltage" to the file. The
 619  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 620  *   update point1 with clock set as 300Mhz and voltage as
 621  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 622  *   as 1000Mhz and voltage 1000mV.
 623  *
 624  * - When you have edited all of the states as needed, write "c" (commit)
 625  *   to the file to commit your changes
 626  *
 627  * - If you want to reset to the default power levels, write "r" (reset)
 628  *   to the file to reset them
 629  *
 630  */
 631
 632 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 633                 struct device_attribute *attr,
 634                 const char *buf,
 635                 size_t count)
 636 {
 637         struct drm_device *ddev = dev_get_drvdata(dev);
 638         struct amdgpu_device *adev = ddev->dev_private;
 639         int ret;
 640         uint32_t parameter_size = 0;
 641         long parameter[64];
 642         char buf_cpy[128];
 643         char *tmp_str;
 644         char *sub_str;
 645         const char delimiter[3] = {' ', '\n', '\0'};
 646         uint32_t type;
 647
 648         if (count > 127)
 649                 return -EINVAL;
 650
 651         if (*buf == 's')
 652                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 653         else if (*buf == 'm')
 654                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 655         else if(*buf == 'r')
 656                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 657         else if (*buf == 'c')
 658                 type = PP_OD_COMMIT_DPM_TABLE;
 659         else if (!strncmp(buf, "vc", 2))
 660                 type = PP_OD_EDIT_VDDC_CURVE;
 661         else
 662                 return -EINVAL;
 663
 664         memcpy(buf_cpy, buf, count+1);
 665
 666         tmp_str = buf_cpy;
 667
 668         if (type == PP_OD_EDIT_VDDC_CURVE)
 669                 tmp_str++;
 670         while (isspace(*++tmp_str));
 671
 672         while (tmp_str[0]) {
 673                 sub_str = strsep(&tmp_str, delimiter);
 674                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 675                 if (ret)
 676                         return -EINVAL;
 677                 parameter_size++;
 678
 679                 while (isspace(*tmp_str))
 680                         tmp_str++;
 681         }
 682
 683         if (is_support_sw_smu(adev)) {
 684                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 685                                             parameter, parameter_size);
 686
 687                 if (ret)
 688                         return -EINVAL;
 689         } else {
 690                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 691                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 692                                                 parameter, parameter_size);
 693
 694                 if (ret)
 695                         return -EINVAL;
 696
 697                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 698                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 699                                 amdgpu_dpm_dispatch_task(adev,
 700                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 701                                                 NULL);
 702                                 return count;
 703                         } else {
 704                                 return -EINVAL;
 705                         }
 706                 }
 707         }
 708
 709         return count;
 710 }
 711
 712 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 713                 struct device_attribute *attr,
 714                 char *buf)
 715 {
 716         struct drm_device *ddev = dev_get_drvdata(dev);
 717         struct amdgpu_device *adev = ddev->dev_private;
 718         uint32_t size = 0;
 719
 720         if (is_support_sw_smu(adev)) {
 721                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 722                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 723                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 724                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 725                 return size;
 726         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 727                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 728                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 729                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 730                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 731                 return size;
 732         } else {
 733                 return snprintf(buf, PAGE_SIZE, "\n");
 734         }
 735
 736 }
 737
 738 /**
 739  * DOC: ppfeatures
 740  *
 741  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 742  * features to be enabled. The file ppfeatures is used for this. And
 743  * this is only available for Vega10 and later dGPUs.
 744  *
 745  * Reading back the file will show you the followings:
 746  * - Current ppfeature masks
 747  * - List of the all supported powerplay features with their naming,
 748  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 749  *
 750  * To manually enable or disable a specific feature, just set or clear
 751  * the corresponding bit from original ppfeature masks and input the
 752  * new ppfeature masks.
 753  */
 754 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 755                 struct device_attribute *attr,
 756                 const char *buf,
 757                 size_t count)
 758 {
 759         struct drm_device *ddev = dev_get_drvdata(dev);
 760         struct amdgpu_device *adev = ddev->dev_private;
 761         uint64_t featuremask;
 762         int ret;
 763
 764         ret = kstrtou64(buf, 0, &featuremask);
 765         if (ret)
 766                 return -EINVAL;
 767
 768         pr_debug("featuremask = 0x%llx\n", featuremask);
 769
 770         if (is_support_sw_smu(adev)) {
 771                 ret = smu_set_ppfeature_status(&adev->smu, featuremask);
 772                 if (ret)
 773                         return -EINVAL;
 774         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 775                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 776                 if (ret)
 777                         return -EINVAL;
 778         }
 779
 780         return count;
 781 }
 782
 783 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 784                 struct device_attribute *attr,
 785                 char *buf)
 786 {
 787         struct drm_device *ddev = dev_get_drvdata(dev);
 788         struct amdgpu_device *adev = ddev->dev_private;
 789
 790         if (is_support_sw_smu(adev)) {
 791                 return smu_get_ppfeature_status(&adev->smu, buf);
 792         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 793                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 794
 795         return snprintf(buf, PAGE_SIZE, "\n");
 796 }
 797
 798 /**
 799  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 800  * pp_dpm_pcie
 801  *
 802  * The amdgpu driver provides a sysfs API for adjusting what power levels
 803  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 804  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 805  * this.
 806  *
 807  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 808  * Vega10 and later ASICs.
 809  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 810  *
 811  * Reading back the files will show you the available power levels within
 812  * the power state and the clock information for those levels.
 813  *
 814  * To manually adjust these states, first select manual using
 815  * power_dpm_force_performance_level.
 816  * Secondly,Enter a new value for each level by inputing a string that
 817  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 818  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 819  *
 820  * NOTE: change to the dcefclk max dpm level is not supported now
 821  */
 822
 823 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 824                 struct device_attribute *attr,
 825                 char *buf)
 826 {
 827         struct drm_device *ddev = dev_get_drvdata(dev);
 828         struct amdgpu_device *adev = ddev->dev_private;
 829
 830         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 831             adev->virt.ops->get_pp_clk)
 832                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 833
 834         if (is_support_sw_smu(adev))
 835                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 836         else if (adev->powerplay.pp_funcs->print_clock_levels)
 837                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 838         else
 839                 return snprintf(buf, PAGE_SIZE, "\n");
 840 }
 841
 842 /*
 843  * Worst case: 32 bits individually specified, in octal at 12 characters
 844  * per line (+1 for \n).
 845  */
 846 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 847
 848 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 849 {
 850         int ret;
 851         long level;
 852         char *sub_str = NULL;
 853         char *tmp;
 854         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 855         const char delimiter[3] = {' ', '\n', '\0'};
 856         size_t bytes;
 857
 858         *mask = 0;
 859
 860         bytes = min(count, sizeof(buf_cpy) - 1);
 861         memcpy(buf_cpy, buf, bytes);
 862         buf_cpy[bytes] = '\0';
 863         tmp = buf_cpy;
 864         while (tmp[0]) {
 865                 sub_str = strsep(&tmp, delimiter);
 866                 if (strlen(sub_str)) {
 867                         ret = kstrtol(sub_str, 0, &level);
 868                         if (ret)
 869                                 return -EINVAL;
 870                         *mask |= 1 << level;
 871                 } else
 872                         break;
 873         }
 874
 875         return 0;
 876 }
 877
 878 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 879                 struct device_attribute *attr,
 880                 const char *buf,
 881                 size_t count)
 882 {
 883         struct drm_device *ddev = dev_get_drvdata(dev);
 884         struct amdgpu_device *adev = ddev->dev_private;
 885         int ret;
 886         uint32_t mask = 0;
 887
 888         ret = amdgpu_read_mask(buf, count, &mask);
 889         if (ret)
 890                 return ret;
 891
 892         if (is_support_sw_smu(adev))
 893                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 894         else if (adev->powerplay.pp_funcs->force_clock_level)
 895                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 896
 897         if (ret)
 898                 return -EINVAL;
 899
 900         return count;
 901 }
 902
 903 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 904                 struct device_attribute *attr,
 905                 char *buf)
 906 {
 907         struct drm_device *ddev = dev_get_drvdata(dev);
 908         struct amdgpu_device *adev = ddev->dev_private;
 909
 910         if (is_support_sw_smu(adev))
 911                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 912         else if (adev->powerplay.pp_funcs->print_clock_levels)
 913                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 914         else
 915                 return snprintf(buf, PAGE_SIZE, "\n");
 916 }
 917
 918 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 919                 struct device_attribute *attr,
 920                 const char *buf,
 921                 size_t count)
 922 {
 923         struct drm_device *ddev = dev_get_drvdata(dev);
 924         struct amdgpu_device *adev = ddev->dev_private;
 925         int ret;
 926         uint32_t mask = 0;
 927
 928         ret = amdgpu_read_mask(buf, count, &mask);
 929         if (ret)
 930                 return ret;
 931
 932         if (is_support_sw_smu(adev))
 933                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 934         else if (adev->powerplay.pp_funcs->force_clock_level)
 935                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 936
 937         if (ret)
 938                 return -EINVAL;
 939
 940         return count;
 941 }
 942
 943 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 944                 struct device_attribute *attr,
 945                 char *buf)
 946 {
 947         struct drm_device *ddev = dev_get_drvdata(dev);
 948         struct amdgpu_device *adev = ddev->dev_private;
 949
 950         if (is_support_sw_smu(adev))
 951                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 952         else if (adev->powerplay.pp_funcs->print_clock_levels)
 953                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 954         else
 955                 return snprintf(buf, PAGE_SIZE, "\n");
 956 }
 957
 958 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 959                 struct device_attribute *attr,
 960                 const char *buf,
 961                 size_t count)
 962 {
 963         struct drm_device *ddev = dev_get_drvdata(dev);
 964         struct amdgpu_device *adev = ddev->dev_private;
 965         int ret;
 966         uint32_t mask = 0;
 967
 968         ret = amdgpu_read_mask(buf, count, &mask);
 969         if (ret)
 970                 return ret;
 971
 972         if (is_support_sw_smu(adev))
 973                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 974         else if (adev->powerplay.pp_funcs->force_clock_level)
 975                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 976
 977         if (ret)
 978                 return -EINVAL;
 979
 980         return count;
 981 }
 982
 983 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 984                 struct device_attribute *attr,
 985                 char *buf)
 986 {
 987         struct drm_device *ddev = dev_get_drvdata(dev);
 988         struct amdgpu_device *adev = ddev->dev_private;
 989
 990         if (is_support_sw_smu(adev))
 991                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
 992         else if (adev->powerplay.pp_funcs->print_clock_levels)
 993                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 994         else
 995                 return snprintf(buf, PAGE_SIZE, "\n");
 996 }
 997
 998 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
 999                 struct device_attribute *attr,
1000                 const char *buf,
1001                 size_t count)
1002 {
1003         struct drm_device *ddev = dev_get_drvdata(dev);
1004         struct amdgpu_device *adev = ddev->dev_private;
1005         int ret;
1006         uint32_t mask = 0;
1007
1008         ret = amdgpu_read_mask(buf, count, &mask);
1009         if (ret)
1010                 return ret;
1011
1012         if (is_support_sw_smu(adev))
1013                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
1014         else if (adev->powerplay.pp_funcs->force_clock_level)
1015                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1016
1017         if (ret)
1018                 return -EINVAL;
1019
1020         return count;
1021 }
1022
1023 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1024                 struct device_attribute *attr,
1025                 char *buf)
1026 {
1027         struct drm_device *ddev = dev_get_drvdata(dev);
1028         struct amdgpu_device *adev = ddev->dev_private;
1029
1030         if (is_support_sw_smu(adev))
1031                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
1032         else if (adev->powerplay.pp_funcs->print_clock_levels)
1033                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1034         else
1035                 return snprintf(buf, PAGE_SIZE, "\n");
1036 }
1037
1038 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1039                 struct device_attribute *attr,
1040                 const char *buf,
1041                 size_t count)
1042 {
1043         struct drm_device *ddev = dev_get_drvdata(dev);
1044         struct amdgpu_device *adev = ddev->dev_private;
1045         int ret;
1046         uint32_t mask = 0;
1047
1048         ret = amdgpu_read_mask(buf, count, &mask);
1049         if (ret)
1050                 return ret;
1051
1052         if (is_support_sw_smu(adev))
1053                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1054         else if (adev->powerplay.pp_funcs->force_clock_level)
1055                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1056
1057         if (ret)
1058                 return -EINVAL;
1059
1060         return count;
1061 }
1062
1063 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1064                 struct device_attribute *attr,
1065                 char *buf)
1066 {
1067         struct drm_device *ddev = dev_get_drvdata(dev);
1068         struct amdgpu_device *adev = ddev->dev_private;
1069
1070         if (is_support_sw_smu(adev))
1071                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1072         else if (adev->powerplay.pp_funcs->print_clock_levels)
1073                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1074         else
1075                 return snprintf(buf, PAGE_SIZE, "\n");
1076 }
1077
1078 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1079                 struct device_attribute *attr,
1080                 const char *buf,
1081                 size_t count)
1082 {
1083         struct drm_device *ddev = dev_get_drvdata(dev);
1084         struct amdgpu_device *adev = ddev->dev_private;
1085         int ret;
1086         uint32_t mask = 0;
1087
1088         ret = amdgpu_read_mask(buf, count, &mask);
1089         if (ret)
1090                 return ret;
1091
1092         if (is_support_sw_smu(adev))
1093                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1094         else if (adev->powerplay.pp_funcs->force_clock_level)
1095                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1096
1097         if (ret)
1098                 return -EINVAL;
1099
1100         return count;
1101 }
1102
1103 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1104                 struct device_attribute *attr,
1105                 char *buf)
1106 {
1107         struct drm_device *ddev = dev_get_drvdata(dev);
1108         struct amdgpu_device *adev = ddev->dev_private;
1109         uint32_t value = 0;
1110
1111         if (is_support_sw_smu(adev))
1112                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1113         else if (adev->powerplay.pp_funcs->get_sclk_od)
1114                 value = amdgpu_dpm_get_sclk_od(adev);
1115
1116         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1117 }
1118
1119 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1120                 struct device_attribute *attr,
1121                 const char *buf,
1122                 size_t count)
1123 {
1124         struct drm_device *ddev = dev_get_drvdata(dev);
1125         struct amdgpu_device *adev = ddev->dev_private;
1126         int ret;
1127         long int value;
1128
1129         ret = kstrtol(buf, 0, &value);
1130
1131         if (ret) {
1132                 count = -EINVAL;
1133                 goto fail;
1134         }
1135
1136         if (is_support_sw_smu(adev)) {
1137                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1138         } else {
1139                 if (adev->powerplay.pp_funcs->set_sclk_od)
1140                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1141
1142                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1143                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1144                 } else {
1145                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1146                         amdgpu_pm_compute_clocks(adev);
1147                 }
1148         }
1149
1150 fail:
1151         return count;
1152 }
1153
1154 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1155                 struct device_attribute *attr,
1156                 char *buf)
1157 {
1158         struct drm_device *ddev = dev_get_drvdata(dev);
1159         struct amdgpu_device *adev = ddev->dev_private;
1160         uint32_t value = 0;
1161
1162         if (is_support_sw_smu(adev))
1163                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1164         else if (adev->powerplay.pp_funcs->get_mclk_od)
1165                 value = amdgpu_dpm_get_mclk_od(adev);
1166
1167         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1168 }
1169
1170 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1171                 struct device_attribute *attr,
1172                 const char *buf,
1173                 size_t count)
1174 {
1175         struct drm_device *ddev = dev_get_drvdata(dev);
1176         struct amdgpu_device *adev = ddev->dev_private;
1177         int ret;
1178         long int value;
1179
1180         ret = kstrtol(buf, 0, &value);
1181
1182         if (ret) {
1183                 count = -EINVAL;
1184                 goto fail;
1185         }
1186
1187         if (is_support_sw_smu(adev)) {
1188                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1189         } else {
1190                 if (adev->powerplay.pp_funcs->set_mclk_od)
1191                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1192
1193                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1194                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1195                 } else {
1196                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1197                         amdgpu_pm_compute_clocks(adev);
1198                 }
1199         }
1200
1201 fail:
1202         return count;
1203 }
1204
1205 /**
1206  * DOC: pp_power_profile_mode
1207  *
1208  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1209  * related to switching between power levels in a power state.  The file
1210  * pp_power_profile_mode is used for this.
1211  *
1212  * Reading this file outputs a list of all of the predefined power profiles
1213  * and the relevant heuristics settings for that profile.
1214  *
1215  * To select a profile or create a custom profile, first select manual using
1216  * power_dpm_force_performance_level.  Writing the number of a predefined
1217  * profile to pp_power_profile_mode will enable those heuristics.  To
1218  * create a custom set of heuristics, write a string of numbers to the file
1219  * starting with the number of the custom profile along with a setting
1220  * for each heuristic parameter.  Due to differences across asic families
1221  * the heuristic parameters vary from family to family.
1222  *
1223  */
1224
1225 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1226                 struct device_attribute *attr,
1227                 char *buf)
1228 {
1229         struct drm_device *ddev = dev_get_drvdata(dev);
1230         struct amdgpu_device *adev = ddev->dev_private;
1231
1232         if (is_support_sw_smu(adev))
1233                 return smu_get_power_profile_mode(&adev->smu, buf);
1234         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1235                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1236
1237         return snprintf(buf, PAGE_SIZE, "\n");
1238 }
1239
1240
1241 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1242                 struct device_attribute *attr,
1243                 const char *buf,
1244                 size_t count)
1245 {
1246         int ret = 0xff;
1247         struct drm_device *ddev = dev_get_drvdata(dev);
1248         struct amdgpu_device *adev = ddev->dev_private;
1249         uint32_t parameter_size = 0;
1250         long parameter[64];
1251         char *sub_str, buf_cpy[128];
1252         char *tmp_str;
1253         uint32_t i = 0;
1254         char tmp[2];
1255         long int profile_mode = 0;
1256         const char delimiter[3] = {' ', '\n', '\0'};
1257
1258         tmp[0] = *(buf);
1259         tmp[1] = '\0';
1260         ret = kstrtol(tmp, 0, &profile_mode);
1261         if (ret)
1262                 goto fail;
1263
1264         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1265                 if (count < 2 || count > 127)
1266                         return -EINVAL;
1267                 while (isspace(*++buf))
1268                         i++;
1269                 memcpy(buf_cpy, buf, count-i);
1270                 tmp_str = buf_cpy;
1271                 while (tmp_str[0]) {
1272                         sub_str = strsep(&tmp_str, delimiter);
1273                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1274                         if (ret) {
1275                                 count = -EINVAL;
1276                                 goto fail;
1277                         }
1278                         parameter_size++;
1279                         while (isspace(*tmp_str))
1280                                 tmp_str++;
1281                 }
1282         }
1283         parameter[parameter_size] = profile_mode;
1284         if (is_support_sw_smu(adev))
1285                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1286         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1287                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1288         if (!ret)
1289                 return count;
1290 fail:
1291         return -EINVAL;
1292 }
1293
1294 /**
1295  * DOC: busy_percent
1296  *
1297  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1298  * is as a percentage.  The file gpu_busy_percent is used for this.
1299  * The SMU firmware computes a percentage of load based on the
1300  * aggregate activity level in the IP cores.
1301  */
1302 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1303                 struct device_attribute *attr,
1304                 char *buf)
1305 {
1306         struct drm_device *ddev = dev_get_drvdata(dev);
1307         struct amdgpu_device *adev = ddev->dev_private;
1308         int r, value, size = sizeof(value);
1309
1310         /* read the IP busy sensor */
1311         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1312                                    (void *)&value, &size);
1313
1314         if (r)
1315                 return r;
1316
1317         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1318 }
1319
1320 /**
1321  * DOC: mem_busy_percent
1322  *
1323  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1324  * is as a percentage.  The file mem_busy_percent is used for this.
1325  * The SMU firmware computes a percentage of load based on the
1326  * aggregate activity level in the IP cores.
1327  */
1328 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1329                 struct device_attribute *attr,
1330                 char *buf)
1331 {
1332         struct drm_device *ddev = dev_get_drvdata(dev);
1333         struct amdgpu_device *adev = ddev->dev_private;
1334         int r, value, size = sizeof(value);
1335
1336         /* read the IP busy sensor */
1337         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1338                                    (void *)&value, &size);
1339
1340         if (r)
1341                 return r;
1342
1343         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1344 }
1345
1346 /**
1347  * DOC: pcie_bw
1348  *
1349  * The amdgpu driver provides a sysfs API for estimating how much data
1350  * has been received and sent by the GPU in the last second through PCIe.
1351  * The file pcie_bw is used for this.
1352  * The Perf counters count the number of received and sent messages and return
1353  * those values, as well as the maximum payload size of a PCIe packet (mps).
1354  * Note that it is not possible to easily and quickly obtain the size of each
1355  * packet transmitted, so we output the max payload size (mps) to allow for
1356  * quick estimation of the PCIe bandwidth usage
1357  */
1358 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1359                 struct device_attribute *attr,
1360                 char *buf)
1361 {
1362         struct drm_device *ddev = dev_get_drvdata(dev);
1363         struct amdgpu_device *adev = ddev->dev_private;
1364         uint64_t count0, count1;
1365
1366         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1367         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1368                         count0, count1, pcie_get_mps(adev->pdev));
1369 }
1370
1371 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1372 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1373                    amdgpu_get_dpm_forced_performance_level,
1374                    amdgpu_set_dpm_forced_performance_level);
1375 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1376 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1377 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1378                 amdgpu_get_pp_force_state,
1379                 amdgpu_set_pp_force_state);
1380 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1381                 amdgpu_get_pp_table,
1382                 amdgpu_set_pp_table);
1383 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1384                 amdgpu_get_pp_dpm_sclk,
1385                 amdgpu_set_pp_dpm_sclk);
1386 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1387                 amdgpu_get_pp_dpm_mclk,
1388                 amdgpu_set_pp_dpm_mclk);
1389 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1390                 amdgpu_get_pp_dpm_socclk,
1391                 amdgpu_set_pp_dpm_socclk);
1392 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1393                 amdgpu_get_pp_dpm_fclk,
1394                 amdgpu_set_pp_dpm_fclk);
1395 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1396                 amdgpu_get_pp_dpm_dcefclk,
1397                 amdgpu_set_pp_dpm_dcefclk);
1398 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1399                 amdgpu_get_pp_dpm_pcie,
1400                 amdgpu_set_pp_dpm_pcie);
1401 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1402                 amdgpu_get_pp_sclk_od,
1403                 amdgpu_set_pp_sclk_od);
1404 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1405                 amdgpu_get_pp_mclk_od,
1406                 amdgpu_set_pp_mclk_od);
1407 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1408                 amdgpu_get_pp_power_profile_mode,
1409                 amdgpu_set_pp_power_profile_mode);
1410 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1411                 amdgpu_get_pp_od_clk_voltage,
1412                 amdgpu_set_pp_od_clk_voltage);
1413 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1414                 amdgpu_get_busy_percent, NULL);
1415 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1416                 amdgpu_get_memory_busy_percent, NULL);
1417 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1418 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1419                 amdgpu_get_ppfeature_status,
1420                 amdgpu_set_ppfeature_status);
1421
1422 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1423                                       struct device_attribute *attr,
1424                                       char *buf)
1425 {
1426         struct amdgpu_device *adev = dev_get_drvdata(dev);
1427         struct drm_device *ddev = adev->ddev;
1428         int channel = to_sensor_dev_attr(attr)->index;
1429         int r, temp, size = sizeof(temp);
1430
1431         /* Can't get temperature when the card is off */
1432         if  ((adev->flags & AMD_IS_PX) &&
1433              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1434                 return -EINVAL;
1435
1436         if (channel >= PP_TEMP_MAX)
1437                 return -EINVAL;
1438
1439         switch (channel) {
1440         case PP_TEMP_JUNCTION:
1441                 /* get current junction temperature */
1442                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1443                                            (void *)&temp, &size);
1444                 if (r)
1445                         return r;
1446                 break;
1447         case PP_TEMP_EDGE:
1448                 /* get current edge temperature */
1449                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1450                                            (void *)&temp, &size);
1451                 if (r)
1452                         return r;
1453                 break;
1454         case PP_TEMP_MEM:
1455                 /* get current memory temperature */
1456                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1457                                            (void *)&temp, &size);
1458                 if (r)
1459                         return r;
1460                 break;
1461         }
1462
1463         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1464 }
1465
1466 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1467                                              struct device_attribute *attr,
1468                                              char *buf)
1469 {
1470         struct amdgpu_device *adev = dev_get_drvdata(dev);
1471         int hyst = to_sensor_dev_attr(attr)->index;
1472         int temp;
1473
1474         if (hyst)
1475                 temp = adev->pm.dpm.thermal.min_temp;
1476         else
1477                 temp = adev->pm.dpm.thermal.max_temp;
1478
1479         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1480 }
1481
1482 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1483                                              struct device_attribute *attr,
1484                                              char *buf)
1485 {
1486         struct amdgpu_device *adev = dev_get_drvdata(dev);
1487         int hyst = to_sensor_dev_attr(attr)->index;
1488         int temp;
1489
1490         if (hyst)
1491                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1492         else
1493                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1494
1495         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1496 }
1497
1498 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1499                                              struct device_attribute *attr,
1500                                              char *buf)
1501 {
1502         struct amdgpu_device *adev = dev_get_drvdata(dev);
1503         int hyst = to_sensor_dev_attr(attr)->index;
1504         int temp;
1505
1506         if (hyst)
1507                 temp = adev->pm.dpm.thermal.min_mem_temp;
1508         else
1509                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1510
1511         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1512 }
1513
1514 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1515                                              struct device_attribute *attr,
1516                                              char *buf)
1517 {
1518         int channel = to_sensor_dev_attr(attr)->index;
1519
1520         if (channel >= PP_TEMP_MAX)
1521                 return -EINVAL;
1522
1523         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1524 }
1525
1526 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1527                                              struct device_attribute *attr,
1528                                              char *buf)
1529 {
1530         struct amdgpu_device *adev = dev_get_drvdata(dev);
1531         int channel = to_sensor_dev_attr(attr)->index;
1532         int temp = 0;
1533
1534         if (channel >= PP_TEMP_MAX)
1535                 return -EINVAL;
1536
1537         switch (channel) {
1538         case PP_TEMP_JUNCTION:
1539                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1540                 break;
1541         case PP_TEMP_EDGE:
1542                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1543                 break;
1544         case PP_TEMP_MEM:
1545                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1546                 break;
1547         }
1548
1549         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1550 }
1551
1552 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1553                                             struct device_attribute *attr,
1554                                             char *buf)
1555 {
1556         struct amdgpu_device *adev = dev_get_drvdata(dev);
1557         u32 pwm_mode = 0;
1558         if (is_support_sw_smu(adev)) {
1559                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1560         } else {
1561                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1562                         return -EINVAL;
1563
1564                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1565         }
1566
1567         return sprintf(buf, "%i\n", pwm_mode);
1568 }
1569
1570 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1571                                             struct device_attribute *attr,
1572                                             const char *buf,
1573                                             size_t count)
1574 {
1575         struct amdgpu_device *adev = dev_get_drvdata(dev);
1576         int err;
1577         int value;
1578
1579         /* Can't adjust fan when the card is off */
1580         if  ((adev->flags & AMD_IS_PX) &&
1581              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1582                 return -EINVAL;
1583
1584         if (is_support_sw_smu(adev)) {
1585                 err = kstrtoint(buf, 10, &value);
1586                 if (err)
1587                         return err;
1588
1589                 smu_set_fan_control_mode(&adev->smu, value);
1590         } else {
1591                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1592                         return -EINVAL;
1593
1594                 err = kstrtoint(buf, 10, &value);
1595                 if (err)
1596                         return err;
1597
1598                 amdgpu_dpm_set_fan_control_mode(adev, value);
1599         }
1600
1601         return count;
1602 }
1603
1604 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1605                                          struct device_attribute *attr,
1606                                          char *buf)
1607 {
1608         return sprintf(buf, "%i\n", 0);
1609 }
1610
1611 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1612                                          struct device_attribute *attr,
1613                                          char *buf)
1614 {
1615         return sprintf(buf, "%i\n", 255);
1616 }
1617
1618 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1619                                      struct device_attribute *attr,
1620                                      const char *buf, size_t count)
1621 {
1622         struct amdgpu_device *adev = dev_get_drvdata(dev);
1623         int err;
1624         u32 value;
1625         u32 pwm_mode;
1626
1627         /* Can't adjust fan when the card is off */
1628         if  ((adev->flags & AMD_IS_PX) &&
1629              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1630                 return -EINVAL;
1631         if (is_support_sw_smu(adev))
1632                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1633         else
1634                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1635         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1636                 pr_info("manual fan speed control should be enabled first\n");
1637                 return -EINVAL;
1638         }
1639
1640         err = kstrtou32(buf, 10, &value);
1641         if (err)
1642                 return err;
1643
1644         value = (value * 100) / 255;
1645
1646         if (is_support_sw_smu(adev)) {
1647                 err = smu_set_fan_speed_percent(&adev->smu, value);
1648                 if (err)
1649                         return err;
1650         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1651                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1652                 if (err)
1653                         return err;
1654         }
1655
1656         return count;
1657 }
1658
1659 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1660                                      struct device_attribute *attr,
1661                                      char *buf)
1662 {
1663         struct amdgpu_device *adev = dev_get_drvdata(dev);
1664         int err;
1665         u32 speed = 0;
1666
1667         /* Can't adjust fan when the card is off */
1668         if  ((adev->flags & AMD_IS_PX) &&
1669              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1670                 return -EINVAL;
1671
1672         if (is_support_sw_smu(adev)) {
1673                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1674                 if (err)
1675                         return err;
1676         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1677                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1678                 if (err)
1679                         return err;
1680         }
1681
1682         speed = (speed * 255) / 100;
1683
1684         return sprintf(buf, "%i\n", speed);
1685 }
1686
1687 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1688                                            struct device_attribute *attr,
1689                                            char *buf)
1690 {
1691         struct amdgpu_device *adev = dev_get_drvdata(dev);
1692         int err;
1693         u32 speed = 0;
1694
1695         /* Can't adjust fan when the card is off */
1696         if  ((adev->flags & AMD_IS_PX) &&
1697              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1698                 return -EINVAL;
1699
1700         if (is_support_sw_smu(adev)) {
1701                 err = smu_get_current_rpm(&adev->smu, &speed);
1702                 if (err)
1703                         return err;
1704         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1705                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1706                 if (err)
1707                         return err;
1708         }
1709
1710         return sprintf(buf, "%i\n", speed);
1711 }
1712
1713 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1714                                          struct device_attribute *attr,
1715                                          char *buf)
1716 {
1717         struct amdgpu_device *adev = dev_get_drvdata(dev);
1718         u32 min_rpm = 0;
1719         u32 size = sizeof(min_rpm);
1720         int r;
1721
1722         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1723                                    (void *)&min_rpm, &size);
1724         if (r)
1725                 return r;
1726
1727         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1728 }
1729
1730 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1731                                          struct device_attribute *attr,
1732                                          char *buf)
1733 {
1734         struct amdgpu_device *adev = dev_get_drvdata(dev);
1735         u32 max_rpm = 0;
1736         u32 size = sizeof(max_rpm);
1737         int r;
1738
1739         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1740                                    (void *)&max_rpm, &size);
1741         if (r)
1742                 return r;
1743
1744         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1745 }
1746
1747 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1748                                            struct device_attribute *attr,
1749                                            char *buf)
1750 {
1751         struct amdgpu_device *adev = dev_get_drvdata(dev);
1752         int err;
1753         u32 rpm = 0;
1754
1755         /* Can't adjust fan when the card is off */
1756         if  ((adev->flags & AMD_IS_PX) &&
1757              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1758                 return -EINVAL;
1759
1760         if (is_support_sw_smu(adev)) {
1761                 err = smu_get_current_rpm(&adev->smu, &rpm);
1762                 if (err)
1763                         return err;
1764         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1765                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1766                 if (err)
1767                         return err;
1768         }
1769
1770         return sprintf(buf, "%i\n", rpm);
1771 }
1772
1773 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1774                                      struct device_attribute *attr,
1775                                      const char *buf, size_t count)
1776 {
1777         struct amdgpu_device *adev = dev_get_drvdata(dev);
1778         int err;
1779         u32 value;
1780         u32 pwm_mode;
1781
1782         if (is_support_sw_smu(adev))
1783                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1784         else
1785                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1786
1787         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1788                 return -ENODATA;
1789
1790         /* Can't adjust fan when the card is off */
1791         if  ((adev->flags & AMD_IS_PX) &&
1792              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1793                 return -EINVAL;
1794
1795         err = kstrtou32(buf, 10, &value);
1796         if (err)
1797                 return err;
1798
1799         if (is_support_sw_smu(adev)) {
1800                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1801                 if (err)
1802                         return err;
1803         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1804                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1805                 if (err)
1806                         return err;
1807         }
1808
1809         return count;
1810 }
1811
1812 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1813                                             struct device_attribute *attr,
1814                                             char *buf)
1815 {
1816         struct amdgpu_device *adev = dev_get_drvdata(dev);
1817         u32 pwm_mode = 0;
1818
1819         if (is_support_sw_smu(adev)) {
1820                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1821         } else {
1822                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1823                         return -EINVAL;
1824
1825                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1826         }
1827         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1828 }
1829
1830 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1831                                             struct device_attribute *attr,
1832                                             const char *buf,
1833                                             size_t count)
1834 {
1835         struct amdgpu_device *adev = dev_get_drvdata(dev);
1836         int err;
1837         int value;
1838         u32 pwm_mode;
1839
1840         /* Can't adjust fan when the card is off */
1841         if  ((adev->flags & AMD_IS_PX) &&
1842              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1843                 return -EINVAL;
1844
1845
1846         err = kstrtoint(buf, 10, &value);
1847         if (err)
1848                 return err;
1849
1850         if (value == 0)
1851                 pwm_mode = AMD_FAN_CTRL_AUTO;
1852         else if (value == 1)
1853                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1854         else
1855                 return -EINVAL;
1856
1857         if (is_support_sw_smu(adev)) {
1858                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1859         } else {
1860                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1861                         return -EINVAL;
1862                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1863         }
1864
1865         return count;
1866 }
1867
1868 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1869                                         struct device_attribute *attr,
1870                                         char *buf)
1871 {
1872         struct amdgpu_device *adev = dev_get_drvdata(dev);
1873         struct drm_device *ddev = adev->ddev;
1874         u32 vddgfx;
1875         int r, size = sizeof(vddgfx);
1876
1877         /* Can't get voltage when the card is off */
1878         if  ((adev->flags & AMD_IS_PX) &&
1879              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1880                 return -EINVAL;
1881
1882         /* get the voltage */
1883         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1884                                    (void *)&vddgfx, &size);
1885         if (r)
1886                 return r;
1887
1888         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1889 }
1890
1891 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1892                                               struct device_attribute *attr,
1893                                               char *buf)
1894 {
1895         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1896 }
1897
1898 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1899                                        struct device_attribute *attr,
1900                                        char *buf)
1901 {
1902         struct amdgpu_device *adev = dev_get_drvdata(dev);
1903         struct drm_device *ddev = adev->ddev;
1904         u32 vddnb;
1905         int r, size = sizeof(vddnb);
1906
1907         /* only APUs have vddnb */
1908         if  (!(adev->flags & AMD_IS_APU))
1909                 return -EINVAL;
1910
1911         /* Can't get voltage when the card is off */
1912         if  ((adev->flags & AMD_IS_PX) &&
1913              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1914                 return -EINVAL;
1915
1916         /* get the voltage */
1917         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1918                                    (void *)&vddnb, &size);
1919         if (r)
1920                 return r;
1921
1922         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1923 }
1924
1925 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1926                                               struct device_attribute *attr,
1927                                               char *buf)
1928 {
1929         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1930 }
1931
1932 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1933                                            struct device_attribute *attr,
1934                                            char *buf)
1935 {
1936         struct amdgpu_device *adev = dev_get_drvdata(dev);
1937         struct drm_device *ddev = adev->ddev;
1938         u32 query = 0;
1939         int r, size = sizeof(u32);
1940         unsigned uw;
1941
1942         /* Can't get power when the card is off */
1943         if  ((adev->flags & AMD_IS_PX) &&
1944              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1945                 return -EINVAL;
1946
1947         /* get the voltage */
1948         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1949                                    (void *)&query, &size);
1950         if (r)
1951                 return r;
1952
1953         /* convert to microwatts */
1954         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1955
1956         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1957 }
1958
1959 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1960                                          struct device_attribute *attr,
1961                                          char *buf)
1962 {
1963         return sprintf(buf, "%i\n", 0);
1964 }
1965
1966 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1967                                          struct device_attribute *attr,
1968                                          char *buf)
1969 {
1970         struct amdgpu_device *adev = dev_get_drvdata(dev);
1971         uint32_t limit = 0;
1972
1973         if (is_support_sw_smu(adev)) {
1974                 smu_get_power_limit(&adev->smu, &limit, true);
1975                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1976         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1977                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1978                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1979         } else {
1980                 return snprintf(buf, PAGE_SIZE, "\n");
1981         }
1982 }
1983
1984 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1985                                          struct device_attribute *attr,
1986                                          char *buf)
1987 {
1988         struct amdgpu_device *adev = dev_get_drvdata(dev);
1989         uint32_t limit = 0;
1990
1991         if (is_support_sw_smu(adev)) {
1992                 smu_get_power_limit(&adev->smu, &limit, false);
1993                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1994         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1995                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1996                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1997         } else {
1998                 return snprintf(buf, PAGE_SIZE, "\n");
1999         }
2000 }
2001
2002
2003 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2004                 struct device_attribute *attr,
2005                 const char *buf,
2006                 size_t count)
2007 {
2008         struct amdgpu_device *adev = dev_get_drvdata(dev);
2009         int err;
2010         u32 value;
2011
2012         err = kstrtou32(buf, 10, &value);
2013         if (err)
2014                 return err;
2015
2016         value = value / 1000000; /* convert to Watt */
2017         if (is_support_sw_smu(adev)) {
2018                 adev->smu.funcs->set_power_limit(&adev->smu, value);
2019         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2020                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2021                 if (err)
2022                         return err;
2023         } else {
2024                 return -EINVAL;
2025         }
2026
2027         return count;
2028 }
2029
2030 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2031                                       struct device_attribute *attr,
2032                                       char *buf)
2033 {
2034         struct amdgpu_device *adev = dev_get_drvdata(dev);
2035         struct drm_device *ddev = adev->ddev;
2036         uint32_t sclk;
2037         int r, size = sizeof(sclk);
2038
2039         /* Can't get voltage when the card is off */
2040         if  ((adev->flags & AMD_IS_PX) &&
2041              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2042                 return -EINVAL;
2043
2044         /* sanity check PP is enabled */
2045         if (!(adev->powerplay.pp_funcs &&
2046               adev->powerplay.pp_funcs->read_sensor))
2047               return -EINVAL;
2048
2049         /* get the sclk */
2050         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2051                                    (void *)&sclk, &size);
2052         if (r)
2053                 return r;
2054
2055         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2056 }
2057
2058 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2059                                             struct device_attribute *attr,
2060                                             char *buf)
2061 {
2062         return snprintf(buf, PAGE_SIZE, "sclk\n");
2063 }
2064
2065 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2066                                       struct device_attribute *attr,
2067                                       char *buf)
2068 {
2069         struct amdgpu_device *adev = dev_get_drvdata(dev);
2070         struct drm_device *ddev = adev->ddev;
2071         uint32_t mclk;
2072         int r, size = sizeof(mclk);
2073
2074         /* Can't get voltage when the card is off */
2075         if  ((adev->flags & AMD_IS_PX) &&
2076              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2077                 return -EINVAL;
2078
2079         /* sanity check PP is enabled */
2080         if (!(adev->powerplay.pp_funcs &&
2081               adev->powerplay.pp_funcs->read_sensor))
2082               return -EINVAL;
2083
2084         /* get the sclk */
2085         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2086                                    (void *)&mclk, &size);
2087         if (r)
2088                 return r;
2089
2090         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2091 }
2092
2093 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2094                                             struct device_attribute *attr,
2095                                             char *buf)
2096 {
2097         return snprintf(buf, PAGE_SIZE, "mclk\n");
2098 }
2099
2100 /**
2101  * DOC: hwmon
2102  *
2103  * The amdgpu driver exposes the following sensor interfaces:
2104  *
2105  * - GPU temperature (via the on-die sensor)
2106  *
2107  * - GPU voltage
2108  *
2109  * - Northbridge voltage (APUs only)
2110  *
2111  * - GPU power
2112  *
2113  * - GPU fan
2114  *
2115  * - GPU gfx/compute engine clock
2116  *
2117  * - GPU memory clock (dGPU only)
2118  *
2119  * hwmon interfaces for GPU temperature:
2120  *
2121  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2122  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2123  *
2124  * - temp[1-3]_label: temperature channel label
2125  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2126  *
2127  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2128  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2129  *
2130  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2131  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2132  *
2133  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2134  *   - these are supported on SOC15 dGPUs only
2135  *
2136  * hwmon interfaces for GPU voltage:
2137  *
2138  * - in0_input: the voltage on the GPU in millivolts
2139  *
2140  * - in1_input: the voltage on the Northbridge in millivolts
2141  *
2142  * hwmon interfaces for GPU power:
2143  *
2144  * - power1_average: average power used by the GPU in microWatts
2145  *
2146  * - power1_cap_min: minimum cap supported in microWatts
2147  *
2148  * - power1_cap_max: maximum cap supported in microWatts
2149  *
2150  * - power1_cap: selected power cap in microWatts
2151  *
2152  * hwmon interfaces for GPU fan:
2153  *
2154  * - pwm1: pulse width modulation fan level (0-255)
2155  *
2156  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2157  *
2158  * - pwm1_min: pulse width modulation fan control minimum level (0)
2159  *
2160  * - pwm1_max: pulse width modulation fan control maximum level (255)
2161  *
2162  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2163  *
2164  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2165  *
2166  * - fan1_input: fan speed in RPM
2167  *
2168  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2169  *
2170  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2171  *
2172  * hwmon interfaces for GPU clocks:
2173  *
2174  * - freq1_input: the gfx/compute clock in hertz
2175  *
2176  * - freq2_input: the memory clock in hertz
2177  *
2178  * You can use hwmon tools like sensors to view this information on your system.
2179  *
2180  */
2181
2182 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2183 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2184 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2185 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2186 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2187 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2188 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2189 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2190 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2191 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2192 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2193 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2194 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2195 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2196 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2197 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2198 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2199 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2200 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2201 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2202 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2203 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2204 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2205 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2206 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2207 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2208 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2209 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2210 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2211 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2212 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2213 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2214 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2215 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2216 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2217 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2218
2219 static struct attribute *hwmon_attributes[] = {
2220         &sensor_dev_attr_temp1_input.dev_attr.attr,
2221         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2222         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2223         &sensor_dev_attr_temp2_input.dev_attr.attr,
2224         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2225         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2226         &sensor_dev_attr_temp3_input.dev_attr.attr,
2227         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2228         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2229         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2230         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2231         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2232         &sensor_dev_attr_temp1_label.dev_attr.attr,
2233         &sensor_dev_attr_temp2_label.dev_attr.attr,
2234         &sensor_dev_attr_temp3_label.dev_attr.attr,
2235         &sensor_dev_attr_pwm1.dev_attr.attr,
2236         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2237         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2238         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2239         &sensor_dev_attr_fan1_input.dev_attr.attr,
2240         &sensor_dev_attr_fan1_min.dev_attr.attr,
2241         &sensor_dev_attr_fan1_max.dev_attr.attr,
2242         &sensor_dev_attr_fan1_target.dev_attr.attr,
2243         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2244         &sensor_dev_attr_in0_input.dev_attr.attr,
2245         &sensor_dev_attr_in0_label.dev_attr.attr,
2246         &sensor_dev_attr_in1_input.dev_attr.attr,
2247         &sensor_dev_attr_in1_label.dev_attr.attr,
2248         &sensor_dev_attr_power1_average.dev_attr.attr,
2249         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2250         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2251         &sensor_dev_attr_power1_cap.dev_attr.attr,
2252         &sensor_dev_attr_freq1_input.dev_attr.attr,
2253         &sensor_dev_attr_freq1_label.dev_attr.attr,
2254         &sensor_dev_attr_freq2_input.dev_attr.attr,
2255         &sensor_dev_attr_freq2_label.dev_attr.attr,
2256         NULL
2257 };
2258
2259 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2260                                         struct attribute *attr, int index)
2261 {
2262         struct device *dev = kobj_to_dev(kobj);
2263         struct amdgpu_device *adev = dev_get_drvdata(dev);
2264         umode_t effective_mode = attr->mode;
2265
2266         /* Skip fan attributes if fan is not present */
2267         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2268             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2269             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2270             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2271             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2272             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2273             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2274             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2275             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2276                 return 0;
2277
2278         /* Skip fan attributes on APU */
2279         if ((adev->flags & AMD_IS_APU) &&
2280             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2281              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2282              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2283              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2284              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2285              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2286              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2287              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2288              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2289                 return 0;
2290
2291         /* Skip limit attributes if DPM is not enabled */
2292         if (!adev->pm.dpm_enabled &&
2293             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2294              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2295              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2296              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2297              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2298              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2299              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2300              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2301              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2302              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2303              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2304                 return 0;
2305
2306         if (!is_support_sw_smu(adev)) {
2307                 /* mask fan attributes if we have no bindings for this asic to expose */
2308                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2309                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2310                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2311                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2312                         effective_mode &= ~S_IRUGO;
2313
2314                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2315                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2316                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2317                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2318                         effective_mode &= ~S_IWUSR;
2319         }
2320
2321         if ((adev->flags & AMD_IS_APU) &&
2322             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2323              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2324              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2325              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2326                 return 0;
2327
2328         if (!is_support_sw_smu(adev)) {
2329                 /* hide max/min values if we can't both query and manage the fan */
2330                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2331                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2332                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2333                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2334                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2335                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2336                         return 0;
2337
2338                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2339                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2340                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2341                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2342                         return 0;
2343         }
2344
2345         /* only APUs have vddnb */
2346         if (!(adev->flags & AMD_IS_APU) &&
2347             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2348              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2349                 return 0;
2350
2351         /* no mclk on APUs */
2352         if ((adev->flags & AMD_IS_APU) &&
2353             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2354              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2355                 return 0;
2356
2357         /* only SOC15 dGPUs support hotspot and mem temperatures */
2358         if (((adev->flags & AMD_IS_APU) ||
2359              adev->asic_type < CHIP_VEGA10) &&
2360             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2361              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2362              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2363              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2364              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2365              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2366              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2367              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2368              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2369              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2370              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2371                 return 0;
2372
2373         return effective_mode;
2374 }
2375
2376 static const struct attribute_group hwmon_attrgroup = {
2377         .attrs = hwmon_attributes,
2378         .is_visible = hwmon_attributes_visible,
2379 };
2380
2381 static const struct attribute_group *hwmon_groups[] = {
2382         &hwmon_attrgroup,
2383         NULL
2384 };
2385
2386 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2387 {
2388         struct amdgpu_device *adev =
2389                 container_of(work, struct amdgpu_device,
2390                              pm.dpm.thermal.work);
2391         /* switch to the thermal state */
2392         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2393         int temp, size = sizeof(temp);
2394
2395         if (!adev->pm.dpm_enabled)
2396                 return;
2397
2398         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2399                                     (void *)&temp, &size)) {
2400                 if (temp < adev->pm.dpm.thermal.min_temp)
2401                         /* switch back the user state */
2402                         dpm_state = adev->pm.dpm.user_state;
2403         } else {
2404                 if (adev->pm.dpm.thermal.high_to_low)
2405                         /* switch back the user state */
2406                         dpm_state = adev->pm.dpm.user_state;
2407         }
2408         mutex_lock(&adev->pm.mutex);
2409         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2410                 adev->pm.dpm.thermal_active = true;
2411         else
2412                 adev->pm.dpm.thermal_active = false;
2413         adev->pm.dpm.state = dpm_state;
2414         mutex_unlock(&adev->pm.mutex);
2415
2416         amdgpu_pm_compute_clocks(adev);
2417 }
2418
2419 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2420                                                      enum amd_pm_state_type dpm_state)
2421 {
2422         int i;
2423         struct amdgpu_ps *ps;
2424         u32 ui_class;
2425         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2426                 true : false;
2427
2428         /* check if the vblank period is too short to adjust the mclk */
2429         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2430                 if (amdgpu_dpm_vblank_too_short(adev))
2431                         single_display = false;
2432         }
2433
2434         /* certain older asics have a separare 3D performance state,
2435          * so try that first if the user selected performance
2436          */
2437         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2438                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2439         /* balanced states don't exist at the moment */
2440         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2441                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2442
2443 restart_search:
2444         /* Pick the best power state based on current conditions */
2445         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2446                 ps = &adev->pm.dpm.ps[i];
2447                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2448                 switch (dpm_state) {
2449                 /* user states */
2450                 case POWER_STATE_TYPE_BATTERY:
2451                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2452                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2453                                         if (single_display)
2454                                                 return ps;
2455                                 } else
2456                                         return ps;
2457                         }
2458                         break;
2459                 case POWER_STATE_TYPE_BALANCED:
2460                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2461                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2462                                         if (single_display)
2463                                                 return ps;
2464                                 } else
2465                                         return ps;
2466                         }
2467                         break;
2468                 case POWER_STATE_TYPE_PERFORMANCE:
2469                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2470                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2471                                         if (single_display)
2472                                                 return ps;
2473                                 } else
2474                                         return ps;
2475                         }
2476                         break;
2477                 /* internal states */
2478                 case POWER_STATE_TYPE_INTERNAL_UVD:
2479                         if (adev->pm.dpm.uvd_ps)
2480                                 return adev->pm.dpm.uvd_ps;
2481                         else
2482                                 break;
2483                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2484                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2485                                 return ps;
2486                         break;
2487                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2488                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2489                                 return ps;
2490                         break;
2491                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2492                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2493                                 return ps;
2494                         break;
2495                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2496                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2497                                 return ps;
2498                         break;
2499                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2500                         return adev->pm.dpm.boot_ps;
2501                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2502                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2503                                 return ps;
2504                         break;
2505                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2506                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2507                                 return ps;
2508                         break;
2509                 case POWER_STATE_TYPE_INTERNAL_ULV:
2510                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2511                                 return ps;
2512                         break;
2513                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2514                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2515                                 return ps;
2516                         break;
2517                 default:
2518                         break;
2519                 }
2520         }
2521         /* use a fallback state if we didn't match */
2522         switch (dpm_state) {
2523         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2524                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2525                 goto restart_search;
2526         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2527         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2528         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2529                 if (adev->pm.dpm.uvd_ps) {
2530                         return adev->pm.dpm.uvd_ps;
2531                 } else {
2532                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2533                         goto restart_search;
2534                 }
2535         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2536                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2537                 goto restart_search;
2538         case POWER_STATE_TYPE_INTERNAL_ACPI:
2539                 dpm_state = POWER_STATE_TYPE_BATTERY;
2540                 goto restart_search;
2541         case POWER_STATE_TYPE_BATTERY:
2542         case POWER_STATE_TYPE_BALANCED:
2543         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2544                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2545                 goto restart_search;
2546         default:
2547                 break;
2548         }
2549
2550         return NULL;
2551 }
2552
2553 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2554 {
2555         struct amdgpu_ps *ps;
2556         enum amd_pm_state_type dpm_state;
2557         int ret;
2558         bool equal = false;
2559
2560         /* if dpm init failed */
2561         if (!adev->pm.dpm_enabled)
2562                 return;
2563
2564         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2565                 /* add other state override checks here */
2566                 if ((!adev->pm.dpm.thermal_active) &&
2567                     (!adev->pm.dpm.uvd_active))
2568                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2569         }
2570         dpm_state = adev->pm.dpm.state;
2571
2572         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2573         if (ps)
2574                 adev->pm.dpm.requested_ps = ps;
2575         else
2576                 return;
2577
2578         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2579                 printk("switching from power state:\n");
2580                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2581                 printk("switching to power state:\n");
2582                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2583         }
2584
2585         /* update whether vce is active */
2586         ps->vce_active = adev->pm.dpm.vce_active;
2587         if (adev->powerplay.pp_funcs->display_configuration_changed)
2588                 amdgpu_dpm_display_configuration_changed(adev);
2589
2590         ret = amdgpu_dpm_pre_set_power_state(adev);
2591         if (ret)
2592                 return;
2593
2594         if (adev->powerplay.pp_funcs->check_state_equal) {
2595                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2596                         equal = false;
2597         }
2598
2599         if (equal)
2600                 return;
2601
2602         amdgpu_dpm_set_power_state(adev);
2603         amdgpu_dpm_post_set_power_state(adev);
2604
2605         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2606         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2607
2608         if (adev->powerplay.pp_funcs->force_performance_level) {
2609                 if (adev->pm.dpm.thermal_active) {
2610                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2611                         /* force low perf level for thermal */
2612                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2613                         /* save the user's level */
2614                         adev->pm.dpm.forced_level = level;
2615                 } else {
2616                         /* otherwise, user selected level */
2617                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2618                 }
2619         }
2620 }
2621
2622 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2623 {
2624         int ret = 0;
2625         if (is_support_sw_smu(adev)) {
2626             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2627             if (ret)
2628                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2629                           enable ? "true" : "false", ret);
2630         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2631                 /* enable/disable UVD */
2632                 mutex_lock(&adev->pm.mutex);
2633                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2634                 mutex_unlock(&adev->pm.mutex);
2635         }
2636         /* enable/disable Low Memory PState for UVD (4k videos) */
2637         if (adev->asic_type == CHIP_STONEY &&
2638                 adev->uvd.decode_image_width >= WIDTH_4K) {
2639                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2640
2641                 if (hwmgr && hwmgr->hwmgr_func &&
2642                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2643                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2644                                                                !enable,
2645                                                                true);
2646         }
2647 }
2648
2649 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2650 {
2651         int ret = 0;
2652         if (is_support_sw_smu(adev)) {
2653             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2654             if (ret)
2655                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2656                           enable ? "true" : "false", ret);
2657         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2658                 /* enable/disable VCE */
2659                 mutex_lock(&adev->pm.mutex);
2660                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2661                 mutex_unlock(&adev->pm.mutex);
2662         }
2663 }
2664
2665 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2666 {
2667         int i;
2668
2669         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2670                 return;
2671
2672         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2673                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2674
2675 }
2676
2677 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2678 {
2679         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2680         int ret;
2681
2682         if (adev->pm.sysfs_initialized)
2683                 return 0;
2684
2685         if (adev->pm.dpm_enabled == 0)
2686                 return 0;
2687
2688         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2689                                                                    DRIVER_NAME, adev,
2690                                                                    hwmon_groups);
2691         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2692                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2693                 dev_err(adev->dev,
2694                         "Unable to register hwmon device: %d\n", ret);
2695                 return ret;
2696         }
2697
2698         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2699         if (ret) {
2700                 DRM_ERROR("failed to create device file for dpm state\n");
2701                 return ret;
2702         }
2703         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2704         if (ret) {
2705                 DRM_ERROR("failed to create device file for dpm state\n");
2706                 return ret;
2707         }
2708
2709
2710         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2711         if (ret) {
2712                 DRM_ERROR("failed to create device file pp_num_states\n");
2713                 return ret;
2714         }
2715         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2716         if (ret) {
2717                 DRM_ERROR("failed to create device file pp_cur_state\n");
2718                 return ret;
2719         }
2720         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2721         if (ret) {
2722                 DRM_ERROR("failed to create device file pp_force_state\n");
2723                 return ret;
2724         }
2725         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2726         if (ret) {
2727                 DRM_ERROR("failed to create device file pp_table\n");
2728                 return ret;
2729         }
2730
2731         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2732         if (ret) {
2733                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2734                 return ret;
2735         }
2736         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2737         if (ret) {
2738                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2739                 return ret;
2740         }
2741         if (adev->asic_type >= CHIP_VEGA10) {
2742                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2743                 if (ret) {
2744                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2745                         return ret;
2746                 }
2747                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2748                 if (ret) {
2749                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2750                         return ret;
2751                 }
2752         }
2753         if (adev->asic_type >= CHIP_VEGA20) {
2754                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2755                 if (ret) {
2756                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2757                         return ret;
2758                 }
2759         }
2760         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2761         if (ret) {
2762                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2763                 return ret;
2764         }
2765         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2766         if (ret) {
2767                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2768                 return ret;
2769         }
2770         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2771         if (ret) {
2772                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2773                 return ret;
2774         }
2775         ret = device_create_file(adev->dev,
2776                         &dev_attr_pp_power_profile_mode);
2777         if (ret) {
2778                 DRM_ERROR("failed to create device file "
2779                                 "pp_power_profile_mode\n");
2780                 return ret;
2781         }
2782         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2783             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2784                 ret = device_create_file(adev->dev,
2785                                 &dev_attr_pp_od_clk_voltage);
2786                 if (ret) {
2787                         DRM_ERROR("failed to create device file "
2788                                         "pp_od_clk_voltage\n");
2789                         return ret;
2790                 }
2791         }
2792         ret = device_create_file(adev->dev,
2793                         &dev_attr_gpu_busy_percent);
2794         if (ret) {
2795                 DRM_ERROR("failed to create device file "
2796                                 "gpu_busy_level\n");
2797                 return ret;
2798         }
2799         /* APU does not have its own dedicated memory */
2800         if (!(adev->flags & AMD_IS_APU)) {
2801                 ret = device_create_file(adev->dev,
2802                                 &dev_attr_mem_busy_percent);
2803                 if (ret) {
2804                         DRM_ERROR("failed to create device file "
2805                                         "mem_busy_percent\n");
2806                         return ret;
2807                 }
2808         }
2809         /* PCIe Perf counters won't work on APU nodes */
2810         if (!(adev->flags & AMD_IS_APU)) {
2811                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2812                 if (ret) {
2813                         DRM_ERROR("failed to create device file pcie_bw\n");
2814                         return ret;
2815                 }
2816         }
2817         ret = amdgpu_debugfs_pm_init(adev);
2818         if (ret) {
2819                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2820                 return ret;
2821         }
2822
2823         if ((adev->asic_type >= CHIP_VEGA10) &&
2824             !(adev->flags & AMD_IS_APU)) {
2825                 ret = device_create_file(adev->dev,
2826                                 &dev_attr_ppfeatures);
2827                 if (ret) {
2828                         DRM_ERROR("failed to create device file "
2829                                         "ppfeatures\n");
2830                         return ret;
2831                 }
2832         }
2833
2834         adev->pm.sysfs_initialized = true;
2835
2836         return 0;
2837 }
2838
2839 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2840 {
2841         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2842
2843         if (adev->pm.dpm_enabled == 0)
2844                 return;
2845
2846         if (adev->pm.int_hwmon_dev)
2847                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2848         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2849         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2850
2851         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2852         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2853         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2854         device_remove_file(adev->dev, &dev_attr_pp_table);
2855
2856         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2857         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2858         if (adev->asic_type >= CHIP_VEGA10) {
2859                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2860                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2861         }
2862         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2863         if (adev->asic_type >= CHIP_VEGA20)
2864                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2865         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2866         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2867         device_remove_file(adev->dev,
2868                         &dev_attr_pp_power_profile_mode);
2869         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2870             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2871                 device_remove_file(adev->dev,
2872                                 &dev_attr_pp_od_clk_voltage);
2873         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2874         if (!(adev->flags & AMD_IS_APU))
2875                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2876         if (!(adev->flags & AMD_IS_APU))
2877                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2878         if ((adev->asic_type >= CHIP_VEGA10) &&
2879             !(adev->flags & AMD_IS_APU))
2880                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2881 }
2882
2883 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2884 {
2885         int i = 0;
2886
2887         if (!adev->pm.dpm_enabled)
2888                 return;
2889
2890         if (adev->mode_info.num_crtc)
2891                 amdgpu_display_bandwidth_update(adev);
2892
2893         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2894                 struct amdgpu_ring *ring = adev->rings[i];
2895                 if (ring && ring->sched.ready)
2896                         amdgpu_fence_wait_empty(ring);
2897         }
2898
2899         if (is_support_sw_smu(adev)) {
2900                 struct smu_context *smu = &adev->smu;
2901                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2902                 mutex_lock(&(smu->mutex));
2903                 smu_handle_task(&adev->smu,
2904                                 smu_dpm->dpm_level,
2905                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2906                 mutex_unlock(&(smu->mutex));
2907         } else {
2908                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2909                         if (!amdgpu_device_has_dc_support(adev)) {
2910                                 mutex_lock(&adev->pm.mutex);
2911                                 amdgpu_dpm_get_active_displays(adev);
2912                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2913                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2914                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2915                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2916                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
2917                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
2918                                 if (adev->powerplay.pp_funcs->display_configuration_change)
2919                                         adev->powerplay.pp_funcs->display_configuration_change(
2920                                                                         adev->powerplay.pp_handle,
2921                                                                         &adev->pm.pm_display_cfg);
2922                                 mutex_unlock(&adev->pm.mutex);
2923                         }
2924                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2925                 } else {
2926                         mutex_lock(&adev->pm.mutex);
2927                         amdgpu_dpm_get_active_displays(adev);
2928                         amdgpu_dpm_change_power_state_locked(adev);
2929                         mutex_unlock(&adev->pm.mutex);
2930                 }
2931         }
2932 }
2933
2934 /*
2935  * Debugfs info
2936  */
2937 #if defined(CONFIG_DEBUG_FS)
2938
2939 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2940 {
2941         uint32_t value;
2942         uint64_t value64;
2943         uint32_t query = 0;
2944         int size;
2945
2946         /* GPU Clocks */
2947         size = sizeof(value);
2948         seq_printf(m, "GFX Clocks and Power:\n");
2949         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2950                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2951         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2952                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2953         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2954                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2955         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2956                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2957         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2958                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2959         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2960                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2961         size = sizeof(uint32_t);
2962         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2963                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2964         size = sizeof(value);
2965         seq_printf(m, "\n");
2966
2967         /* GPU Temp */
2968         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2969                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2970
2971         /* GPU Load */
2972         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2973                 seq_printf(m, "GPU Load: %u %%\n", value);
2974         /* MEM Load */
2975         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
2976                 seq_printf(m, "MEM Load: %u %%\n", value);
2977
2978         seq_printf(m, "\n");
2979
2980         /* SMC feature mask */
2981         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2982                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2983
2984         /* UVD clocks */
2985         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2986                 if (!value) {
2987                         seq_printf(m, "UVD: Disabled\n");
2988                 } else {
2989                         seq_printf(m, "UVD: Enabled\n");
2990                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2991                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2992                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2993                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2994                 }
2995         }
2996         seq_printf(m, "\n");
2997
2998         /* VCE clocks */
2999         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3000                 if (!value) {
3001                         seq_printf(m, "VCE: Disabled\n");
3002                 } else {
3003                         seq_printf(m, "VCE: Enabled\n");
3004                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3005                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3006                 }
3007         }
3008
3009         return 0;
3010 }
3011
3012 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3013 {
3014         int i;
3015
3016         for (i = 0; clocks[i].flag; i++)
3017                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3018                            (flags & clocks[i].flag) ? "On" : "Off");
3019 }
3020
3021 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3022 {
3023         struct drm_info_node *node = (struct drm_info_node *) m->private;
3024         struct drm_device *dev = node->minor->dev;
3025         struct amdgpu_device *adev = dev->dev_private;
3026         struct drm_device *ddev = adev->ddev;
3027         u32 flags = 0;
3028
3029         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3030         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3031         amdgpu_parse_cg_state(m, flags);
3032         seq_printf(m, "\n");
3033
3034         if (!adev->pm.dpm_enabled) {
3035                 seq_printf(m, "dpm not enabled\n");
3036                 return 0;
3037         }
3038         if  ((adev->flags & AMD_IS_PX) &&
3039              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3040                 seq_printf(m, "PX asic powered off\n");
3041         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3042                 mutex_lock(&adev->pm.mutex);
3043                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3044                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3045                 else
3046                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3047                 mutex_unlock(&adev->pm.mutex);
3048         } else {
3049                 return amdgpu_debugfs_pm_info_pp(m, adev);
3050         }
3051
3052         return 0;
3053 }
3054
3055 static const struct drm_info_list amdgpu_pm_info_list[] = {
3056         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3057 };
3058 #endif
3059
3060 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3061 {
3062 #if defined(CONFIG_DEBUG_FS)
3063         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3064 #else
3065         return 0;
3066 #endif
3067 }