drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_display.h"
  33 #include "amdgpu_smu.h"
  34 #include "atom.h"
  35 #include <linux/power_supply.h>
  36 #include <linux/pci.h>
  37 #include <linux/hwmon.h>
  38 #include <linux/hwmon-sysfs.h>
  39 #include <linux/nospec.h>
  40 #include "hwmgr.h"
  41 #define WIDTH_4K 3840
  42
  43 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  44
  45 static const struct cg_flag_name clocks[] = {
  46         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  47         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  51         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  52         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  53         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  56         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  57         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  59         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  62         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  65         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  67         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  68         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  70         {0, NULL},
  71 };
  72
  73 static const struct hwmon_temp_label {
  74         enum PP_HWMON_TEMP channel;
  75         const char *label;
  76 } temp_label[] = {
  77         {PP_TEMP_EDGE, "edge"},
  78         {PP_TEMP_JUNCTION, "junction"},
  79         {PP_TEMP_MEM, "mem"},
  80 };
  81
  82 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  83 {
  84         if (adev->pm.dpm_enabled) {
  85                 mutex_lock(&adev->pm.mutex);
  86                 if (power_supply_is_system_supplied() > 0)
  87                         adev->pm.ac_power = true;
  88                 else
  89                         adev->pm.ac_power = false;
  90                 if (adev->powerplay.pp_funcs->enable_bapm)
  91                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
  92                 mutex_unlock(&adev->pm.mutex);
  93         }
  94 }
  95
  96 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
  97                            void *data, uint32_t *size)
  98 {
  99         int ret = 0;
 100
 101         if (!data || !size)
 102                 return -EINVAL;
 103
 104         if (is_support_sw_smu(adev))
 105                 ret = smu_read_sensor(&adev->smu, sensor, data, size);
 106         else {
 107                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
 108                         ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle,
 109                                                                     sensor, data, size);
 110                 else
 111                         ret = -EINVAL;
 112         }
 113
 114         return ret;
 115 }
 116
 117 /**
 118  * DOC: power_dpm_state
 119  *
 120  * The power_dpm_state file is a legacy interface and is only provided for
 121  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 122  * certain power related parameters.  The file power_dpm_state is used for this.
 123  * It accepts the following arguments:
 124  *
 125  * - battery
 126  *
 127  * - balanced
 128  *
 129  * - performance
 130  *
 131  * battery
 132  *
 133  * On older GPUs, the vbios provided a special power state for battery
 134  * operation.  Selecting battery switched to this state.  This is no
 135  * longer provided on newer GPUs so the option does nothing in that case.
 136  *
 137  * balanced
 138  *
 139  * On older GPUs, the vbios provided a special power state for balanced
 140  * operation.  Selecting balanced switched to this state.  This is no
 141  * longer provided on newer GPUs so the option does nothing in that case.
 142  *
 143  * performance
 144  *
 145  * On older GPUs, the vbios provided a special power state for performance
 146  * operation.  Selecting performance switched to this state.  This is no
 147  * longer provided on newer GPUs so the option does nothing in that case.
 148  *
 149  */
 150
 151 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 152                                     struct device_attribute *attr,
 153                                     char *buf)
 154 {
 155         struct drm_device *ddev = dev_get_drvdata(dev);
 156         struct amdgpu_device *adev = ddev->dev_private;
 157         enum amd_pm_state_type pm;
 158
 159         if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
 160                 pm = amdgpu_smu_get_current_power_state(adev);
 161         else if (adev->powerplay.pp_funcs->get_current_power_state)
 162                 pm = amdgpu_dpm_get_current_power_state(adev);
 163         else
 164                 pm = adev->pm.dpm.user_state;
 165
 166         return snprintf(buf, PAGE_SIZE, "%s\n",
 167                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 168                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 169 }
 170
 171 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 172                                     struct device_attribute *attr,
 173                                     const char *buf,
 174                                     size_t count)
 175 {
 176         struct drm_device *ddev = dev_get_drvdata(dev);
 177         struct amdgpu_device *adev = ddev->dev_private;
 178         enum amd_pm_state_type  state;
 179
 180         if (strncmp("battery", buf, strlen("battery")) == 0)
 181                 state = POWER_STATE_TYPE_BATTERY;
 182         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 183                 state = POWER_STATE_TYPE_BALANCED;
 184         else if (strncmp("performance", buf, strlen("performance")) == 0)
 185                 state = POWER_STATE_TYPE_PERFORMANCE;
 186         else {
 187                 count = -EINVAL;
 188                 goto fail;
 189         }
 190
 191         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 192                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 193         } else {
 194                 mutex_lock(&adev->pm.mutex);
 195                 adev->pm.dpm.user_state = state;
 196                 mutex_unlock(&adev->pm.mutex);
 197
 198                 /* Can't set dpm state when the card is off */
 199                 if (!(adev->flags & AMD_IS_PX) ||
 200                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 201                         amdgpu_pm_compute_clocks(adev);
 202         }
 203 fail:
 204         return count;
 205 }
 206
 207
 208 /**
 209  * DOC: power_dpm_force_performance_level
 210  *
 211  * The amdgpu driver provides a sysfs API for adjusting certain power
 212  * related parameters.  The file power_dpm_force_performance_level is
 213  * used for this.  It accepts the following arguments:
 214  *
 215  * - auto
 216  *
 217  * - low
 218  *
 219  * - high
 220  *
 221  * - manual
 222  *
 223  * - profile_standard
 224  *
 225  * - profile_min_sclk
 226  *
 227  * - profile_min_mclk
 228  *
 229  * - profile_peak
 230  *
 231  * auto
 232  *
 233  * When auto is selected, the driver will attempt to dynamically select
 234  * the optimal power profile for current conditions in the driver.
 235  *
 236  * low
 237  *
 238  * When low is selected, the clocks are forced to the lowest power state.
 239  *
 240  * high
 241  *
 242  * When high is selected, the clocks are forced to the highest power state.
 243  *
 244  * manual
 245  *
 246  * When manual is selected, the user can manually adjust which power states
 247  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 248  * and pp_dpm_pcie files and adjust the power state transition heuristics
 249  * via the pp_power_profile_mode sysfs file.
 250  *
 251  * profile_standard
 252  * profile_min_sclk
 253  * profile_min_mclk
 254  * profile_peak
 255  *
 256  * When the profiling modes are selected, clock and power gating are
 257  * disabled and the clocks are set for different profiling cases. This
 258  * mode is recommended for profiling specific work loads where you do
 259  * not want clock or power gating for clock fluctuation to interfere
 260  * with your results. profile_standard sets the clocks to a fixed clock
 261  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 262  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 263  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 264  *
 265  */
 266
 267 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 268                                                 struct device_attribute *attr,
 269                                                                 char *buf)
 270 {
 271         struct drm_device *ddev = dev_get_drvdata(dev);
 272         struct amdgpu_device *adev = ddev->dev_private;
 273         enum amd_dpm_forced_level level = 0xff;
 274
 275         if  ((adev->flags & AMD_IS_PX) &&
 276              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 277                 return snprintf(buf, PAGE_SIZE, "off\n");
 278
 279         if (is_support_sw_smu(adev))
 280                 level = smu_get_performance_level(&adev->smu);
 281         else if (adev->powerplay.pp_funcs->get_performance_level)
 282                 level = amdgpu_dpm_get_performance_level(adev);
 283         else
 284                 level = adev->pm.dpm.forced_level;
 285
 286         return snprintf(buf, PAGE_SIZE, "%s\n",
 287                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 288                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 289                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 290                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 291                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 292                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 293                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 294                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 295                         "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 299                                                        struct device_attribute *attr,
 300                                                        const char *buf,
 301                                                        size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = ddev->dev_private;
 305         enum amd_dpm_forced_level level;
 306         enum amd_dpm_forced_level current_level = 0xff;
 307         int ret = 0;
 308
 309         /* Can't force performance level when the card is off */
 310         if  ((adev->flags & AMD_IS_PX) &&
 311              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 312                 return -EINVAL;
 313
 314         if (is_support_sw_smu(adev))
 315                 current_level = smu_get_performance_level(&adev->smu);
 316         else if (adev->powerplay.pp_funcs->get_performance_level)
 317                 current_level = amdgpu_dpm_get_performance_level(adev);
 318
 319         if (strncmp("low", buf, strlen("low")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_LOW;
 321         } else if (strncmp("high", buf, strlen("high")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 323         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 325         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 327         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 329         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 331         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 333         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 335         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 337         }  else {
 338                 count = -EINVAL;
 339                 goto fail;
 340         }
 341
 342         if (amdgpu_sriov_vf(adev)) {
 343                 if (amdgim_is_hwperf(adev) &&
 344                     adev->virt.ops->force_dpm_level) {
 345                         mutex_lock(&adev->pm.mutex);
 346                         adev->virt.ops->force_dpm_level(adev, level);
 347                         mutex_unlock(&adev->pm.mutex);
 348                         return count;
 349                 } else {
 350                         return -EINVAL;
 351                 }
 352         }
 353
 354         if (current_level == level)
 355                 return count;
 356
 357         /* profile_exit setting is valid only when current mode is in profile mode */
 358         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 359             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 360             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 361             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 362             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 363                 pr_err("Currently not in any profile mode!\n");
 364                 return -EINVAL;
 365         }
 366
 367         if (is_support_sw_smu(adev)) {
 368                 mutex_lock(&adev->pm.mutex);
 369                 if (adev->pm.dpm.thermal_active) {
 370                         count = -EINVAL;
 371                         mutex_unlock(&adev->pm.mutex);
 372                         goto fail;
 373                 }
 374                 ret = smu_force_performance_level(&adev->smu, level);
 375                 if (ret)
 376                         count = -EINVAL;
 377                 else
 378                         adev->pm.dpm.forced_level = level;
 379                 mutex_unlock(&adev->pm.mutex);
 380         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 381                 mutex_lock(&adev->pm.mutex);
 382                 if (adev->pm.dpm.thermal_active) {
 383                         count = -EINVAL;
 384                         mutex_unlock(&adev->pm.mutex);
 385                         goto fail;
 386                 }
 387                 ret = amdgpu_dpm_force_performance_level(adev, level);
 388                 if (ret)
 389                         count = -EINVAL;
 390                 else
 391                         adev->pm.dpm.forced_level = level;
 392                 mutex_unlock(&adev->pm.mutex);
 393         }
 394
 395 fail:
 396         return count;
 397 }
 398
 399 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 400                 struct device_attribute *attr,
 401                 char *buf)
 402 {
 403         struct drm_device *ddev = dev_get_drvdata(dev);
 404         struct amdgpu_device *adev = ddev->dev_private;
 405         struct pp_states_info data;
 406         int i, buf_len, ret;
 407
 408         if (is_support_sw_smu(adev)) {
 409                 ret = smu_get_power_num_states(&adev->smu, &data);
 410                 if (ret)
 411                         return ret;
 412         } else if (adev->powerplay.pp_funcs->get_pp_num_states)
 413                 amdgpu_dpm_get_pp_num_states(adev, &data);
 414
 415         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 416         for (i = 0; i < data.nums; i++)
 417                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 418                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 419                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 420                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 421                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 422
 423         return buf_len;
 424 }
 425
 426 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 427                 struct device_attribute *attr,
 428                 char *buf)
 429 {
 430         struct drm_device *ddev = dev_get_drvdata(dev);
 431         struct amdgpu_device *adev = ddev->dev_private;
 432         struct pp_states_info data;
 433         struct smu_context *smu = &adev->smu;
 434         enum amd_pm_state_type pm = 0;
 435         int i = 0, ret = 0;
 436
 437         if (is_support_sw_smu(adev)) {
 438                 pm = smu_get_current_power_state(smu);
 439                 ret = smu_get_power_num_states(smu, &data);
 440                 if (ret)
 441                         return ret;
 442         } else if (adev->powerplay.pp_funcs->get_current_power_state
 443                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 444                 pm = amdgpu_dpm_get_current_power_state(adev);
 445                 amdgpu_dpm_get_pp_num_states(adev, &data);
 446         }
 447
 448         for (i = 0; i < data.nums; i++) {
 449                 if (pm == data.states[i])
 450                         break;
 451         }
 452
 453         if (i == data.nums)
 454                 i = -EINVAL;
 455
 456         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 457 }
 458
 459 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 460                 struct device_attribute *attr,
 461                 char *buf)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = ddev->dev_private;
 465
 466         if (adev->pp_force_state_enabled)
 467                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 468         else
 469                 return snprintf(buf, PAGE_SIZE, "\n");
 470 }
 471
 472 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 473                 struct device_attribute *attr,
 474                 const char *buf,
 475                 size_t count)
 476 {
 477         struct drm_device *ddev = dev_get_drvdata(dev);
 478         struct amdgpu_device *adev = ddev->dev_private;
 479         enum amd_pm_state_type state = 0;
 480         unsigned long idx;
 481         int ret;
 482
 483         if (strlen(buf) == 1)
 484                 adev->pp_force_state_enabled = false;
 485         else if (is_support_sw_smu(adev))
 486                 adev->pp_force_state_enabled = false;
 487         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 488                         adev->powerplay.pp_funcs->get_pp_num_states) {
 489                 struct pp_states_info data;
 490
 491                 ret = kstrtoul(buf, 0, &idx);
 492                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 493                         count = -EINVAL;
 494                         goto fail;
 495                 }
 496                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 497
 498                 amdgpu_dpm_get_pp_num_states(adev, &data);
 499                 state = data.states[idx];
 500                 /* only set user selected power states */
 501                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 502                     state != POWER_STATE_TYPE_DEFAULT) {
 503                         amdgpu_dpm_dispatch_task(adev,
 504                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 505                         adev->pp_force_state_enabled = true;
 506                 }
 507         }
 508 fail:
 509         return count;
 510 }
 511
 512 /**
 513  * DOC: pp_table
 514  *
 515  * The amdgpu driver provides a sysfs API for uploading new powerplay
 516  * tables.  The file pp_table is used for this.  Reading the file
 517  * will dump the current power play table.  Writing to the file
 518  * will attempt to upload a new powerplay table and re-initialize
 519  * powerplay using that new table.
 520  *
 521  */
 522
 523 static ssize_t amdgpu_get_pp_table(struct device *dev,
 524                 struct device_attribute *attr,
 525                 char *buf)
 526 {
 527         struct drm_device *ddev = dev_get_drvdata(dev);
 528         struct amdgpu_device *adev = ddev->dev_private;
 529         char *table = NULL;
 530         int size;
 531
 532         if (is_support_sw_smu(adev)) {
 533                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 534                 if (size < 0)
 535                         return size;
 536         }
 537         else if (adev->powerplay.pp_funcs->get_pp_table)
 538                 size = amdgpu_dpm_get_pp_table(adev, &table);
 539         else
 540                 return 0;
 541
 542         if (size >= PAGE_SIZE)
 543                 size = PAGE_SIZE - 1;
 544
 545         memcpy(buf, table, size);
 546
 547         return size;
 548 }
 549
 550 static ssize_t amdgpu_set_pp_table(struct device *dev,
 551                 struct device_attribute *attr,
 552                 const char *buf,
 553                 size_t count)
 554 {
 555         struct drm_device *ddev = dev_get_drvdata(dev);
 556         struct amdgpu_device *adev = ddev->dev_private;
 557         int ret = 0;
 558
 559         if (is_support_sw_smu(adev)) {
 560                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 561                 if (ret)
 562                         return ret;
 563         } else if (adev->powerplay.pp_funcs->set_pp_table)
 564                 amdgpu_dpm_set_pp_table(adev, buf, count);
 565
 566         return count;
 567 }
 568
 569 /**
 570  * DOC: pp_od_clk_voltage
 571  *
 572  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 573  * in each power level within a power state.  The pp_od_clk_voltage is used for
 574  * this.
 575  *
 576  * < For Vega10 and previous ASICs >
 577  *
 578  * Reading the file will display:
 579  *
 580  * - a list of engine clock levels and voltages labeled OD_SCLK
 581  *
 582  * - a list of memory clock levels and voltages labeled OD_MCLK
 583  *
 584  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 585  *
 586  * To manually adjust these settings, first select manual using
 587  * power_dpm_force_performance_level. Enter a new value for each
 588  * level by writing a string that contains "s/m level clock voltage" to
 589  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 590  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 591  * 810 mV.  When you have edited all of the states as needed, write
 592  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 593  * default power levels, write "r" (reset) to the file to reset them.
 594  *
 595  *
 596  * < For Vega20 >
 597  *
 598  * Reading the file will display:
 599  *
 600  * - minimum and maximum engine clock labeled OD_SCLK
 601  *
 602  * - maximum memory clock labeled OD_MCLK
 603  *
 604  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 605  *   They can be used to calibrate the sclk voltage curve.
 606  *
 607  * - a list of valid ranges for sclk, mclk, and voltage curve points
 608  *   labeled OD_RANGE
 609  *
 610  * To manually adjust these settings:
 611  *
 612  * - First select manual using power_dpm_force_performance_level
 613  *
 614  * - For clock frequency setting, enter a new value by writing a
 615  *   string that contains "s/m index clock" to the file. The index
 616  *   should be 0 if to set minimum clock. And 1 if to set maximum
 617  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 618  *   "m 1 800" will update maximum mclk to be 800Mhz.
 619  *
 620  *   For sclk voltage curve, enter the new values by writing a
 621  *   string that contains "vc point clock voltage" to the file. The
 622  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 623  *   update point1 with clock set as 300Mhz and voltage as
 624  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 625  *   as 1000Mhz and voltage 1000mV.
 626  *
 627  * - When you have edited all of the states as needed, write "c" (commit)
 628  *   to the file to commit your changes
 629  *
 630  * - If you want to reset to the default power levels, write "r" (reset)
 631  *   to the file to reset them
 632  *
 633  */
 634
 635 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 636                 struct device_attribute *attr,
 637                 const char *buf,
 638                 size_t count)
 639 {
 640         struct drm_device *ddev = dev_get_drvdata(dev);
 641         struct amdgpu_device *adev = ddev->dev_private;
 642         int ret;
 643         uint32_t parameter_size = 0;
 644         long parameter[64];
 645         char buf_cpy[128];
 646         char *tmp_str;
 647         char *sub_str;
 648         const char delimiter[3] = {' ', '\n', '\0'};
 649         uint32_t type;
 650
 651         if (count > 127)
 652                 return -EINVAL;
 653
 654         if (*buf == 's')
 655                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 656         else if (*buf == 'm')
 657                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 658         else if(*buf == 'r')
 659                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 660         else if (*buf == 'c')
 661                 type = PP_OD_COMMIT_DPM_TABLE;
 662         else if (!strncmp(buf, "vc", 2))
 663                 type = PP_OD_EDIT_VDDC_CURVE;
 664         else
 665                 return -EINVAL;
 666
 667         memcpy(buf_cpy, buf, count+1);
 668
 669         tmp_str = buf_cpy;
 670
 671         if (type == PP_OD_EDIT_VDDC_CURVE)
 672                 tmp_str++;
 673         while (isspace(*++tmp_str));
 674
 675         while (tmp_str[0]) {
 676                 sub_str = strsep(&tmp_str, delimiter);
 677                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 678                 if (ret)
 679                         return -EINVAL;
 680                 parameter_size++;
 681
 682                 while (isspace(*tmp_str))
 683                         tmp_str++;
 684         }
 685
 686         if (is_support_sw_smu(adev)) {
 687                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 688                                             parameter, parameter_size);
 689
 690                 if (ret)
 691                         return -EINVAL;
 692         } else {
 693                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 694                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 695                                                 parameter, parameter_size);
 696
 697                 if (ret)
 698                         return -EINVAL;
 699
 700                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 701                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 702                                 amdgpu_dpm_dispatch_task(adev,
 703                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 704                                                 NULL);
 705                                 return count;
 706                         } else {
 707                                 return -EINVAL;
 708                         }
 709                 }
 710         }
 711
 712         return count;
 713 }
 714
 715 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 716                 struct device_attribute *attr,
 717                 char *buf)
 718 {
 719         struct drm_device *ddev = dev_get_drvdata(dev);
 720         struct amdgpu_device *adev = ddev->dev_private;
 721         uint32_t size = 0;
 722
 723         if (is_support_sw_smu(adev)) {
 724                 size = smu_print_clk_levels(&adev->smu, OD_SCLK, buf);
 725                 size += smu_print_clk_levels(&adev->smu, OD_MCLK, buf+size);
 726                 size += smu_print_clk_levels(&adev->smu, OD_VDDC_CURVE, buf+size);
 727                 size += smu_print_clk_levels(&adev->smu, OD_RANGE, buf+size);
 728                 return size;
 729         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 730                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 731                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 732                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 733                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 734                 return size;
 735         } else {
 736                 return snprintf(buf, PAGE_SIZE, "\n");
 737         }
 738
 739 }
 740
 741 /**
 742  * DOC: ppfeatures
 743  *
 744  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 745  * features to be enabled. The file ppfeatures is used for this. And
 746  * this is only available for Vega10 and later dGPUs.
 747  *
 748  * Reading back the file will show you the followings:
 749  * - Current ppfeature masks
 750  * - List of the all supported powerplay features with their naming,
 751  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 752  *
 753  * To manually enable or disable a specific feature, just set or clear
 754  * the corresponding bit from original ppfeature masks and input the
 755  * new ppfeature masks.
 756  */
 757 static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 758                 struct device_attribute *attr,
 759                 const char *buf,
 760                 size_t count)
 761 {
 762         struct drm_device *ddev = dev_get_drvdata(dev);
 763         struct amdgpu_device *adev = ddev->dev_private;
 764         uint64_t featuremask;
 765         int ret;
 766
 767         ret = kstrtou64(buf, 0, &featuremask);
 768         if (ret)
 769                 return -EINVAL;
 770
 771         pr_debug("featuremask = 0x%llx\n", featuremask);
 772
 773         if (is_support_sw_smu(adev)) {
 774                 ret = smu_set_ppfeature_status(&adev->smu, featuremask);
 775                 if (ret)
 776                         return -EINVAL;
 777         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 778                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 779                 if (ret)
 780                         return -EINVAL;
 781         }
 782
 783         return count;
 784 }
 785
 786 static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 787                 struct device_attribute *attr,
 788                 char *buf)
 789 {
 790         struct drm_device *ddev = dev_get_drvdata(dev);
 791         struct amdgpu_device *adev = ddev->dev_private;
 792
 793         if (is_support_sw_smu(adev)) {
 794                 return smu_get_ppfeature_status(&adev->smu, buf);
 795         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 796                 return amdgpu_dpm_get_ppfeature_status(adev, buf);
 797
 798         return snprintf(buf, PAGE_SIZE, "\n");
 799 }
 800
 801 /**
 802  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
 803  * pp_dpm_pcie
 804  *
 805  * The amdgpu driver provides a sysfs API for adjusting what power levels
 806  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 807  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 808  * this.
 809  *
 810  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 811  * Vega10 and later ASICs.
 812  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 813  *
 814  * Reading back the files will show you the available power levels within
 815  * the power state and the clock information for those levels.
 816  *
 817  * To manually adjust these states, first select manual using
 818  * power_dpm_force_performance_level.
 819  * Secondly,Enter a new value for each level by inputing a string that
 820  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 821  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
 822  *
 823  * NOTE: change to the dcefclk max dpm level is not supported now
 824  */
 825
 826 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 827                 struct device_attribute *attr,
 828                 char *buf)
 829 {
 830         struct drm_device *ddev = dev_get_drvdata(dev);
 831         struct amdgpu_device *adev = ddev->dev_private;
 832
 833         if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 834             adev->virt.ops->get_pp_clk)
 835                 return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
 836
 837         if (is_support_sw_smu(adev))
 838                 return smu_print_clk_levels(&adev->smu, PP_SCLK, buf);
 839         else if (adev->powerplay.pp_funcs->print_clock_levels)
 840                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 841         else
 842                 return snprintf(buf, PAGE_SIZE, "\n");
 843 }
 844
 845 /*
 846  * Worst case: 32 bits individually specified, in octal at 12 characters
 847  * per line (+1 for \n).
 848  */
 849 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
 850
 851 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 852 {
 853         int ret;
 854         long level;
 855         char *sub_str = NULL;
 856         char *tmp;
 857         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
 858         const char delimiter[3] = {' ', '\n', '\0'};
 859         size_t bytes;
 860
 861         *mask = 0;
 862
 863         bytes = min(count, sizeof(buf_cpy) - 1);
 864         memcpy(buf_cpy, buf, bytes);
 865         buf_cpy[bytes] = '\0';
 866         tmp = buf_cpy;
 867         while (tmp[0]) {
 868                 sub_str = strsep(&tmp, delimiter);
 869                 if (strlen(sub_str)) {
 870                         ret = kstrtol(sub_str, 0, &level);
 871                         if (ret)
 872                                 return -EINVAL;
 873                         *mask |= 1 << level;
 874                 } else
 875                         break;
 876         }
 877
 878         return 0;
 879 }
 880
 881 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 882                 struct device_attribute *attr,
 883                 const char *buf,
 884                 size_t count)
 885 {
 886         struct drm_device *ddev = dev_get_drvdata(dev);
 887         struct amdgpu_device *adev = ddev->dev_private;
 888         int ret;
 889         uint32_t mask = 0;
 890
 891         ret = amdgpu_read_mask(buf, count, &mask);
 892         if (ret)
 893                 return ret;
 894
 895         if (is_support_sw_smu(adev))
 896                 ret = smu_force_clk_levels(&adev->smu, PP_SCLK, mask);
 897         else if (adev->powerplay.pp_funcs->force_clock_level)
 898                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 899
 900         if (ret)
 901                 return -EINVAL;
 902
 903         return count;
 904 }
 905
 906 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 907                 struct device_attribute *attr,
 908                 char *buf)
 909 {
 910         struct drm_device *ddev = dev_get_drvdata(dev);
 911         struct amdgpu_device *adev = ddev->dev_private;
 912
 913         if (is_support_sw_smu(adev))
 914                 return smu_print_clk_levels(&adev->smu, PP_MCLK, buf);
 915         else if (adev->powerplay.pp_funcs->print_clock_levels)
 916                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 917         else
 918                 return snprintf(buf, PAGE_SIZE, "\n");
 919 }
 920
 921 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 922                 struct device_attribute *attr,
 923                 const char *buf,
 924                 size_t count)
 925 {
 926         struct drm_device *ddev = dev_get_drvdata(dev);
 927         struct amdgpu_device *adev = ddev->dev_private;
 928         int ret;
 929         uint32_t mask = 0;
 930
 931         ret = amdgpu_read_mask(buf, count, &mask);
 932         if (ret)
 933                 return ret;
 934
 935         if (is_support_sw_smu(adev))
 936                 ret = smu_force_clk_levels(&adev->smu, PP_MCLK, mask);
 937         else if (adev->powerplay.pp_funcs->force_clock_level)
 938                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 939
 940         if (ret)
 941                 return -EINVAL;
 942
 943         return count;
 944 }
 945
 946 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
 947                 struct device_attribute *attr,
 948                 char *buf)
 949 {
 950         struct drm_device *ddev = dev_get_drvdata(dev);
 951         struct amdgpu_device *adev = ddev->dev_private;
 952
 953         if (is_support_sw_smu(adev))
 954                 return smu_print_clk_levels(&adev->smu, PP_SOCCLK, buf);
 955         else if (adev->powerplay.pp_funcs->print_clock_levels)
 956                 return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
 957         else
 958                 return snprintf(buf, PAGE_SIZE, "\n");
 959 }
 960
 961 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
 962                 struct device_attribute *attr,
 963                 const char *buf,
 964                 size_t count)
 965 {
 966         struct drm_device *ddev = dev_get_drvdata(dev);
 967         struct amdgpu_device *adev = ddev->dev_private;
 968         int ret;
 969         uint32_t mask = 0;
 970
 971         ret = amdgpu_read_mask(buf, count, &mask);
 972         if (ret)
 973                 return ret;
 974
 975         if (is_support_sw_smu(adev))
 976                 ret = smu_force_clk_levels(&adev->smu, PP_SOCCLK, mask);
 977         else if (adev->powerplay.pp_funcs->force_clock_level)
 978                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
 979
 980         if (ret)
 981                 return -EINVAL;
 982
 983         return count;
 984 }
 985
 986 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
 987                 struct device_attribute *attr,
 988                 char *buf)
 989 {
 990         struct drm_device *ddev = dev_get_drvdata(dev);
 991         struct amdgpu_device *adev = ddev->dev_private;
 992
 993         if (is_support_sw_smu(adev))
 994                 return smu_print_clk_levels(&adev->smu, PP_FCLK, buf);
 995         else if (adev->powerplay.pp_funcs->print_clock_levels)
 996                 return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
 997         else
 998                 return snprintf(buf, PAGE_SIZE, "\n");
 999 }
1000
1001 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1002                 struct device_attribute *attr,
1003                 const char *buf,
1004                 size_t count)
1005 {
1006         struct drm_device *ddev = dev_get_drvdata(dev);
1007         struct amdgpu_device *adev = ddev->dev_private;
1008         int ret;
1009         uint32_t mask = 0;
1010
1011         ret = amdgpu_read_mask(buf, count, &mask);
1012         if (ret)
1013                 return ret;
1014
1015         if (is_support_sw_smu(adev))
1016                 ret = smu_force_clk_levels(&adev->smu, PP_FCLK, mask);
1017         else if (adev->powerplay.pp_funcs->force_clock_level)
1018                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1019
1020         if (ret)
1021                 return -EINVAL;
1022
1023         return count;
1024 }
1025
1026 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1027                 struct device_attribute *attr,
1028                 char *buf)
1029 {
1030         struct drm_device *ddev = dev_get_drvdata(dev);
1031         struct amdgpu_device *adev = ddev->dev_private;
1032
1033         if (is_support_sw_smu(adev))
1034                 return smu_print_clk_levels(&adev->smu, PP_DCEFCLK, buf);
1035         else if (adev->powerplay.pp_funcs->print_clock_levels)
1036                 return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1037         else
1038                 return snprintf(buf, PAGE_SIZE, "\n");
1039 }
1040
1041 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1042                 struct device_attribute *attr,
1043                 const char *buf,
1044                 size_t count)
1045 {
1046         struct drm_device *ddev = dev_get_drvdata(dev);
1047         struct amdgpu_device *adev = ddev->dev_private;
1048         int ret;
1049         uint32_t mask = 0;
1050
1051         ret = amdgpu_read_mask(buf, count, &mask);
1052         if (ret)
1053                 return ret;
1054
1055         if (is_support_sw_smu(adev))
1056                 ret = smu_force_clk_levels(&adev->smu, PP_DCEFCLK, mask);
1057         else if (adev->powerplay.pp_funcs->force_clock_level)
1058                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1059
1060         if (ret)
1061                 return -EINVAL;
1062
1063         return count;
1064 }
1065
1066 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1067                 struct device_attribute *attr,
1068                 char *buf)
1069 {
1070         struct drm_device *ddev = dev_get_drvdata(dev);
1071         struct amdgpu_device *adev = ddev->dev_private;
1072
1073         if (is_support_sw_smu(adev))
1074                 return smu_print_clk_levels(&adev->smu, PP_PCIE, buf);
1075         else if (adev->powerplay.pp_funcs->print_clock_levels)
1076                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1077         else
1078                 return snprintf(buf, PAGE_SIZE, "\n");
1079 }
1080
1081 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1082                 struct device_attribute *attr,
1083                 const char *buf,
1084                 size_t count)
1085 {
1086         struct drm_device *ddev = dev_get_drvdata(dev);
1087         struct amdgpu_device *adev = ddev->dev_private;
1088         int ret;
1089         uint32_t mask = 0;
1090
1091         ret = amdgpu_read_mask(buf, count, &mask);
1092         if (ret)
1093                 return ret;
1094
1095         if (is_support_sw_smu(adev))
1096                 ret = smu_force_clk_levels(&adev->smu, PP_PCIE, mask);
1097         else if (adev->powerplay.pp_funcs->force_clock_level)
1098                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1099
1100         if (ret)
1101                 return -EINVAL;
1102
1103         return count;
1104 }
1105
1106 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1107                 struct device_attribute *attr,
1108                 char *buf)
1109 {
1110         struct drm_device *ddev = dev_get_drvdata(dev);
1111         struct amdgpu_device *adev = ddev->dev_private;
1112         uint32_t value = 0;
1113
1114         if (is_support_sw_smu(adev))
1115                 value = smu_get_od_percentage(&(adev->smu), OD_SCLK);
1116         else if (adev->powerplay.pp_funcs->get_sclk_od)
1117                 value = amdgpu_dpm_get_sclk_od(adev);
1118
1119         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1120 }
1121
1122 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1123                 struct device_attribute *attr,
1124                 const char *buf,
1125                 size_t count)
1126 {
1127         struct drm_device *ddev = dev_get_drvdata(dev);
1128         struct amdgpu_device *adev = ddev->dev_private;
1129         int ret;
1130         long int value;
1131
1132         ret = kstrtol(buf, 0, &value);
1133
1134         if (ret) {
1135                 count = -EINVAL;
1136                 goto fail;
1137         }
1138
1139         if (is_support_sw_smu(adev)) {
1140                 value = smu_set_od_percentage(&(adev->smu), OD_SCLK, (uint32_t)value);
1141         } else {
1142                 if (adev->powerplay.pp_funcs->set_sclk_od)
1143                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1144
1145                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1146                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1147                 } else {
1148                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1149                         amdgpu_pm_compute_clocks(adev);
1150                 }
1151         }
1152
1153 fail:
1154         return count;
1155 }
1156
1157 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1158                 struct device_attribute *attr,
1159                 char *buf)
1160 {
1161         struct drm_device *ddev = dev_get_drvdata(dev);
1162         struct amdgpu_device *adev = ddev->dev_private;
1163         uint32_t value = 0;
1164
1165         if (is_support_sw_smu(adev))
1166                 value = smu_get_od_percentage(&(adev->smu), OD_MCLK);
1167         else if (adev->powerplay.pp_funcs->get_mclk_od)
1168                 value = amdgpu_dpm_get_mclk_od(adev);
1169
1170         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1171 }
1172
1173 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1174                 struct device_attribute *attr,
1175                 const char *buf,
1176                 size_t count)
1177 {
1178         struct drm_device *ddev = dev_get_drvdata(dev);
1179         struct amdgpu_device *adev = ddev->dev_private;
1180         int ret;
1181         long int value;
1182
1183         ret = kstrtol(buf, 0, &value);
1184
1185         if (ret) {
1186                 count = -EINVAL;
1187                 goto fail;
1188         }
1189
1190         if (is_support_sw_smu(adev)) {
1191                 value = smu_set_od_percentage(&(adev->smu), OD_MCLK, (uint32_t)value);
1192         } else {
1193                 if (adev->powerplay.pp_funcs->set_mclk_od)
1194                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1195
1196                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1197                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1198                 } else {
1199                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1200                         amdgpu_pm_compute_clocks(adev);
1201                 }
1202         }
1203
1204 fail:
1205         return count;
1206 }
1207
1208 /**
1209  * DOC: pp_power_profile_mode
1210  *
1211  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1212  * related to switching between power levels in a power state.  The file
1213  * pp_power_profile_mode is used for this.
1214  *
1215  * Reading this file outputs a list of all of the predefined power profiles
1216  * and the relevant heuristics settings for that profile.
1217  *
1218  * To select a profile or create a custom profile, first select manual using
1219  * power_dpm_force_performance_level.  Writing the number of a predefined
1220  * profile to pp_power_profile_mode will enable those heuristics.  To
1221  * create a custom set of heuristics, write a string of numbers to the file
1222  * starting with the number of the custom profile along with a setting
1223  * for each heuristic parameter.  Due to differences across asic families
1224  * the heuristic parameters vary from family to family.
1225  *
1226  */
1227
1228 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1229                 struct device_attribute *attr,
1230                 char *buf)
1231 {
1232         struct drm_device *ddev = dev_get_drvdata(dev);
1233         struct amdgpu_device *adev = ddev->dev_private;
1234
1235         if (is_support_sw_smu(adev))
1236                 return smu_get_power_profile_mode(&adev->smu, buf);
1237         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1238                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
1239
1240         return snprintf(buf, PAGE_SIZE, "\n");
1241 }
1242
1243
1244 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1245                 struct device_attribute *attr,
1246                 const char *buf,
1247                 size_t count)
1248 {
1249         int ret = 0xff;
1250         struct drm_device *ddev = dev_get_drvdata(dev);
1251         struct amdgpu_device *adev = ddev->dev_private;
1252         uint32_t parameter_size = 0;
1253         long parameter[64];
1254         char *sub_str, buf_cpy[128];
1255         char *tmp_str;
1256         uint32_t i = 0;
1257         char tmp[2];
1258         long int profile_mode = 0;
1259         const char delimiter[3] = {' ', '\n', '\0'};
1260
1261         tmp[0] = *(buf);
1262         tmp[1] = '\0';
1263         ret = kstrtol(tmp, 0, &profile_mode);
1264         if (ret)
1265                 goto fail;
1266
1267         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1268                 if (count < 2 || count > 127)
1269                         return -EINVAL;
1270                 while (isspace(*++buf))
1271                         i++;
1272                 memcpy(buf_cpy, buf, count-i);
1273                 tmp_str = buf_cpy;
1274                 while (tmp_str[0]) {
1275                         sub_str = strsep(&tmp_str, delimiter);
1276                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1277                         if (ret) {
1278                                 count = -EINVAL;
1279                                 goto fail;
1280                         }
1281                         parameter_size++;
1282                         while (isspace(*tmp_str))
1283                                 tmp_str++;
1284                 }
1285         }
1286         parameter[parameter_size] = profile_mode;
1287         if (is_support_sw_smu(adev))
1288                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size);
1289         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1290                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1291         if (!ret)
1292                 return count;
1293 fail:
1294         return -EINVAL;
1295 }
1296
1297 /**
1298  * DOC: busy_percent
1299  *
1300  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1301  * is as a percentage.  The file gpu_busy_percent is used for this.
1302  * The SMU firmware computes a percentage of load based on the
1303  * aggregate activity level in the IP cores.
1304  */
1305 static ssize_t amdgpu_get_busy_percent(struct device *dev,
1306                 struct device_attribute *attr,
1307                 char *buf)
1308 {
1309         struct drm_device *ddev = dev_get_drvdata(dev);
1310         struct amdgpu_device *adev = ddev->dev_private;
1311         int r, value, size = sizeof(value);
1312
1313         /* read the IP busy sensor */
1314         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1315                                    (void *)&value, &size);
1316
1317         if (r)
1318                 return r;
1319
1320         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1321 }
1322
1323 /**
1324  * DOC: mem_busy_percent
1325  *
1326  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1327  * is as a percentage.  The file mem_busy_percent is used for this.
1328  * The SMU firmware computes a percentage of load based on the
1329  * aggregate activity level in the IP cores.
1330  */
1331 static ssize_t amdgpu_get_memory_busy_percent(struct device *dev,
1332                 struct device_attribute *attr,
1333                 char *buf)
1334 {
1335         struct drm_device *ddev = dev_get_drvdata(dev);
1336         struct amdgpu_device *adev = ddev->dev_private;
1337         int r, value, size = sizeof(value);
1338
1339         /* read the IP busy sensor */
1340         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1341                                    (void *)&value, &size);
1342
1343         if (r)
1344                 return r;
1345
1346         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1347 }
1348
1349 /**
1350  * DOC: pcie_bw
1351  *
1352  * The amdgpu driver provides a sysfs API for estimating how much data
1353  * has been received and sent by the GPU in the last second through PCIe.
1354  * The file pcie_bw is used for this.
1355  * The Perf counters count the number of received and sent messages and return
1356  * those values, as well as the maximum payload size of a PCIe packet (mps).
1357  * Note that it is not possible to easily and quickly obtain the size of each
1358  * packet transmitted, so we output the max payload size (mps) to allow for
1359  * quick estimation of the PCIe bandwidth usage
1360  */
1361 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1362                 struct device_attribute *attr,
1363                 char *buf)
1364 {
1365         struct drm_device *ddev = dev_get_drvdata(dev);
1366         struct amdgpu_device *adev = ddev->dev_private;
1367         uint64_t count0, count1;
1368
1369         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1370         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1371                         count0, count1, pcie_get_mps(adev->pdev));
1372 }
1373
1374 /**
1375  * DOC: unique_id
1376  *
1377  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1378  * The file unique_id is used for this.
1379  * This will provide a Unique ID that will persist from machine to machine
1380  *
1381  * NOTE: This will only work for GFX9 and newer. This file will be absent
1382  * on unsupported ASICs (GFX8 and older)
1383  */
1384 static ssize_t amdgpu_get_unique_id(struct device *dev,
1385                 struct device_attribute *attr,
1386                 char *buf)
1387 {
1388         struct drm_device *ddev = dev_get_drvdata(dev);
1389         struct amdgpu_device *adev = ddev->dev_private;
1390
1391         if (adev->unique_id)
1392                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1393
1394         return 0;
1395 }
1396
1397 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
1398 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
1399                    amdgpu_get_dpm_forced_performance_level,
1400                    amdgpu_set_dpm_forced_performance_level);
1401 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
1402 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
1403 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1404                 amdgpu_get_pp_force_state,
1405                 amdgpu_set_pp_force_state);
1406 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1407                 amdgpu_get_pp_table,
1408                 amdgpu_set_pp_table);
1409 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1410                 amdgpu_get_pp_dpm_sclk,
1411                 amdgpu_set_pp_dpm_sclk);
1412 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1413                 amdgpu_get_pp_dpm_mclk,
1414                 amdgpu_set_pp_dpm_mclk);
1415 static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
1416                 amdgpu_get_pp_dpm_socclk,
1417                 amdgpu_set_pp_dpm_socclk);
1418 static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
1419                 amdgpu_get_pp_dpm_fclk,
1420                 amdgpu_set_pp_dpm_fclk);
1421 static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
1422                 amdgpu_get_pp_dpm_dcefclk,
1423                 amdgpu_set_pp_dpm_dcefclk);
1424 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1425                 amdgpu_get_pp_dpm_pcie,
1426                 amdgpu_set_pp_dpm_pcie);
1427 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1428                 amdgpu_get_pp_sclk_od,
1429                 amdgpu_set_pp_sclk_od);
1430 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1431                 amdgpu_get_pp_mclk_od,
1432                 amdgpu_set_pp_mclk_od);
1433 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1434                 amdgpu_get_pp_power_profile_mode,
1435                 amdgpu_set_pp_power_profile_mode);
1436 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1437                 amdgpu_get_pp_od_clk_voltage,
1438                 amdgpu_set_pp_od_clk_voltage);
1439 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1440                 amdgpu_get_busy_percent, NULL);
1441 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
1442                 amdgpu_get_memory_busy_percent, NULL);
1443 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
1444 static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
1445                 amdgpu_get_ppfeature_status,
1446                 amdgpu_set_ppfeature_status);
1447 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
1448
1449 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1450                                       struct device_attribute *attr,
1451                                       char *buf)
1452 {
1453         struct amdgpu_device *adev = dev_get_drvdata(dev);
1454         struct drm_device *ddev = adev->ddev;
1455         int channel = to_sensor_dev_attr(attr)->index;
1456         int r, temp, size = sizeof(temp);
1457
1458         /* Can't get temperature when the card is off */
1459         if  ((adev->flags & AMD_IS_PX) &&
1460              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1461                 return -EINVAL;
1462
1463         if (channel >= PP_TEMP_MAX)
1464                 return -EINVAL;
1465
1466         switch (channel) {
1467         case PP_TEMP_JUNCTION:
1468                 /* get current junction temperature */
1469                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1470                                            (void *)&temp, &size);
1471                 if (r)
1472                         return r;
1473                 break;
1474         case PP_TEMP_EDGE:
1475                 /* get current edge temperature */
1476                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
1477                                            (void *)&temp, &size);
1478                 if (r)
1479                         return r;
1480                 break;
1481         case PP_TEMP_MEM:
1482                 /* get current memory temperature */
1483                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
1484                                            (void *)&temp, &size);
1485                 if (r)
1486                         return r;
1487                 break;
1488         }
1489
1490         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1491 }
1492
1493 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1494                                              struct device_attribute *attr,
1495                                              char *buf)
1496 {
1497         struct amdgpu_device *adev = dev_get_drvdata(dev);
1498         int hyst = to_sensor_dev_attr(attr)->index;
1499         int temp;
1500
1501         if (hyst)
1502                 temp = adev->pm.dpm.thermal.min_temp;
1503         else
1504                 temp = adev->pm.dpm.thermal.max_temp;
1505
1506         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1507 }
1508
1509 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
1510                                              struct device_attribute *attr,
1511                                              char *buf)
1512 {
1513         struct amdgpu_device *adev = dev_get_drvdata(dev);
1514         int hyst = to_sensor_dev_attr(attr)->index;
1515         int temp;
1516
1517         if (hyst)
1518                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
1519         else
1520                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
1521
1522         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1523 }
1524
1525 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
1526                                              struct device_attribute *attr,
1527                                              char *buf)
1528 {
1529         struct amdgpu_device *adev = dev_get_drvdata(dev);
1530         int hyst = to_sensor_dev_attr(attr)->index;
1531         int temp;
1532
1533         if (hyst)
1534                 temp = adev->pm.dpm.thermal.min_mem_temp;
1535         else
1536                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
1537
1538         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1539 }
1540
1541 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
1542                                              struct device_attribute *attr,
1543                                              char *buf)
1544 {
1545         int channel = to_sensor_dev_attr(attr)->index;
1546
1547         if (channel >= PP_TEMP_MAX)
1548                 return -EINVAL;
1549
1550         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
1551 }
1552
1553 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
1554                                              struct device_attribute *attr,
1555                                              char *buf)
1556 {
1557         struct amdgpu_device *adev = dev_get_drvdata(dev);
1558         int channel = to_sensor_dev_attr(attr)->index;
1559         int temp = 0;
1560
1561         if (channel >= PP_TEMP_MAX)
1562                 return -EINVAL;
1563
1564         switch (channel) {
1565         case PP_TEMP_JUNCTION:
1566                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
1567                 break;
1568         case PP_TEMP_EDGE:
1569                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
1570                 break;
1571         case PP_TEMP_MEM:
1572                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
1573                 break;
1574         }
1575
1576         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1577 }
1578
1579 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1580                                             struct device_attribute *attr,
1581                                             char *buf)
1582 {
1583         struct amdgpu_device *adev = dev_get_drvdata(dev);
1584         u32 pwm_mode = 0;
1585         if (is_support_sw_smu(adev)) {
1586                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1587         } else {
1588                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1589                         return -EINVAL;
1590
1591                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1592         }
1593
1594         return sprintf(buf, "%i\n", pwm_mode);
1595 }
1596
1597 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1598                                             struct device_attribute *attr,
1599                                             const char *buf,
1600                                             size_t count)
1601 {
1602         struct amdgpu_device *adev = dev_get_drvdata(dev);
1603         int err;
1604         int value;
1605
1606         /* Can't adjust fan when the card is off */
1607         if  ((adev->flags & AMD_IS_PX) &&
1608              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1609                 return -EINVAL;
1610
1611         if (is_support_sw_smu(adev)) {
1612                 err = kstrtoint(buf, 10, &value);
1613                 if (err)
1614                         return err;
1615
1616                 smu_set_fan_control_mode(&adev->smu, value);
1617         } else {
1618                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1619                         return -EINVAL;
1620
1621                 err = kstrtoint(buf, 10, &value);
1622                 if (err)
1623                         return err;
1624
1625                 amdgpu_dpm_set_fan_control_mode(adev, value);
1626         }
1627
1628         return count;
1629 }
1630
1631 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1632                                          struct device_attribute *attr,
1633                                          char *buf)
1634 {
1635         return sprintf(buf, "%i\n", 0);
1636 }
1637
1638 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1639                                          struct device_attribute *attr,
1640                                          char *buf)
1641 {
1642         return sprintf(buf, "%i\n", 255);
1643 }
1644
1645 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1646                                      struct device_attribute *attr,
1647                                      const char *buf, size_t count)
1648 {
1649         struct amdgpu_device *adev = dev_get_drvdata(dev);
1650         int err;
1651         u32 value;
1652         u32 pwm_mode;
1653
1654         /* Can't adjust fan when the card is off */
1655         if  ((adev->flags & AMD_IS_PX) &&
1656              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1657                 return -EINVAL;
1658         if (is_support_sw_smu(adev))
1659                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1660         else
1661                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1662         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1663                 pr_info("manual fan speed control should be enabled first\n");
1664                 return -EINVAL;
1665         }
1666
1667         err = kstrtou32(buf, 10, &value);
1668         if (err)
1669                 return err;
1670
1671         value = (value * 100) / 255;
1672
1673         if (is_support_sw_smu(adev)) {
1674                 err = smu_set_fan_speed_percent(&adev->smu, value);
1675                 if (err)
1676                         return err;
1677         } else if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1678                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1679                 if (err)
1680                         return err;
1681         }
1682
1683         return count;
1684 }
1685
1686 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1687                                      struct device_attribute *attr,
1688                                      char *buf)
1689 {
1690         struct amdgpu_device *adev = dev_get_drvdata(dev);
1691         int err;
1692         u32 speed = 0;
1693
1694         /* Can't adjust fan when the card is off */
1695         if  ((adev->flags & AMD_IS_PX) &&
1696              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1697                 return -EINVAL;
1698
1699         if (is_support_sw_smu(adev)) {
1700                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
1701                 if (err)
1702                         return err;
1703         } else if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1704                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1705                 if (err)
1706                         return err;
1707         }
1708
1709         speed = (speed * 255) / 100;
1710
1711         return sprintf(buf, "%i\n", speed);
1712 }
1713
1714 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1715                                            struct device_attribute *attr,
1716                                            char *buf)
1717 {
1718         struct amdgpu_device *adev = dev_get_drvdata(dev);
1719         int err;
1720         u32 speed = 0;
1721
1722         /* Can't adjust fan when the card is off */
1723         if  ((adev->flags & AMD_IS_PX) &&
1724              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1725                 return -EINVAL;
1726
1727         if (is_support_sw_smu(adev)) {
1728                 err = smu_get_current_rpm(&adev->smu, &speed);
1729                 if (err)
1730                         return err;
1731         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1732                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1733                 if (err)
1734                         return err;
1735         }
1736
1737         return sprintf(buf, "%i\n", speed);
1738 }
1739
1740 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1741                                          struct device_attribute *attr,
1742                                          char *buf)
1743 {
1744         struct amdgpu_device *adev = dev_get_drvdata(dev);
1745         u32 min_rpm = 0;
1746         u32 size = sizeof(min_rpm);
1747         int r;
1748
1749         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1750                                    (void *)&min_rpm, &size);
1751         if (r)
1752                 return r;
1753
1754         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1755 }
1756
1757 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1758                                          struct device_attribute *attr,
1759                                          char *buf)
1760 {
1761         struct amdgpu_device *adev = dev_get_drvdata(dev);
1762         u32 max_rpm = 0;
1763         u32 size = sizeof(max_rpm);
1764         int r;
1765
1766         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1767                                    (void *)&max_rpm, &size);
1768         if (r)
1769                 return r;
1770
1771         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1772 }
1773
1774 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1775                                            struct device_attribute *attr,
1776                                            char *buf)
1777 {
1778         struct amdgpu_device *adev = dev_get_drvdata(dev);
1779         int err;
1780         u32 rpm = 0;
1781
1782         /* Can't adjust fan when the card is off */
1783         if  ((adev->flags & AMD_IS_PX) &&
1784              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1785                 return -EINVAL;
1786
1787         if (is_support_sw_smu(adev)) {
1788                 err = smu_get_current_rpm(&adev->smu, &rpm);
1789                 if (err)
1790                         return err;
1791         } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1792                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1793                 if (err)
1794                         return err;
1795         }
1796
1797         return sprintf(buf, "%i\n", rpm);
1798 }
1799
1800 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1801                                      struct device_attribute *attr,
1802                                      const char *buf, size_t count)
1803 {
1804         struct amdgpu_device *adev = dev_get_drvdata(dev);
1805         int err;
1806         u32 value;
1807         u32 pwm_mode;
1808
1809         if (is_support_sw_smu(adev))
1810                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1811         else
1812                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1813
1814         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1815                 return -ENODATA;
1816
1817         /* Can't adjust fan when the card is off */
1818         if  ((adev->flags & AMD_IS_PX) &&
1819              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1820                 return -EINVAL;
1821
1822         err = kstrtou32(buf, 10, &value);
1823         if (err)
1824                 return err;
1825
1826         if (is_support_sw_smu(adev)) {
1827                 err = smu_set_fan_speed_rpm(&adev->smu, value);
1828                 if (err)
1829                         return err;
1830         } else if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1831                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1832                 if (err)
1833                         return err;
1834         }
1835
1836         return count;
1837 }
1838
1839 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1840                                             struct device_attribute *attr,
1841                                             char *buf)
1842 {
1843         struct amdgpu_device *adev = dev_get_drvdata(dev);
1844         u32 pwm_mode = 0;
1845
1846         if (is_support_sw_smu(adev)) {
1847                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
1848         } else {
1849                 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1850                         return -EINVAL;
1851
1852                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1853         }
1854         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1855 }
1856
1857 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1858                                             struct device_attribute *attr,
1859                                             const char *buf,
1860                                             size_t count)
1861 {
1862         struct amdgpu_device *adev = dev_get_drvdata(dev);
1863         int err;
1864         int value;
1865         u32 pwm_mode;
1866
1867         /* Can't adjust fan when the card is off */
1868         if  ((adev->flags & AMD_IS_PX) &&
1869              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1870                 return -EINVAL;
1871
1872
1873         err = kstrtoint(buf, 10, &value);
1874         if (err)
1875                 return err;
1876
1877         if (value == 0)
1878                 pwm_mode = AMD_FAN_CTRL_AUTO;
1879         else if (value == 1)
1880                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1881         else
1882                 return -EINVAL;
1883
1884         if (is_support_sw_smu(adev)) {
1885                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
1886         } else {
1887                 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1888                         return -EINVAL;
1889                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1890         }
1891
1892         return count;
1893 }
1894
1895 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1896                                         struct device_attribute *attr,
1897                                         char *buf)
1898 {
1899         struct amdgpu_device *adev = dev_get_drvdata(dev);
1900         struct drm_device *ddev = adev->ddev;
1901         u32 vddgfx;
1902         int r, size = sizeof(vddgfx);
1903
1904         /* Can't get voltage when the card is off */
1905         if  ((adev->flags & AMD_IS_PX) &&
1906              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1907                 return -EINVAL;
1908
1909         /* get the voltage */
1910         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1911                                    (void *)&vddgfx, &size);
1912         if (r)
1913                 return r;
1914
1915         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1916 }
1917
1918 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1919                                               struct device_attribute *attr,
1920                                               char *buf)
1921 {
1922         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1923 }
1924
1925 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1926                                        struct device_attribute *attr,
1927                                        char *buf)
1928 {
1929         struct amdgpu_device *adev = dev_get_drvdata(dev);
1930         struct drm_device *ddev = adev->ddev;
1931         u32 vddnb;
1932         int r, size = sizeof(vddnb);
1933
1934         /* only APUs have vddnb */
1935         if  (!(adev->flags & AMD_IS_APU))
1936                 return -EINVAL;
1937
1938         /* Can't get voltage when the card is off */
1939         if  ((adev->flags & AMD_IS_PX) &&
1940              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1941                 return -EINVAL;
1942
1943         /* get the voltage */
1944         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1945                                    (void *)&vddnb, &size);
1946         if (r)
1947                 return r;
1948
1949         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1950 }
1951
1952 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1953                                               struct device_attribute *attr,
1954                                               char *buf)
1955 {
1956         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1957 }
1958
1959 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1960                                            struct device_attribute *attr,
1961                                            char *buf)
1962 {
1963         struct amdgpu_device *adev = dev_get_drvdata(dev);
1964         struct drm_device *ddev = adev->ddev;
1965         u32 query = 0;
1966         int r, size = sizeof(u32);
1967         unsigned uw;
1968
1969         /* Can't get power when the card is off */
1970         if  ((adev->flags & AMD_IS_PX) &&
1971              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1972                 return -EINVAL;
1973
1974         /* get the voltage */
1975         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1976                                    (void *)&query, &size);
1977         if (r)
1978                 return r;
1979
1980         /* convert to microwatts */
1981         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1982
1983         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1984 }
1985
1986 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1987                                          struct device_attribute *attr,
1988                                          char *buf)
1989 {
1990         return sprintf(buf, "%i\n", 0);
1991 }
1992
1993 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1994                                          struct device_attribute *attr,
1995                                          char *buf)
1996 {
1997         struct amdgpu_device *adev = dev_get_drvdata(dev);
1998         uint32_t limit = 0;
1999
2000         if (is_support_sw_smu(adev)) {
2001                 smu_get_power_limit(&adev->smu, &limit, true);
2002                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2003         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2004                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2005                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2006         } else {
2007                 return snprintf(buf, PAGE_SIZE, "\n");
2008         }
2009 }
2010
2011 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2012                                          struct device_attribute *attr,
2013                                          char *buf)
2014 {
2015         struct amdgpu_device *adev = dev_get_drvdata(dev);
2016         uint32_t limit = 0;
2017
2018         if (is_support_sw_smu(adev)) {
2019                 smu_get_power_limit(&adev->smu, &limit, false);
2020                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2021         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2022                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2023                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2024         } else {
2025                 return snprintf(buf, PAGE_SIZE, "\n");
2026         }
2027 }
2028
2029
2030 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2031                 struct device_attribute *attr,
2032                 const char *buf,
2033                 size_t count)
2034 {
2035         struct amdgpu_device *adev = dev_get_drvdata(dev);
2036         int err;
2037         u32 value;
2038
2039         err = kstrtou32(buf, 10, &value);
2040         if (err)
2041                 return err;
2042
2043         value = value / 1000000; /* convert to Watt */
2044         if (is_support_sw_smu(adev)) {
2045                 adev->smu.funcs->set_power_limit(&adev->smu, value);
2046         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
2047                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2048                 if (err)
2049                         return err;
2050         } else {
2051                 return -EINVAL;
2052         }
2053
2054         return count;
2055 }
2056
2057 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
2058                                       struct device_attribute *attr,
2059                                       char *buf)
2060 {
2061         struct amdgpu_device *adev = dev_get_drvdata(dev);
2062         struct drm_device *ddev = adev->ddev;
2063         uint32_t sclk;
2064         int r, size = sizeof(sclk);
2065
2066         /* Can't get voltage when the card is off */
2067         if  ((adev->flags & AMD_IS_PX) &&
2068              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2069                 return -EINVAL;
2070
2071         /* sanity check PP is enabled */
2072         if (!(adev->powerplay.pp_funcs &&
2073               adev->powerplay.pp_funcs->read_sensor))
2074               return -EINVAL;
2075
2076         /* get the sclk */
2077         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
2078                                    (void *)&sclk, &size);
2079         if (r)
2080                 return r;
2081
2082         return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
2083 }
2084
2085 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
2086                                             struct device_attribute *attr,
2087                                             char *buf)
2088 {
2089         return snprintf(buf, PAGE_SIZE, "sclk\n");
2090 }
2091
2092 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
2093                                       struct device_attribute *attr,
2094                                       char *buf)
2095 {
2096         struct amdgpu_device *adev = dev_get_drvdata(dev);
2097         struct drm_device *ddev = adev->ddev;
2098         uint32_t mclk;
2099         int r, size = sizeof(mclk);
2100
2101         /* Can't get voltage when the card is off */
2102         if  ((adev->flags & AMD_IS_PX) &&
2103              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
2104                 return -EINVAL;
2105
2106         /* sanity check PP is enabled */
2107         if (!(adev->powerplay.pp_funcs &&
2108               adev->powerplay.pp_funcs->read_sensor))
2109               return -EINVAL;
2110
2111         /* get the sclk */
2112         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
2113                                    (void *)&mclk, &size);
2114         if (r)
2115                 return r;
2116
2117         return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
2118 }
2119
2120 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
2121                                             struct device_attribute *attr,
2122                                             char *buf)
2123 {
2124         return snprintf(buf, PAGE_SIZE, "mclk\n");
2125 }
2126
2127 /**
2128  * DOC: hwmon
2129  *
2130  * The amdgpu driver exposes the following sensor interfaces:
2131  *
2132  * - GPU temperature (via the on-die sensor)
2133  *
2134  * - GPU voltage
2135  *
2136  * - Northbridge voltage (APUs only)
2137  *
2138  * - GPU power
2139  *
2140  * - GPU fan
2141  *
2142  * - GPU gfx/compute engine clock
2143  *
2144  * - GPU memory clock (dGPU only)
2145  *
2146  * hwmon interfaces for GPU temperature:
2147  *
2148  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
2149  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
2150  *
2151  * - temp[1-3]_label: temperature channel label
2152  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
2153  *
2154  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
2155  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
2156  *
2157  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
2158  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
2159  *
2160  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
2161  *   - these are supported on SOC15 dGPUs only
2162  *
2163  * hwmon interfaces for GPU voltage:
2164  *
2165  * - in0_input: the voltage on the GPU in millivolts
2166  *
2167  * - in1_input: the voltage on the Northbridge in millivolts
2168  *
2169  * hwmon interfaces for GPU power:
2170  *
2171  * - power1_average: average power used by the GPU in microWatts
2172  *
2173  * - power1_cap_min: minimum cap supported in microWatts
2174  *
2175  * - power1_cap_max: maximum cap supported in microWatts
2176  *
2177  * - power1_cap: selected power cap in microWatts
2178  *
2179  * hwmon interfaces for GPU fan:
2180  *
2181  * - pwm1: pulse width modulation fan level (0-255)
2182  *
2183  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
2184  *
2185  * - pwm1_min: pulse width modulation fan control minimum level (0)
2186  *
2187  * - pwm1_max: pulse width modulation fan control maximum level (255)
2188  *
2189  * - fan1_min: an minimum value Unit: revolution/min (RPM)
2190  *
2191  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
2192  *
2193  * - fan1_input: fan speed in RPM
2194  *
2195  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
2196  *
2197  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
2198  *
2199  * hwmon interfaces for GPU clocks:
2200  *
2201  * - freq1_input: the gfx/compute clock in hertz
2202  *
2203  * - freq2_input: the memory clock in hertz
2204  *
2205  * You can use hwmon tools like sensors to view this information on your system.
2206  *
2207  */
2208
2209 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
2210 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
2211 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
2212 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
2213 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
2214 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
2215 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
2216 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
2217 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
2218 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
2219 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
2220 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
2221 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
2222 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
2223 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
2224 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
2225 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
2226 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
2227 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
2228 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
2229 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
2230 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
2231 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
2232 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
2233 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
2234 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
2235 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
2236 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
2237 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
2238 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
2239 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
2240 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
2241 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
2242 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
2243 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
2244 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
2245
2246 static struct attribute *hwmon_attributes[] = {
2247         &sensor_dev_attr_temp1_input.dev_attr.attr,
2248         &sensor_dev_attr_temp1_crit.dev_attr.attr,
2249         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
2250         &sensor_dev_attr_temp2_input.dev_attr.attr,
2251         &sensor_dev_attr_temp2_crit.dev_attr.attr,
2252         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
2253         &sensor_dev_attr_temp3_input.dev_attr.attr,
2254         &sensor_dev_attr_temp3_crit.dev_attr.attr,
2255         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
2256         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
2257         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
2258         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
2259         &sensor_dev_attr_temp1_label.dev_attr.attr,
2260         &sensor_dev_attr_temp2_label.dev_attr.attr,
2261         &sensor_dev_attr_temp3_label.dev_attr.attr,
2262         &sensor_dev_attr_pwm1.dev_attr.attr,
2263         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2264         &sensor_dev_attr_pwm1_min.dev_attr.attr,
2265         &sensor_dev_attr_pwm1_max.dev_attr.attr,
2266         &sensor_dev_attr_fan1_input.dev_attr.attr,
2267         &sensor_dev_attr_fan1_min.dev_attr.attr,
2268         &sensor_dev_attr_fan1_max.dev_attr.attr,
2269         &sensor_dev_attr_fan1_target.dev_attr.attr,
2270         &sensor_dev_attr_fan1_enable.dev_attr.attr,
2271         &sensor_dev_attr_in0_input.dev_attr.attr,
2272         &sensor_dev_attr_in0_label.dev_attr.attr,
2273         &sensor_dev_attr_in1_input.dev_attr.attr,
2274         &sensor_dev_attr_in1_label.dev_attr.attr,
2275         &sensor_dev_attr_power1_average.dev_attr.attr,
2276         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
2277         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
2278         &sensor_dev_attr_power1_cap.dev_attr.attr,
2279         &sensor_dev_attr_freq1_input.dev_attr.attr,
2280         &sensor_dev_attr_freq1_label.dev_attr.attr,
2281         &sensor_dev_attr_freq2_input.dev_attr.attr,
2282         &sensor_dev_attr_freq2_label.dev_attr.attr,
2283         NULL
2284 };
2285
2286 static umode_t hwmon_attributes_visible(struct kobject *kobj,
2287                                         struct attribute *attr, int index)
2288 {
2289         struct device *dev = kobj_to_dev(kobj);
2290         struct amdgpu_device *adev = dev_get_drvdata(dev);
2291         umode_t effective_mode = attr->mode;
2292
2293         /* Skip fan attributes if fan is not present */
2294         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2295             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2296             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2297             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2298             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2299             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2300             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2301             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2302             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2303                 return 0;
2304
2305         /* Skip fan attributes on APU */
2306         if ((adev->flags & AMD_IS_APU) &&
2307             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2308              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2309              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2310              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2311              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2312              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2313              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2314              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2315              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2316                 return 0;
2317
2318         /* Skip limit attributes if DPM is not enabled */
2319         if (!adev->pm.dpm_enabled &&
2320             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
2321              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
2322              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
2323              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
2324              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2325              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
2326              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
2327              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
2328              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2329              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
2330              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
2331                 return 0;
2332
2333         if (!is_support_sw_smu(adev)) {
2334                 /* mask fan attributes if we have no bindings for this asic to expose */
2335                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
2336                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
2337                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
2338                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
2339                         effective_mode &= ~S_IRUGO;
2340
2341                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2342                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
2343                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
2344                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
2345                         effective_mode &= ~S_IWUSR;
2346         }
2347
2348         if ((adev->flags & AMD_IS_APU) &&
2349             (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
2350              attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
2351              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
2352              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
2353                 return 0;
2354
2355         if (!is_support_sw_smu(adev)) {
2356                 /* hide max/min values if we can't both query and manage the fan */
2357                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
2358                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
2359                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2360                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2361                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
2362                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
2363                         return 0;
2364
2365                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
2366                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
2367                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
2368                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
2369                         return 0;
2370         }
2371
2372         /* only APUs have vddnb */
2373         if (!(adev->flags & AMD_IS_APU) &&
2374             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
2375              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
2376                 return 0;
2377
2378         /* no mclk on APUs */
2379         if ((adev->flags & AMD_IS_APU) &&
2380             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
2381              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
2382                 return 0;
2383
2384         /* only SOC15 dGPUs support hotspot and mem temperatures */
2385         if (((adev->flags & AMD_IS_APU) ||
2386              adev->asic_type < CHIP_VEGA10) &&
2387             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
2388              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
2389              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
2390              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
2391              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
2392              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
2393              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
2394              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
2395              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
2396              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
2397              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
2398                 return 0;
2399
2400         return effective_mode;
2401 }
2402
2403 static const struct attribute_group hwmon_attrgroup = {
2404         .attrs = hwmon_attributes,
2405         .is_visible = hwmon_attributes_visible,
2406 };
2407
2408 static const struct attribute_group *hwmon_groups[] = {
2409         &hwmon_attrgroup,
2410         NULL
2411 };
2412
2413 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
2414 {
2415         struct amdgpu_device *adev =
2416                 container_of(work, struct amdgpu_device,
2417                              pm.dpm.thermal.work);
2418         /* switch to the thermal state */
2419         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
2420         int temp, size = sizeof(temp);
2421
2422         if (!adev->pm.dpm_enabled)
2423                 return;
2424
2425         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
2426                                     (void *)&temp, &size)) {
2427                 if (temp < adev->pm.dpm.thermal.min_temp)
2428                         /* switch back the user state */
2429                         dpm_state = adev->pm.dpm.user_state;
2430         } else {
2431                 if (adev->pm.dpm.thermal.high_to_low)
2432                         /* switch back the user state */
2433                         dpm_state = adev->pm.dpm.user_state;
2434         }
2435         mutex_lock(&adev->pm.mutex);
2436         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
2437                 adev->pm.dpm.thermal_active = true;
2438         else
2439                 adev->pm.dpm.thermal_active = false;
2440         adev->pm.dpm.state = dpm_state;
2441         mutex_unlock(&adev->pm.mutex);
2442
2443         amdgpu_pm_compute_clocks(adev);
2444 }
2445
2446 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
2447                                                      enum amd_pm_state_type dpm_state)
2448 {
2449         int i;
2450         struct amdgpu_ps *ps;
2451         u32 ui_class;
2452         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
2453                 true : false;
2454
2455         /* check if the vblank period is too short to adjust the mclk */
2456         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
2457                 if (amdgpu_dpm_vblank_too_short(adev))
2458                         single_display = false;
2459         }
2460
2461         /* certain older asics have a separare 3D performance state,
2462          * so try that first if the user selected performance
2463          */
2464         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
2465                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
2466         /* balanced states don't exist at the moment */
2467         if (dpm_state == POWER_STATE_TYPE_BALANCED)
2468                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2469
2470 restart_search:
2471         /* Pick the best power state based on current conditions */
2472         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2473                 ps = &adev->pm.dpm.ps[i];
2474                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
2475                 switch (dpm_state) {
2476                 /* user states */
2477                 case POWER_STATE_TYPE_BATTERY:
2478                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
2479                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2480                                         if (single_display)
2481                                                 return ps;
2482                                 } else
2483                                         return ps;
2484                         }
2485                         break;
2486                 case POWER_STATE_TYPE_BALANCED:
2487                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
2488                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2489                                         if (single_display)
2490                                                 return ps;
2491                                 } else
2492                                         return ps;
2493                         }
2494                         break;
2495                 case POWER_STATE_TYPE_PERFORMANCE:
2496                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2497                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
2498                                         if (single_display)
2499                                                 return ps;
2500                                 } else
2501                                         return ps;
2502                         }
2503                         break;
2504                 /* internal states */
2505                 case POWER_STATE_TYPE_INTERNAL_UVD:
2506                         if (adev->pm.dpm.uvd_ps)
2507                                 return adev->pm.dpm.uvd_ps;
2508                         else
2509                                 break;
2510                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2511                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
2512                                 return ps;
2513                         break;
2514                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2515                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
2516                                 return ps;
2517                         break;
2518                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2519                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
2520                                 return ps;
2521                         break;
2522                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2523                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
2524                                 return ps;
2525                         break;
2526                 case POWER_STATE_TYPE_INTERNAL_BOOT:
2527                         return adev->pm.dpm.boot_ps;
2528                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
2529                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
2530                                 return ps;
2531                         break;
2532                 case POWER_STATE_TYPE_INTERNAL_ACPI:
2533                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
2534                                 return ps;
2535                         break;
2536                 case POWER_STATE_TYPE_INTERNAL_ULV:
2537                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
2538                                 return ps;
2539                         break;
2540                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
2541                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2542                                 return ps;
2543                         break;
2544                 default:
2545                         break;
2546                 }
2547         }
2548         /* use a fallback state if we didn't match */
2549         switch (dpm_state) {
2550         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
2551                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
2552                 goto restart_search;
2553         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
2554         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
2555         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
2556                 if (adev->pm.dpm.uvd_ps) {
2557                         return adev->pm.dpm.uvd_ps;
2558                 } else {
2559                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2560                         goto restart_search;
2561                 }
2562         case POWER_STATE_TYPE_INTERNAL_THERMAL:
2563                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
2564                 goto restart_search;
2565         case POWER_STATE_TYPE_INTERNAL_ACPI:
2566                 dpm_state = POWER_STATE_TYPE_BATTERY;
2567                 goto restart_search;
2568         case POWER_STATE_TYPE_BATTERY:
2569         case POWER_STATE_TYPE_BALANCED:
2570         case POWER_STATE_TYPE_INTERNAL_3DPERF:
2571                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
2572                 goto restart_search;
2573         default:
2574                 break;
2575         }
2576
2577         return NULL;
2578 }
2579
2580 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
2581 {
2582         struct amdgpu_ps *ps;
2583         enum amd_pm_state_type dpm_state;
2584         int ret;
2585         bool equal = false;
2586
2587         /* if dpm init failed */
2588         if (!adev->pm.dpm_enabled)
2589                 return;
2590
2591         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
2592                 /* add other state override checks here */
2593                 if ((!adev->pm.dpm.thermal_active) &&
2594                     (!adev->pm.dpm.uvd_active))
2595                         adev->pm.dpm.state = adev->pm.dpm.user_state;
2596         }
2597         dpm_state = adev->pm.dpm.state;
2598
2599         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
2600         if (ps)
2601                 adev->pm.dpm.requested_ps = ps;
2602         else
2603                 return;
2604
2605         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
2606                 printk("switching from power state:\n");
2607                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
2608                 printk("switching to power state:\n");
2609                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
2610         }
2611
2612         /* update whether vce is active */
2613         ps->vce_active = adev->pm.dpm.vce_active;
2614         if (adev->powerplay.pp_funcs->display_configuration_changed)
2615                 amdgpu_dpm_display_configuration_changed(adev);
2616
2617         ret = amdgpu_dpm_pre_set_power_state(adev);
2618         if (ret)
2619                 return;
2620
2621         if (adev->powerplay.pp_funcs->check_state_equal) {
2622                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
2623                         equal = false;
2624         }
2625
2626         if (equal)
2627                 return;
2628
2629         amdgpu_dpm_set_power_state(adev);
2630         amdgpu_dpm_post_set_power_state(adev);
2631
2632         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
2633         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
2634
2635         if (adev->powerplay.pp_funcs->force_performance_level) {
2636                 if (adev->pm.dpm.thermal_active) {
2637                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
2638                         /* force low perf level for thermal */
2639                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
2640                         /* save the user's level */
2641                         adev->pm.dpm.forced_level = level;
2642                 } else {
2643                         /* otherwise, user selected level */
2644                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
2645                 }
2646         }
2647 }
2648
2649 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
2650 {
2651         int ret = 0;
2652         if (is_support_sw_smu(adev)) {
2653             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
2654             if (ret)
2655                 DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
2656                           enable ? "true" : "false", ret);
2657         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2658                 /* enable/disable UVD */
2659                 mutex_lock(&adev->pm.mutex);
2660                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
2661                 mutex_unlock(&adev->pm.mutex);
2662         }
2663         /* enable/disable Low Memory PState for UVD (4k videos) */
2664         if (adev->asic_type == CHIP_STONEY &&
2665                 adev->uvd.decode_image_width >= WIDTH_4K) {
2666                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2667
2668                 if (hwmgr && hwmgr->hwmgr_func &&
2669                     hwmgr->hwmgr_func->update_nbdpm_pstate)
2670                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
2671                                                                !enable,
2672                                                                true);
2673         }
2674 }
2675
2676 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
2677 {
2678         int ret = 0;
2679         if (is_support_sw_smu(adev)) {
2680             ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
2681             if (ret)
2682                 DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
2683                           enable ? "true" : "false", ret);
2684         } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
2685                 /* enable/disable VCE */
2686                 mutex_lock(&adev->pm.mutex);
2687                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
2688                 mutex_unlock(&adev->pm.mutex);
2689         }
2690 }
2691
2692 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
2693 {
2694         int i;
2695
2696         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2697                 return;
2698
2699         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2700                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2701
2702 }
2703
2704 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
2705 {
2706         int r;
2707
2708         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
2709                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
2710                 if (r) {
2711                         pr_err("smu firmware loading failed\n");
2712                         return r;
2713                 }
2714                 *smu_version = adev->pm.fw_version;
2715         }
2716         return 0;
2717 }
2718
2719 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2720 {
2721         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2722         int ret;
2723
2724         if (adev->pm.sysfs_initialized)
2725                 return 0;
2726
2727         if (adev->pm.dpm_enabled == 0)
2728                 return 0;
2729
2730         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2731                                                                    DRIVER_NAME, adev,
2732                                                                    hwmon_groups);
2733         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2734                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2735                 dev_err(adev->dev,
2736                         "Unable to register hwmon device: %d\n", ret);
2737                 return ret;
2738         }
2739
2740         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2741         if (ret) {
2742                 DRM_ERROR("failed to create device file for dpm state\n");
2743                 return ret;
2744         }
2745         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2746         if (ret) {
2747                 DRM_ERROR("failed to create device file for dpm state\n");
2748                 return ret;
2749         }
2750
2751
2752         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2753         if (ret) {
2754                 DRM_ERROR("failed to create device file pp_num_states\n");
2755                 return ret;
2756         }
2757         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2758         if (ret) {
2759                 DRM_ERROR("failed to create device file pp_cur_state\n");
2760                 return ret;
2761         }
2762         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2763         if (ret) {
2764                 DRM_ERROR("failed to create device file pp_force_state\n");
2765                 return ret;
2766         }
2767         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2768         if (ret) {
2769                 DRM_ERROR("failed to create device file pp_table\n");
2770                 return ret;
2771         }
2772
2773         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2774         if (ret) {
2775                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2776                 return ret;
2777         }
2778         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2779         if (ret) {
2780                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2781                 return ret;
2782         }
2783         if (adev->asic_type >= CHIP_VEGA10) {
2784                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
2785                 if (ret) {
2786                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
2787                         return ret;
2788                 }
2789                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2790                 if (ret) {
2791                         DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
2792                         return ret;
2793                 }
2794         }
2795         if (adev->asic_type >= CHIP_VEGA20) {
2796                 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
2797                 if (ret) {
2798                         DRM_ERROR("failed to create device file pp_dpm_fclk\n");
2799                         return ret;
2800                 }
2801         }
2802         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2803         if (ret) {
2804                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2805                 return ret;
2806         }
2807         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2808         if (ret) {
2809                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2810                 return ret;
2811         }
2812         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2813         if (ret) {
2814                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2815                 return ret;
2816         }
2817         ret = device_create_file(adev->dev,
2818                         &dev_attr_pp_power_profile_mode);
2819         if (ret) {
2820                 DRM_ERROR("failed to create device file "
2821                                 "pp_power_profile_mode\n");
2822                 return ret;
2823         }
2824         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2825             (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
2826                 ret = device_create_file(adev->dev,
2827                                 &dev_attr_pp_od_clk_voltage);
2828                 if (ret) {
2829                         DRM_ERROR("failed to create device file "
2830                                         "pp_od_clk_voltage\n");
2831                         return ret;
2832                 }
2833         }
2834         ret = device_create_file(adev->dev,
2835                         &dev_attr_gpu_busy_percent);
2836         if (ret) {
2837                 DRM_ERROR("failed to create device file "
2838                                 "gpu_busy_level\n");
2839                 return ret;
2840         }
2841         /* APU does not have its own dedicated memory */
2842         if (!(adev->flags & AMD_IS_APU)) {
2843                 ret = device_create_file(adev->dev,
2844                                 &dev_attr_mem_busy_percent);
2845                 if (ret) {
2846                         DRM_ERROR("failed to create device file "
2847                                         "mem_busy_percent\n");
2848                         return ret;
2849                 }
2850         }
2851         /* PCIe Perf counters won't work on APU nodes */
2852         if (!(adev->flags & AMD_IS_APU)) {
2853                 ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
2854                 if (ret) {
2855                         DRM_ERROR("failed to create device file pcie_bw\n");
2856                         return ret;
2857                 }
2858         }
2859         if (adev->unique_id)
2860                 ret = device_create_file(adev->dev, &dev_attr_unique_id);
2861         if (ret) {
2862                 DRM_ERROR("failed to create device file unique_id\n");
2863                 return ret;
2864         }
2865         ret = amdgpu_debugfs_pm_init(adev);
2866         if (ret) {
2867                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2868                 return ret;
2869         }
2870
2871         if ((adev->asic_type >= CHIP_VEGA10) &&
2872             !(adev->flags & AMD_IS_APU)) {
2873                 ret = device_create_file(adev->dev,
2874                                 &dev_attr_ppfeatures);
2875                 if (ret) {
2876                         DRM_ERROR("failed to create device file "
2877                                         "ppfeatures\n");
2878                         return ret;
2879                 }
2880         }
2881
2882         adev->pm.sysfs_initialized = true;
2883
2884         return 0;
2885 }
2886
2887 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2888 {
2889         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2890
2891         if (adev->pm.dpm_enabled == 0)
2892                 return;
2893
2894         if (adev->pm.int_hwmon_dev)
2895                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2896         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2897         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2898
2899         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2900         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2901         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2902         device_remove_file(adev->dev, &dev_attr_pp_table);
2903
2904         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2905         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2906         if (adev->asic_type >= CHIP_VEGA10) {
2907                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
2908                 device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
2909         }
2910         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2911         if (adev->asic_type >= CHIP_VEGA20)
2912                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
2913         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2914         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2915         device_remove_file(adev->dev,
2916                         &dev_attr_pp_power_profile_mode);
2917         if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2918             (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2919                 device_remove_file(adev->dev,
2920                                 &dev_attr_pp_od_clk_voltage);
2921         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2922         if (!(adev->flags & AMD_IS_APU))
2923                 device_remove_file(adev->dev, &dev_attr_mem_busy_percent);
2924         if (!(adev->flags & AMD_IS_APU))
2925                 device_remove_file(adev->dev, &dev_attr_pcie_bw);
2926         if (adev->unique_id)
2927                 device_remove_file(adev->dev, &dev_attr_unique_id);
2928         if ((adev->asic_type >= CHIP_VEGA10) &&
2929             !(adev->flags & AMD_IS_APU))
2930                 device_remove_file(adev->dev, &dev_attr_ppfeatures);
2931 }
2932
2933 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2934 {
2935         int i = 0;
2936
2937         if (!adev->pm.dpm_enabled)
2938                 return;
2939
2940         if (adev->mode_info.num_crtc)
2941                 amdgpu_display_bandwidth_update(adev);
2942
2943         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2944                 struct amdgpu_ring *ring = adev->rings[i];
2945                 if (ring && ring->sched.ready)
2946                         amdgpu_fence_wait_empty(ring);
2947         }
2948
2949         if (is_support_sw_smu(adev)) {
2950                 struct smu_context *smu = &adev->smu;
2951                 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm;
2952                 mutex_lock(&(smu->mutex));
2953                 smu_handle_task(&adev->smu,
2954                                 smu_dpm->dpm_level,
2955                                 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE);
2956                 mutex_unlock(&(smu->mutex));
2957         } else {
2958                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
2959                         if (!amdgpu_device_has_dc_support(adev)) {
2960                                 mutex_lock(&adev->pm.mutex);
2961                                 amdgpu_dpm_get_active_displays(adev);
2962                                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2963                                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2964                                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2965                                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2966                                 if (adev->pm.pm_display_cfg.vrefresh > 120)
2967                                         adev->pm.pm_display_cfg.min_vblank_time = 0;
2968                                 if (adev->powerplay.pp_funcs->display_configuration_change)
2969                                         adev->powerplay.pp_funcs->display_configuration_change(
2970                                                                         adev->powerplay.pp_handle,
2971                                                                         &adev->pm.pm_display_cfg);
2972                                 mutex_unlock(&adev->pm.mutex);
2973                         }
2974                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2975                 } else {
2976                         mutex_lock(&adev->pm.mutex);
2977                         amdgpu_dpm_get_active_displays(adev);
2978                         amdgpu_dpm_change_power_state_locked(adev);
2979                         mutex_unlock(&adev->pm.mutex);
2980                 }
2981         }
2982 }
2983
2984 /*
2985  * Debugfs info
2986  */
2987 #if defined(CONFIG_DEBUG_FS)
2988
2989 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2990 {
2991         uint32_t value;
2992         uint64_t value64;
2993         uint32_t query = 0;
2994         int size;
2995
2996         /* GPU Clocks */
2997         size = sizeof(value);
2998         seq_printf(m, "GFX Clocks and Power:\n");
2999         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3000                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3001         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3002                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3003         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3004                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3005         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3006                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3007         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3008                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3009         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3010                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3011         size = sizeof(uint32_t);
3012         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3013                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3014         size = sizeof(value);
3015         seq_printf(m, "\n");
3016
3017         /* GPU Temp */
3018         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3019                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3020
3021         /* GPU Load */
3022         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3023                 seq_printf(m, "GPU Load: %u %%\n", value);
3024         /* MEM Load */
3025         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3026                 seq_printf(m, "MEM Load: %u %%\n", value);
3027
3028         seq_printf(m, "\n");
3029
3030         /* SMC feature mask */
3031         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3032                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3033
3034         /* UVD clocks */
3035         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3036                 if (!value) {
3037                         seq_printf(m, "UVD: Disabled\n");
3038                 } else {
3039                         seq_printf(m, "UVD: Enabled\n");
3040                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3041                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3042                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3043                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3044                 }
3045         }
3046         seq_printf(m, "\n");
3047
3048         /* VCE clocks */
3049         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3050                 if (!value) {
3051                         seq_printf(m, "VCE: Disabled\n");
3052                 } else {
3053                         seq_printf(m, "VCE: Enabled\n");
3054                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3055                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3056                 }
3057         }
3058
3059         return 0;
3060 }
3061
3062 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3063 {
3064         int i;
3065
3066         for (i = 0; clocks[i].flag; i++)
3067                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3068                            (flags & clocks[i].flag) ? "On" : "Off");
3069 }
3070
3071 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3072 {
3073         struct drm_info_node *node = (struct drm_info_node *) m->private;
3074         struct drm_device *dev = node->minor->dev;
3075         struct amdgpu_device *adev = dev->dev_private;
3076         struct drm_device *ddev = adev->ddev;
3077         u32 flags = 0;
3078
3079         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3080         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3081         amdgpu_parse_cg_state(m, flags);
3082         seq_printf(m, "\n");
3083
3084         if (!adev->pm.dpm_enabled) {
3085                 seq_printf(m, "dpm not enabled\n");
3086                 return 0;
3087         }
3088         if  ((adev->flags & AMD_IS_PX) &&
3089              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
3090                 seq_printf(m, "PX asic powered off\n");
3091         } else if (!is_support_sw_smu(adev) && adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3092                 mutex_lock(&adev->pm.mutex);
3093                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3094                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3095                 else
3096                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3097                 mutex_unlock(&adev->pm.mutex);
3098         } else {
3099                 return amdgpu_debugfs_pm_info_pp(m, adev);
3100         }
3101
3102         return 0;
3103 }
3104
3105 static const struct drm_info_list amdgpu_pm_info_list[] = {
3106         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3107 };
3108 #endif
3109
3110 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3111 {
3112 #if defined(CONFIG_DEBUG_FS)
3113         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3114 #else
3115         return 0;
3116 #endif
3117 }