Merge branch 'drm-fixes-5.0' of git://people.freedesktop.org/~agd5f/linux into drm...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c
1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Rafał Miłecki <zajec5@gmail.com>
23  *          Alex Deucher <alexdeucher@gmail.com>
24  */
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_display.h"
31 #include "atom.h"
32 #include <linux/power_supply.h>
33 #include <linux/hwmon.h>
34 #include <linux/hwmon-sysfs.h>
35 #include <linux/nospec.h>
36 #include "hwmgr.h"
37 #define WIDTH_4K 3840
38
39 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
40
41 static const struct cg_flag_name clocks[] = {
42         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
43         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
44         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
45         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
46         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
47         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
48         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
49         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
50         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
51         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
52         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
53         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
54         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
55         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
56         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
57         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
58         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
59         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
60         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
61         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
62         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
63         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
64         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
65         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
66         {0, NULL},
67 };
68
69 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
70 {
71         if (adev->pm.dpm_enabled) {
72                 mutex_lock(&adev->pm.mutex);
73                 if (power_supply_is_system_supplied() > 0)
74                         adev->pm.ac_power = true;
75                 else
76                         adev->pm.ac_power = false;
77                 if (adev->powerplay.pp_funcs->enable_bapm)
78                         amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power);
79                 mutex_unlock(&adev->pm.mutex);
80         }
81 }
82
83 /**
84  * DOC: power_dpm_state
85  *
86  * The power_dpm_state file is a legacy interface and is only provided for
87  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
88  * certain power related parameters.  The file power_dpm_state is used for this.
89  * It accepts the following arguments:
90  *
91  * - battery
92  *
93  * - balanced
94  *
95  * - performance
96  *
97  * battery
98  *
99  * On older GPUs, the vbios provided a special power state for battery
100  * operation.  Selecting battery switched to this state.  This is no
101  * longer provided on newer GPUs so the option does nothing in that case.
102  *
103  * balanced
104  *
105  * On older GPUs, the vbios provided a special power state for balanced
106  * operation.  Selecting balanced switched to this state.  This is no
107  * longer provided on newer GPUs so the option does nothing in that case.
108  *
109  * performance
110  *
111  * On older GPUs, the vbios provided a special power state for performance
112  * operation.  Selecting performance switched to this state.  This is no
113  * longer provided on newer GPUs so the option does nothing in that case.
114  *
115  */
116
117 static ssize_t amdgpu_get_dpm_state(struct device *dev,
118                                     struct device_attribute *attr,
119                                     char *buf)
120 {
121         struct drm_device *ddev = dev_get_drvdata(dev);
122         struct amdgpu_device *adev = ddev->dev_private;
123         enum amd_pm_state_type pm;
124
125         if (adev->powerplay.pp_funcs->get_current_power_state)
126                 pm = amdgpu_dpm_get_current_power_state(adev);
127         else
128                 pm = adev->pm.dpm.user_state;
129
130         return snprintf(buf, PAGE_SIZE, "%s\n",
131                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
132                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
133 }
134
135 static ssize_t amdgpu_set_dpm_state(struct device *dev,
136                                     struct device_attribute *attr,
137                                     const char *buf,
138                                     size_t count)
139 {
140         struct drm_device *ddev = dev_get_drvdata(dev);
141         struct amdgpu_device *adev = ddev->dev_private;
142         enum amd_pm_state_type  state;
143
144         if (strncmp("battery", buf, strlen("battery")) == 0)
145                 state = POWER_STATE_TYPE_BATTERY;
146         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
147                 state = POWER_STATE_TYPE_BALANCED;
148         else if (strncmp("performance", buf, strlen("performance")) == 0)
149                 state = POWER_STATE_TYPE_PERFORMANCE;
150         else {
151                 count = -EINVAL;
152                 goto fail;
153         }
154
155         if (adev->powerplay.pp_funcs->dispatch_tasks) {
156                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
157         } else {
158                 mutex_lock(&adev->pm.mutex);
159                 adev->pm.dpm.user_state = state;
160                 mutex_unlock(&adev->pm.mutex);
161
162                 /* Can't set dpm state when the card is off */
163                 if (!(adev->flags & AMD_IS_PX) ||
164                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
165                         amdgpu_pm_compute_clocks(adev);
166         }
167 fail:
168         return count;
169 }
170
171
172 /**
173  * DOC: power_dpm_force_performance_level
174  *
175  * The amdgpu driver provides a sysfs API for adjusting certain power
176  * related parameters.  The file power_dpm_force_performance_level is
177  * used for this.  It accepts the following arguments:
178  *
179  * - auto
180  *
181  * - low
182  *
183  * - high
184  *
185  * - manual
186  *
187  * - profile_standard
188  *
189  * - profile_min_sclk
190  *
191  * - profile_min_mclk
192  *
193  * - profile_peak
194  *
195  * auto
196  *
197  * When auto is selected, the driver will attempt to dynamically select
198  * the optimal power profile for current conditions in the driver.
199  *
200  * low
201  *
202  * When low is selected, the clocks are forced to the lowest power state.
203  *
204  * high
205  *
206  * When high is selected, the clocks are forced to the highest power state.
207  *
208  * manual
209  *
210  * When manual is selected, the user can manually adjust which power states
211  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
212  * and pp_dpm_pcie files and adjust the power state transition heuristics
213  * via the pp_power_profile_mode sysfs file.
214  *
215  * profile_standard
216  * profile_min_sclk
217  * profile_min_mclk
218  * profile_peak
219  *
220  * When the profiling modes are selected, clock and power gating are
221  * disabled and the clocks are set for different profiling cases. This
222  * mode is recommended for profiling specific work loads where you do
223  * not want clock or power gating for clock fluctuation to interfere
224  * with your results. profile_standard sets the clocks to a fixed clock
225  * level which varies from asic to asic.  profile_min_sclk forces the sclk
226  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
227  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
228  *
229  */
230
231 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
232                                                 struct device_attribute *attr,
233                                                                 char *buf)
234 {
235         struct drm_device *ddev = dev_get_drvdata(dev);
236         struct amdgpu_device *adev = ddev->dev_private;
237         enum amd_dpm_forced_level level = 0xff;
238
239         if  ((adev->flags & AMD_IS_PX) &&
240              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
241                 return snprintf(buf, PAGE_SIZE, "off\n");
242
243         if (adev->powerplay.pp_funcs->get_performance_level)
244                 level = amdgpu_dpm_get_performance_level(adev);
245         else
246                 level = adev->pm.dpm.forced_level;
247
248         return snprintf(buf, PAGE_SIZE, "%s\n",
249                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
250                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
251                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
252                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
253                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
254                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
255                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
256                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
257                         "unknown");
258 }
259
260 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
261                                                        struct device_attribute *attr,
262                                                        const char *buf,
263                                                        size_t count)
264 {
265         struct drm_device *ddev = dev_get_drvdata(dev);
266         struct amdgpu_device *adev = ddev->dev_private;
267         enum amd_dpm_forced_level level;
268         enum amd_dpm_forced_level current_level = 0xff;
269         int ret = 0;
270
271         /* Can't force performance level when the card is off */
272         if  ((adev->flags & AMD_IS_PX) &&
273              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
274                 return -EINVAL;
275
276         if (adev->powerplay.pp_funcs->get_performance_level)
277                 current_level = amdgpu_dpm_get_performance_level(adev);
278
279         if (strncmp("low", buf, strlen("low")) == 0) {
280                 level = AMD_DPM_FORCED_LEVEL_LOW;
281         } else if (strncmp("high", buf, strlen("high")) == 0) {
282                 level = AMD_DPM_FORCED_LEVEL_HIGH;
283         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
284                 level = AMD_DPM_FORCED_LEVEL_AUTO;
285         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
286                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
287         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
288                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
289         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
290                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
291         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
292                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
293         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
294                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
295         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
296                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
297         }  else {
298                 count = -EINVAL;
299                 goto fail;
300         }
301
302         if (current_level == level)
303                 return count;
304
305         if (adev->powerplay.pp_funcs->force_performance_level) {
306                 mutex_lock(&adev->pm.mutex);
307                 if (adev->pm.dpm.thermal_active) {
308                         count = -EINVAL;
309                         mutex_unlock(&adev->pm.mutex);
310                         goto fail;
311                 }
312                 ret = amdgpu_dpm_force_performance_level(adev, level);
313                 if (ret)
314                         count = -EINVAL;
315                 else
316                         adev->pm.dpm.forced_level = level;
317                 mutex_unlock(&adev->pm.mutex);
318         }
319
320 fail:
321         return count;
322 }
323
324 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
325                 struct device_attribute *attr,
326                 char *buf)
327 {
328         struct drm_device *ddev = dev_get_drvdata(dev);
329         struct amdgpu_device *adev = ddev->dev_private;
330         struct pp_states_info data;
331         int i, buf_len;
332
333         if (adev->powerplay.pp_funcs->get_pp_num_states)
334                 amdgpu_dpm_get_pp_num_states(adev, &data);
335
336         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
337         for (i = 0; i < data.nums; i++)
338                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
339                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
340                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
341                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
342                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
343
344         return buf_len;
345 }
346
347 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
348                 struct device_attribute *attr,
349                 char *buf)
350 {
351         struct drm_device *ddev = dev_get_drvdata(dev);
352         struct amdgpu_device *adev = ddev->dev_private;
353         struct pp_states_info data;
354         enum amd_pm_state_type pm = 0;
355         int i = 0;
356
357         if (adev->powerplay.pp_funcs->get_current_power_state
358                  && adev->powerplay.pp_funcs->get_pp_num_states) {
359                 pm = amdgpu_dpm_get_current_power_state(adev);
360                 amdgpu_dpm_get_pp_num_states(adev, &data);
361
362                 for (i = 0; i < data.nums; i++) {
363                         if (pm == data.states[i])
364                                 break;
365                 }
366
367                 if (i == data.nums)
368                         i = -EINVAL;
369         }
370
371         return snprintf(buf, PAGE_SIZE, "%d\n", i);
372 }
373
374 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
375                 struct device_attribute *attr,
376                 char *buf)
377 {
378         struct drm_device *ddev = dev_get_drvdata(dev);
379         struct amdgpu_device *adev = ddev->dev_private;
380
381         if (adev->pp_force_state_enabled)
382                 return amdgpu_get_pp_cur_state(dev, attr, buf);
383         else
384                 return snprintf(buf, PAGE_SIZE, "\n");
385 }
386
387 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
388                 struct device_attribute *attr,
389                 const char *buf,
390                 size_t count)
391 {
392         struct drm_device *ddev = dev_get_drvdata(dev);
393         struct amdgpu_device *adev = ddev->dev_private;
394         enum amd_pm_state_type state = 0;
395         unsigned long idx;
396         int ret;
397
398         if (strlen(buf) == 1)
399                 adev->pp_force_state_enabled = false;
400         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
401                         adev->powerplay.pp_funcs->get_pp_num_states) {
402                 struct pp_states_info data;
403
404                 ret = kstrtoul(buf, 0, &idx);
405                 if (ret || idx >= ARRAY_SIZE(data.states)) {
406                         count = -EINVAL;
407                         goto fail;
408                 }
409                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
410
411                 amdgpu_dpm_get_pp_num_states(adev, &data);
412                 state = data.states[idx];
413                 /* only set user selected power states */
414                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
415                     state != POWER_STATE_TYPE_DEFAULT) {
416                         amdgpu_dpm_dispatch_task(adev,
417                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
418                         adev->pp_force_state_enabled = true;
419                 }
420         }
421 fail:
422         return count;
423 }
424
425 /**
426  * DOC: pp_table
427  *
428  * The amdgpu driver provides a sysfs API for uploading new powerplay
429  * tables.  The file pp_table is used for this.  Reading the file
430  * will dump the current power play table.  Writing to the file
431  * will attempt to upload a new powerplay table and re-initialize
432  * powerplay using that new table.
433  *
434  */
435
436 static ssize_t amdgpu_get_pp_table(struct device *dev,
437                 struct device_attribute *attr,
438                 char *buf)
439 {
440         struct drm_device *ddev = dev_get_drvdata(dev);
441         struct amdgpu_device *adev = ddev->dev_private;
442         char *table = NULL;
443         int size;
444
445         if (adev->powerplay.pp_funcs->get_pp_table)
446                 size = amdgpu_dpm_get_pp_table(adev, &table);
447         else
448                 return 0;
449
450         if (size >= PAGE_SIZE)
451                 size = PAGE_SIZE - 1;
452
453         memcpy(buf, table, size);
454
455         return size;
456 }
457
458 static ssize_t amdgpu_set_pp_table(struct device *dev,
459                 struct device_attribute *attr,
460                 const char *buf,
461                 size_t count)
462 {
463         struct drm_device *ddev = dev_get_drvdata(dev);
464         struct amdgpu_device *adev = ddev->dev_private;
465
466         if (adev->powerplay.pp_funcs->set_pp_table)
467                 amdgpu_dpm_set_pp_table(adev, buf, count);
468
469         return count;
470 }
471
472 /**
473  * DOC: pp_od_clk_voltage
474  *
475  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
476  * in each power level within a power state.  The pp_od_clk_voltage is used for
477  * this.
478  *
479  * < For Vega10 and previous ASICs >
480  *
481  * Reading the file will display:
482  *
483  * - a list of engine clock levels and voltages labeled OD_SCLK
484  *
485  * - a list of memory clock levels and voltages labeled OD_MCLK
486  *
487  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
488  *
489  * To manually adjust these settings, first select manual using
490  * power_dpm_force_performance_level. Enter a new value for each
491  * level by writing a string that contains "s/m level clock voltage" to
492  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
493  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
494  * 810 mV.  When you have edited all of the states as needed, write
495  * "c" (commit) to the file to commit your changes.  If you want to reset to the
496  * default power levels, write "r" (reset) to the file to reset them.
497  *
498  *
499  * < For Vega20 >
500  *
501  * Reading the file will display:
502  *
503  * - minimum and maximum engine clock labeled OD_SCLK
504  *
505  * - maximum memory clock labeled OD_MCLK
506  *
507  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
508  *   They can be used to calibrate the sclk voltage curve.
509  *
510  * - a list of valid ranges for sclk, mclk, and voltage curve points
511  *   labeled OD_RANGE
512  *
513  * To manually adjust these settings:
514  *
515  * - First select manual using power_dpm_force_performance_level
516  *
517  * - For clock frequency setting, enter a new value by writing a
518  *   string that contains "s/m index clock" to the file. The index
519  *   should be 0 if to set minimum clock. And 1 if to set maximum
520  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
521  *   "m 1 800" will update maximum mclk to be 800Mhz.
522  *
523  *   For sclk voltage curve, enter the new values by writing a
524  *   string that contains "vc point clock voltage" to the file. The
525  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
526  *   update point1 with clock set as 300Mhz and voltage as
527  *   600mV. "vc 2 1000 1000" will update point3 with clock set
528  *   as 1000Mhz and voltage 1000mV.
529  *
530  * - When you have edited all of the states as needed, write "c" (commit)
531  *   to the file to commit your changes
532  *
533  * - If you want to reset to the default power levels, write "r" (reset)
534  *   to the file to reset them
535  *
536  */
537
538 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
539                 struct device_attribute *attr,
540                 const char *buf,
541                 size_t count)
542 {
543         struct drm_device *ddev = dev_get_drvdata(dev);
544         struct amdgpu_device *adev = ddev->dev_private;
545         int ret;
546         uint32_t parameter_size = 0;
547         long parameter[64];
548         char buf_cpy[128];
549         char *tmp_str;
550         char *sub_str;
551         const char delimiter[3] = {' ', '\n', '\0'};
552         uint32_t type;
553
554         if (count > 127)
555                 return -EINVAL;
556
557         if (*buf == 's')
558                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
559         else if (*buf == 'm')
560                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
561         else if(*buf == 'r')
562                 type = PP_OD_RESTORE_DEFAULT_TABLE;
563         else if (*buf == 'c')
564                 type = PP_OD_COMMIT_DPM_TABLE;
565         else if (!strncmp(buf, "vc", 2))
566                 type = PP_OD_EDIT_VDDC_CURVE;
567         else
568                 return -EINVAL;
569
570         memcpy(buf_cpy, buf, count+1);
571
572         tmp_str = buf_cpy;
573
574         if (type == PP_OD_EDIT_VDDC_CURVE)
575                 tmp_str++;
576         while (isspace(*++tmp_str));
577
578         while (tmp_str[0]) {
579                 sub_str = strsep(&tmp_str, delimiter);
580                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
581                 if (ret)
582                         return -EINVAL;
583                 parameter_size++;
584
585                 while (isspace(*tmp_str))
586                         tmp_str++;
587         }
588
589         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
590                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
591                                                 parameter, parameter_size);
592
593         if (ret)
594                 return -EINVAL;
595
596         if (type == PP_OD_COMMIT_DPM_TABLE) {
597                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
598                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
599                         return count;
600                 } else {
601                         return -EINVAL;
602                 }
603         }
604
605         return count;
606 }
607
608 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
609                 struct device_attribute *attr,
610                 char *buf)
611 {
612         struct drm_device *ddev = dev_get_drvdata(dev);
613         struct amdgpu_device *adev = ddev->dev_private;
614         uint32_t size = 0;
615
616         if (adev->powerplay.pp_funcs->print_clock_levels) {
617                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
618                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
619                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
620                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
621                 return size;
622         } else {
623                 return snprintf(buf, PAGE_SIZE, "\n");
624         }
625
626 }
627
628 /**
629  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
630  *
631  * The amdgpu driver provides a sysfs API for adjusting what power levels
632  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
633  * and pp_dpm_pcie are used for this.
634  *
635  * Reading back the files will show you the available power levels within
636  * the power state and the clock information for those levels.
637  *
638  * To manually adjust these states, first select manual using
639  * power_dpm_force_performance_level.
640  * Secondly,Enter a new value for each level by inputing a string that
641  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
642  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
643  */
644
645 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
646                 struct device_attribute *attr,
647                 char *buf)
648 {
649         struct drm_device *ddev = dev_get_drvdata(dev);
650         struct amdgpu_device *adev = ddev->dev_private;
651
652         if (adev->powerplay.pp_funcs->print_clock_levels)
653                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
654         else
655                 return snprintf(buf, PAGE_SIZE, "\n");
656 }
657
658 /*
659  * Worst case: 32 bits individually specified, in octal at 12 characters
660  * per line (+1 for \n).
661  */
662 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
663
664 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
665 {
666         int ret;
667         long level;
668         char *sub_str = NULL;
669         char *tmp;
670         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
671         const char delimiter[3] = {' ', '\n', '\0'};
672         size_t bytes;
673
674         *mask = 0;
675
676         bytes = min(count, sizeof(buf_cpy) - 1);
677         memcpy(buf_cpy, buf, bytes);
678         buf_cpy[bytes] = '\0';
679         tmp = buf_cpy;
680         while (tmp[0]) {
681                 sub_str = strsep(&tmp, delimiter);
682                 if (strlen(sub_str)) {
683                         ret = kstrtol(sub_str, 0, &level);
684                         if (ret)
685                                 return -EINVAL;
686                         *mask |= 1 << level;
687                 } else
688                         break;
689         }
690
691         return 0;
692 }
693
694 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
695                 struct device_attribute *attr,
696                 const char *buf,
697                 size_t count)
698 {
699         struct drm_device *ddev = dev_get_drvdata(dev);
700         struct amdgpu_device *adev = ddev->dev_private;
701         int ret;
702         uint32_t mask = 0;
703
704         ret = amdgpu_read_mask(buf, count, &mask);
705         if (ret)
706                 return ret;
707
708         if (adev->powerplay.pp_funcs->force_clock_level)
709                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
710
711         if (ret)
712                 return -EINVAL;
713
714         return count;
715 }
716
717 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
718                 struct device_attribute *attr,
719                 char *buf)
720 {
721         struct drm_device *ddev = dev_get_drvdata(dev);
722         struct amdgpu_device *adev = ddev->dev_private;
723
724         if (adev->powerplay.pp_funcs->print_clock_levels)
725                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
726         else
727                 return snprintf(buf, PAGE_SIZE, "\n");
728 }
729
730 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
731                 struct device_attribute *attr,
732                 const char *buf,
733                 size_t count)
734 {
735         struct drm_device *ddev = dev_get_drvdata(dev);
736         struct amdgpu_device *adev = ddev->dev_private;
737         int ret;
738         uint32_t mask = 0;
739
740         ret = amdgpu_read_mask(buf, count, &mask);
741         if (ret)
742                 return ret;
743
744         if (adev->powerplay.pp_funcs->force_clock_level)
745                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
746
747         if (ret)
748                 return -EINVAL;
749
750         return count;
751 }
752
753 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
754                 struct device_attribute *attr,
755                 char *buf)
756 {
757         struct drm_device *ddev = dev_get_drvdata(dev);
758         struct amdgpu_device *adev = ddev->dev_private;
759
760         if (adev->powerplay.pp_funcs->print_clock_levels)
761                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
762         else
763                 return snprintf(buf, PAGE_SIZE, "\n");
764 }
765
766 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
767                 struct device_attribute *attr,
768                 const char *buf,
769                 size_t count)
770 {
771         struct drm_device *ddev = dev_get_drvdata(dev);
772         struct amdgpu_device *adev = ddev->dev_private;
773         int ret;
774         uint32_t mask = 0;
775
776         ret = amdgpu_read_mask(buf, count, &mask);
777         if (ret)
778                 return ret;
779
780         if (adev->powerplay.pp_funcs->force_clock_level)
781                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
782
783         if (ret)
784                 return -EINVAL;
785
786         return count;
787 }
788
789 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
790                 struct device_attribute *attr,
791                 char *buf)
792 {
793         struct drm_device *ddev = dev_get_drvdata(dev);
794         struct amdgpu_device *adev = ddev->dev_private;
795         uint32_t value = 0;
796
797         if (adev->powerplay.pp_funcs->get_sclk_od)
798                 value = amdgpu_dpm_get_sclk_od(adev);
799
800         return snprintf(buf, PAGE_SIZE, "%d\n", value);
801 }
802
803 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
804                 struct device_attribute *attr,
805                 const char *buf,
806                 size_t count)
807 {
808         struct drm_device *ddev = dev_get_drvdata(dev);
809         struct amdgpu_device *adev = ddev->dev_private;
810         int ret;
811         long int value;
812
813         ret = kstrtol(buf, 0, &value);
814
815         if (ret) {
816                 count = -EINVAL;
817                 goto fail;
818         }
819         if (adev->powerplay.pp_funcs->set_sclk_od)
820                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
821
822         if (adev->powerplay.pp_funcs->dispatch_tasks) {
823                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
824         } else {
825                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
826                 amdgpu_pm_compute_clocks(adev);
827         }
828
829 fail:
830         return count;
831 }
832
833 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
834                 struct device_attribute *attr,
835                 char *buf)
836 {
837         struct drm_device *ddev = dev_get_drvdata(dev);
838         struct amdgpu_device *adev = ddev->dev_private;
839         uint32_t value = 0;
840
841         if (adev->powerplay.pp_funcs->get_mclk_od)
842                 value = amdgpu_dpm_get_mclk_od(adev);
843
844         return snprintf(buf, PAGE_SIZE, "%d\n", value);
845 }
846
847 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
848                 struct device_attribute *attr,
849                 const char *buf,
850                 size_t count)
851 {
852         struct drm_device *ddev = dev_get_drvdata(dev);
853         struct amdgpu_device *adev = ddev->dev_private;
854         int ret;
855         long int value;
856
857         ret = kstrtol(buf, 0, &value);
858
859         if (ret) {
860                 count = -EINVAL;
861                 goto fail;
862         }
863         if (adev->powerplay.pp_funcs->set_mclk_od)
864                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
865
866         if (adev->powerplay.pp_funcs->dispatch_tasks) {
867                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
868         } else {
869                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
870                 amdgpu_pm_compute_clocks(adev);
871         }
872
873 fail:
874         return count;
875 }
876
877 /**
878  * DOC: pp_power_profile_mode
879  *
880  * The amdgpu driver provides a sysfs API for adjusting the heuristics
881  * related to switching between power levels in a power state.  The file
882  * pp_power_profile_mode is used for this.
883  *
884  * Reading this file outputs a list of all of the predefined power profiles
885  * and the relevant heuristics settings for that profile.
886  *
887  * To select a profile or create a custom profile, first select manual using
888  * power_dpm_force_performance_level.  Writing the number of a predefined
889  * profile to pp_power_profile_mode will enable those heuristics.  To
890  * create a custom set of heuristics, write a string of numbers to the file
891  * starting with the number of the custom profile along with a setting
892  * for each heuristic parameter.  Due to differences across asic families
893  * the heuristic parameters vary from family to family.
894  *
895  */
896
897 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
898                 struct device_attribute *attr,
899                 char *buf)
900 {
901         struct drm_device *ddev = dev_get_drvdata(dev);
902         struct amdgpu_device *adev = ddev->dev_private;
903
904         if (adev->powerplay.pp_funcs->get_power_profile_mode)
905                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
906
907         return snprintf(buf, PAGE_SIZE, "\n");
908 }
909
910
911 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
912                 struct device_attribute *attr,
913                 const char *buf,
914                 size_t count)
915 {
916         int ret = 0xff;
917         struct drm_device *ddev = dev_get_drvdata(dev);
918         struct amdgpu_device *adev = ddev->dev_private;
919         uint32_t parameter_size = 0;
920         long parameter[64];
921         char *sub_str, buf_cpy[128];
922         char *tmp_str;
923         uint32_t i = 0;
924         char tmp[2];
925         long int profile_mode = 0;
926         const char delimiter[3] = {' ', '\n', '\0'};
927
928         tmp[0] = *(buf);
929         tmp[1] = '\0';
930         ret = kstrtol(tmp, 0, &profile_mode);
931         if (ret)
932                 goto fail;
933
934         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
935                 if (count < 2 || count > 127)
936                         return -EINVAL;
937                 while (isspace(*++buf))
938                         i++;
939                 memcpy(buf_cpy, buf, count-i);
940                 tmp_str = buf_cpy;
941                 while (tmp_str[0]) {
942                         sub_str = strsep(&tmp_str, delimiter);
943                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
944                         if (ret) {
945                                 count = -EINVAL;
946                                 goto fail;
947                         }
948                         parameter_size++;
949                         while (isspace(*tmp_str))
950                                 tmp_str++;
951                 }
952         }
953         parameter[parameter_size] = profile_mode;
954         if (adev->powerplay.pp_funcs->set_power_profile_mode)
955                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
956
957         if (!ret)
958                 return count;
959 fail:
960         return -EINVAL;
961 }
962
963 /**
964  * DOC: busy_percent
965  *
966  * The amdgpu driver provides a sysfs API for reading how busy the GPU
967  * is as a percentage.  The file gpu_busy_percent is used for this.
968  * The SMU firmware computes a percentage of load based on the
969  * aggregate activity level in the IP cores.
970  */
971 static ssize_t amdgpu_get_busy_percent(struct device *dev,
972                 struct device_attribute *attr,
973                 char *buf)
974 {
975         struct drm_device *ddev = dev_get_drvdata(dev);
976         struct amdgpu_device *adev = ddev->dev_private;
977         int r, value, size = sizeof(value);
978
979         /* sanity check PP is enabled */
980         if (!(adev->powerplay.pp_funcs &&
981               adev->powerplay.pp_funcs->read_sensor))
982                 return -EINVAL;
983
984         /* read the IP busy sensor */
985         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
986                                    (void *)&value, &size);
987         if (r)
988                 return r;
989
990         return snprintf(buf, PAGE_SIZE, "%d\n", value);
991 }
992
993 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
994 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
995                    amdgpu_get_dpm_forced_performance_level,
996                    amdgpu_set_dpm_forced_performance_level);
997 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
998 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
999 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
1000                 amdgpu_get_pp_force_state,
1001                 amdgpu_set_pp_force_state);
1002 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
1003                 amdgpu_get_pp_table,
1004                 amdgpu_set_pp_table);
1005 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
1006                 amdgpu_get_pp_dpm_sclk,
1007                 amdgpu_set_pp_dpm_sclk);
1008 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
1009                 amdgpu_get_pp_dpm_mclk,
1010                 amdgpu_set_pp_dpm_mclk);
1011 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
1012                 amdgpu_get_pp_dpm_pcie,
1013                 amdgpu_set_pp_dpm_pcie);
1014 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
1015                 amdgpu_get_pp_sclk_od,
1016                 amdgpu_set_pp_sclk_od);
1017 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
1018                 amdgpu_get_pp_mclk_od,
1019                 amdgpu_set_pp_mclk_od);
1020 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
1021                 amdgpu_get_pp_power_profile_mode,
1022                 amdgpu_set_pp_power_profile_mode);
1023 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
1024                 amdgpu_get_pp_od_clk_voltage,
1025                 amdgpu_set_pp_od_clk_voltage);
1026 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
1027                 amdgpu_get_busy_percent, NULL);
1028
1029 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
1030                                       struct device_attribute *attr,
1031                                       char *buf)
1032 {
1033         struct amdgpu_device *adev = dev_get_drvdata(dev);
1034         struct drm_device *ddev = adev->ddev;
1035         int r, temp, size = sizeof(temp);
1036
1037         /* Can't get temperature when the card is off */
1038         if  ((adev->flags & AMD_IS_PX) &&
1039              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1040                 return -EINVAL;
1041
1042         /* sanity check PP is enabled */
1043         if (!(adev->powerplay.pp_funcs &&
1044               adev->powerplay.pp_funcs->read_sensor))
1045                 return -EINVAL;
1046
1047         /* get the temperature */
1048         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1049                                    (void *)&temp, &size);
1050         if (r)
1051                 return r;
1052
1053         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1054 }
1055
1056 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
1057                                              struct device_attribute *attr,
1058                                              char *buf)
1059 {
1060         struct amdgpu_device *adev = dev_get_drvdata(dev);
1061         int hyst = to_sensor_dev_attr(attr)->index;
1062         int temp;
1063
1064         if (hyst)
1065                 temp = adev->pm.dpm.thermal.min_temp;
1066         else
1067                 temp = adev->pm.dpm.thermal.max_temp;
1068
1069         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
1070 }
1071
1072 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
1073                                             struct device_attribute *attr,
1074                                             char *buf)
1075 {
1076         struct amdgpu_device *adev = dev_get_drvdata(dev);
1077         u32 pwm_mode = 0;
1078
1079         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1080                 return -EINVAL;
1081
1082         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1083
1084         return sprintf(buf, "%i\n", pwm_mode);
1085 }
1086
1087 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
1088                                             struct device_attribute *attr,
1089                                             const char *buf,
1090                                             size_t count)
1091 {
1092         struct amdgpu_device *adev = dev_get_drvdata(dev);
1093         int err;
1094         int value;
1095
1096         /* Can't adjust fan when the card is off */
1097         if  ((adev->flags & AMD_IS_PX) &&
1098              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1099                 return -EINVAL;
1100
1101         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1102                 return -EINVAL;
1103
1104         err = kstrtoint(buf, 10, &value);
1105         if (err)
1106                 return err;
1107
1108         amdgpu_dpm_set_fan_control_mode(adev, value);
1109
1110         return count;
1111 }
1112
1113 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
1114                                          struct device_attribute *attr,
1115                                          char *buf)
1116 {
1117         return sprintf(buf, "%i\n", 0);
1118 }
1119
1120 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
1121                                          struct device_attribute *attr,
1122                                          char *buf)
1123 {
1124         return sprintf(buf, "%i\n", 255);
1125 }
1126
1127 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1128                                      struct device_attribute *attr,
1129                                      const char *buf, size_t count)
1130 {
1131         struct amdgpu_device *adev = dev_get_drvdata(dev);
1132         int err;
1133         u32 value;
1134         u32 pwm_mode;
1135
1136         /* Can't adjust fan when the card is off */
1137         if  ((adev->flags & AMD_IS_PX) &&
1138              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1139                 return -EINVAL;
1140
1141         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1142         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
1143                 pr_info("manual fan speed control should be enabled first\n");
1144                 return -EINVAL;
1145         }
1146
1147         err = kstrtou32(buf, 10, &value);
1148         if (err)
1149                 return err;
1150
1151         value = (value * 100) / 255;
1152
1153         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1154                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1155                 if (err)
1156                         return err;
1157         }
1158
1159         return count;
1160 }
1161
1162 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1163                                      struct device_attribute *attr,
1164                                      char *buf)
1165 {
1166         struct amdgpu_device *adev = dev_get_drvdata(dev);
1167         int err;
1168         u32 speed = 0;
1169
1170         /* Can't adjust fan when the card is off */
1171         if  ((adev->flags & AMD_IS_PX) &&
1172              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1173                 return -EINVAL;
1174
1175         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1176                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1177                 if (err)
1178                         return err;
1179         }
1180
1181         speed = (speed * 255) / 100;
1182
1183         return sprintf(buf, "%i\n", speed);
1184 }
1185
1186 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1187                                            struct device_attribute *attr,
1188                                            char *buf)
1189 {
1190         struct amdgpu_device *adev = dev_get_drvdata(dev);
1191         int err;
1192         u32 speed = 0;
1193
1194         /* Can't adjust fan when the card is off */
1195         if  ((adev->flags & AMD_IS_PX) &&
1196              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1197                 return -EINVAL;
1198
1199         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1200                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1201                 if (err)
1202                         return err;
1203         }
1204
1205         return sprintf(buf, "%i\n", speed);
1206 }
1207
1208 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
1209                                          struct device_attribute *attr,
1210                                          char *buf)
1211 {
1212         struct amdgpu_device *adev = dev_get_drvdata(dev);
1213         u32 min_rpm = 0;
1214         u32 size = sizeof(min_rpm);
1215         int r;
1216
1217         if (!adev->powerplay.pp_funcs->read_sensor)
1218                 return -EINVAL;
1219
1220         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
1221                                    (void *)&min_rpm, &size);
1222         if (r)
1223                 return r;
1224
1225         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
1226 }
1227
1228 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
1229                                          struct device_attribute *attr,
1230                                          char *buf)
1231 {
1232         struct amdgpu_device *adev = dev_get_drvdata(dev);
1233         u32 max_rpm = 0;
1234         u32 size = sizeof(max_rpm);
1235         int r;
1236
1237         if (!adev->powerplay.pp_funcs->read_sensor)
1238                 return -EINVAL;
1239
1240         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
1241                                    (void *)&max_rpm, &size);
1242         if (r)
1243                 return r;
1244
1245         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
1246 }
1247
1248 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
1249                                            struct device_attribute *attr,
1250                                            char *buf)
1251 {
1252         struct amdgpu_device *adev = dev_get_drvdata(dev);
1253         int err;
1254         u32 rpm = 0;
1255
1256         /* Can't adjust fan when the card is off */
1257         if  ((adev->flags & AMD_IS_PX) &&
1258              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1259                 return -EINVAL;
1260
1261         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1262                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
1263                 if (err)
1264                         return err;
1265         }
1266
1267         return sprintf(buf, "%i\n", rpm);
1268 }
1269
1270 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
1271                                      struct device_attribute *attr,
1272                                      const char *buf, size_t count)
1273 {
1274         struct amdgpu_device *adev = dev_get_drvdata(dev);
1275         int err;
1276         u32 value;
1277         u32 pwm_mode;
1278
1279         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1280         if (pwm_mode != AMD_FAN_CTRL_MANUAL)
1281                 return -ENODATA;
1282
1283         /* Can't adjust fan when the card is off */
1284         if  ((adev->flags & AMD_IS_PX) &&
1285              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1286                 return -EINVAL;
1287
1288         err = kstrtou32(buf, 10, &value);
1289         if (err)
1290                 return err;
1291
1292         if (adev->powerplay.pp_funcs->set_fan_speed_rpm) {
1293                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
1294                 if (err)
1295                         return err;
1296         }
1297
1298         return count;
1299 }
1300
1301 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
1302                                             struct device_attribute *attr,
1303                                             char *buf)
1304 {
1305         struct amdgpu_device *adev = dev_get_drvdata(dev);
1306         u32 pwm_mode = 0;
1307
1308         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
1309                 return -EINVAL;
1310
1311         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
1312
1313         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
1314 }
1315
1316 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
1317                                             struct device_attribute *attr,
1318                                             const char *buf,
1319                                             size_t count)
1320 {
1321         struct amdgpu_device *adev = dev_get_drvdata(dev);
1322         int err;
1323         int value;
1324         u32 pwm_mode;
1325
1326         /* Can't adjust fan when the card is off */
1327         if  ((adev->flags & AMD_IS_PX) &&
1328              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1329                 return -EINVAL;
1330
1331         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
1332                 return -EINVAL;
1333
1334         err = kstrtoint(buf, 10, &value);
1335         if (err)
1336                 return err;
1337
1338         if (value == 0)
1339                 pwm_mode = AMD_FAN_CTRL_AUTO;
1340         else if (value == 1)
1341                 pwm_mode = AMD_FAN_CTRL_MANUAL;
1342         else
1343                 return -EINVAL;
1344
1345         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
1346
1347         return count;
1348 }
1349
1350 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1351                                         struct device_attribute *attr,
1352                                         char *buf)
1353 {
1354         struct amdgpu_device *adev = dev_get_drvdata(dev);
1355         struct drm_device *ddev = adev->ddev;
1356         u32 vddgfx;
1357         int r, size = sizeof(vddgfx);
1358
1359         /* Can't get voltage when the card is off */
1360         if  ((adev->flags & AMD_IS_PX) &&
1361              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1362                 return -EINVAL;
1363
1364         /* sanity check PP is enabled */
1365         if (!(adev->powerplay.pp_funcs &&
1366               adev->powerplay.pp_funcs->read_sensor))
1367               return -EINVAL;
1368
1369         /* get the voltage */
1370         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1371                                    (void *)&vddgfx, &size);
1372         if (r)
1373                 return r;
1374
1375         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1376 }
1377
1378 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1379                                               struct device_attribute *attr,
1380                                               char *buf)
1381 {
1382         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1383 }
1384
1385 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1386                                        struct device_attribute *attr,
1387                                        char *buf)
1388 {
1389         struct amdgpu_device *adev = dev_get_drvdata(dev);
1390         struct drm_device *ddev = adev->ddev;
1391         u32 vddnb;
1392         int r, size = sizeof(vddnb);
1393
1394         /* only APUs have vddnb */
1395         if  (!(adev->flags & AMD_IS_APU))
1396                 return -EINVAL;
1397
1398         /* Can't get voltage when the card is off */
1399         if  ((adev->flags & AMD_IS_PX) &&
1400              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1401                 return -EINVAL;
1402
1403         /* sanity check PP is enabled */
1404         if (!(adev->powerplay.pp_funcs &&
1405               adev->powerplay.pp_funcs->read_sensor))
1406               return -EINVAL;
1407
1408         /* get the voltage */
1409         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1410                                    (void *)&vddnb, &size);
1411         if (r)
1412                 return r;
1413
1414         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1415 }
1416
1417 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1418                                               struct device_attribute *attr,
1419                                               char *buf)
1420 {
1421         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1422 }
1423
1424 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1425                                            struct device_attribute *attr,
1426                                            char *buf)
1427 {
1428         struct amdgpu_device *adev = dev_get_drvdata(dev);
1429         struct drm_device *ddev = adev->ddev;
1430         u32 query = 0;
1431         int r, size = sizeof(u32);
1432         unsigned uw;
1433
1434         /* Can't get power when the card is off */
1435         if  ((adev->flags & AMD_IS_PX) &&
1436              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1437                 return -EINVAL;
1438
1439         /* sanity check PP is enabled */
1440         if (!(adev->powerplay.pp_funcs &&
1441               adev->powerplay.pp_funcs->read_sensor))
1442               return -EINVAL;
1443
1444         /* get the voltage */
1445         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1446                                    (void *)&query, &size);
1447         if (r)
1448                 return r;
1449
1450         /* convert to microwatts */
1451         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1452
1453         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1454 }
1455
1456 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1457                                          struct device_attribute *attr,
1458                                          char *buf)
1459 {
1460         return sprintf(buf, "%i\n", 0);
1461 }
1462
1463 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1464                                          struct device_attribute *attr,
1465                                          char *buf)
1466 {
1467         struct amdgpu_device *adev = dev_get_drvdata(dev);
1468         uint32_t limit = 0;
1469
1470         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1471                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1472                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1473         } else {
1474                 return snprintf(buf, PAGE_SIZE, "\n");
1475         }
1476 }
1477
1478 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1479                                          struct device_attribute *attr,
1480                                          char *buf)
1481 {
1482         struct amdgpu_device *adev = dev_get_drvdata(dev);
1483         uint32_t limit = 0;
1484
1485         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1486                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1487                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1488         } else {
1489                 return snprintf(buf, PAGE_SIZE, "\n");
1490         }
1491 }
1492
1493
1494 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1495                 struct device_attribute *attr,
1496                 const char *buf,
1497                 size_t count)
1498 {
1499         struct amdgpu_device *adev = dev_get_drvdata(dev);
1500         int err;
1501         u32 value;
1502
1503         err = kstrtou32(buf, 10, &value);
1504         if (err)
1505                 return err;
1506
1507         value = value / 1000000; /* convert to Watt */
1508         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1509                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1510                 if (err)
1511                         return err;
1512         } else {
1513                 return -EINVAL;
1514         }
1515
1516         return count;
1517 }
1518
1519
1520 /**
1521  * DOC: hwmon
1522  *
1523  * The amdgpu driver exposes the following sensor interfaces:
1524  *
1525  * - GPU temperature (via the on-die sensor)
1526  *
1527  * - GPU voltage
1528  *
1529  * - Northbridge voltage (APUs only)
1530  *
1531  * - GPU power
1532  *
1533  * - GPU fan
1534  *
1535  * hwmon interfaces for GPU temperature:
1536  *
1537  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1538  *
1539  * - temp1_crit: temperature critical max value in millidegrees Celsius
1540  *
1541  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1542  *
1543  * hwmon interfaces for GPU voltage:
1544  *
1545  * - in0_input: the voltage on the GPU in millivolts
1546  *
1547  * - in1_input: the voltage on the Northbridge in millivolts
1548  *
1549  * hwmon interfaces for GPU power:
1550  *
1551  * - power1_average: average power used by the GPU in microWatts
1552  *
1553  * - power1_cap_min: minimum cap supported in microWatts
1554  *
1555  * - power1_cap_max: maximum cap supported in microWatts
1556  *
1557  * - power1_cap: selected power cap in microWatts
1558  *
1559  * hwmon interfaces for GPU fan:
1560  *
1561  * - pwm1: pulse width modulation fan level (0-255)
1562  *
1563  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
1564  *
1565  * - pwm1_min: pulse width modulation fan control minimum level (0)
1566  *
1567  * - pwm1_max: pulse width modulation fan control maximum level (255)
1568  *
1569  * - fan1_min: an minimum value Unit: revolution/min (RPM)
1570  *
1571  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
1572  *
1573  * - fan1_input: fan speed in RPM
1574  *
1575  * - fan[1-*]_target: Desired fan speed Unit: revolution/min (RPM)
1576  *
1577  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
1578  *
1579  * You can use hwmon tools like sensors to view this information on your system.
1580  *
1581  */
1582
1583 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1584 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1585 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1586 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1587 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1588 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1589 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1590 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1591 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
1592 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
1593 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
1594 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
1595 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1596 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1597 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1598 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1599 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1600 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1601 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1602 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1603
1604 static struct attribute *hwmon_attributes[] = {
1605         &sensor_dev_attr_temp1_input.dev_attr.attr,
1606         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1607         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1608         &sensor_dev_attr_pwm1.dev_attr.attr,
1609         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1610         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1611         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1612         &sensor_dev_attr_fan1_input.dev_attr.attr,
1613         &sensor_dev_attr_fan1_min.dev_attr.attr,
1614         &sensor_dev_attr_fan1_max.dev_attr.attr,
1615         &sensor_dev_attr_fan1_target.dev_attr.attr,
1616         &sensor_dev_attr_fan1_enable.dev_attr.attr,
1617         &sensor_dev_attr_in0_input.dev_attr.attr,
1618         &sensor_dev_attr_in0_label.dev_attr.attr,
1619         &sensor_dev_attr_in1_input.dev_attr.attr,
1620         &sensor_dev_attr_in1_label.dev_attr.attr,
1621         &sensor_dev_attr_power1_average.dev_attr.attr,
1622         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1623         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1624         &sensor_dev_attr_power1_cap.dev_attr.attr,
1625         NULL
1626 };
1627
1628 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1629                                         struct attribute *attr, int index)
1630 {
1631         struct device *dev = kobj_to_dev(kobj);
1632         struct amdgpu_device *adev = dev_get_drvdata(dev);
1633         umode_t effective_mode = attr->mode;
1634
1635         /* Skip fan attributes if fan is not present */
1636         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1637             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1638             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1639             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1640             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1641             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1642             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1643             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1644             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1645                 return 0;
1646
1647         /* Skip fan attributes on APU */
1648         if ((adev->flags & AMD_IS_APU) &&
1649             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1650              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1651              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1652              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1653              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1654              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1655              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1656              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1657              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1658                 return 0;
1659
1660         /* Skip limit attributes if DPM is not enabled */
1661         if (!adev->pm.dpm_enabled &&
1662             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1663              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1664              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1665              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1666              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1667              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
1668              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
1669              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
1670              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1671              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
1672              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
1673                 return 0;
1674
1675         /* mask fan attributes if we have no bindings for this asic to expose */
1676         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1677              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1678             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1679              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1680                 effective_mode &= ~S_IRUGO;
1681
1682         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1683              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1684             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1685              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1686                 effective_mode &= ~S_IWUSR;
1687
1688         if ((adev->flags & AMD_IS_APU) &&
1689             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1690              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1691              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1692                 return 0;
1693
1694         /* hide max/min values if we can't both query and manage the fan */
1695         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1696              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1697              (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
1698              !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
1699             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1700              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1701                 return 0;
1702
1703         if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
1704              !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
1705             (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
1706              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
1707                 return 0;
1708
1709         /* only APUs have vddnb */
1710         if (!(adev->flags & AMD_IS_APU) &&
1711             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1712              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1713                 return 0;
1714
1715         return effective_mode;
1716 }
1717
1718 static const struct attribute_group hwmon_attrgroup = {
1719         .attrs = hwmon_attributes,
1720         .is_visible = hwmon_attributes_visible,
1721 };
1722
1723 static const struct attribute_group *hwmon_groups[] = {
1724         &hwmon_attrgroup,
1725         NULL
1726 };
1727
1728 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1729 {
1730         struct amdgpu_device *adev =
1731                 container_of(work, struct amdgpu_device,
1732                              pm.dpm.thermal.work);
1733         /* switch to the thermal state */
1734         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1735         int temp, size = sizeof(temp);
1736
1737         if (!adev->pm.dpm_enabled)
1738                 return;
1739
1740         if (adev->powerplay.pp_funcs &&
1741             adev->powerplay.pp_funcs->read_sensor &&
1742             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1743                                     (void *)&temp, &size)) {
1744                 if (temp < adev->pm.dpm.thermal.min_temp)
1745                         /* switch back the user state */
1746                         dpm_state = adev->pm.dpm.user_state;
1747         } else {
1748                 if (adev->pm.dpm.thermal.high_to_low)
1749                         /* switch back the user state */
1750                         dpm_state = adev->pm.dpm.user_state;
1751         }
1752         mutex_lock(&adev->pm.mutex);
1753         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1754                 adev->pm.dpm.thermal_active = true;
1755         else
1756                 adev->pm.dpm.thermal_active = false;
1757         adev->pm.dpm.state = dpm_state;
1758         mutex_unlock(&adev->pm.mutex);
1759
1760         amdgpu_pm_compute_clocks(adev);
1761 }
1762
1763 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1764                                                      enum amd_pm_state_type dpm_state)
1765 {
1766         int i;
1767         struct amdgpu_ps *ps;
1768         u32 ui_class;
1769         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1770                 true : false;
1771
1772         /* check if the vblank period is too short to adjust the mclk */
1773         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1774                 if (amdgpu_dpm_vblank_too_short(adev))
1775                         single_display = false;
1776         }
1777
1778         /* certain older asics have a separare 3D performance state,
1779          * so try that first if the user selected performance
1780          */
1781         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1782                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1783         /* balanced states don't exist at the moment */
1784         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1785                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1786
1787 restart_search:
1788         /* Pick the best power state based on current conditions */
1789         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1790                 ps = &adev->pm.dpm.ps[i];
1791                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1792                 switch (dpm_state) {
1793                 /* user states */
1794                 case POWER_STATE_TYPE_BATTERY:
1795                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1796                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1797                                         if (single_display)
1798                                                 return ps;
1799                                 } else
1800                                         return ps;
1801                         }
1802                         break;
1803                 case POWER_STATE_TYPE_BALANCED:
1804                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1805                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1806                                         if (single_display)
1807                                                 return ps;
1808                                 } else
1809                                         return ps;
1810                         }
1811                         break;
1812                 case POWER_STATE_TYPE_PERFORMANCE:
1813                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1814                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1815                                         if (single_display)
1816                                                 return ps;
1817                                 } else
1818                                         return ps;
1819                         }
1820                         break;
1821                 /* internal states */
1822                 case POWER_STATE_TYPE_INTERNAL_UVD:
1823                         if (adev->pm.dpm.uvd_ps)
1824                                 return adev->pm.dpm.uvd_ps;
1825                         else
1826                                 break;
1827                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1828                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1829                                 return ps;
1830                         break;
1831                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1832                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1833                                 return ps;
1834                         break;
1835                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1836                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1837                                 return ps;
1838                         break;
1839                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1840                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1841                                 return ps;
1842                         break;
1843                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1844                         return adev->pm.dpm.boot_ps;
1845                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1846                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1847                                 return ps;
1848                         break;
1849                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1850                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1851                                 return ps;
1852                         break;
1853                 case POWER_STATE_TYPE_INTERNAL_ULV:
1854                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1855                                 return ps;
1856                         break;
1857                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1858                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1859                                 return ps;
1860                         break;
1861                 default:
1862                         break;
1863                 }
1864         }
1865         /* use a fallback state if we didn't match */
1866         switch (dpm_state) {
1867         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1868                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1869                 goto restart_search;
1870         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1871         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1872         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1873                 if (adev->pm.dpm.uvd_ps) {
1874                         return adev->pm.dpm.uvd_ps;
1875                 } else {
1876                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1877                         goto restart_search;
1878                 }
1879         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1880                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1881                 goto restart_search;
1882         case POWER_STATE_TYPE_INTERNAL_ACPI:
1883                 dpm_state = POWER_STATE_TYPE_BATTERY;
1884                 goto restart_search;
1885         case POWER_STATE_TYPE_BATTERY:
1886         case POWER_STATE_TYPE_BALANCED:
1887         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1888                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1889                 goto restart_search;
1890         default:
1891                 break;
1892         }
1893
1894         return NULL;
1895 }
1896
1897 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1898 {
1899         struct amdgpu_ps *ps;
1900         enum amd_pm_state_type dpm_state;
1901         int ret;
1902         bool equal = false;
1903
1904         /* if dpm init failed */
1905         if (!adev->pm.dpm_enabled)
1906                 return;
1907
1908         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1909                 /* add other state override checks here */
1910                 if ((!adev->pm.dpm.thermal_active) &&
1911                     (!adev->pm.dpm.uvd_active))
1912                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1913         }
1914         dpm_state = adev->pm.dpm.state;
1915
1916         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1917         if (ps)
1918                 adev->pm.dpm.requested_ps = ps;
1919         else
1920                 return;
1921
1922         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1923                 printk("switching from power state:\n");
1924                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1925                 printk("switching to power state:\n");
1926                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1927         }
1928
1929         /* update whether vce is active */
1930         ps->vce_active = adev->pm.dpm.vce_active;
1931         if (adev->powerplay.pp_funcs->display_configuration_changed)
1932                 amdgpu_dpm_display_configuration_changed(adev);
1933
1934         ret = amdgpu_dpm_pre_set_power_state(adev);
1935         if (ret)
1936                 return;
1937
1938         if (adev->powerplay.pp_funcs->check_state_equal) {
1939                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1940                         equal = false;
1941         }
1942
1943         if (equal)
1944                 return;
1945
1946         amdgpu_dpm_set_power_state(adev);
1947         amdgpu_dpm_post_set_power_state(adev);
1948
1949         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1950         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1951
1952         if (adev->powerplay.pp_funcs->force_performance_level) {
1953                 if (adev->pm.dpm.thermal_active) {
1954                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1955                         /* force low perf level for thermal */
1956                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1957                         /* save the user's level */
1958                         adev->pm.dpm.forced_level = level;
1959                 } else {
1960                         /* otherwise, user selected level */
1961                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1962                 }
1963         }
1964 }
1965
1966 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1967 {
1968         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
1969                 /* enable/disable UVD */
1970                 mutex_lock(&adev->pm.mutex);
1971                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
1972                 mutex_unlock(&adev->pm.mutex);
1973         }
1974         /* enable/disable Low Memory PState for UVD (4k videos) */
1975         if (adev->asic_type == CHIP_STONEY &&
1976                 adev->uvd.decode_image_width >= WIDTH_4K) {
1977                 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
1978
1979                 if (hwmgr && hwmgr->hwmgr_func &&
1980                     hwmgr->hwmgr_func->update_nbdpm_pstate)
1981                         hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
1982                                                                !enable,
1983                                                                true);
1984         }
1985 }
1986
1987 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1988 {
1989         if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
1990                 /* enable/disable VCE */
1991                 mutex_lock(&adev->pm.mutex);
1992                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
1993                 mutex_unlock(&adev->pm.mutex);
1994         }
1995 }
1996
1997 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1998 {
1999         int i;
2000
2001         if (adev->powerplay.pp_funcs->print_power_state == NULL)
2002                 return;
2003
2004         for (i = 0; i < adev->pm.dpm.num_ps; i++)
2005                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
2006
2007 }
2008
2009 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
2010 {
2011         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2012         int ret;
2013
2014         if (adev->pm.sysfs_initialized)
2015                 return 0;
2016
2017         if (adev->pm.dpm_enabled == 0)
2018                 return 0;
2019
2020         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
2021                                                                    DRIVER_NAME, adev,
2022                                                                    hwmon_groups);
2023         if (IS_ERR(adev->pm.int_hwmon_dev)) {
2024                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
2025                 dev_err(adev->dev,
2026                         "Unable to register hwmon device: %d\n", ret);
2027                 return ret;
2028         }
2029
2030         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
2031         if (ret) {
2032                 DRM_ERROR("failed to create device file for dpm state\n");
2033                 return ret;
2034         }
2035         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2036         if (ret) {
2037                 DRM_ERROR("failed to create device file for dpm state\n");
2038                 return ret;
2039         }
2040
2041
2042         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
2043         if (ret) {
2044                 DRM_ERROR("failed to create device file pp_num_states\n");
2045                 return ret;
2046         }
2047         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
2048         if (ret) {
2049                 DRM_ERROR("failed to create device file pp_cur_state\n");
2050                 return ret;
2051         }
2052         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
2053         if (ret) {
2054                 DRM_ERROR("failed to create device file pp_force_state\n");
2055                 return ret;
2056         }
2057         ret = device_create_file(adev->dev, &dev_attr_pp_table);
2058         if (ret) {
2059                 DRM_ERROR("failed to create device file pp_table\n");
2060                 return ret;
2061         }
2062
2063         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
2064         if (ret) {
2065                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
2066                 return ret;
2067         }
2068         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
2069         if (ret) {
2070                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
2071                 return ret;
2072         }
2073         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
2074         if (ret) {
2075                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
2076                 return ret;
2077         }
2078         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
2079         if (ret) {
2080                 DRM_ERROR("failed to create device file pp_sclk_od\n");
2081                 return ret;
2082         }
2083         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
2084         if (ret) {
2085                 DRM_ERROR("failed to create device file pp_mclk_od\n");
2086                 return ret;
2087         }
2088         ret = device_create_file(adev->dev,
2089                         &dev_attr_pp_power_profile_mode);
2090         if (ret) {
2091                 DRM_ERROR("failed to create device file "
2092                                 "pp_power_profile_mode\n");
2093                 return ret;
2094         }
2095         if (hwmgr->od_enabled) {
2096                 ret = device_create_file(adev->dev,
2097                                 &dev_attr_pp_od_clk_voltage);
2098                 if (ret) {
2099                         DRM_ERROR("failed to create device file "
2100                                         "pp_od_clk_voltage\n");
2101                         return ret;
2102                 }
2103         }
2104         ret = device_create_file(adev->dev,
2105                         &dev_attr_gpu_busy_percent);
2106         if (ret) {
2107                 DRM_ERROR("failed to create device file "
2108                                 "gpu_busy_level\n");
2109                 return ret;
2110         }
2111         ret = amdgpu_debugfs_pm_init(adev);
2112         if (ret) {
2113                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
2114                 return ret;
2115         }
2116
2117         adev->pm.sysfs_initialized = true;
2118
2119         return 0;
2120 }
2121
2122 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
2123 {
2124         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2125
2126         if (adev->pm.dpm_enabled == 0)
2127                 return;
2128
2129         if (adev->pm.int_hwmon_dev)
2130                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
2131         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
2132         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
2133
2134         device_remove_file(adev->dev, &dev_attr_pp_num_states);
2135         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
2136         device_remove_file(adev->dev, &dev_attr_pp_force_state);
2137         device_remove_file(adev->dev, &dev_attr_pp_table);
2138
2139         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
2140         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
2141         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
2142         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
2143         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
2144         device_remove_file(adev->dev,
2145                         &dev_attr_pp_power_profile_mode);
2146         if (hwmgr->od_enabled)
2147                 device_remove_file(adev->dev,
2148                                 &dev_attr_pp_od_clk_voltage);
2149         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
2150 }
2151
2152 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
2153 {
2154         int i = 0;
2155
2156         if (!adev->pm.dpm_enabled)
2157                 return;
2158
2159         if (adev->mode_info.num_crtc)
2160                 amdgpu_display_bandwidth_update(adev);
2161
2162         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2163                 struct amdgpu_ring *ring = adev->rings[i];
2164                 if (ring && ring->sched.ready)
2165                         amdgpu_fence_wait_empty(ring);
2166         }
2167
2168         if (adev->powerplay.pp_funcs->dispatch_tasks) {
2169                 if (!amdgpu_device_has_dc_support(adev)) {
2170                         mutex_lock(&adev->pm.mutex);
2171                         amdgpu_dpm_get_active_displays(adev);
2172                         adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
2173                         adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
2174                         adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
2175                         /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
2176                         if (adev->pm.pm_display_cfg.vrefresh > 120)
2177                                 adev->pm.pm_display_cfg.min_vblank_time = 0;
2178                         if (adev->powerplay.pp_funcs->display_configuration_change)
2179                                 adev->powerplay.pp_funcs->display_configuration_change(
2180                                                                 adev->powerplay.pp_handle,
2181                                                                 &adev->pm.pm_display_cfg);
2182                         mutex_unlock(&adev->pm.mutex);
2183                 }
2184                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
2185         } else {
2186                 mutex_lock(&adev->pm.mutex);
2187                 amdgpu_dpm_get_active_displays(adev);
2188                 amdgpu_dpm_change_power_state_locked(adev);
2189                 mutex_unlock(&adev->pm.mutex);
2190         }
2191 }
2192
2193 /*
2194  * Debugfs info
2195  */
2196 #if defined(CONFIG_DEBUG_FS)
2197
2198 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
2199 {
2200         uint32_t value;
2201         uint64_t value64;
2202         uint32_t query = 0;
2203         int size;
2204
2205         /* sanity check PP is enabled */
2206         if (!(adev->powerplay.pp_funcs &&
2207               adev->powerplay.pp_funcs->read_sensor))
2208               return -EINVAL;
2209
2210         /* GPU Clocks */
2211         size = sizeof(value);
2212         seq_printf(m, "GFX Clocks and Power:\n");
2213         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
2214                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
2215         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
2216                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
2217         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
2218                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
2219         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
2220                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
2221         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
2222                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
2223         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
2224                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
2225         size = sizeof(uint32_t);
2226         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
2227                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
2228         size = sizeof(value);
2229         seq_printf(m, "\n");
2230
2231         /* GPU Temp */
2232         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
2233                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
2234
2235         /* GPU Load */
2236         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
2237                 seq_printf(m, "GPU Load: %u %%\n", value);
2238         seq_printf(m, "\n");
2239
2240         /* SMC feature mask */
2241         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
2242                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
2243
2244         /* UVD clocks */
2245         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
2246                 if (!value) {
2247                         seq_printf(m, "UVD: Disabled\n");
2248                 } else {
2249                         seq_printf(m, "UVD: Enabled\n");
2250                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
2251                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
2252                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
2253                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
2254                 }
2255         }
2256         seq_printf(m, "\n");
2257
2258         /* VCE clocks */
2259         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
2260                 if (!value) {
2261                         seq_printf(m, "VCE: Disabled\n");
2262                 } else {
2263                         seq_printf(m, "VCE: Enabled\n");
2264                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
2265                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
2266                 }
2267         }
2268
2269         return 0;
2270 }
2271
2272 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
2273 {
2274         int i;
2275
2276         for (i = 0; clocks[i].flag; i++)
2277                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
2278                            (flags & clocks[i].flag) ? "On" : "Off");
2279 }
2280
2281 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
2282 {
2283         struct drm_info_node *node = (struct drm_info_node *) m->private;
2284         struct drm_device *dev = node->minor->dev;
2285         struct amdgpu_device *adev = dev->dev_private;
2286         struct drm_device *ddev = adev->ddev;
2287         u32 flags = 0;
2288
2289         amdgpu_device_ip_get_clockgating_state(adev, &flags);
2290         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
2291         amdgpu_parse_cg_state(m, flags);
2292         seq_printf(m, "\n");
2293
2294         if (!adev->pm.dpm_enabled) {
2295                 seq_printf(m, "dpm not enabled\n");
2296                 return 0;
2297         }
2298         if  ((adev->flags & AMD_IS_PX) &&
2299              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
2300                 seq_printf(m, "PX asic powered off\n");
2301         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
2302                 mutex_lock(&adev->pm.mutex);
2303                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
2304                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
2305                 else
2306                         seq_printf(m, "Debugfs support not implemented for this asic\n");
2307                 mutex_unlock(&adev->pm.mutex);
2308         } else {
2309                 return amdgpu_debugfs_pm_info_pp(m, adev);
2310         }
2311
2312         return 0;
2313 }
2314
2315 static const struct drm_info_list amdgpu_pm_info_list[] = {
2316         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
2317 };
2318 #endif
2319
2320 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2321 {
2322 #if defined(CONFIG_DEBUG_FS)
2323         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2324 #else
2325         return 0;
2326 #endif
2327 }