drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/kthread.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_trace.h"
  30
  31 static void amdgpu_job_timedout(struct amd_sched_job *s_job)
  32 {
  33         struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
  34
  35         DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
  36                   job->base.sched->name,
  37                   atomic_read(&job->ring->fence_drv.last_seq),
  38                   job->ring->fence_drv.sync_seq);
  39
  40         if (amdgpu_sriov_vf(job->adev))
  41                 amdgpu_sriov_gpu_reset(job->adev, job);
  42         else
  43                 amdgpu_gpu_reset(job->adev);
  44 }
  45
  46 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  47                      struct amdgpu_job **job, struct amdgpu_vm *vm)
  48 {
  49         size_t size = sizeof(struct amdgpu_job);
  50
  51         if (num_ibs == 0)
  52                 return -EINVAL;
  53
  54         size += sizeof(struct amdgpu_ib) * num_ibs;
  55
  56         *job = kzalloc(size, GFP_KERNEL);
  57         if (!*job)
  58                 return -ENOMEM;
  59
  60         (*job)->adev = adev;
  61         (*job)->vm = vm;
  62         (*job)->ibs = (void *)&(*job)[1];
  63         (*job)->num_ibs = num_ibs;
  64
  65         amdgpu_sync_create(&(*job)->sync);
  66         amdgpu_sync_create(&(*job)->dep_sync);
  67         amdgpu_sync_create(&(*job)->sched_sync);
  68
  69         return 0;
  70 }
  71
  72 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  73                              struct amdgpu_job **job)
  74 {
  75         int r;
  76
  77         r = amdgpu_job_alloc(adev, 1, job, NULL);
  78         if (r)
  79                 return r;
  80
  81         r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
  82         if (r)
  83                 kfree(*job);
  84
  85         return r;
  86 }
  87
  88 void amdgpu_job_free_resources(struct amdgpu_job *job)
  89 {
  90         struct dma_fence *f;
  91         unsigned i;
  92
  93         /* use sched fence if available */
  94         f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
  95
  96         for (i = 0; i < job->num_ibs; ++i)
  97                 amdgpu_ib_free(job->adev, &job->ibs[i], f);
  98 }
  99
 100 static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
 101 {
 102         struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
 103
 104         dma_fence_put(job->fence);
 105         amdgpu_sync_free(&job->sync);
 106         amdgpu_sync_free(&job->dep_sync);
 107         amdgpu_sync_free(&job->sched_sync);
 108         kfree(job);
 109 }
 110
 111 void amdgpu_job_free(struct amdgpu_job *job)
 112 {
 113         amdgpu_job_free_resources(job);
 114
 115         dma_fence_put(job->fence);
 116         amdgpu_sync_free(&job->sync);
 117         amdgpu_sync_free(&job->dep_sync);
 118         amdgpu_sync_free(&job->sched_sync);
 119         kfree(job);
 120 }
 121
 122 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
 123                       struct amd_sched_entity *entity, void *owner,
 124                       struct dma_fence **f)
 125 {
 126         int r;
 127         job->ring = ring;
 128
 129         if (!f)
 130                 return -EINVAL;
 131
 132         r = amd_sched_job_init(&job->base, &ring->sched, entity, owner);
 133         if (r)
 134                 return r;
 135
 136         job->owner = owner;
 137         job->fence_ctx = entity->fence_context;
 138         *f = dma_fence_get(&job->base.s_fence->finished);
 139         amdgpu_job_free_resources(job);
 140         amd_sched_entity_push_job(&job->base);
 141
 142         return 0;
 143 }
 144
 145 static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
 146 {
 147         struct amdgpu_job *job = to_amdgpu_job(sched_job);
 148         struct amdgpu_vm *vm = job->vm;
 149
 150         struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync);
 151         int r;
 152
 153         if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) {
 154                 r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence);
 155                 if (r)
 156                         DRM_ERROR("Error adding fence to sync (%d)\n", r);
 157         }
 158         if (!fence)
 159                 fence = amdgpu_sync_get_fence(&job->sync);
 160         while (fence == NULL && vm && !job->vm_id) {
 161                 struct amdgpu_ring *ring = job->ring;
 162
 163                 r = amdgpu_vm_grab_id(vm, ring, &job->sync,
 164                                       &job->base.s_fence->finished,
 165                                       job);
 166                 if (r)
 167                         DRM_ERROR("Error getting VM ID (%d)\n", r);
 168
 169                 fence = amdgpu_sync_get_fence(&job->sync);
 170         }
 171
 172         return fence;
 173 }
 174
 175 static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
 176 {
 177         struct dma_fence *fence = NULL;
 178         struct amdgpu_job *job;
 179         struct amdgpu_fpriv *fpriv = NULL;
 180         int r;
 181
 182         if (!sched_job) {
 183                 DRM_ERROR("job is null\n");
 184                 return NULL;
 185         }
 186         job = to_amdgpu_job(sched_job);
 187
 188         BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
 189
 190         trace_amdgpu_sched_run_job(job);
 191         if (job->vm)
 192                 fpriv = container_of(job->vm, struct amdgpu_fpriv, vm);
 193         /* skip ib schedule when vram is lost */
 194         if (fpriv && amdgpu_kms_vram_lost(job->adev, fpriv))
 195                 DRM_ERROR("Skip scheduling IBs!\n");
 196         else {
 197                 r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence);
 198                 if (r)
 199                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
 200         }
 201         /* if gpu reset, hw fence will be replaced here */
 202         dma_fence_put(job->fence);
 203         job->fence = dma_fence_get(fence);
 204         amdgpu_job_free_resources(job);
 205         return fence;
 206 }
 207
 208 const struct amd_sched_backend_ops amdgpu_sched_ops = {
 209         .dependency = amdgpu_job_dependency,
 210         .run_job = amdgpu_job_run,
 211         .timedout_job = amdgpu_job_timedout,
 212         .free_job = amdgpu_job_free_cb
 213 };