2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/irq.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_ih.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_trace.h"
38 #include <linux/pm_runtime.h>
40 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
43 * Handle hotplug events outside the interrupt handler proper.
46 * amdgpu_hotplug_work_func - display hotplug work handler
50 * This is the hot plug event work handler (all asics).
51 * The work gets scheduled from the irq handler if there
52 * was a hot plug interrupt. It walks the connector table
53 * and calls the hotplug handler for each one, then sends
54 * a drm hotplug event to alert userspace.
56 static void amdgpu_hotplug_work_func(struct work_struct *work)
58 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
60 struct drm_device *dev = adev->ddev;
61 struct drm_mode_config *mode_config = &dev->mode_config;
62 struct drm_connector *connector;
64 mutex_lock(&mode_config->mutex);
65 list_for_each_entry(connector, &mode_config->connector_list, head)
66 amdgpu_connector_hotplug(connector);
67 mutex_unlock(&mode_config->mutex);
68 /* Just fire off a uevent and let userspace tell us what to do */
69 drm_helper_hpd_irq_event(dev);
73 * amdgpu_irq_reset_work_func - execute gpu reset
77 * Execute scheduled gpu reset (cayman+).
78 * This function is called when the irq handler
79 * thinks we need a gpu reset.
81 static void amdgpu_irq_reset_work_func(struct work_struct *work)
83 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
86 if (!amdgpu_sriov_vf(adev))
87 amdgpu_gpu_reset(adev);
90 /* Disable *all* interrupts */
91 static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
93 unsigned long irqflags;
97 spin_lock_irqsave(&adev->irq.lock, irqflags);
98 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
99 if (!adev->irq.client[i].sources)
102 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
103 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
105 if (!src || !src->funcs->set || !src->num_types)
108 for (k = 0; k < src->num_types; ++k) {
109 atomic_set(&src->enabled_types[k], 0);
110 r = src->funcs->set(adev, src, k,
111 AMDGPU_IRQ_STATE_DISABLE);
113 DRM_ERROR("error disabling interrupt (%d)\n",
118 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
122 * amdgpu_irq_preinstall - drm irq preinstall callback
124 * @dev: drm dev pointer
126 * Gets the hw ready to enable irqs (all asics).
127 * This function disables all interrupt sources on the GPU.
129 void amdgpu_irq_preinstall(struct drm_device *dev)
131 struct amdgpu_device *adev = dev->dev_private;
133 /* Disable *all* interrupts */
134 amdgpu_irq_disable_all(adev);
136 amdgpu_ih_process(adev);
140 * amdgpu_irq_postinstall - drm irq preinstall callback
142 * @dev: drm dev pointer
144 * Handles stuff to be done after enabling irqs (all asics).
145 * Returns 0 on success.
147 int amdgpu_irq_postinstall(struct drm_device *dev)
149 dev->max_vblank_count = 0x00ffffff;
154 * amdgpu_irq_uninstall - drm irq uninstall callback
156 * @dev: drm dev pointer
158 * This function disables all interrupt sources on the GPU (all asics).
160 void amdgpu_irq_uninstall(struct drm_device *dev)
162 struct amdgpu_device *adev = dev->dev_private;
167 amdgpu_irq_disable_all(adev);
171 * amdgpu_irq_handler - irq handler
173 * @int irq, void *arg: args
175 * This is the irq handler for the amdgpu driver (all asics).
177 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
179 struct drm_device *dev = (struct drm_device *) arg;
180 struct amdgpu_device *adev = dev->dev_private;
183 ret = amdgpu_ih_process(adev);
184 if (ret == IRQ_HANDLED)
185 pm_runtime_mark_last_busy(dev->dev);
190 * amdgpu_msi_ok - asic specific msi checks
192 * @adev: amdgpu device pointer
194 * Handles asic specific MSI checks to determine if
195 * MSIs should be enabled on a particular chip (all asics).
196 * Returns true if MSIs should be enabled, false if MSIs
197 * should not be enabled.
199 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
204 else if (amdgpu_msi == 0)
211 * amdgpu_irq_init - init driver interrupt info
213 * @adev: amdgpu device pointer
215 * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
216 * Returns 0 for success, error for failure.
218 int amdgpu_irq_init(struct amdgpu_device *adev)
222 spin_lock_init(&adev->irq.lock);
224 /* Disable vblank irqs aggressively for power-saving */
225 adev->ddev->vblank_disable_immediate = true;
227 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
233 adev->irq.msi_enabled = false;
235 if (amdgpu_msi_ok(adev)) {
236 int ret = pci_enable_msi(adev->pdev);
238 adev->irq.msi_enabled = true;
239 dev_info(adev->dev, "amdgpu: using MSI.\n");
243 INIT_WORK(&adev->hotplug_work, amdgpu_hotplug_work_func);
244 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
246 adev->irq.installed = true;
247 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
249 adev->irq.installed = false;
250 flush_work(&adev->hotplug_work);
251 cancel_work_sync(&adev->reset_work);
255 DRM_INFO("amdgpu: irq initialized.\n");
260 * amdgpu_irq_fini - tear down driver interrupt info
262 * @adev: amdgpu device pointer
264 * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
266 void amdgpu_irq_fini(struct amdgpu_device *adev)
270 if (adev->irq.installed) {
271 drm_irq_uninstall(adev->ddev);
272 adev->irq.installed = false;
273 if (adev->irq.msi_enabled)
274 pci_disable_msi(adev->pdev);
275 flush_work(&adev->hotplug_work);
276 cancel_work_sync(&adev->reset_work);
279 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
280 if (!adev->irq.client[i].sources)
283 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
284 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
289 kfree(src->enabled_types);
290 src->enabled_types = NULL;
294 adev->irq.client[i].sources[j] = NULL;
297 kfree(adev->irq.client[i].sources);
302 * amdgpu_irq_add_id - register irq source
304 * @adev: amdgpu device pointer
305 * @src_id: source id for this source
306 * @source: irq source
309 int amdgpu_irq_add_id(struct amdgpu_device *adev,
310 unsigned client_id, unsigned src_id,
311 struct amdgpu_irq_src *source)
313 if (client_id >= AMDGPU_IH_CLIENTID_MAX)
316 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
322 if (!adev->irq.client[client_id].sources) {
323 adev->irq.client[client_id].sources =
324 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
325 sizeof(struct amdgpu_irq_src *),
327 if (!adev->irq.client[client_id].sources)
331 if (adev->irq.client[client_id].sources[src_id] != NULL)
334 if (source->num_types && !source->enabled_types) {
337 types = kcalloc(source->num_types, sizeof(atomic_t),
342 source->enabled_types = types;
345 adev->irq.client[client_id].sources[src_id] = source;
350 * amdgpu_irq_dispatch - dispatch irq to IP blocks
352 * @adev: amdgpu device pointer
353 * @entry: interrupt vector
355 * Dispatches the irq to the different IP blocks
357 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
358 struct amdgpu_iv_entry *entry)
360 unsigned client_id = entry->client_id;
361 unsigned src_id = entry->src_id;
362 struct amdgpu_irq_src *src;
365 trace_amdgpu_iv(entry);
367 if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
368 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
372 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
373 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
377 if (adev->irq.virq[src_id]) {
378 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
380 if (!adev->irq.client[client_id].sources) {
381 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
386 src = adev->irq.client[client_id].sources[src_id];
388 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
392 r = src->funcs->process(adev, src, entry);
394 DRM_ERROR("error processing interrupt (%d)\n", r);
399 * amdgpu_irq_update - update hw interrupt state
401 * @adev: amdgpu device pointer
402 * @src: interrupt src you want to enable
403 * @type: type of interrupt you want to update
405 * Updates the interrupt state for a specific src (all asics).
407 int amdgpu_irq_update(struct amdgpu_device *adev,
408 struct amdgpu_irq_src *src, unsigned type)
410 unsigned long irqflags;
411 enum amdgpu_interrupt_state state;
414 spin_lock_irqsave(&adev->irq.lock, irqflags);
416 /* we need to determine after taking the lock, otherwise
417 we might disable just enabled interrupts again */
418 if (amdgpu_irq_enabled(adev, src, type))
419 state = AMDGPU_IRQ_STATE_ENABLE;
421 state = AMDGPU_IRQ_STATE_DISABLE;
423 r = src->funcs->set(adev, src, type, state);
424 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
428 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
432 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
433 if (!adev->irq.client[i].sources)
436 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
437 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
441 for (k = 0; k < src->num_types; k++)
442 amdgpu_irq_update(adev, src, k);
448 * amdgpu_irq_get - enable interrupt
450 * @adev: amdgpu device pointer
451 * @src: interrupt src you want to enable
452 * @type: type of interrupt you want to enable
454 * Enables the interrupt type for a specific src (all asics).
456 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
459 if (!adev->ddev->irq_enabled)
462 if (type >= src->num_types)
465 if (!src->enabled_types || !src->funcs->set)
468 if (atomic_inc_return(&src->enabled_types[type]) == 1)
469 return amdgpu_irq_update(adev, src, type);
475 * amdgpu_irq_put - disable interrupt
477 * @adev: amdgpu device pointer
478 * @src: interrupt src you want to disable
479 * @type: type of interrupt you want to disable
481 * Disables the interrupt type for a specific src (all asics).
483 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
486 if (!adev->ddev->irq_enabled)
489 if (type >= src->num_types)
492 if (!src->enabled_types || !src->funcs->set)
495 if (atomic_dec_and_test(&src->enabled_types[type]))
496 return amdgpu_irq_update(adev, src, type);
502 * amdgpu_irq_enabled - test if irq is enabled or not
504 * @adev: amdgpu device pointer
505 * @idx: interrupt src you want to test
507 * Tests if the given interrupt source is enabled or not
509 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
512 if (!adev->ddev->irq_enabled)
515 if (type >= src->num_types)
518 if (!src->enabled_types || !src->funcs->set)
521 return !!atomic_read(&src->enabled_types[type]);
525 static void amdgpu_irq_mask(struct irq_data *irqd)
530 static void amdgpu_irq_unmask(struct irq_data *irqd)
535 static struct irq_chip amdgpu_irq_chip = {
537 .irq_mask = amdgpu_irq_mask,
538 .irq_unmask = amdgpu_irq_unmask,
541 static int amdgpu_irqdomain_map(struct irq_domain *d,
542 unsigned int irq, irq_hw_number_t hwirq)
544 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
547 irq_set_chip_and_handler(irq,
548 &amdgpu_irq_chip, handle_simple_irq);
552 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
553 .map = amdgpu_irqdomain_map,
557 * amdgpu_irq_add_domain - create a linear irq domain
559 * @adev: amdgpu device pointer
561 * Create an irq domain for GPU interrupt sources
562 * that may be driven by another driver (e.g., ACP).
564 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
566 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
567 &amdgpu_hw_irqdomain_ops, adev);
568 if (!adev->irq.domain) {
569 DRM_ERROR("GPU irq add domain failed\n");
577 * amdgpu_irq_remove_domain - remove the irq domain
579 * @adev: amdgpu device pointer
581 * Remove the irq domain for GPU interrupt sources
582 * that may be driven by another driver (e.g., ACP).
584 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
586 if (adev->irq.domain) {
587 irq_domain_remove(adev->irq.domain);
588 adev->irq.domain = NULL;
593 * amdgpu_irq_create_mapping - create a mapping between a domain irq and a
596 * @adev: amdgpu device pointer
597 * @src_id: IH source id
599 * Create a mapping between a domain irq (GPU IH src id) and a Linux irq
600 * Use this for components that generate a GPU interrupt, but are driven
601 * by a different driver (e.g., ACP).
602 * Returns the Linux irq.
604 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
606 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
608 return adev->irq.virq[src_id];