2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
39 if (robj->gem_base.import_attach)
40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
41 amdgpu_mn_unregister(robj);
42 amdgpu_bo_unref(&robj);
46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47 int alignment, u32 initial_domain,
48 u64 flags, bool kernel,
49 struct reservation_object *resv,
50 struct drm_gem_object **obj)
56 /* At least align on page size */
57 if (alignment < PAGE_SIZE) {
58 alignment = PAGE_SIZE;
62 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
63 flags, NULL, resv, 0, &bo);
65 if (r != -ERESTARTSYS) {
66 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
67 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
70 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
71 size, initial_domain, alignment, r);
80 void amdgpu_gem_force_release(struct amdgpu_device *adev)
82 struct drm_device *ddev = adev->ddev;
83 struct drm_file *file;
85 mutex_lock(&ddev->filelist_mutex);
87 list_for_each_entry(file, &ddev->filelist, lhead) {
88 struct drm_gem_object *gobj;
91 WARN_ONCE(1, "Still active user space clients!\n");
92 spin_lock(&file->table_lock);
93 idr_for_each_entry(&file->object_idr, gobj, handle) {
94 WARN_ONCE(1, "And also active allocations!\n");
95 drm_gem_object_put_unlocked(gobj);
97 idr_destroy(&file->object_idr);
98 spin_unlock(&file->table_lock);
101 mutex_unlock(&ddev->filelist_mutex);
105 * Call from drm_gem_handle_create which appear in both new and open ioctl
108 int amdgpu_gem_object_open(struct drm_gem_object *obj,
109 struct drm_file *file_priv)
111 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
112 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
113 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
114 struct amdgpu_vm *vm = &fpriv->vm;
115 struct amdgpu_bo_va *bo_va;
116 struct mm_struct *mm;
119 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
120 if (mm && mm != current->mm)
123 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
124 abo->tbo.resv != vm->root.base.bo->tbo.resv)
127 r = amdgpu_bo_reserve(abo, false);
131 bo_va = amdgpu_vm_bo_find(vm, abo);
133 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
137 amdgpu_bo_unreserve(abo);
141 void amdgpu_gem_object_close(struct drm_gem_object *obj,
142 struct drm_file *file_priv)
144 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
145 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
146 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
147 struct amdgpu_vm *vm = &fpriv->vm;
149 struct amdgpu_bo_list_entry vm_pd;
150 struct list_head list, duplicates;
151 struct ttm_validate_buffer tv;
152 struct ww_acquire_ctx ticket;
153 struct amdgpu_bo_va *bo_va;
156 INIT_LIST_HEAD(&list);
157 INIT_LIST_HEAD(&duplicates);
161 list_add(&tv.head, &list);
163 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
165 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
167 dev_err(adev->dev, "leaking bo va because "
168 "we fail to reserve bo (%d)\n", r);
171 bo_va = amdgpu_vm_bo_find(vm, bo);
172 if (bo_va && --bo_va->ref_count == 0) {
173 amdgpu_vm_bo_rmv(adev, bo_va);
175 if (amdgpu_vm_ready(vm)) {
176 struct dma_fence *fence = NULL;
178 r = amdgpu_vm_clear_freed(adev, vm, &fence);
180 dev_err(adev->dev, "failed to clear page "
181 "tables on GEM object close (%d)\n", r);
185 amdgpu_bo_fence(bo, fence, true);
186 dma_fence_put(fence);
190 ttm_eu_backoff_reservation(&ticket, &list);
196 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
197 struct drm_file *filp)
199 struct amdgpu_device *adev = dev->dev_private;
200 struct amdgpu_fpriv *fpriv = filp->driver_priv;
201 struct amdgpu_vm *vm = &fpriv->vm;
202 union drm_amdgpu_gem_create *args = data;
203 uint64_t flags = args->in.domain_flags;
204 uint64_t size = args->in.bo_size;
205 struct reservation_object *resv = NULL;
206 struct drm_gem_object *gobj;
210 /* reject invalid gem flags */
211 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
212 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
213 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
214 AMDGPU_GEM_CREATE_VRAM_CLEARED |
215 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
216 AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
220 /* reject invalid gem domains */
221 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
222 AMDGPU_GEM_DOMAIN_GTT |
223 AMDGPU_GEM_DOMAIN_VRAM |
224 AMDGPU_GEM_DOMAIN_GDS |
225 AMDGPU_GEM_DOMAIN_GWS |
226 AMDGPU_GEM_DOMAIN_OA))
229 /* create a gem object to contain this object in */
230 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
231 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
232 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
233 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
234 size = size << AMDGPU_GDS_SHIFT;
235 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
236 size = size << AMDGPU_GWS_SHIFT;
237 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
238 size = size << AMDGPU_OA_SHIFT;
242 size = roundup(size, PAGE_SIZE);
244 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
245 r = amdgpu_bo_reserve(vm->root.base.bo, false);
249 resv = vm->root.base.bo->tbo.resv;
252 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
253 (u32)(0xffffffff & args->in.domains),
254 flags, false, resv, &gobj);
255 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
257 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
259 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
261 amdgpu_bo_unreserve(vm->root.base.bo);
266 r = drm_gem_handle_create(filp, gobj, &handle);
267 /* drop reference from allocate - handle holds it now */
268 drm_gem_object_put_unlocked(gobj);
272 memset(args, 0, sizeof(*args));
273 args->out.handle = handle;
277 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
278 struct drm_file *filp)
280 struct amdgpu_device *adev = dev->dev_private;
281 struct drm_amdgpu_gem_userptr *args = data;
282 struct drm_gem_object *gobj;
283 struct amdgpu_bo *bo;
287 if (offset_in_page(args->addr | args->size))
290 /* reject unknown flag values */
291 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
292 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
293 AMDGPU_GEM_USERPTR_REGISTER))
296 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
297 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
299 /* if we want to write to it we must install a MMU notifier */
303 /* create a gem object to contain this object in */
304 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
309 bo = gem_to_amdgpu_bo(gobj);
310 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
311 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
312 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
316 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
317 r = amdgpu_mn_register(bo, args->addr);
322 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
323 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
326 goto unlock_mmap_sem;
328 r = amdgpu_bo_reserve(bo, true);
332 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
333 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
334 amdgpu_bo_unreserve(bo);
339 r = drm_gem_handle_create(filp, gobj, &handle);
340 /* drop reference from allocate - handle holds it now */
341 drm_gem_object_put_unlocked(gobj);
345 args->handle = handle;
349 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
352 up_read(¤t->mm->mmap_sem);
355 drm_gem_object_put_unlocked(gobj);
360 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
361 struct drm_device *dev,
362 uint32_t handle, uint64_t *offset_p)
364 struct drm_gem_object *gobj;
365 struct amdgpu_bo *robj;
367 gobj = drm_gem_object_lookup(filp, handle);
371 robj = gem_to_amdgpu_bo(gobj);
372 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
373 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
374 drm_gem_object_put_unlocked(gobj);
377 *offset_p = amdgpu_bo_mmap_offset(robj);
378 drm_gem_object_put_unlocked(gobj);
382 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
383 struct drm_file *filp)
385 union drm_amdgpu_gem_mmap *args = data;
386 uint32_t handle = args->in.handle;
387 memset(args, 0, sizeof(*args));
388 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
392 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
394 * @timeout_ns: timeout in ns
396 * Calculate the timeout in jiffies from an absolute timeout in ns.
398 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
400 unsigned long timeout_jiffies;
403 /* clamp timeout if it's to large */
404 if (((int64_t)timeout_ns) < 0)
405 return MAX_SCHEDULE_TIMEOUT;
407 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
408 if (ktime_to_ns(timeout) < 0)
411 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
412 /* clamp timeout to avoid unsigned-> signed overflow */
413 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
414 return MAX_SCHEDULE_TIMEOUT - 1;
416 return timeout_jiffies;
419 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
420 struct drm_file *filp)
422 union drm_amdgpu_gem_wait_idle *args = data;
423 struct drm_gem_object *gobj;
424 struct amdgpu_bo *robj;
425 uint32_t handle = args->in.handle;
426 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
430 gobj = drm_gem_object_lookup(filp, handle);
434 robj = gem_to_amdgpu_bo(gobj);
435 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
438 /* ret == 0 means not signaled,
439 * ret > 0 means signaled
440 * ret < 0 means interrupted before timeout
443 memset(args, 0, sizeof(*args));
444 args->out.status = (ret == 0);
448 drm_gem_object_put_unlocked(gobj);
452 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
453 struct drm_file *filp)
455 struct drm_amdgpu_gem_metadata *args = data;
456 struct drm_gem_object *gobj;
457 struct amdgpu_bo *robj;
460 DRM_DEBUG("%d \n", args->handle);
461 gobj = drm_gem_object_lookup(filp, args->handle);
464 robj = gem_to_amdgpu_bo(gobj);
466 r = amdgpu_bo_reserve(robj, false);
467 if (unlikely(r != 0))
470 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
471 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
472 r = amdgpu_bo_get_metadata(robj, args->data.data,
473 sizeof(args->data.data),
474 &args->data.data_size_bytes,
476 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
477 if (args->data.data_size_bytes > sizeof(args->data.data)) {
481 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
483 r = amdgpu_bo_set_metadata(robj, args->data.data,
484 args->data.data_size_bytes,
489 amdgpu_bo_unreserve(robj);
491 drm_gem_object_put_unlocked(gobj);
496 * amdgpu_gem_va_update_vm -update the bo_va in its VM
498 * @adev: amdgpu_device pointer
500 * @bo_va: bo_va to update
501 * @list: validation list
502 * @operation: map, unmap or clear
504 * Update the bo_va directly after setting its address. Errors are not
505 * vital here, so they are not reported back to userspace.
507 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
508 struct amdgpu_vm *vm,
509 struct amdgpu_bo_va *bo_va,
510 struct list_head *list,
515 if (!amdgpu_vm_ready(vm))
518 r = amdgpu_vm_update_directories(adev, vm);
522 r = amdgpu_vm_clear_freed(adev, vm, NULL);
526 if (operation == AMDGPU_VA_OP_MAP ||
527 operation == AMDGPU_VA_OP_REPLACE)
528 r = amdgpu_vm_bo_update(adev, bo_va, false);
531 if (r && r != -ERESTARTSYS)
532 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
535 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
536 struct drm_file *filp)
538 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
539 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
540 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
541 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
544 struct drm_amdgpu_gem_va *args = data;
545 struct drm_gem_object *gobj;
546 struct amdgpu_device *adev = dev->dev_private;
547 struct amdgpu_fpriv *fpriv = filp->driver_priv;
548 struct amdgpu_bo *abo;
549 struct amdgpu_bo_va *bo_va;
550 struct amdgpu_bo_list_entry vm_pd;
551 struct ttm_validate_buffer tv;
552 struct ww_acquire_ctx ticket;
553 struct list_head list, duplicates;
557 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
558 dev_err(&dev->pdev->dev,
559 "va_address 0x%lX is in reserved area 0x%X\n",
560 (unsigned long)args->va_address,
561 AMDGPU_VA_RESERVED_SIZE);
565 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
566 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
571 switch (args->operation) {
572 case AMDGPU_VA_OP_MAP:
573 case AMDGPU_VA_OP_UNMAP:
574 case AMDGPU_VA_OP_CLEAR:
575 case AMDGPU_VA_OP_REPLACE:
578 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
583 INIT_LIST_HEAD(&list);
584 INIT_LIST_HEAD(&duplicates);
585 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
586 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
587 gobj = drm_gem_object_lookup(filp, args->handle);
590 abo = gem_to_amdgpu_bo(gobj);
593 list_add(&tv.head, &list);
599 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
601 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
606 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
611 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
612 bo_va = fpriv->prt_va;
617 switch (args->operation) {
618 case AMDGPU_VA_OP_MAP:
619 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
624 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
625 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
626 args->offset_in_bo, args->map_size,
629 case AMDGPU_VA_OP_UNMAP:
630 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
633 case AMDGPU_VA_OP_CLEAR:
634 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
638 case AMDGPU_VA_OP_REPLACE:
639 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
644 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
645 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
646 args->offset_in_bo, args->map_size,
652 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
653 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
657 ttm_eu_backoff_reservation(&ticket, &list);
660 drm_gem_object_put_unlocked(gobj);
664 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
665 struct drm_file *filp)
667 struct amdgpu_device *adev = dev->dev_private;
668 struct drm_amdgpu_gem_op *args = data;
669 struct drm_gem_object *gobj;
670 struct amdgpu_bo *robj;
673 gobj = drm_gem_object_lookup(filp, args->handle);
677 robj = gem_to_amdgpu_bo(gobj);
679 r = amdgpu_bo_reserve(robj, false);
684 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
685 struct drm_amdgpu_gem_create_in info;
686 void __user *out = u64_to_user_ptr(args->value);
688 info.bo_size = robj->gem_base.size;
689 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
690 info.domains = robj->preferred_domains;
691 info.domain_flags = robj->flags;
692 amdgpu_bo_unreserve(robj);
693 if (copy_to_user(out, &info, sizeof(info)))
697 case AMDGPU_GEM_OP_SET_PLACEMENT:
698 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
700 amdgpu_bo_unreserve(robj);
703 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
705 amdgpu_bo_unreserve(robj);
708 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
709 AMDGPU_GEM_DOMAIN_GTT |
710 AMDGPU_GEM_DOMAIN_CPU);
711 robj->allowed_domains = robj->preferred_domains;
712 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
713 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
715 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
716 amdgpu_vm_bo_invalidate(adev, robj, true);
718 amdgpu_bo_unreserve(robj);
721 amdgpu_bo_unreserve(robj);
726 drm_gem_object_put_unlocked(gobj);
730 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
731 struct drm_device *dev,
732 struct drm_mode_create_dumb *args)
734 struct amdgpu_device *adev = dev->dev_private;
735 struct drm_gem_object *gobj;
739 args->pitch = amdgpu_align_pitch(adev, args->width,
740 DIV_ROUND_UP(args->bpp, 8), 0);
741 args->size = (u64)args->pitch * args->height;
742 args->size = ALIGN(args->size, PAGE_SIZE);
744 r = amdgpu_gem_object_create(adev, args->size, 0,
745 AMDGPU_GEM_DOMAIN_VRAM,
746 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
751 r = drm_gem_handle_create(file_priv, gobj, &handle);
752 /* drop reference from allocate - handle holds it now */
753 drm_gem_object_put_unlocked(gobj);
757 args->handle = handle;
761 #if defined(CONFIG_DEBUG_FS)
762 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
764 struct drm_gem_object *gobj = ptr;
765 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
766 struct seq_file *m = data;
769 const char *placement;
773 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
775 case AMDGPU_GEM_DOMAIN_VRAM:
778 case AMDGPU_GEM_DOMAIN_GTT:
781 case AMDGPU_GEM_DOMAIN_CPU:
786 seq_printf(m, "\t0x%08x: %12ld byte %s",
787 id, amdgpu_bo_size(bo), placement);
789 offset = READ_ONCE(bo->tbo.mem.start);
790 if (offset != AMDGPU_BO_INVALID_OFFSET)
791 seq_printf(m, " @ 0x%010Lx", offset);
793 pin_count = READ_ONCE(bo->pin_count);
795 seq_printf(m, " pin count %d", pin_count);
801 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
803 struct drm_info_node *node = (struct drm_info_node *)m->private;
804 struct drm_device *dev = node->minor->dev;
805 struct drm_file *file;
808 r = mutex_lock_interruptible(&dev->filelist_mutex);
812 list_for_each_entry(file, &dev->filelist, lhead) {
813 struct task_struct *task;
816 * Although we have a valid reference on file->pid, that does
817 * not guarantee that the task_struct who called get_pid() is
818 * still alive (e.g. get_pid(current) => fork() => exit()).
819 * Therefore, we need to protect this ->comm access using RCU.
822 task = pid_task(file->pid, PIDTYPE_PID);
823 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
824 task ? task->comm : "<unknown>");
827 spin_lock(&file->table_lock);
828 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
829 spin_unlock(&file->table_lock);
832 mutex_unlock(&dev->filelist_mutex);
836 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
837 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
841 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
843 #if defined(CONFIG_DEBUG_FS)
844 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);