mm: remove cold parameter for release_pages
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gem.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
30 #include <drm/drmP.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
35 {
36         struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
37
38         if (robj) {
39                 if (robj->gem_base.import_attach)
40                         drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
41                 amdgpu_mn_unregister(robj);
42                 amdgpu_bo_unref(&robj);
43         }
44 }
45
46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47                                 int alignment, u32 initial_domain,
48                                 u64 flags, bool kernel,
49                                 struct drm_gem_object **obj)
50 {
51         struct amdgpu_bo *robj;
52         int r;
53
54         *obj = NULL;
55         /* At least align on page size */
56         if (alignment < PAGE_SIZE) {
57                 alignment = PAGE_SIZE;
58         }
59
60 retry:
61         r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
62                              flags, NULL, NULL, 0, &robj);
63         if (r) {
64                 if (r != -ERESTARTSYS) {
65                         if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
66                                 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
67                                 goto retry;
68                         }
69                         DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
70                                   size, initial_domain, alignment, r);
71                 }
72                 return r;
73         }
74         *obj = &robj->gem_base;
75
76         return 0;
77 }
78
79 void amdgpu_gem_force_release(struct amdgpu_device *adev)
80 {
81         struct drm_device *ddev = adev->ddev;
82         struct drm_file *file;
83
84         mutex_lock(&ddev->filelist_mutex);
85
86         list_for_each_entry(file, &ddev->filelist, lhead) {
87                 struct drm_gem_object *gobj;
88                 int handle;
89
90                 WARN_ONCE(1, "Still active user space clients!\n");
91                 spin_lock(&file->table_lock);
92                 idr_for_each_entry(&file->object_idr, gobj, handle) {
93                         WARN_ONCE(1, "And also active allocations!\n");
94                         drm_gem_object_put_unlocked(gobj);
95                 }
96                 idr_destroy(&file->object_idr);
97                 spin_unlock(&file->table_lock);
98         }
99
100         mutex_unlock(&ddev->filelist_mutex);
101 }
102
103 /*
104  * Call from drm_gem_handle_create which appear in both new and open ioctl
105  * case.
106  */
107 int amdgpu_gem_object_open(struct drm_gem_object *obj,
108                            struct drm_file *file_priv)
109 {
110         struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
111         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
112         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
113         struct amdgpu_vm *vm = &fpriv->vm;
114         struct amdgpu_bo_va *bo_va;
115         int r;
116         r = amdgpu_bo_reserve(abo, false);
117         if (r)
118                 return r;
119
120         bo_va = amdgpu_vm_bo_find(vm, abo);
121         if (!bo_va) {
122                 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
123         } else {
124                 ++bo_va->ref_count;
125         }
126         amdgpu_bo_unreserve(abo);
127         return 0;
128 }
129
130 static int amdgpu_gem_vm_check(void *param, struct amdgpu_bo *bo)
131 {
132         /* if anything is swapped out don't swap it in here,
133            just abort and wait for the next CS */
134         if (!amdgpu_bo_gpu_accessible(bo))
135                 return -ERESTARTSYS;
136
137         if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
138                 return -ERESTARTSYS;
139
140         return 0;
141 }
142
143 static bool amdgpu_gem_vm_ready(struct amdgpu_device *adev,
144                                 struct amdgpu_vm *vm,
145                                 struct list_head *list)
146 {
147         struct ttm_validate_buffer *entry;
148
149         list_for_each_entry(entry, list, head) {
150                 struct amdgpu_bo *bo =
151                         container_of(entry->bo, struct amdgpu_bo, tbo);
152                 if (amdgpu_gem_vm_check(NULL, bo))
153                         return false;
154         }
155
156         return !amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_vm_check, NULL);
157 }
158
159 void amdgpu_gem_object_close(struct drm_gem_object *obj,
160                              struct drm_file *file_priv)
161 {
162         struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
163         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
164         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
165         struct amdgpu_vm *vm = &fpriv->vm;
166
167         struct amdgpu_bo_list_entry vm_pd;
168         struct list_head list;
169         struct ttm_validate_buffer tv;
170         struct ww_acquire_ctx ticket;
171         struct amdgpu_bo_va *bo_va;
172         int r;
173
174         INIT_LIST_HEAD(&list);
175
176         tv.bo = &bo->tbo;
177         tv.shared = true;
178         list_add(&tv.head, &list);
179
180         amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
181
182         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
183         if (r) {
184                 dev_err(adev->dev, "leaking bo va because "
185                         "we fail to reserve bo (%d)\n", r);
186                 return;
187         }
188         bo_va = amdgpu_vm_bo_find(vm, bo);
189         if (bo_va && --bo_va->ref_count == 0) {
190                 amdgpu_vm_bo_rmv(adev, bo_va);
191
192                 if (amdgpu_gem_vm_ready(adev, vm, &list)) {
193                         struct dma_fence *fence = NULL;
194
195                         r = amdgpu_vm_clear_freed(adev, vm, &fence);
196                         if (unlikely(r)) {
197                                 dev_err(adev->dev, "failed to clear page "
198                                         "tables on GEM object close (%d)\n", r);
199                         }
200
201                         if (fence) {
202                                 amdgpu_bo_fence(bo, fence, true);
203                                 dma_fence_put(fence);
204                         }
205                 }
206         }
207         ttm_eu_backoff_reservation(&ticket, &list);
208 }
209
210 /*
211  * GEM ioctls.
212  */
213 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
214                             struct drm_file *filp)
215 {
216         struct amdgpu_device *adev = dev->dev_private;
217         union drm_amdgpu_gem_create *args = data;
218         uint64_t size = args->in.bo_size;
219         struct drm_gem_object *gobj;
220         uint32_t handle;
221         bool kernel = false;
222         int r;
223
224         /* reject invalid gem flags */
225         if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
226                                       AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
227                                       AMDGPU_GEM_CREATE_CPU_GTT_USWC |
228                                       AMDGPU_GEM_CREATE_VRAM_CLEARED))
229                 return -EINVAL;
230
231         /* reject invalid gem domains */
232         if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
233                                  AMDGPU_GEM_DOMAIN_GTT |
234                                  AMDGPU_GEM_DOMAIN_VRAM |
235                                  AMDGPU_GEM_DOMAIN_GDS |
236                                  AMDGPU_GEM_DOMAIN_GWS |
237                                  AMDGPU_GEM_DOMAIN_OA))
238                 return -EINVAL;
239
240         /* create a gem object to contain this object in */
241         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
242             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
243                 kernel = true;
244                 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
245                         size = size << AMDGPU_GDS_SHIFT;
246                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
247                         size = size << AMDGPU_GWS_SHIFT;
248                 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
249                         size = size << AMDGPU_OA_SHIFT;
250                 else
251                         return -EINVAL;
252         }
253         size = roundup(size, PAGE_SIZE);
254
255         r = amdgpu_gem_object_create(adev, size, args->in.alignment,
256                                      (u32)(0xffffffff & args->in.domains),
257                                      args->in.domain_flags,
258                                      kernel, &gobj);
259         if (r)
260                 return r;
261
262         r = drm_gem_handle_create(filp, gobj, &handle);
263         /* drop reference from allocate - handle holds it now */
264         drm_gem_object_put_unlocked(gobj);
265         if (r)
266                 return r;
267
268         memset(args, 0, sizeof(*args));
269         args->out.handle = handle;
270         return 0;
271 }
272
273 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
274                              struct drm_file *filp)
275 {
276         struct amdgpu_device *adev = dev->dev_private;
277         struct drm_amdgpu_gem_userptr *args = data;
278         struct drm_gem_object *gobj;
279         struct amdgpu_bo *bo;
280         uint32_t handle;
281         int r;
282
283         if (offset_in_page(args->addr | args->size))
284                 return -EINVAL;
285
286         /* reject unknown flag values */
287         if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
288             AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
289             AMDGPU_GEM_USERPTR_REGISTER))
290                 return -EINVAL;
291
292         if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
293              !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
294
295                 /* if we want to write to it we must install a MMU notifier */
296                 return -EACCES;
297         }
298
299         /* create a gem object to contain this object in */
300         r = amdgpu_gem_object_create(adev, args->size, 0,
301                                      AMDGPU_GEM_DOMAIN_CPU, 0,
302                                      0, &gobj);
303         if (r)
304                 return r;
305
306         bo = gem_to_amdgpu_bo(gobj);
307         bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
308         bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
309         r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
310         if (r)
311                 goto release_object;
312
313         if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
314                 r = amdgpu_mn_register(bo, args->addr);
315                 if (r)
316                         goto release_object;
317         }
318
319         if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
320                 down_read(&current->mm->mmap_sem);
321
322                 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
323                                                  bo->tbo.ttm->pages);
324                 if (r)
325                         goto unlock_mmap_sem;
326
327                 r = amdgpu_bo_reserve(bo, true);
328                 if (r)
329                         goto free_pages;
330
331                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
332                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
333                 amdgpu_bo_unreserve(bo);
334                 if (r)
335                         goto free_pages;
336
337                 up_read(&current->mm->mmap_sem);
338         }
339
340         r = drm_gem_handle_create(filp, gobj, &handle);
341         /* drop reference from allocate - handle holds it now */
342         drm_gem_object_put_unlocked(gobj);
343         if (r)
344                 return r;
345
346         args->handle = handle;
347         return 0;
348
349 free_pages:
350         release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
351
352 unlock_mmap_sem:
353         up_read(&current->mm->mmap_sem);
354
355 release_object:
356         drm_gem_object_put_unlocked(gobj);
357
358         return r;
359 }
360
361 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
362                           struct drm_device *dev,
363                           uint32_t handle, uint64_t *offset_p)
364 {
365         struct drm_gem_object *gobj;
366         struct amdgpu_bo *robj;
367
368         gobj = drm_gem_object_lookup(filp, handle);
369         if (gobj == NULL) {
370                 return -ENOENT;
371         }
372         robj = gem_to_amdgpu_bo(gobj);
373         if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
374             (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
375                 drm_gem_object_put_unlocked(gobj);
376                 return -EPERM;
377         }
378         *offset_p = amdgpu_bo_mmap_offset(robj);
379         drm_gem_object_put_unlocked(gobj);
380         return 0;
381 }
382
383 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
384                           struct drm_file *filp)
385 {
386         union drm_amdgpu_gem_mmap *args = data;
387         uint32_t handle = args->in.handle;
388         memset(args, 0, sizeof(*args));
389         return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
390 }
391
392 /**
393  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
394  *
395  * @timeout_ns: timeout in ns
396  *
397  * Calculate the timeout in jiffies from an absolute timeout in ns.
398  */
399 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
400 {
401         unsigned long timeout_jiffies;
402         ktime_t timeout;
403
404         /* clamp timeout if it's to large */
405         if (((int64_t)timeout_ns) < 0)
406                 return MAX_SCHEDULE_TIMEOUT;
407
408         timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
409         if (ktime_to_ns(timeout) < 0)
410                 return 0;
411
412         timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
413         /*  clamp timeout to avoid unsigned-> signed overflow */
414         if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
415                 return MAX_SCHEDULE_TIMEOUT - 1;
416
417         return timeout_jiffies;
418 }
419
420 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
421                               struct drm_file *filp)
422 {
423         union drm_amdgpu_gem_wait_idle *args = data;
424         struct drm_gem_object *gobj;
425         struct amdgpu_bo *robj;
426         uint32_t handle = args->in.handle;
427         unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
428         int r = 0;
429         long ret;
430
431         gobj = drm_gem_object_lookup(filp, handle);
432         if (gobj == NULL) {
433                 return -ENOENT;
434         }
435         robj = gem_to_amdgpu_bo(gobj);
436         ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
437                                                   timeout);
438
439         /* ret == 0 means not signaled,
440          * ret > 0 means signaled
441          * ret < 0 means interrupted before timeout
442          */
443         if (ret >= 0) {
444                 memset(args, 0, sizeof(*args));
445                 args->out.status = (ret == 0);
446         } else
447                 r = ret;
448
449         drm_gem_object_put_unlocked(gobj);
450         return r;
451 }
452
453 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
454                                 struct drm_file *filp)
455 {
456         struct drm_amdgpu_gem_metadata *args = data;
457         struct drm_gem_object *gobj;
458         struct amdgpu_bo *robj;
459         int r = -1;
460
461         DRM_DEBUG("%d \n", args->handle);
462         gobj = drm_gem_object_lookup(filp, args->handle);
463         if (gobj == NULL)
464                 return -ENOENT;
465         robj = gem_to_amdgpu_bo(gobj);
466
467         r = amdgpu_bo_reserve(robj, false);
468         if (unlikely(r != 0))
469                 goto out;
470
471         if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
472                 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
473                 r = amdgpu_bo_get_metadata(robj, args->data.data,
474                                            sizeof(args->data.data),
475                                            &args->data.data_size_bytes,
476                                            &args->data.flags);
477         } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
478                 if (args->data.data_size_bytes > sizeof(args->data.data)) {
479                         r = -EINVAL;
480                         goto unreserve;
481                 }
482                 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
483                 if (!r)
484                         r = amdgpu_bo_set_metadata(robj, args->data.data,
485                                                    args->data.data_size_bytes,
486                                                    args->data.flags);
487         }
488
489 unreserve:
490         amdgpu_bo_unreserve(robj);
491 out:
492         drm_gem_object_put_unlocked(gobj);
493         return r;
494 }
495
496 /**
497  * amdgpu_gem_va_update_vm -update the bo_va in its VM
498  *
499  * @adev: amdgpu_device pointer
500  * @vm: vm to update
501  * @bo_va: bo_va to update
502  * @list: validation list
503  * @operation: map, unmap or clear
504  *
505  * Update the bo_va directly after setting its address. Errors are not
506  * vital here, so they are not reported back to userspace.
507  */
508 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
509                                     struct amdgpu_vm *vm,
510                                     struct amdgpu_bo_va *bo_va,
511                                     struct list_head *list,
512                                     uint32_t operation)
513 {
514         int r = -ERESTARTSYS;
515
516         if (!amdgpu_gem_vm_ready(adev, vm, list))
517                 goto error;
518
519         r = amdgpu_vm_update_directories(adev, vm);
520         if (r)
521                 goto error;
522
523         r = amdgpu_vm_clear_freed(adev, vm, NULL);
524         if (r)
525                 goto error;
526
527         if (operation == AMDGPU_VA_OP_MAP ||
528             operation == AMDGPU_VA_OP_REPLACE)
529                 r = amdgpu_vm_bo_update(adev, bo_va, false);
530
531 error:
532         if (r && r != -ERESTARTSYS)
533                 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
534 }
535
536 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
537                           struct drm_file *filp)
538 {
539         const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
540                 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
541                 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
542         const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
543                 AMDGPU_VM_PAGE_PRT;
544
545         struct drm_amdgpu_gem_va *args = data;
546         struct drm_gem_object *gobj;
547         struct amdgpu_device *adev = dev->dev_private;
548         struct amdgpu_fpriv *fpriv = filp->driver_priv;
549         struct amdgpu_bo *abo;
550         struct amdgpu_bo_va *bo_va;
551         struct amdgpu_bo_list_entry vm_pd;
552         struct ttm_validate_buffer tv;
553         struct ww_acquire_ctx ticket;
554         struct list_head list;
555         uint64_t va_flags;
556         int r = 0;
557
558         if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
559                 dev_err(&dev->pdev->dev,
560                         "va_address 0x%lX is in reserved area 0x%X\n",
561                         (unsigned long)args->va_address,
562                         AMDGPU_VA_RESERVED_SIZE);
563                 return -EINVAL;
564         }
565
566         if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
567                 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
568                         args->flags);
569                 return -EINVAL;
570         }
571
572         switch (args->operation) {
573         case AMDGPU_VA_OP_MAP:
574         case AMDGPU_VA_OP_UNMAP:
575         case AMDGPU_VA_OP_CLEAR:
576         case AMDGPU_VA_OP_REPLACE:
577                 break;
578         default:
579                 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
580                         args->operation);
581                 return -EINVAL;
582         }
583         if ((args->operation == AMDGPU_VA_OP_MAP) ||
584             (args->operation == AMDGPU_VA_OP_REPLACE)) {
585                 if (amdgpu_kms_vram_lost(adev, fpriv))
586                         return -ENODEV;
587         }
588
589         INIT_LIST_HEAD(&list);
590         if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
591             !(args->flags & AMDGPU_VM_PAGE_PRT)) {
592                 gobj = drm_gem_object_lookup(filp, args->handle);
593                 if (gobj == NULL)
594                         return -ENOENT;
595                 abo = gem_to_amdgpu_bo(gobj);
596                 tv.bo = &abo->tbo;
597                 tv.shared = false;
598                 list_add(&tv.head, &list);
599         } else {
600                 gobj = NULL;
601                 abo = NULL;
602         }
603
604         amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
605
606         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
607         if (r)
608                 goto error_unref;
609
610         if (abo) {
611                 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
612                 if (!bo_va) {
613                         r = -ENOENT;
614                         goto error_backoff;
615                 }
616         } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
617                 bo_va = fpriv->prt_va;
618         } else {
619                 bo_va = NULL;
620         }
621
622         switch (args->operation) {
623         case AMDGPU_VA_OP_MAP:
624                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
625                                         args->map_size);
626                 if (r)
627                         goto error_backoff;
628
629                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
630                 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
631                                      args->offset_in_bo, args->map_size,
632                                      va_flags);
633                 break;
634         case AMDGPU_VA_OP_UNMAP:
635                 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
636                 break;
637
638         case AMDGPU_VA_OP_CLEAR:
639                 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
640                                                 args->va_address,
641                                                 args->map_size);
642                 break;
643         case AMDGPU_VA_OP_REPLACE:
644                 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
645                                         args->map_size);
646                 if (r)
647                         goto error_backoff;
648
649                 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
650                 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
651                                              args->offset_in_bo, args->map_size,
652                                              va_flags);
653                 break;
654         default:
655                 break;
656         }
657         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
658                 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
659                                         args->operation);
660
661 error_backoff:
662         ttm_eu_backoff_reservation(&ticket, &list);
663
664 error_unref:
665         drm_gem_object_put_unlocked(gobj);
666         return r;
667 }
668
669 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
670                         struct drm_file *filp)
671 {
672         struct drm_amdgpu_gem_op *args = data;
673         struct drm_gem_object *gobj;
674         struct amdgpu_bo *robj;
675         int r;
676
677         gobj = drm_gem_object_lookup(filp, args->handle);
678         if (gobj == NULL) {
679                 return -ENOENT;
680         }
681         robj = gem_to_amdgpu_bo(gobj);
682
683         r = amdgpu_bo_reserve(robj, false);
684         if (unlikely(r))
685                 goto out;
686
687         switch (args->op) {
688         case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
689                 struct drm_amdgpu_gem_create_in info;
690                 void __user *out = u64_to_user_ptr(args->value);
691
692                 info.bo_size = robj->gem_base.size;
693                 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
694                 info.domains = robj->preferred_domains;
695                 info.domain_flags = robj->flags;
696                 amdgpu_bo_unreserve(robj);
697                 if (copy_to_user(out, &info, sizeof(info)))
698                         r = -EFAULT;
699                 break;
700         }
701         case AMDGPU_GEM_OP_SET_PLACEMENT:
702                 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
703                         r = -EINVAL;
704                         amdgpu_bo_unreserve(robj);
705                         break;
706                 }
707                 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
708                         r = -EPERM;
709                         amdgpu_bo_unreserve(robj);
710                         break;
711                 }
712                 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
713                                                         AMDGPU_GEM_DOMAIN_GTT |
714                                                         AMDGPU_GEM_DOMAIN_CPU);
715                 robj->allowed_domains = robj->preferred_domains;
716                 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
717                         robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
718
719                 amdgpu_bo_unreserve(robj);
720                 break;
721         default:
722                 amdgpu_bo_unreserve(robj);
723                 r = -EINVAL;
724         }
725
726 out:
727         drm_gem_object_put_unlocked(gobj);
728         return r;
729 }
730
731 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
732                             struct drm_device *dev,
733                             struct drm_mode_create_dumb *args)
734 {
735         struct amdgpu_device *adev = dev->dev_private;
736         struct drm_gem_object *gobj;
737         uint32_t handle;
738         int r;
739
740         args->pitch = amdgpu_align_pitch(adev, args->width,
741                                          DIV_ROUND_UP(args->bpp, 8), 0);
742         args->size = (u64)args->pitch * args->height;
743         args->size = ALIGN(args->size, PAGE_SIZE);
744
745         r = amdgpu_gem_object_create(adev, args->size, 0,
746                                      AMDGPU_GEM_DOMAIN_VRAM,
747                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
748                                      ttm_bo_type_device,
749                                      &gobj);
750         if (r)
751                 return -ENOMEM;
752
753         r = drm_gem_handle_create(file_priv, gobj, &handle);
754         /* drop reference from allocate - handle holds it now */
755         drm_gem_object_put_unlocked(gobj);
756         if (r) {
757                 return r;
758         }
759         args->handle = handle;
760         return 0;
761 }
762
763 #if defined(CONFIG_DEBUG_FS)
764 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
765 {
766         struct drm_gem_object *gobj = ptr;
767         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
768         struct seq_file *m = data;
769
770         unsigned domain;
771         const char *placement;
772         unsigned pin_count;
773         uint64_t offset;
774
775         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
776         switch (domain) {
777         case AMDGPU_GEM_DOMAIN_VRAM:
778                 placement = "VRAM";
779                 break;
780         case AMDGPU_GEM_DOMAIN_GTT:
781                 placement = " GTT";
782                 break;
783         case AMDGPU_GEM_DOMAIN_CPU:
784         default:
785                 placement = " CPU";
786                 break;
787         }
788         seq_printf(m, "\t0x%08x: %12ld byte %s",
789                    id, amdgpu_bo_size(bo), placement);
790
791         offset = READ_ONCE(bo->tbo.mem.start);
792         if (offset != AMDGPU_BO_INVALID_OFFSET)
793                 seq_printf(m, " @ 0x%010Lx", offset);
794
795         pin_count = READ_ONCE(bo->pin_count);
796         if (pin_count)
797                 seq_printf(m, " pin count %d", pin_count);
798         seq_printf(m, "\n");
799
800         return 0;
801 }
802
803 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
804 {
805         struct drm_info_node *node = (struct drm_info_node *)m->private;
806         struct drm_device *dev = node->minor->dev;
807         struct drm_file *file;
808         int r;
809
810         r = mutex_lock_interruptible(&dev->filelist_mutex);
811         if (r)
812                 return r;
813
814         list_for_each_entry(file, &dev->filelist, lhead) {
815                 struct task_struct *task;
816
817                 /*
818                  * Although we have a valid reference on file->pid, that does
819                  * not guarantee that the task_struct who called get_pid() is
820                  * still alive (e.g. get_pid(current) => fork() => exit()).
821                  * Therefore, we need to protect this ->comm access using RCU.
822                  */
823                 rcu_read_lock();
824                 task = pid_task(file->pid, PIDTYPE_PID);
825                 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
826                            task ? task->comm : "<unknown>");
827                 rcu_read_unlock();
828
829                 spin_lock(&file->table_lock);
830                 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
831                 spin_unlock(&file->table_lock);
832         }
833
834         mutex_unlock(&dev->filelist_mutex);
835         return 0;
836 }
837
838 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
839         {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
840 };
841 #endif
842
843 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
844 {
845 #if defined(CONFIG_DEBUG_FS)
846         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
847 #endif
848         return 0;
849 }