2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/amdgpu_drm.h>
37 #include <linux/vgaarb.h>
38 #include <linux/vga_switcheroo.h>
39 #include <linux/efi.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_i2c.h"
44 #include "amdgpu_atombios.h"
45 #include "amdgpu_atomfirmware.h"
47 #ifdef CONFIG_DRM_AMDGPU_SI
50 #ifdef CONFIG_DRM_AMDGPU_CIK
55 #include "bif/bif_4_1_d.h"
56 #include <linux/pci.h>
57 #include <linux/firmware.h>
58 #include "amdgpu_vf_error.h"
60 #include "amdgpu_amdkfd.h"
61 #include "amdgpu_pm.h"
63 #include "amdgpu_xgmi.h"
64 #include "amdgpu_ras.h"
66 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
67 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
68 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
69 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
70 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
72 #define AMDGPU_RESUME_MS 2000
74 static const char *amdgpu_asic_name[] = {
102 * DOC: pcie_replay_count
104 * The amdgpu driver provides a sysfs API for reporting the total number
105 * of PCIe replays (NAKs)
106 * The file pcie_replay_count is used for this and returns the total
107 * number of replays as a sum of the NAKs generated and NAKs received
110 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
111 struct device_attribute *attr, char *buf)
113 struct drm_device *ddev = dev_get_drvdata(dev);
114 struct amdgpu_device *adev = ddev->dev_private;
115 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
117 return snprintf(buf, PAGE_SIZE, "%llu\n", cnt);
120 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
121 amdgpu_device_get_pcie_replay_count, NULL);
123 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
126 * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
128 * @dev: drm_device pointer
130 * Returns true if the device is a dGPU with HG/PX power control,
131 * otherwise return false.
133 bool amdgpu_device_is_px(struct drm_device *dev)
135 struct amdgpu_device *adev = dev->dev_private;
137 if (adev->flags & AMD_IS_PX)
143 * MMIO register access helper functions.
146 * amdgpu_mm_rreg - read a memory mapped IO register
148 * @adev: amdgpu_device pointer
149 * @reg: dword aligned register offset
150 * @acc_flags: access flags which require special behavior
152 * Returns the 32 bit value from the offset specified.
154 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
159 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
160 return amdgpu_virt_kiq_rreg(adev, reg);
162 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
163 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
167 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
168 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
169 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
170 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
172 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
177 * MMIO register read with bytes helper functions
178 * @offset:bytes offset from MMIO start
183 * amdgpu_mm_rreg8 - read a memory mapped IO register
185 * @adev: amdgpu_device pointer
186 * @offset: byte aligned register offset
188 * Returns the 8 bit value from the offset specified.
190 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
191 if (offset < adev->rmmio_size)
192 return (readb(adev->rmmio + offset));
197 * MMIO register write with bytes helper functions
198 * @offset:bytes offset from MMIO start
199 * @value: the value want to be written to the register
203 * amdgpu_mm_wreg8 - read a memory mapped IO register
205 * @adev: amdgpu_device pointer
206 * @offset: byte aligned register offset
207 * @value: 8 bit value to write
209 * Writes the value specified to the offset specified.
211 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
212 if (offset < adev->rmmio_size)
213 writeb(value, adev->rmmio + offset);
219 * amdgpu_mm_wreg - write to a memory mapped IO register
221 * @adev: amdgpu_device pointer
222 * @reg: dword aligned register offset
223 * @v: 32 bit value to write to the register
224 * @acc_flags: access flags which require special behavior
226 * Writes the value specified to the offset specified.
228 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
231 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
233 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
234 adev->last_mm_index = v;
237 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
238 return amdgpu_virt_kiq_wreg(adev, reg, v);
240 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
241 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
245 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
246 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
247 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
248 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
251 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
257 * amdgpu_io_rreg - read an IO register
259 * @adev: amdgpu_device pointer
260 * @reg: dword aligned register offset
262 * Returns the 32 bit value from the offset specified.
264 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
266 if ((reg * 4) < adev->rio_mem_size)
267 return ioread32(adev->rio_mem + (reg * 4));
269 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
270 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
275 * amdgpu_io_wreg - write to an IO register
277 * @adev: amdgpu_device pointer
278 * @reg: dword aligned register offset
279 * @v: 32 bit value to write to the register
281 * Writes the value specified to the offset specified.
283 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
285 if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
286 adev->last_mm_index = v;
289 if ((reg * 4) < adev->rio_mem_size)
290 iowrite32(v, adev->rio_mem + (reg * 4));
292 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
293 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
296 if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
302 * amdgpu_mm_rdoorbell - read a doorbell dword
304 * @adev: amdgpu_device pointer
305 * @index: doorbell index
307 * Returns the value in the doorbell aperture at the
308 * requested doorbell index (CIK).
310 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
312 if (index < adev->doorbell.num_doorbells) {
313 return readl(adev->doorbell.ptr + index);
315 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
321 * amdgpu_mm_wdoorbell - write a doorbell dword
323 * @adev: amdgpu_device pointer
324 * @index: doorbell index
327 * Writes @v to the doorbell aperture at the
328 * requested doorbell index (CIK).
330 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
332 if (index < adev->doorbell.num_doorbells) {
333 writel(v, adev->doorbell.ptr + index);
335 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
340 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
342 * @adev: amdgpu_device pointer
343 * @index: doorbell index
345 * Returns the value in the doorbell aperture at the
346 * requested doorbell index (VEGA10+).
348 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
350 if (index < adev->doorbell.num_doorbells) {
351 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
353 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
359 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
361 * @adev: amdgpu_device pointer
362 * @index: doorbell index
365 * Writes @v to the doorbell aperture at the
366 * requested doorbell index (VEGA10+).
368 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
370 if (index < adev->doorbell.num_doorbells) {
371 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
373 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
378 * amdgpu_invalid_rreg - dummy reg read function
380 * @adev: amdgpu device pointer
381 * @reg: offset of register
383 * Dummy register read function. Used for register blocks
384 * that certain asics don't have (all asics).
385 * Returns the value in the register.
387 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
389 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
395 * amdgpu_invalid_wreg - dummy reg write function
397 * @adev: amdgpu device pointer
398 * @reg: offset of register
399 * @v: value to write to the register
401 * Dummy register read function. Used for register blocks
402 * that certain asics don't have (all asics).
404 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
406 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
412 * amdgpu_block_invalid_rreg - dummy reg read function
414 * @adev: amdgpu device pointer
415 * @block: offset of instance
416 * @reg: offset of register
418 * Dummy register read function. Used for register blocks
419 * that certain asics don't have (all asics).
420 * Returns the value in the register.
422 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
423 uint32_t block, uint32_t reg)
425 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
432 * amdgpu_block_invalid_wreg - dummy reg write function
434 * @adev: amdgpu device pointer
435 * @block: offset of instance
436 * @reg: offset of register
437 * @v: value to write to the register
439 * Dummy register read function. Used for register blocks
440 * that certain asics don't have (all asics).
442 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
444 uint32_t reg, uint32_t v)
446 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
452 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
454 * @adev: amdgpu device pointer
456 * Allocates a scratch page of VRAM for use by various things in the
459 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
461 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
462 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
463 &adev->vram_scratch.robj,
464 &adev->vram_scratch.gpu_addr,
465 (void **)&adev->vram_scratch.ptr);
469 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
471 * @adev: amdgpu device pointer
473 * Frees the VRAM scratch page.
475 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
477 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
481 * amdgpu_device_program_register_sequence - program an array of registers.
483 * @adev: amdgpu_device pointer
484 * @registers: pointer to the register array
485 * @array_size: size of the register array
487 * Programs an array or registers with and and or masks.
488 * This is a helper for setting golden registers.
490 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
491 const u32 *registers,
492 const u32 array_size)
494 u32 tmp, reg, and_mask, or_mask;
500 for (i = 0; i < array_size; i +=3) {
501 reg = registers[i + 0];
502 and_mask = registers[i + 1];
503 or_mask = registers[i + 2];
505 if (and_mask == 0xffffffff) {
517 * amdgpu_device_pci_config_reset - reset the GPU
519 * @adev: amdgpu_device pointer
521 * Resets the GPU using the pci config reset sequence.
522 * Only applicable to asics prior to vega10.
524 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
526 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
530 * GPU doorbell aperture helpers function.
533 * amdgpu_device_doorbell_init - Init doorbell driver information.
535 * @adev: amdgpu_device pointer
537 * Init doorbell driver information (CIK)
538 * Returns 0 on success, error on failure.
540 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
543 /* No doorbell on SI hardware generation */
544 if (adev->asic_type < CHIP_BONAIRE) {
545 adev->doorbell.base = 0;
546 adev->doorbell.size = 0;
547 adev->doorbell.num_doorbells = 0;
548 adev->doorbell.ptr = NULL;
552 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
555 amdgpu_asic_init_doorbell_index(adev);
557 /* doorbell bar mapping */
558 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
559 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
561 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
562 adev->doorbell_index.max_assignment+1);
563 if (adev->doorbell.num_doorbells == 0)
566 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
567 * paging queue doorbell use the second page. The
568 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
569 * doorbells are in the first page. So with paging queue enabled,
570 * the max num_doorbells should + 1 page (0x400 in dword)
572 if (adev->asic_type >= CHIP_VEGA10)
573 adev->doorbell.num_doorbells += 0x400;
575 adev->doorbell.ptr = ioremap(adev->doorbell.base,
576 adev->doorbell.num_doorbells *
578 if (adev->doorbell.ptr == NULL)
585 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
587 * @adev: amdgpu_device pointer
589 * Tear down doorbell driver information (CIK)
591 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
593 iounmap(adev->doorbell.ptr);
594 adev->doorbell.ptr = NULL;
600 * amdgpu_device_wb_*()
601 * Writeback is the method by which the GPU updates special pages in memory
602 * with the status of certain GPU events (fences, ring pointers,etc.).
606 * amdgpu_device_wb_fini - Disable Writeback and free memory
608 * @adev: amdgpu_device pointer
610 * Disables Writeback and frees the Writeback memory (all asics).
611 * Used at driver shutdown.
613 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
615 if (adev->wb.wb_obj) {
616 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
618 (void **)&adev->wb.wb);
619 adev->wb.wb_obj = NULL;
624 * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
626 * @adev: amdgpu_device pointer
628 * Initializes writeback and allocates writeback memory (all asics).
629 * Used at driver startup.
630 * Returns 0 on success or an -error on failure.
632 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
636 if (adev->wb.wb_obj == NULL) {
637 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
638 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
639 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
640 &adev->wb.wb_obj, &adev->wb.gpu_addr,
641 (void **)&adev->wb.wb);
643 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
647 adev->wb.num_wb = AMDGPU_MAX_WB;
648 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
650 /* clear wb memory */
651 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
658 * amdgpu_device_wb_get - Allocate a wb entry
660 * @adev: amdgpu_device pointer
663 * Allocate a wb slot for use by the driver (all asics).
664 * Returns 0 on success or -EINVAL on failure.
666 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
668 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
670 if (offset < adev->wb.num_wb) {
671 __set_bit(offset, adev->wb.used);
672 *wb = offset << 3; /* convert to dw offset */
680 * amdgpu_device_wb_free - Free a wb entry
682 * @adev: amdgpu_device pointer
685 * Free a wb slot allocated for use by the driver (all asics)
687 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
690 if (wb < adev->wb.num_wb)
691 __clear_bit(wb, adev->wb.used);
695 * amdgpu_device_resize_fb_bar - try to resize FB BAR
697 * @adev: amdgpu_device pointer
699 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
700 * to fail, but if any of the BARs is not accessible after the size we abort
701 * driver loading by returning -ENODEV.
703 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
705 u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
706 u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
707 struct pci_bus *root;
708 struct resource *res;
714 if (amdgpu_sriov_vf(adev))
717 /* Check if the root BUS has 64bit memory resources */
718 root = adev->pdev->bus;
722 pci_bus_for_each_resource(root, res, i) {
723 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
724 res->start > 0x100000000ull)
728 /* Trying to resize is pointless without a root hub window above 4GB */
732 /* Disable memory decoding while we change the BAR addresses and size */
733 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
734 pci_write_config_word(adev->pdev, PCI_COMMAND,
735 cmd & ~PCI_COMMAND_MEMORY);
737 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
738 amdgpu_device_doorbell_fini(adev);
739 if (adev->asic_type >= CHIP_BONAIRE)
740 pci_release_resource(adev->pdev, 2);
742 pci_release_resource(adev->pdev, 0);
744 r = pci_resize_resource(adev->pdev, 0, rbar_size);
746 DRM_INFO("Not enough PCI address space for a large BAR.");
747 else if (r && r != -ENOTSUPP)
748 DRM_ERROR("Problem resizing BAR0 (%d).", r);
750 pci_assign_unassigned_bus_resources(adev->pdev->bus);
752 /* When the doorbell or fb BAR isn't available we have no chance of
755 r = amdgpu_device_doorbell_init(adev);
756 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
759 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
765 * GPU helpers function.
768 * amdgpu_device_need_post - check if the hw need post or not
770 * @adev: amdgpu_device pointer
772 * Check if the asic has been initialized (all asics) at driver startup
773 * or post is needed if hw reset is performed.
774 * Returns true if need or false if not.
776 bool amdgpu_device_need_post(struct amdgpu_device *adev)
780 if (amdgpu_sriov_vf(adev))
783 if (amdgpu_passthrough(adev)) {
784 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
785 * some old smc fw still need driver do vPost otherwise gpu hang, while
786 * those smc fw version above 22.15 doesn't have this flaw, so we force
787 * vpost executed for smc version below 22.15
789 if (adev->asic_type == CHIP_FIJI) {
792 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
793 /* force vPost if error occured */
797 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
798 if (fw_ver < 0x00160e00)
803 if (adev->has_hw_reset) {
804 adev->has_hw_reset = false;
808 /* bios scratch used on CIK+ */
809 if (adev->asic_type >= CHIP_BONAIRE)
810 return amdgpu_atombios_scratch_need_asic_init(adev);
812 /* check MEM_SIZE for older asics */
813 reg = amdgpu_asic_get_config_memsize(adev);
815 if ((reg != 0) && (reg != 0xffffffff))
821 /* if we get transitioned to only one device, take VGA back */
823 * amdgpu_device_vga_set_decode - enable/disable vga decode
825 * @cookie: amdgpu_device pointer
826 * @state: enable/disable vga decode
828 * Enable/disable vga decode (all asics).
829 * Returns VGA resource flags.
831 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
833 struct amdgpu_device *adev = cookie;
834 amdgpu_asic_set_vga_state(adev, state);
836 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
837 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
839 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
843 * amdgpu_device_check_block_size - validate the vm block size
845 * @adev: amdgpu_device pointer
847 * Validates the vm block size specified via module parameter.
848 * The vm block size defines number of bits in page table versus page directory,
849 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
850 * page table and the remaining bits are in the page directory.
852 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
854 /* defines number of bits in page table versus page directory,
855 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
856 * page table and the remaining bits are in the page directory */
857 if (amdgpu_vm_block_size == -1)
860 if (amdgpu_vm_block_size < 9) {
861 dev_warn(adev->dev, "VM page table size (%d) too small\n",
862 amdgpu_vm_block_size);
863 amdgpu_vm_block_size = -1;
868 * amdgpu_device_check_vm_size - validate the vm size
870 * @adev: amdgpu_device pointer
872 * Validates the vm size in GB specified via module parameter.
873 * The VM size is the size of the GPU virtual memory space in GB.
875 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
877 /* no need to check the default value */
878 if (amdgpu_vm_size == -1)
881 if (amdgpu_vm_size < 1) {
882 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
888 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
891 bool is_os_64 = (sizeof(void *) == 8) ? true : false;
892 uint64_t total_memory;
893 uint64_t dram_size_seven_GB = 0x1B8000000;
894 uint64_t dram_size_three_GB = 0xB8000000;
896 if (amdgpu_smu_memory_pool_size == 0)
900 DRM_WARN("Not 64-bit OS, feature not supported\n");
904 total_memory = (uint64_t)si.totalram * si.mem_unit;
906 if ((amdgpu_smu_memory_pool_size == 1) ||
907 (amdgpu_smu_memory_pool_size == 2)) {
908 if (total_memory < dram_size_three_GB)
910 } else if ((amdgpu_smu_memory_pool_size == 4) ||
911 (amdgpu_smu_memory_pool_size == 8)) {
912 if (total_memory < dram_size_seven_GB)
915 DRM_WARN("Smu memory pool size not supported\n");
918 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
923 DRM_WARN("No enough system memory\n");
925 adev->pm.smu_prv_buffer_size = 0;
929 * amdgpu_device_check_arguments - validate module params
931 * @adev: amdgpu_device pointer
933 * Validates certain module parameters and updates
934 * the associated values used by the driver (all asics).
936 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
940 if (amdgpu_sched_jobs < 4) {
941 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
943 amdgpu_sched_jobs = 4;
944 } else if (!is_power_of_2(amdgpu_sched_jobs)){
945 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
947 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
950 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
951 /* gart size must be greater or equal to 32M */
952 dev_warn(adev->dev, "gart size (%d) too small\n",
954 amdgpu_gart_size = -1;
957 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
958 /* gtt size must be greater or equal to 32M */
959 dev_warn(adev->dev, "gtt size (%d) too small\n",
961 amdgpu_gtt_size = -1;
964 /* valid range is between 4 and 9 inclusive */
965 if (amdgpu_vm_fragment_size != -1 &&
966 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
967 dev_warn(adev->dev, "valid range is between 4 and 9\n");
968 amdgpu_vm_fragment_size = -1;
971 amdgpu_device_check_smu_prv_buffer_size(adev);
973 amdgpu_device_check_vm_size(adev);
975 amdgpu_device_check_block_size(adev);
977 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
978 !is_power_of_2(amdgpu_vram_page_split))) {
979 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
980 amdgpu_vram_page_split);
981 amdgpu_vram_page_split = 1024;
984 ret = amdgpu_device_get_job_timeout_settings(adev);
986 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
990 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
996 * amdgpu_switcheroo_set_state - set switcheroo state
998 * @pdev: pci dev pointer
999 * @state: vga_switcheroo state
1001 * Callback for the switcheroo driver. Suspends or resumes the
1002 * the asics before or after it is powered up using ACPI methods.
1004 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1006 struct drm_device *dev = pci_get_drvdata(pdev);
1008 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1011 if (state == VGA_SWITCHEROO_ON) {
1012 pr_info("amdgpu: switched on\n");
1013 /* don't suspend or resume card normally */
1014 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1016 amdgpu_device_resume(dev, true, true);
1018 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1019 drm_kms_helper_poll_enable(dev);
1021 pr_info("amdgpu: switched off\n");
1022 drm_kms_helper_poll_disable(dev);
1023 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1024 amdgpu_device_suspend(dev, true, true);
1025 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1030 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1032 * @pdev: pci dev pointer
1034 * Callback for the switcheroo driver. Check of the switcheroo
1035 * state can be changed.
1036 * Returns true if the state can be changed, false if not.
1038 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1040 struct drm_device *dev = pci_get_drvdata(pdev);
1043 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1044 * locking inversion with the driver load path. And the access here is
1045 * completely racy anyway. So don't bother with locking for now.
1047 return dev->open_count == 0;
1050 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1051 .set_gpu_state = amdgpu_switcheroo_set_state,
1053 .can_switch = amdgpu_switcheroo_can_switch,
1057 * amdgpu_device_ip_set_clockgating_state - set the CG state
1059 * @dev: amdgpu_device pointer
1060 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1061 * @state: clockgating state (gate or ungate)
1063 * Sets the requested clockgating state for all instances of
1064 * the hardware IP specified.
1065 * Returns the error code from the last instance.
1067 int amdgpu_device_ip_set_clockgating_state(void *dev,
1068 enum amd_ip_block_type block_type,
1069 enum amd_clockgating_state state)
1071 struct amdgpu_device *adev = dev;
1074 for (i = 0; i < adev->num_ip_blocks; i++) {
1075 if (!adev->ip_blocks[i].status.valid)
1077 if (adev->ip_blocks[i].version->type != block_type)
1079 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1081 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1082 (void *)adev, state);
1084 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1085 adev->ip_blocks[i].version->funcs->name, r);
1091 * amdgpu_device_ip_set_powergating_state - set the PG state
1093 * @dev: amdgpu_device pointer
1094 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1095 * @state: powergating state (gate or ungate)
1097 * Sets the requested powergating state for all instances of
1098 * the hardware IP specified.
1099 * Returns the error code from the last instance.
1101 int amdgpu_device_ip_set_powergating_state(void *dev,
1102 enum amd_ip_block_type block_type,
1103 enum amd_powergating_state state)
1105 struct amdgpu_device *adev = dev;
1108 for (i = 0; i < adev->num_ip_blocks; i++) {
1109 if (!adev->ip_blocks[i].status.valid)
1111 if (adev->ip_blocks[i].version->type != block_type)
1113 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1115 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1116 (void *)adev, state);
1118 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1119 adev->ip_blocks[i].version->funcs->name, r);
1125 * amdgpu_device_ip_get_clockgating_state - get the CG state
1127 * @adev: amdgpu_device pointer
1128 * @flags: clockgating feature flags
1130 * Walks the list of IPs on the device and updates the clockgating
1131 * flags for each IP.
1132 * Updates @flags with the feature flags for each hardware IP where
1133 * clockgating is enabled.
1135 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1140 for (i = 0; i < adev->num_ip_blocks; i++) {
1141 if (!adev->ip_blocks[i].status.valid)
1143 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1144 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1149 * amdgpu_device_ip_wait_for_idle - wait for idle
1151 * @adev: amdgpu_device pointer
1152 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1154 * Waits for the request hardware IP to be idle.
1155 * Returns 0 for success or a negative error code on failure.
1157 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1158 enum amd_ip_block_type block_type)
1162 for (i = 0; i < adev->num_ip_blocks; i++) {
1163 if (!adev->ip_blocks[i].status.valid)
1165 if (adev->ip_blocks[i].version->type == block_type) {
1166 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1177 * amdgpu_device_ip_is_idle - is the hardware IP idle
1179 * @adev: amdgpu_device pointer
1180 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1182 * Check if the hardware IP is idle or not.
1183 * Returns true if it the IP is idle, false if not.
1185 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1186 enum amd_ip_block_type block_type)
1190 for (i = 0; i < adev->num_ip_blocks; i++) {
1191 if (!adev->ip_blocks[i].status.valid)
1193 if (adev->ip_blocks[i].version->type == block_type)
1194 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1201 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1203 * @adev: amdgpu_device pointer
1204 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1206 * Returns a pointer to the hardware IP block structure
1207 * if it exists for the asic, otherwise NULL.
1209 struct amdgpu_ip_block *
1210 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1211 enum amd_ip_block_type type)
1215 for (i = 0; i < adev->num_ip_blocks; i++)
1216 if (adev->ip_blocks[i].version->type == type)
1217 return &adev->ip_blocks[i];
1223 * amdgpu_device_ip_block_version_cmp
1225 * @adev: amdgpu_device pointer
1226 * @type: enum amd_ip_block_type
1227 * @major: major version
1228 * @minor: minor version
1230 * return 0 if equal or greater
1231 * return 1 if smaller or the ip_block doesn't exist
1233 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1234 enum amd_ip_block_type type,
1235 u32 major, u32 minor)
1237 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1239 if (ip_block && ((ip_block->version->major > major) ||
1240 ((ip_block->version->major == major) &&
1241 (ip_block->version->minor >= minor))))
1248 * amdgpu_device_ip_block_add
1250 * @adev: amdgpu_device pointer
1251 * @ip_block_version: pointer to the IP to add
1253 * Adds the IP block driver information to the collection of IPs
1256 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1257 const struct amdgpu_ip_block_version *ip_block_version)
1259 if (!ip_block_version)
1262 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1263 ip_block_version->funcs->name);
1265 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1271 * amdgpu_device_enable_virtual_display - enable virtual display feature
1273 * @adev: amdgpu_device pointer
1275 * Enabled the virtual display feature if the user has enabled it via
1276 * the module parameter virtual_display. This feature provides a virtual
1277 * display hardware on headless boards or in virtualized environments.
1278 * This function parses and validates the configuration string specified by
1279 * the user and configues the virtual display configuration (number of
1280 * virtual connectors, crtcs, etc.) specified.
1282 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1284 adev->enable_virtual_display = false;
1286 if (amdgpu_virtual_display) {
1287 struct drm_device *ddev = adev->ddev;
1288 const char *pci_address_name = pci_name(ddev->pdev);
1289 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1291 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1292 pciaddstr_tmp = pciaddstr;
1293 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1294 pciaddname = strsep(&pciaddname_tmp, ",");
1295 if (!strcmp("all", pciaddname)
1296 || !strcmp(pci_address_name, pciaddname)) {
1300 adev->enable_virtual_display = true;
1303 res = kstrtol(pciaddname_tmp, 10,
1311 adev->mode_info.num_crtc = num_crtc;
1313 adev->mode_info.num_crtc = 1;
1319 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1320 amdgpu_virtual_display, pci_address_name,
1321 adev->enable_virtual_display, adev->mode_info.num_crtc);
1328 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1330 * @adev: amdgpu_device pointer
1332 * Parses the asic configuration parameters specified in the gpu info
1333 * firmware and makes them availale to the driver for use in configuring
1335 * Returns 0 on success, -EINVAL on failure.
1337 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1339 const char *chip_name;
1342 const struct gpu_info_firmware_header_v1_0 *hdr;
1344 adev->firmware.gpu_info_fw = NULL;
1346 switch (adev->asic_type) {
1350 case CHIP_POLARIS10:
1351 case CHIP_POLARIS11:
1352 case CHIP_POLARIS12:
1356 #ifdef CONFIG_DRM_AMDGPU_SI
1363 #ifdef CONFIG_DRM_AMDGPU_CIK
1374 chip_name = "vega10";
1377 chip_name = "vega12";
1380 if (adev->rev_id >= 8)
1381 chip_name = "raven2";
1382 else if (adev->pdev->device == 0x15d8)
1383 chip_name = "picasso";
1385 chip_name = "raven";
1389 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1390 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1393 "Failed to load gpu_info firmware \"%s\"\n",
1397 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1400 "Failed to validate gpu_info firmware \"%s\"\n",
1405 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1406 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1408 switch (hdr->version_major) {
1411 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1412 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1413 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1415 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1416 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1417 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1418 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1419 adev->gfx.config.max_texture_channel_caches =
1420 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1421 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1422 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1423 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1424 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1425 adev->gfx.config.double_offchip_lds_buf =
1426 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1427 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1428 adev->gfx.cu_info.max_waves_per_simd =
1429 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1430 adev->gfx.cu_info.max_scratch_slots_per_cu =
1431 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1432 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1437 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1446 * amdgpu_device_ip_early_init - run early init for hardware IPs
1448 * @adev: amdgpu_device pointer
1450 * Early initialization pass for hardware IPs. The hardware IPs that make
1451 * up each asic are discovered each IP's early_init callback is run. This
1452 * is the first stage in initializing the asic.
1453 * Returns 0 on success, negative error code on failure.
1455 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1459 amdgpu_device_enable_virtual_display(adev);
1461 switch (adev->asic_type) {
1465 case CHIP_POLARIS10:
1466 case CHIP_POLARIS11:
1467 case CHIP_POLARIS12:
1471 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1472 adev->family = AMDGPU_FAMILY_CZ;
1474 adev->family = AMDGPU_FAMILY_VI;
1476 r = vi_set_ip_blocks(adev);
1480 #ifdef CONFIG_DRM_AMDGPU_SI
1486 adev->family = AMDGPU_FAMILY_SI;
1487 r = si_set_ip_blocks(adev);
1492 #ifdef CONFIG_DRM_AMDGPU_CIK
1498 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1499 adev->family = AMDGPU_FAMILY_CI;
1501 adev->family = AMDGPU_FAMILY_KV;
1503 r = cik_set_ip_blocks(adev);
1512 if (adev->asic_type == CHIP_RAVEN)
1513 adev->family = AMDGPU_FAMILY_RV;
1515 adev->family = AMDGPU_FAMILY_AI;
1517 r = soc15_set_ip_blocks(adev);
1522 /* FIXME: not supported yet */
1526 r = amdgpu_device_parse_gpu_info_fw(adev);
1530 amdgpu_amdkfd_device_probe(adev);
1532 if (amdgpu_sriov_vf(adev)) {
1533 r = amdgpu_virt_request_full_gpu(adev, true);
1537 /* query the reg access mode at the very beginning */
1538 amdgpu_virt_init_reg_access_mode(adev);
1541 adev->pm.pp_feature = amdgpu_pp_feature_mask;
1542 if (amdgpu_sriov_vf(adev))
1543 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1546 if (!amdgpu_get_bios(adev))
1549 r = amdgpu_atombios_init(adev);
1551 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1552 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
1556 for (i = 0; i < adev->num_ip_blocks; i++) {
1557 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1558 DRM_ERROR("disabled ip block: %d <%s>\n",
1559 i, adev->ip_blocks[i].version->funcs->name);
1560 adev->ip_blocks[i].status.valid = false;
1562 if (adev->ip_blocks[i].version->funcs->early_init) {
1563 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1565 adev->ip_blocks[i].status.valid = false;
1567 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1568 adev->ip_blocks[i].version->funcs->name, r);
1571 adev->ip_blocks[i].status.valid = true;
1574 adev->ip_blocks[i].status.valid = true;
1579 adev->cg_flags &= amdgpu_cg_mask;
1580 adev->pg_flags &= amdgpu_pg_mask;
1585 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1589 for (i = 0; i < adev->num_ip_blocks; i++) {
1590 if (!adev->ip_blocks[i].status.sw)
1592 if (adev->ip_blocks[i].status.hw)
1594 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1595 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
1596 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1597 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1599 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1600 adev->ip_blocks[i].version->funcs->name, r);
1603 adev->ip_blocks[i].status.hw = true;
1610 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1614 for (i = 0; i < adev->num_ip_blocks; i++) {
1615 if (!adev->ip_blocks[i].status.sw)
1617 if (adev->ip_blocks[i].status.hw)
1619 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1621 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1622 adev->ip_blocks[i].version->funcs->name, r);
1625 adev->ip_blocks[i].status.hw = true;
1631 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1635 uint32_t smu_version;
1637 if (adev->asic_type >= CHIP_VEGA10) {
1638 for (i = 0; i < adev->num_ip_blocks; i++) {
1639 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1640 if (adev->in_gpu_reset || adev->in_suspend) {
1641 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1642 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1643 r = adev->ip_blocks[i].version->funcs->resume(adev);
1645 DRM_ERROR("resume of IP block <%s> failed %d\n",
1646 adev->ip_blocks[i].version->funcs->name, r);
1650 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1652 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1653 adev->ip_blocks[i].version->funcs->name, r);
1657 adev->ip_blocks[i].status.hw = true;
1661 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
1667 * amdgpu_device_ip_init - run init for hardware IPs
1669 * @adev: amdgpu_device pointer
1671 * Main initialization pass for hardware IPs. The list of all the hardware
1672 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1673 * are run. sw_init initializes the software state associated with each IP
1674 * and hw_init initializes the hardware associated with each IP.
1675 * Returns 0 on success, negative error code on failure.
1677 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1681 r = amdgpu_ras_init(adev);
1685 for (i = 0; i < adev->num_ip_blocks; i++) {
1686 if (!adev->ip_blocks[i].status.valid)
1688 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1690 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1691 adev->ip_blocks[i].version->funcs->name, r);
1694 adev->ip_blocks[i].status.sw = true;
1696 /* need to do gmc hw init early so we can allocate gpu mem */
1697 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1698 r = amdgpu_device_vram_scratch_init(adev);
1700 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1703 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1705 DRM_ERROR("hw_init %d failed %d\n", i, r);
1708 r = amdgpu_device_wb_init(adev);
1710 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1713 adev->ip_blocks[i].status.hw = true;
1715 /* right after GMC hw init, we create CSA */
1716 if (amdgpu_sriov_vf(adev)) {
1717 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1718 AMDGPU_GEM_DOMAIN_VRAM,
1721 DRM_ERROR("allocate CSA failed %d\n", r);
1728 r = amdgpu_ib_pool_init(adev);
1730 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1731 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
1735 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1739 r = amdgpu_device_ip_hw_init_phase1(adev);
1743 r = amdgpu_device_fw_loading(adev);
1747 r = amdgpu_device_ip_hw_init_phase2(adev);
1751 if (adev->gmc.xgmi.num_physical_nodes > 1)
1752 amdgpu_xgmi_add_device(adev);
1753 amdgpu_amdkfd_device_init(adev);
1756 if (amdgpu_sriov_vf(adev)) {
1758 amdgpu_virt_init_data_exchange(adev);
1759 amdgpu_virt_release_full_gpu(adev, true);
1766 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1768 * @adev: amdgpu_device pointer
1770 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
1771 * this function before a GPU reset. If the value is retained after a
1772 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
1774 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1776 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1780 * amdgpu_device_check_vram_lost - check if vram is valid
1782 * @adev: amdgpu_device pointer
1784 * Checks the reset magic value written to the gart pointer in VRAM.
1785 * The driver calls this after a GPU reset to see if the contents of
1786 * VRAM is lost or now.
1787 * returns true if vram is lost, false if not.
1789 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1791 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1792 AMDGPU_RESET_MAGIC_NUM);
1796 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1798 * @adev: amdgpu_device pointer
1800 * The list of all the hardware IPs that make up the asic is walked and the
1801 * set_clockgating_state callbacks are run.
1802 * Late initialization pass enabling clockgating for hardware IPs.
1803 * Fini or suspend, pass disabling clockgating for hardware IPs.
1804 * Returns 0 on success, negative error code on failure.
1807 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1808 enum amd_clockgating_state state)
1812 if (amdgpu_emu_mode == 1)
1815 for (j = 0; j < adev->num_ip_blocks; j++) {
1816 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1817 if (!adev->ip_blocks[i].status.late_initialized)
1819 /* skip CG for VCE/UVD, it's handled specially */
1820 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1821 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1822 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1823 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1824 /* enable clockgating to save power */
1825 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1828 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1829 adev->ip_blocks[i].version->funcs->name, r);
1838 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1842 if (amdgpu_emu_mode == 1)
1845 for (j = 0; j < adev->num_ip_blocks; j++) {
1846 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1847 if (!adev->ip_blocks[i].status.late_initialized)
1849 /* skip CG for VCE/UVD, it's handled specially */
1850 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1851 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1852 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1853 adev->ip_blocks[i].version->funcs->set_powergating_state) {
1854 /* enable powergating to save power */
1855 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1858 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1859 adev->ip_blocks[i].version->funcs->name, r);
1867 static int amdgpu_device_enable_mgpu_fan_boost(void)
1869 struct amdgpu_gpu_instance *gpu_ins;
1870 struct amdgpu_device *adev;
1873 mutex_lock(&mgpu_info.mutex);
1876 * MGPU fan boost feature should be enabled
1877 * only when there are two or more dGPUs in
1880 if (mgpu_info.num_dgpu < 2)
1883 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1884 gpu_ins = &(mgpu_info.gpu_ins[i]);
1885 adev = gpu_ins->adev;
1886 if (!(adev->flags & AMD_IS_APU) &&
1887 !gpu_ins->mgpu_fan_enabled &&
1888 adev->powerplay.pp_funcs &&
1889 adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1890 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1894 gpu_ins->mgpu_fan_enabled = 1;
1899 mutex_unlock(&mgpu_info.mutex);
1905 * amdgpu_device_ip_late_init - run late init for hardware IPs
1907 * @adev: amdgpu_device pointer
1909 * Late initialization pass for hardware IPs. The list of all the hardware
1910 * IPs that make up the asic is walked and the late_init callbacks are run.
1911 * late_init covers any special initialization that an IP requires
1912 * after all of the have been initialized or something that needs to happen
1913 * late in the init process.
1914 * Returns 0 on success, negative error code on failure.
1916 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1920 for (i = 0; i < adev->num_ip_blocks; i++) {
1921 if (!adev->ip_blocks[i].status.hw)
1923 if (adev->ip_blocks[i].version->funcs->late_init) {
1924 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1926 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1927 adev->ip_blocks[i].version->funcs->name, r);
1931 adev->ip_blocks[i].status.late_initialized = true;
1934 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1935 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1937 amdgpu_device_fill_reset_magic(adev);
1939 r = amdgpu_device_enable_mgpu_fan_boost();
1941 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
1943 /* set to low pstate by default */
1944 amdgpu_xgmi_set_pstate(adev, 0);
1950 * amdgpu_device_ip_fini - run fini for hardware IPs
1952 * @adev: amdgpu_device pointer
1954 * Main teardown pass for hardware IPs. The list of all the hardware
1955 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1956 * are run. hw_fini tears down the hardware associated with each IP
1957 * and sw_fini tears down any software state associated with each IP.
1958 * Returns 0 on success, negative error code on failure.
1960 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1964 amdgpu_ras_pre_fini(adev);
1966 if (adev->gmc.xgmi.num_physical_nodes > 1)
1967 amdgpu_xgmi_remove_device(adev);
1969 amdgpu_amdkfd_device_fini(adev);
1971 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1972 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1974 /* need to disable SMC first */
1975 for (i = 0; i < adev->num_ip_blocks; i++) {
1976 if (!adev->ip_blocks[i].status.hw)
1978 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1979 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1980 /* XXX handle errors */
1982 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1983 adev->ip_blocks[i].version->funcs->name, r);
1985 adev->ip_blocks[i].status.hw = false;
1990 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1991 if (!adev->ip_blocks[i].status.hw)
1994 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1995 /* XXX handle errors */
1997 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1998 adev->ip_blocks[i].version->funcs->name, r);
2001 adev->ip_blocks[i].status.hw = false;
2005 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2006 if (!adev->ip_blocks[i].status.sw)
2009 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2010 amdgpu_ucode_free_bo(adev);
2011 amdgpu_free_static_csa(&adev->virt.csa_obj);
2012 amdgpu_device_wb_fini(adev);
2013 amdgpu_device_vram_scratch_fini(adev);
2014 amdgpu_ib_pool_fini(adev);
2017 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2018 /* XXX handle errors */
2020 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2021 adev->ip_blocks[i].version->funcs->name, r);
2023 adev->ip_blocks[i].status.sw = false;
2024 adev->ip_blocks[i].status.valid = false;
2027 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2028 if (!adev->ip_blocks[i].status.late_initialized)
2030 if (adev->ip_blocks[i].version->funcs->late_fini)
2031 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2032 adev->ip_blocks[i].status.late_initialized = false;
2035 amdgpu_ras_fini(adev);
2037 if (amdgpu_sriov_vf(adev))
2038 if (amdgpu_virt_release_full_gpu(adev, false))
2039 DRM_ERROR("failed to release exclusive mode on fini\n");
2045 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2047 * @work: work_struct.
2049 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2051 struct amdgpu_device *adev =
2052 container_of(work, struct amdgpu_device, delayed_init_work.work);
2055 r = amdgpu_ib_ring_tests(adev);
2057 DRM_ERROR("ib ring test failed (%d).\n", r);
2060 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2062 struct amdgpu_device *adev =
2063 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2065 mutex_lock(&adev->gfx.gfx_off_mutex);
2066 if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2067 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2068 adev->gfx.gfx_off_state = true;
2070 mutex_unlock(&adev->gfx.gfx_off_mutex);
2074 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2076 * @adev: amdgpu_device pointer
2078 * Main suspend function for hardware IPs. The list of all the hardware
2079 * IPs that make up the asic is walked, clockgating is disabled and the
2080 * suspend callbacks are run. suspend puts the hardware and software state
2081 * in each IP into a state suitable for suspend.
2082 * Returns 0 on success, negative error code on failure.
2084 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2088 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2089 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2091 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2092 if (!adev->ip_blocks[i].status.valid)
2094 /* displays are handled separately */
2095 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2096 /* XXX handle errors */
2097 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2098 /* XXX handle errors */
2100 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2101 adev->ip_blocks[i].version->funcs->name, r);
2110 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2112 * @adev: amdgpu_device pointer
2114 * Main suspend function for hardware IPs. The list of all the hardware
2115 * IPs that make up the asic is walked, clockgating is disabled and the
2116 * suspend callbacks are run. suspend puts the hardware and software state
2117 * in each IP into a state suitable for suspend.
2118 * Returns 0 on success, negative error code on failure.
2120 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2124 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2125 if (!adev->ip_blocks[i].status.valid)
2127 /* displays are handled in phase1 */
2128 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2130 /* XXX handle errors */
2131 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2132 /* XXX handle errors */
2134 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2135 adev->ip_blocks[i].version->funcs->name, r);
2143 * amdgpu_device_ip_suspend - run suspend for hardware IPs
2145 * @adev: amdgpu_device pointer
2147 * Main suspend function for hardware IPs. The list of all the hardware
2148 * IPs that make up the asic is walked, clockgating is disabled and the
2149 * suspend callbacks are run. suspend puts the hardware and software state
2150 * in each IP into a state suitable for suspend.
2151 * Returns 0 on success, negative error code on failure.
2153 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2157 if (amdgpu_sriov_vf(adev))
2158 amdgpu_virt_request_full_gpu(adev, false);
2160 r = amdgpu_device_ip_suspend_phase1(adev);
2163 r = amdgpu_device_ip_suspend_phase2(adev);
2165 if (amdgpu_sriov_vf(adev))
2166 amdgpu_virt_release_full_gpu(adev, false);
2171 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2175 static enum amd_ip_block_type ip_order[] = {
2176 AMD_IP_BLOCK_TYPE_GMC,
2177 AMD_IP_BLOCK_TYPE_COMMON,
2178 AMD_IP_BLOCK_TYPE_PSP,
2179 AMD_IP_BLOCK_TYPE_IH,
2182 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2184 struct amdgpu_ip_block *block;
2186 for (j = 0; j < adev->num_ip_blocks; j++) {
2187 block = &adev->ip_blocks[j];
2189 if (block->version->type != ip_order[i] ||
2190 !block->status.valid)
2193 r = block->version->funcs->hw_init(adev);
2194 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2203 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2207 static enum amd_ip_block_type ip_order[] = {
2208 AMD_IP_BLOCK_TYPE_SMC,
2209 AMD_IP_BLOCK_TYPE_DCE,
2210 AMD_IP_BLOCK_TYPE_GFX,
2211 AMD_IP_BLOCK_TYPE_SDMA,
2212 AMD_IP_BLOCK_TYPE_UVD,
2213 AMD_IP_BLOCK_TYPE_VCE
2216 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2218 struct amdgpu_ip_block *block;
2220 for (j = 0; j < adev->num_ip_blocks; j++) {
2221 block = &adev->ip_blocks[j];
2223 if (block->version->type != ip_order[i] ||
2224 !block->status.valid)
2227 r = block->version->funcs->hw_init(adev);
2228 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2238 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2240 * @adev: amdgpu_device pointer
2242 * First resume function for hardware IPs. The list of all the hardware
2243 * IPs that make up the asic is walked and the resume callbacks are run for
2244 * COMMON, GMC, and IH. resume puts the hardware into a functional state
2245 * after a suspend and updates the software state as necessary. This
2246 * function is also used for restoring the GPU after a GPU reset.
2247 * Returns 0 on success, negative error code on failure.
2249 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2253 for (i = 0; i < adev->num_ip_blocks; i++) {
2254 if (!adev->ip_blocks[i].status.valid)
2256 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2257 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2258 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2259 r = adev->ip_blocks[i].version->funcs->resume(adev);
2261 DRM_ERROR("resume of IP block <%s> failed %d\n",
2262 adev->ip_blocks[i].version->funcs->name, r);
2272 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2274 * @adev: amdgpu_device pointer
2276 * First resume function for hardware IPs. The list of all the hardware
2277 * IPs that make up the asic is walked and the resume callbacks are run for
2278 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
2279 * functional state after a suspend and updates the software state as
2280 * necessary. This function is also used for restoring the GPU after a GPU
2282 * Returns 0 on success, negative error code on failure.
2284 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2288 for (i = 0; i < adev->num_ip_blocks; i++) {
2289 if (!adev->ip_blocks[i].status.valid)
2291 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2292 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2293 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2294 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2296 r = adev->ip_blocks[i].version->funcs->resume(adev);
2298 DRM_ERROR("resume of IP block <%s> failed %d\n",
2299 adev->ip_blocks[i].version->funcs->name, r);
2308 * amdgpu_device_ip_resume - run resume for hardware IPs
2310 * @adev: amdgpu_device pointer
2312 * Main resume function for hardware IPs. The hardware IPs
2313 * are split into two resume functions because they are
2314 * are also used in in recovering from a GPU reset and some additional
2315 * steps need to be take between them. In this case (S3/S4) they are
2317 * Returns 0 on success, negative error code on failure.
2319 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2323 r = amdgpu_device_ip_resume_phase1(adev);
2327 r = amdgpu_device_fw_loading(adev);
2331 r = amdgpu_device_ip_resume_phase2(adev);
2337 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2339 * @adev: amdgpu_device pointer
2341 * Query the VBIOS data tables to determine if the board supports SR-IOV.
2343 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2345 if (amdgpu_sriov_vf(adev)) {
2346 if (adev->is_atom_fw) {
2347 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2348 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2350 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2351 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2354 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2355 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2360 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2362 * @asic_type: AMD asic type
2364 * Check if there is DC (new modesetting infrastructre) support for an asic.
2365 * returns true if DC has support, false if not.
2367 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2369 switch (asic_type) {
2370 #if defined(CONFIG_DRM_AMD_DC)
2376 * We have systems in the wild with these ASICs that require
2377 * LVDS and VGA support which is not supported with DC.
2379 * Fallback to the non-DC driver here by default so as not to
2380 * cause regressions.
2382 return amdgpu_dc > 0;
2386 case CHIP_POLARIS10:
2387 case CHIP_POLARIS11:
2388 case CHIP_POLARIS12:
2395 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2398 return amdgpu_dc != 0;
2406 * amdgpu_device_has_dc_support - check if dc is supported
2408 * @adev: amdgpu_device_pointer
2410 * Returns true for supported, false for not supported
2412 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2414 if (amdgpu_sriov_vf(adev))
2417 return amdgpu_device_asic_has_dc_support(adev->asic_type);
2421 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2423 struct amdgpu_device *adev =
2424 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2426 adev->asic_reset_res = amdgpu_asic_reset(adev);
2427 if (adev->asic_reset_res)
2428 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
2429 adev->asic_reset_res, adev->ddev->unique);
2434 * amdgpu_device_init - initialize the driver
2436 * @adev: amdgpu_device pointer
2437 * @ddev: drm dev pointer
2438 * @pdev: pci dev pointer
2439 * @flags: driver flags
2441 * Initializes the driver info and hw (all asics).
2442 * Returns 0 for success or an error on failure.
2443 * Called at driver startup.
2445 int amdgpu_device_init(struct amdgpu_device *adev,
2446 struct drm_device *ddev,
2447 struct pci_dev *pdev,
2451 bool runtime = false;
2454 adev->shutdown = false;
2455 adev->dev = &pdev->dev;
2458 adev->flags = flags;
2459 adev->asic_type = flags & AMD_ASIC_MASK;
2460 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2461 if (amdgpu_emu_mode == 1)
2462 adev->usec_timeout *= 2;
2463 adev->gmc.gart_size = 512 * 1024 * 1024;
2464 adev->accel_working = false;
2465 adev->num_rings = 0;
2466 adev->mman.buffer_funcs = NULL;
2467 adev->mman.buffer_funcs_ring = NULL;
2468 adev->vm_manager.vm_pte_funcs = NULL;
2469 adev->vm_manager.vm_pte_num_rqs = 0;
2470 adev->gmc.gmc_funcs = NULL;
2471 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2472 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2474 adev->smc_rreg = &amdgpu_invalid_rreg;
2475 adev->smc_wreg = &amdgpu_invalid_wreg;
2476 adev->pcie_rreg = &amdgpu_invalid_rreg;
2477 adev->pcie_wreg = &amdgpu_invalid_wreg;
2478 adev->pciep_rreg = &amdgpu_invalid_rreg;
2479 adev->pciep_wreg = &amdgpu_invalid_wreg;
2480 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2481 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2482 adev->didt_rreg = &amdgpu_invalid_rreg;
2483 adev->didt_wreg = &amdgpu_invalid_wreg;
2484 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2485 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2486 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2487 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2489 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2490 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2491 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2493 /* mutex initialization are all done here so we
2494 * can recall function without having locking issues */
2495 atomic_set(&adev->irq.ih.lock, 0);
2496 mutex_init(&adev->firmware.mutex);
2497 mutex_init(&adev->pm.mutex);
2498 mutex_init(&adev->gfx.gpu_clock_mutex);
2499 mutex_init(&adev->srbm_mutex);
2500 mutex_init(&adev->gfx.pipe_reserve_mutex);
2501 mutex_init(&adev->gfx.gfx_off_mutex);
2502 mutex_init(&adev->grbm_idx_mutex);
2503 mutex_init(&adev->mn_lock);
2504 mutex_init(&adev->virt.vf_errors.lock);
2505 hash_init(adev->mn_hash);
2506 mutex_init(&adev->lock_reset);
2507 mutex_init(&adev->virt.dpm_mutex);
2509 r = amdgpu_device_check_arguments(adev);
2513 spin_lock_init(&adev->mmio_idx_lock);
2514 spin_lock_init(&adev->smc_idx_lock);
2515 spin_lock_init(&adev->pcie_idx_lock);
2516 spin_lock_init(&adev->uvd_ctx_idx_lock);
2517 spin_lock_init(&adev->didt_idx_lock);
2518 spin_lock_init(&adev->gc_cac_idx_lock);
2519 spin_lock_init(&adev->se_cac_idx_lock);
2520 spin_lock_init(&adev->audio_endpt_idx_lock);
2521 spin_lock_init(&adev->mm_stats.lock);
2523 INIT_LIST_HEAD(&adev->shadow_list);
2524 mutex_init(&adev->shadow_list_lock);
2526 INIT_LIST_HEAD(&adev->ring_lru_list);
2527 spin_lock_init(&adev->ring_lru_list_lock);
2529 INIT_DELAYED_WORK(&adev->delayed_init_work,
2530 amdgpu_device_delayed_init_work_handler);
2531 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2532 amdgpu_device_delay_enable_gfx_off);
2534 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2536 adev->gfx.gfx_off_req_count = 1;
2537 adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2539 /* Registers mapping */
2540 /* TODO: block userspace mapping of io register */
2541 if (adev->asic_type >= CHIP_BONAIRE) {
2542 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2543 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2545 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2546 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2549 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2550 if (adev->rmmio == NULL) {
2553 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2554 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2556 /* io port mapping */
2557 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2558 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2559 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2560 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2564 if (adev->rio_mem == NULL)
2565 DRM_INFO("PCI I/O BAR is not found.\n");
2567 amdgpu_device_get_pcie_info(adev);
2569 /* early init functions */
2570 r = amdgpu_device_ip_early_init(adev);
2574 /* doorbell bar mapping and doorbell index init*/
2575 amdgpu_device_doorbell_init(adev);
2577 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2578 /* this will fail for cards that aren't VGA class devices, just
2580 vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2582 if (amdgpu_device_is_px(ddev))
2584 if (!pci_is_thunderbolt_attached(adev->pdev))
2585 vga_switcheroo_register_client(adev->pdev,
2586 &amdgpu_switcheroo_ops, runtime);
2588 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2590 if (amdgpu_emu_mode == 1) {
2591 /* post the asic on emulation mode */
2592 emu_soc_asic_init(adev);
2593 goto fence_driver_init;
2596 /* detect if we are with an SRIOV vbios */
2597 amdgpu_device_detect_sriov_bios(adev);
2599 /* check if we need to reset the asic
2600 * E.g., driver was not cleanly unloaded previously, etc.
2602 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2603 r = amdgpu_asic_reset(adev);
2605 dev_err(adev->dev, "asic reset on init failed\n");
2610 /* Post card if necessary */
2611 if (amdgpu_device_need_post(adev)) {
2613 dev_err(adev->dev, "no vBIOS found\n");
2617 DRM_INFO("GPU posting now...\n");
2618 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2620 dev_err(adev->dev, "gpu post error!\n");
2625 if (adev->is_atom_fw) {
2626 /* Initialize clocks */
2627 r = amdgpu_atomfirmware_get_clock_info(adev);
2629 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2630 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2634 /* Initialize clocks */
2635 r = amdgpu_atombios_get_clock_info(adev);
2637 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2638 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2641 /* init i2c buses */
2642 if (!amdgpu_device_has_dc_support(adev))
2643 amdgpu_atombios_i2c_init(adev);
2648 r = amdgpu_fence_driver_init(adev);
2650 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2651 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2655 /* init the mode config */
2656 drm_mode_config_init(adev->ddev);
2658 r = amdgpu_device_ip_init(adev);
2660 /* failed in exclusive mode due to timeout */
2661 if (amdgpu_sriov_vf(adev) &&
2662 !amdgpu_sriov_runtime(adev) &&
2663 amdgpu_virt_mmio_blocked(adev) &&
2664 !amdgpu_virt_wait_reset(adev)) {
2665 dev_err(adev->dev, "VF exclusive mode timeout\n");
2666 /* Don't send request since VF is inactive. */
2667 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2668 adev->virt.ops = NULL;
2672 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2673 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2674 if (amdgpu_virt_request_full_gpu(adev, false))
2675 amdgpu_virt_release_full_gpu(adev, false);
2679 adev->accel_working = true;
2681 amdgpu_vm_check_compute_bug(adev);
2683 /* Initialize the buffer migration limit. */
2684 if (amdgpu_moverate >= 0)
2685 max_MBps = amdgpu_moverate;
2687 max_MBps = 8; /* Allow 8 MB/s. */
2688 /* Get a log2 for easy divisions. */
2689 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2691 amdgpu_fbdev_init(adev);
2693 r = amdgpu_pm_sysfs_init(adev);
2695 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2697 r = amdgpu_ucode_sysfs_init(adev);
2699 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
2701 r = amdgpu_debugfs_gem_init(adev);
2703 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2705 r = amdgpu_debugfs_regs_init(adev);
2707 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2709 r = amdgpu_debugfs_firmware_init(adev);
2711 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2713 r = amdgpu_debugfs_init(adev);
2715 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2717 if ((amdgpu_testing & 1)) {
2718 if (adev->accel_working)
2719 amdgpu_test_moves(adev);
2721 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2723 if (amdgpu_benchmarking) {
2724 if (adev->accel_working)
2725 amdgpu_benchmark(adev, amdgpu_benchmarking);
2727 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2730 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2731 * explicit gating rather than handling it automatically.
2733 r = amdgpu_device_ip_late_init(adev);
2735 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2736 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2741 amdgpu_ras_resume(adev);
2743 queue_delayed_work(system_wq, &adev->delayed_init_work,
2744 msecs_to_jiffies(AMDGPU_RESUME_MS));
2746 r = device_create_file(adev->dev, &dev_attr_pcie_replay_count);
2748 dev_err(adev->dev, "Could not create pcie_replay_count");
2755 amdgpu_vf_error_trans_all(adev);
2757 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2763 * amdgpu_device_fini - tear down the driver
2765 * @adev: amdgpu_device pointer
2767 * Tear down the driver info (all asics).
2768 * Called at driver shutdown.
2770 void amdgpu_device_fini(struct amdgpu_device *adev)
2774 DRM_INFO("amdgpu: finishing device.\n");
2775 adev->shutdown = true;
2776 /* disable all interrupts */
2777 amdgpu_irq_disable_all(adev);
2778 if (adev->mode_info.mode_config_initialized){
2779 if (!amdgpu_device_has_dc_support(adev))
2780 drm_helper_force_disable_all(adev->ddev);
2782 drm_atomic_helper_shutdown(adev->ddev);
2784 amdgpu_fence_driver_fini(adev);
2785 amdgpu_pm_sysfs_fini(adev);
2786 amdgpu_fbdev_fini(adev);
2787 r = amdgpu_device_ip_fini(adev);
2788 if (adev->firmware.gpu_info_fw) {
2789 release_firmware(adev->firmware.gpu_info_fw);
2790 adev->firmware.gpu_info_fw = NULL;
2792 adev->accel_working = false;
2793 cancel_delayed_work_sync(&adev->delayed_init_work);
2794 /* free i2c buses */
2795 if (!amdgpu_device_has_dc_support(adev))
2796 amdgpu_i2c_fini(adev);
2798 if (amdgpu_emu_mode != 1)
2799 amdgpu_atombios_fini(adev);
2803 if (!pci_is_thunderbolt_attached(adev->pdev))
2804 vga_switcheroo_unregister_client(adev->pdev);
2805 if (adev->flags & AMD_IS_PX)
2806 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2807 vga_client_register(adev->pdev, NULL, NULL, NULL);
2809 pci_iounmap(adev->pdev, adev->rio_mem);
2810 adev->rio_mem = NULL;
2811 iounmap(adev->rmmio);
2813 amdgpu_device_doorbell_fini(adev);
2814 amdgpu_debugfs_regs_cleanup(adev);
2815 device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
2816 amdgpu_ucode_sysfs_fini(adev);
2824 * amdgpu_device_suspend - initiate device suspend
2826 * @dev: drm dev pointer
2827 * @suspend: suspend state
2828 * @fbcon : notify the fbdev of suspend
2830 * Puts the hw in the suspend state (all asics).
2831 * Returns 0 for success or an error on failure.
2832 * Called at driver suspend.
2834 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2836 struct amdgpu_device *adev;
2837 struct drm_crtc *crtc;
2838 struct drm_connector *connector;
2841 if (dev == NULL || dev->dev_private == NULL) {
2845 adev = dev->dev_private;
2847 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2850 adev->in_suspend = true;
2851 drm_kms_helper_poll_disable(dev);
2854 amdgpu_fbdev_set_suspend(adev, 1);
2856 cancel_delayed_work_sync(&adev->delayed_init_work);
2858 if (!amdgpu_device_has_dc_support(adev)) {
2859 /* turn off display hw */
2860 drm_modeset_lock_all(dev);
2861 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2862 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2864 drm_modeset_unlock_all(dev);
2865 /* unpin the front buffers and cursors */
2866 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2867 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2868 struct drm_framebuffer *fb = crtc->primary->fb;
2869 struct amdgpu_bo *robj;
2871 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2872 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2873 r = amdgpu_bo_reserve(aobj, true);
2875 amdgpu_bo_unpin(aobj);
2876 amdgpu_bo_unreserve(aobj);
2880 if (fb == NULL || fb->obj[0] == NULL) {
2883 robj = gem_to_amdgpu_bo(fb->obj[0]);
2884 /* don't unpin kernel fb objects */
2885 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2886 r = amdgpu_bo_reserve(robj, true);
2888 amdgpu_bo_unpin(robj);
2889 amdgpu_bo_unreserve(robj);
2895 amdgpu_amdkfd_suspend(adev);
2897 amdgpu_ras_suspend(adev);
2899 r = amdgpu_device_ip_suspend_phase1(adev);
2901 /* evict vram memory */
2902 amdgpu_bo_evict_vram(adev);
2904 amdgpu_fence_driver_suspend(adev);
2906 r = amdgpu_device_ip_suspend_phase2(adev);
2908 /* evict remaining vram memory
2909 * This second call to evict vram is to evict the gart page table
2912 amdgpu_bo_evict_vram(adev);
2914 pci_save_state(dev->pdev);
2916 /* Shut down the device */
2917 pci_disable_device(dev->pdev);
2918 pci_set_power_state(dev->pdev, PCI_D3hot);
2920 r = amdgpu_asic_reset(adev);
2922 DRM_ERROR("amdgpu asic reset failed\n");
2929 * amdgpu_device_resume - initiate device resume
2931 * @dev: drm dev pointer
2932 * @resume: resume state
2933 * @fbcon : notify the fbdev of resume
2935 * Bring the hw back to operating state (all asics).
2936 * Returns 0 for success or an error on failure.
2937 * Called at driver resume.
2939 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2941 struct drm_connector *connector;
2942 struct amdgpu_device *adev = dev->dev_private;
2943 struct drm_crtc *crtc;
2946 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2950 pci_set_power_state(dev->pdev, PCI_D0);
2951 pci_restore_state(dev->pdev);
2952 r = pci_enable_device(dev->pdev);
2958 if (amdgpu_device_need_post(adev)) {
2959 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2961 DRM_ERROR("amdgpu asic init failed\n");
2964 r = amdgpu_device_ip_resume(adev);
2966 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2969 amdgpu_fence_driver_resume(adev);
2972 r = amdgpu_device_ip_late_init(adev);
2976 queue_delayed_work(system_wq, &adev->delayed_init_work,
2977 msecs_to_jiffies(AMDGPU_RESUME_MS));
2979 if (!amdgpu_device_has_dc_support(adev)) {
2981 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2982 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2984 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2985 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2986 r = amdgpu_bo_reserve(aobj, true);
2988 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2990 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2991 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2992 amdgpu_bo_unreserve(aobj);
2997 r = amdgpu_amdkfd_resume(adev);
3001 /* Make sure IB tests flushed */
3002 flush_delayed_work(&adev->delayed_init_work);
3004 /* blat the mode back in */
3006 if (!amdgpu_device_has_dc_support(adev)) {
3008 drm_helper_resume_force_mode(dev);
3010 /* turn on display hw */
3011 drm_modeset_lock_all(dev);
3012 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3013 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
3015 drm_modeset_unlock_all(dev);
3017 amdgpu_fbdev_set_suspend(adev, 0);
3020 drm_kms_helper_poll_enable(dev);
3022 amdgpu_ras_resume(adev);
3025 * Most of the connector probing functions try to acquire runtime pm
3026 * refs to ensure that the GPU is powered on when connector polling is
3027 * performed. Since we're calling this from a runtime PM callback,
3028 * trying to acquire rpm refs will cause us to deadlock.
3030 * Since we're guaranteed to be holding the rpm lock, it's safe to
3031 * temporarily disable the rpm helpers so this doesn't deadlock us.
3034 dev->dev->power.disable_depth++;
3036 if (!amdgpu_device_has_dc_support(adev))
3037 drm_helper_hpd_irq_event(dev);
3039 drm_kms_helper_hotplug_event(dev);
3041 dev->dev->power.disable_depth--;
3043 adev->in_suspend = false;
3049 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
3051 * @adev: amdgpu_device pointer
3053 * The list of all the hardware IPs that make up the asic is walked and
3054 * the check_soft_reset callbacks are run. check_soft_reset determines
3055 * if the asic is still hung or not.
3056 * Returns true if any of the IPs are still in a hung state, false if not.
3058 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
3061 bool asic_hang = false;
3063 if (amdgpu_sriov_vf(adev))
3066 if (amdgpu_asic_need_full_reset(adev))
3069 for (i = 0; i < adev->num_ip_blocks; i++) {
3070 if (!adev->ip_blocks[i].status.valid)
3072 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3073 adev->ip_blocks[i].status.hang =
3074 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3075 if (adev->ip_blocks[i].status.hang) {
3076 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3084 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3086 * @adev: amdgpu_device pointer
3088 * The list of all the hardware IPs that make up the asic is walked and the
3089 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
3090 * handles any IP specific hardware or software state changes that are
3091 * necessary for a soft reset to succeed.
3092 * Returns 0 on success, negative error code on failure.
3094 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3098 for (i = 0; i < adev->num_ip_blocks; i++) {
3099 if (!adev->ip_blocks[i].status.valid)
3101 if (adev->ip_blocks[i].status.hang &&
3102 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3103 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3113 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3115 * @adev: amdgpu_device pointer
3117 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
3118 * reset is necessary to recover.
3119 * Returns true if a full asic reset is required, false if not.
3121 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3125 if (amdgpu_asic_need_full_reset(adev))
3128 for (i = 0; i < adev->num_ip_blocks; i++) {
3129 if (!adev->ip_blocks[i].status.valid)
3131 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3132 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3133 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3134 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3135 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3136 if (adev->ip_blocks[i].status.hang) {
3137 DRM_INFO("Some block need full reset!\n");
3146 * amdgpu_device_ip_soft_reset - do a soft reset
3148 * @adev: amdgpu_device pointer
3150 * The list of all the hardware IPs that make up the asic is walked and the
3151 * soft_reset callbacks are run if the block is hung. soft_reset handles any
3152 * IP specific hardware or software state changes that are necessary to soft
3154 * Returns 0 on success, negative error code on failure.
3156 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3160 for (i = 0; i < adev->num_ip_blocks; i++) {
3161 if (!adev->ip_blocks[i].status.valid)
3163 if (adev->ip_blocks[i].status.hang &&
3164 adev->ip_blocks[i].version->funcs->soft_reset) {
3165 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3175 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3177 * @adev: amdgpu_device pointer
3179 * The list of all the hardware IPs that make up the asic is walked and the
3180 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
3181 * handles any IP specific hardware or software state changes that are
3182 * necessary after the IP has been soft reset.
3183 * Returns 0 on success, negative error code on failure.
3185 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3189 for (i = 0; i < adev->num_ip_blocks; i++) {
3190 if (!adev->ip_blocks[i].status.valid)
3192 if (adev->ip_blocks[i].status.hang &&
3193 adev->ip_blocks[i].version->funcs->post_soft_reset)
3194 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3203 * amdgpu_device_recover_vram - Recover some VRAM contents
3205 * @adev: amdgpu_device pointer
3207 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
3208 * restore things like GPUVM page tables after a GPU reset where
3209 * the contents of VRAM might be lost.
3212 * 0 on success, negative error code on failure.
3214 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3216 struct dma_fence *fence = NULL, *next = NULL;
3217 struct amdgpu_bo *shadow;
3220 if (amdgpu_sriov_runtime(adev))
3221 tmo = msecs_to_jiffies(8000);
3223 tmo = msecs_to_jiffies(100);
3225 DRM_INFO("recover vram bo from shadow start\n");
3226 mutex_lock(&adev->shadow_list_lock);
3227 list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3229 /* No need to recover an evicted BO */
3230 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3231 shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3232 shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3235 r = amdgpu_bo_restore_shadow(shadow, &next);
3240 tmo = dma_fence_wait_timeout(fence, false, tmo);
3241 dma_fence_put(fence);
3246 } else if (tmo < 0) {
3254 mutex_unlock(&adev->shadow_list_lock);
3257 tmo = dma_fence_wait_timeout(fence, false, tmo);
3258 dma_fence_put(fence);
3260 if (r < 0 || tmo <= 0) {
3261 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3265 DRM_INFO("recover vram bo from shadow done\n");
3271 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3273 * @adev: amdgpu device pointer
3274 * @from_hypervisor: request from hypervisor
3276 * do VF FLR and reinitialize Asic
3277 * return 0 means succeeded otherwise failed
3279 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3280 bool from_hypervisor)
3284 if (from_hypervisor)
3285 r = amdgpu_virt_request_full_gpu(adev, true);
3287 r = amdgpu_virt_reset_gpu(adev);
3291 amdgpu_amdkfd_pre_reset(adev);
3293 /* Resume IP prior to SMC */
3294 r = amdgpu_device_ip_reinit_early_sriov(adev);
3298 /* we need recover gart prior to run SMC/CP/SDMA resume */
3299 amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3301 r = amdgpu_device_fw_loading(adev);
3305 /* now we are okay to resume SMC/CP/SDMA */
3306 r = amdgpu_device_ip_reinit_late_sriov(adev);
3310 amdgpu_irq_gpu_reset_resume_helper(adev);
3311 r = amdgpu_ib_ring_tests(adev);
3312 amdgpu_amdkfd_post_reset(adev);
3315 amdgpu_virt_init_data_exchange(adev);
3316 amdgpu_virt_release_full_gpu(adev, true);
3317 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3318 atomic_inc(&adev->vram_lost_counter);
3319 r = amdgpu_device_recover_vram(adev);
3326 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3328 * @adev: amdgpu device pointer
3330 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3333 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3335 if (!amdgpu_device_ip_check_soft_reset(adev)) {
3336 DRM_INFO("Timeout, but no hardware hang detected.\n");
3340 if (amdgpu_gpu_recovery == 0)
3343 if (amdgpu_sriov_vf(adev))
3346 if (amdgpu_gpu_recovery == -1) {
3347 switch (adev->asic_type) {
3353 case CHIP_POLARIS10:
3354 case CHIP_POLARIS11:
3355 case CHIP_POLARIS12:
3369 DRM_INFO("GPU recovery disabled.\n");
3374 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3375 struct amdgpu_job *job,
3376 bool *need_full_reset_arg)
3379 bool need_full_reset = *need_full_reset_arg;
3381 /* block all schedulers and reset given job's ring */
3382 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3383 struct amdgpu_ring *ring = adev->rings[i];
3385 if (!ring || !ring->sched.thread)
3388 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3389 amdgpu_fence_driver_force_completion(ring);
3393 drm_sched_increase_karma(&job->base);
3395 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
3396 if (!amdgpu_sriov_vf(adev)) {
3398 if (!need_full_reset)
3399 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3401 if (!need_full_reset) {
3402 amdgpu_device_ip_pre_soft_reset(adev);
3403 r = amdgpu_device_ip_soft_reset(adev);
3404 amdgpu_device_ip_post_soft_reset(adev);
3405 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3406 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3407 need_full_reset = true;
3411 if (need_full_reset)
3412 r = amdgpu_device_ip_suspend(adev);
3414 *need_full_reset_arg = need_full_reset;
3420 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3421 struct list_head *device_list_handle,
3422 bool *need_full_reset_arg)
3424 struct amdgpu_device *tmp_adev = NULL;
3425 bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3429 * ASIC reset has to be done on all HGMI hive nodes ASAP
3430 * to allow proper links negotiation in FW (within 1 sec)
3432 if (need_full_reset) {
3433 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3434 /* For XGMI run all resets in parallel to speed up the process */
3435 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3436 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3439 r = amdgpu_asic_reset(tmp_adev);
3442 DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s",
3443 r, tmp_adev->ddev->unique);
3448 /* For XGMI wait for all PSP resets to complete before proceed */
3450 list_for_each_entry(tmp_adev, device_list_handle,
3452 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3453 flush_work(&tmp_adev->xgmi_reset_work);
3454 r = tmp_adev->asic_reset_res;
3460 list_for_each_entry(tmp_adev, device_list_handle,
3462 amdgpu_ras_reserve_bad_pages(tmp_adev);
3468 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3469 if (need_full_reset) {
3471 if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3472 DRM_WARN("asic atom init failed!");
3475 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3476 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3480 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3482 DRM_INFO("VRAM is lost due to GPU reset!\n");
3483 atomic_inc(&tmp_adev->vram_lost_counter);
3486 r = amdgpu_gtt_mgr_recover(
3487 &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3491 r = amdgpu_device_fw_loading(tmp_adev);
3495 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3500 amdgpu_device_fill_reset_magic(tmp_adev);
3502 r = amdgpu_device_ip_late_init(tmp_adev);
3507 amdgpu_ras_resume(tmp_adev);
3509 /* Update PSP FW topology after reset */
3510 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3511 r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3518 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3519 r = amdgpu_ib_ring_tests(tmp_adev);
3521 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3522 r = amdgpu_device_ip_suspend(tmp_adev);
3523 need_full_reset = true;
3530 r = amdgpu_device_recover_vram(tmp_adev);
3532 tmp_adev->asic_reset_res = r;
3536 *need_full_reset_arg = need_full_reset;
3540 static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
3543 if (!mutex_trylock(&adev->lock_reset))
3546 mutex_lock(&adev->lock_reset);
3548 atomic_inc(&adev->gpu_reset_counter);
3549 adev->in_gpu_reset = 1;
3550 /* Block kfd: SRIOV would do it separately */
3551 if (!amdgpu_sriov_vf(adev))
3552 amdgpu_amdkfd_pre_reset(adev);
3557 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3559 /*unlock kfd: SRIOV would do it separately */
3560 if (!amdgpu_sriov_vf(adev))
3561 amdgpu_amdkfd_post_reset(adev);
3562 amdgpu_vf_error_trans_all(adev);
3563 adev->in_gpu_reset = 0;
3564 mutex_unlock(&adev->lock_reset);
3569 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3571 * @adev: amdgpu device pointer
3572 * @job: which job trigger hang
3574 * Attempt to reset the GPU if it has hung (all asics).
3575 * Attempt to do soft-reset or full-reset and reinitialize Asic
3576 * Returns 0 for success or an error on failure.
3579 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3580 struct amdgpu_job *job)
3582 struct list_head device_list, *device_list_handle = NULL;
3583 bool need_full_reset, job_signaled;
3584 struct amdgpu_hive_info *hive = NULL;
3585 struct amdgpu_device *tmp_adev = NULL;
3588 need_full_reset = job_signaled = false;
3589 INIT_LIST_HEAD(&device_list);
3591 dev_info(adev->dev, "GPU reset begin!\n");
3593 cancel_delayed_work_sync(&adev->delayed_init_work);
3595 hive = amdgpu_get_xgmi_hive(adev, false);
3598 * Here we trylock to avoid chain of resets executing from
3599 * either trigger by jobs on different adevs in XGMI hive or jobs on
3600 * different schedulers for same device while this TO handler is running.
3601 * We always reset all schedulers for device and all devices for XGMI
3602 * hive so that should take care of them too.
3605 if (hive && !mutex_trylock(&hive->reset_lock)) {
3606 DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
3607 job->base.id, hive->hive_id);
3611 /* Start with adev pre asic reset first for soft reset check.*/
3612 if (!amdgpu_device_lock_adev(adev, !hive)) {
3613 DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
3618 /* Build list of devices to reset */
3619 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3621 amdgpu_device_unlock_adev(adev);
3626 * In case we are in XGMI hive mode device reset is done for all the
3627 * nodes in the hive to retrain all XGMI links and hence the reset
3628 * sequence is executed in loop on all nodes.
3630 device_list_handle = &hive->device_list;
3632 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3633 device_list_handle = &device_list;
3636 /* block all schedulers and reset given job's ring */
3637 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3638 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3639 struct amdgpu_ring *ring = tmp_adev->rings[i];
3641 if (!ring || !ring->sched.thread)
3644 drm_sched_stop(&ring->sched, &job->base);
3650 * Must check guilty signal here since after this point all old
3651 * HW fences are force signaled.
3653 * job->base holds a reference to parent fence
3655 if (job && job->base.s_fence->parent &&
3656 dma_fence_is_signaled(job->base.s_fence->parent))
3657 job_signaled = true;
3659 if (!amdgpu_device_ip_need_full_reset(adev))
3660 device_list_handle = &device_list;
3663 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
3668 /* Guilty job will be freed after this*/
3669 r = amdgpu_device_pre_asic_reset(adev,
3673 /*TODO Should we stop ?*/
3674 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3675 r, adev->ddev->unique);
3676 adev->asic_reset_res = r;
3679 retry: /* Rest of adevs pre asic reset from XGMI hive. */
3680 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3682 if (tmp_adev == adev)
3685 amdgpu_device_lock_adev(tmp_adev, false);
3686 r = amdgpu_device_pre_asic_reset(tmp_adev,
3689 /*TODO Should we stop ?*/
3691 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3692 r, tmp_adev->ddev->unique);
3693 tmp_adev->asic_reset_res = r;
3697 /* Actual ASIC resets if needed.*/
3698 /* TODO Implement XGMI hive reset logic for SRIOV */
3699 if (amdgpu_sriov_vf(adev)) {
3700 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3702 adev->asic_reset_res = r;
3704 r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3705 if (r && r == -EAGAIN)
3711 /* Post ASIC reset for all devs .*/
3712 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3713 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3714 struct amdgpu_ring *ring = tmp_adev->rings[i];
3716 if (!ring || !ring->sched.thread)
3719 /* No point to resubmit jobs if we didn't HW reset*/
3720 if (!tmp_adev->asic_reset_res && !job_signaled)
3721 drm_sched_resubmit_jobs(&ring->sched);
3723 drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
3726 if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
3727 drm_helper_resume_force_mode(tmp_adev->ddev);
3730 tmp_adev->asic_reset_res = 0;
3733 /* bad news, how to tell it to userspace ? */
3734 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3735 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3737 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3740 amdgpu_device_unlock_adev(tmp_adev);
3744 mutex_unlock(&hive->reset_lock);
3747 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3752 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3754 * @adev: amdgpu_device pointer
3756 * Fetchs and stores in the driver the PCIE capabilities (gen speed
3757 * and lanes) of the slot the device is in. Handles APUs and
3758 * virtualized environments where PCIE config space may not be available.
3760 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3762 struct pci_dev *pdev;
3763 enum pci_bus_speed speed_cap, platform_speed_cap;
3764 enum pcie_link_width platform_link_width;
3766 if (amdgpu_pcie_gen_cap)
3767 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3769 if (amdgpu_pcie_lane_cap)
3770 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3772 /* covers APUs as well */
3773 if (pci_is_root_bus(adev->pdev->bus)) {
3774 if (adev->pm.pcie_gen_mask == 0)
3775 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3776 if (adev->pm.pcie_mlw_mask == 0)
3777 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3781 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3784 pcie_bandwidth_available(adev->pdev, NULL,
3785 &platform_speed_cap, &platform_link_width);
3787 if (adev->pm.pcie_gen_mask == 0) {
3790 speed_cap = pcie_get_speed_cap(pdev);
3791 if (speed_cap == PCI_SPEED_UNKNOWN) {
3792 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3793 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3794 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3796 if (speed_cap == PCIE_SPEED_16_0GT)
3797 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3798 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3799 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3800 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3801 else if (speed_cap == PCIE_SPEED_8_0GT)
3802 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3803 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3804 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3805 else if (speed_cap == PCIE_SPEED_5_0GT)
3806 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3807 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3809 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3812 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
3813 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3814 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3816 if (platform_speed_cap == PCIE_SPEED_16_0GT)
3817 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3818 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3819 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3820 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3821 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
3822 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3823 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3824 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3825 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
3826 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3827 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3829 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3833 if (adev->pm.pcie_mlw_mask == 0) {
3834 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3835 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3837 switch (platform_link_width) {
3839 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3840 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3841 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3842 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3843 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3844 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3845 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3848 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3849 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3850 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3851 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3852 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3853 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3856 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3857 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3858 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3859 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3860 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3863 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3864 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3865 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3866 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3869 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3870 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3871 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3874 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3875 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3878 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;