drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/power_supply.h>
  29 #include <linux/kthread.h>
  30 #include <linux/console.h>
  31 #include <linux/slab.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_probe_helper.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <linux/vgaarb.h>
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/efi.h>
  39 #include "amdgpu.h"
  40 #include "amdgpu_trace.h"
  41 #include "amdgpu_i2c.h"
  42 #include "atom.h"
  43 #include "amdgpu_atombios.h"
  44 #include "amdgpu_atomfirmware.h"
  45 #include "amd_pcie.h"
  46 #ifdef CONFIG_DRM_AMDGPU_SI
  47 #include "si.h"
  48 #endif
  49 #ifdef CONFIG_DRM_AMDGPU_CIK
  50 #include "cik.h"
  51 #endif
  52 #include "vi.h"
  53 #include "soc15.h"
  54 #include "bif/bif_4_1_d.h"
  55 #include <linux/pci.h>
  56 #include <linux/firmware.h>
  57 #include "amdgpu_vf_error.h"
  58
  59 #include "amdgpu_amdkfd.h"
  60 #include "amdgpu_pm.h"
  61
  62 #include "amdgpu_xgmi.h"
  63
  64 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
  66 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  67 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
  68 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
  69
  70 #define AMDGPU_RESUME_MS                2000
  71
  72 static const char *amdgpu_asic_name[] = {
  73         "TAHITI",
  74         "PITCAIRN",
  75         "VERDE",
  76         "OLAND",
  77         "HAINAN",
  78         "BONAIRE",
  79         "KAVERI",
  80         "KABINI",
  81         "HAWAII",
  82         "MULLINS",
  83         "TOPAZ",
  84         "TONGA",
  85         "FIJI",
  86         "CARRIZO",
  87         "STONEY",
  88         "POLARIS10",
  89         "POLARIS11",
  90         "POLARIS12",
  91         "VEGAM",
  92         "VEGA10",
  93         "VEGA12",
  94         "VEGA20",
  95         "RAVEN",
  96         "LAST",
  97 };
  98
  99 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
 100
 101 /**
 102  * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control
 103  *
 104  * @dev: drm_device pointer
 105  *
 106  * Returns true if the device is a dGPU with HG/PX power control,
 107  * otherwise return false.
 108  */
 109 bool amdgpu_device_is_px(struct drm_device *dev)
 110 {
 111         struct amdgpu_device *adev = dev->dev_private;
 112
 113         if (adev->flags & AMD_IS_PX)
 114                 return true;
 115         return false;
 116 }
 117
 118 /*
 119  * MMIO register access helper functions.
 120  */
 121 /**
 122  * amdgpu_mm_rreg - read a memory mapped IO register
 123  *
 124  * @adev: amdgpu_device pointer
 125  * @reg: dword aligned register offset
 126  * @acc_flags: access flags which require special behavior
 127  *
 128  * Returns the 32 bit value from the offset specified.
 129  */
 130 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
 131                         uint32_t acc_flags)
 132 {
 133         uint32_t ret;
 134
 135         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 136                 return amdgpu_virt_kiq_rreg(adev, reg);
 137
 138         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 139                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
 140         else {
 141                 unsigned long flags;
 142
 143                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 144                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 145                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 146                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 147         }
 148         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 149         return ret;
 150 }
 151
 152 /*
 153  * MMIO register read with bytes helper functions
 154  * @offset:bytes offset from MMIO start
 155  *
 156 */
 157
 158 /**
 159  * amdgpu_mm_rreg8 - read a memory mapped IO register
 160  *
 161  * @adev: amdgpu_device pointer
 162  * @offset: byte aligned register offset
 163  *
 164  * Returns the 8 bit value from the offset specified.
 165  */
 166 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) {
 167         if (offset < adev->rmmio_size)
 168                 return (readb(adev->rmmio + offset));
 169         BUG();
 170 }
 171
 172 /*
 173  * MMIO register write with bytes helper functions
 174  * @offset:bytes offset from MMIO start
 175  * @value: the value want to be written to the register
 176  *
 177 */
 178 /**
 179  * amdgpu_mm_wreg8 - read a memory mapped IO register
 180  *
 181  * @adev: amdgpu_device pointer
 182  * @offset: byte aligned register offset
 183  * @value: 8 bit value to write
 184  *
 185  * Writes the value specified to the offset specified.
 186  */
 187 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) {
 188         if (offset < adev->rmmio_size)
 189                 writeb(value, adev->rmmio + offset);
 190         else
 191                 BUG();
 192 }
 193
 194 /**
 195  * amdgpu_mm_wreg - write to a memory mapped IO register
 196  *
 197  * @adev: amdgpu_device pointer
 198  * @reg: dword aligned register offset
 199  * @v: 32 bit value to write to the register
 200  * @acc_flags: access flags which require special behavior
 201  *
 202  * Writes the value specified to the offset specified.
 203  */
 204 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 205                     uint32_t acc_flags)
 206 {
 207         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 208
 209         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 210                 adev->last_mm_index = v;
 211         }
 212
 213         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
 214                 return amdgpu_virt_kiq_wreg(adev, reg, v);
 215
 216         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
 217                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 218         else {
 219                 unsigned long flags;
 220
 221                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 222                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 223                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 224                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 225         }
 226
 227         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 228                 udelay(500);
 229         }
 230 }
 231
 232 /**
 233  * amdgpu_io_rreg - read an IO register
 234  *
 235  * @adev: amdgpu_device pointer
 236  * @reg: dword aligned register offset
 237  *
 238  * Returns the 32 bit value from the offset specified.
 239  */
 240 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 241 {
 242         if ((reg * 4) < adev->rio_mem_size)
 243                 return ioread32(adev->rio_mem + (reg * 4));
 244         else {
 245                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 246                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 247         }
 248 }
 249
 250 /**
 251  * amdgpu_io_wreg - write to an IO register
 252  *
 253  * @adev: amdgpu_device pointer
 254  * @reg: dword aligned register offset
 255  * @v: 32 bit value to write to the register
 256  *
 257  * Writes the value specified to the offset specified.
 258  */
 259 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 260 {
 261         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
 262                 adev->last_mm_index = v;
 263         }
 264
 265         if ((reg * 4) < adev->rio_mem_size)
 266                 iowrite32(v, adev->rio_mem + (reg * 4));
 267         else {
 268                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 269                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 270         }
 271
 272         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
 273                 udelay(500);
 274         }
 275 }
 276
 277 /**
 278  * amdgpu_mm_rdoorbell - read a doorbell dword
 279  *
 280  * @adev: amdgpu_device pointer
 281  * @index: doorbell index
 282  *
 283  * Returns the value in the doorbell aperture at the
 284  * requested doorbell index (CIK).
 285  */
 286 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 287 {
 288         if (index < adev->doorbell.num_doorbells) {
 289                 return readl(adev->doorbell.ptr + index);
 290         } else {
 291                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 292                 return 0;
 293         }
 294 }
 295
 296 /**
 297  * amdgpu_mm_wdoorbell - write a doorbell dword
 298  *
 299  * @adev: amdgpu_device pointer
 300  * @index: doorbell index
 301  * @v: value to write
 302  *
 303  * Writes @v to the doorbell aperture at the
 304  * requested doorbell index (CIK).
 305  */
 306 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 307 {
 308         if (index < adev->doorbell.num_doorbells) {
 309                 writel(v, adev->doorbell.ptr + index);
 310         } else {
 311                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 312         }
 313 }
 314
 315 /**
 316  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
 317  *
 318  * @adev: amdgpu_device pointer
 319  * @index: doorbell index
 320  *
 321  * Returns the value in the doorbell aperture at the
 322  * requested doorbell index (VEGA10+).
 323  */
 324 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
 325 {
 326         if (index < adev->doorbell.num_doorbells) {
 327                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
 328         } else {
 329                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 330                 return 0;
 331         }
 332 }
 333
 334 /**
 335  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
 336  *
 337  * @adev: amdgpu_device pointer
 338  * @index: doorbell index
 339  * @v: value to write
 340  *
 341  * Writes @v to the doorbell aperture at the
 342  * requested doorbell index (VEGA10+).
 343  */
 344 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
 345 {
 346         if (index < adev->doorbell.num_doorbells) {
 347                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
 348         } else {
 349                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 350         }
 351 }
 352
 353 /**
 354  * amdgpu_invalid_rreg - dummy reg read function
 355  *
 356  * @adev: amdgpu device pointer
 357  * @reg: offset of register
 358  *
 359  * Dummy register read function.  Used for register blocks
 360  * that certain asics don't have (all asics).
 361  * Returns the value in the register.
 362  */
 363 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 364 {
 365         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 366         BUG();
 367         return 0;
 368 }
 369
 370 /**
 371  * amdgpu_invalid_wreg - dummy reg write function
 372  *
 373  * @adev: amdgpu device pointer
 374  * @reg: offset of register
 375  * @v: value to write to the register
 376  *
 377  * Dummy register read function.  Used for register blocks
 378  * that certain asics don't have (all asics).
 379  */
 380 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 381 {
 382         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 383                   reg, v);
 384         BUG();
 385 }
 386
 387 /**
 388  * amdgpu_block_invalid_rreg - dummy reg read function
 389  *
 390  * @adev: amdgpu device pointer
 391  * @block: offset of instance
 392  * @reg: offset of register
 393  *
 394  * Dummy register read function.  Used for register blocks
 395  * that certain asics don't have (all asics).
 396  * Returns the value in the register.
 397  */
 398 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 399                                           uint32_t block, uint32_t reg)
 400 {
 401         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 402                   reg, block);
 403         BUG();
 404         return 0;
 405 }
 406
 407 /**
 408  * amdgpu_block_invalid_wreg - dummy reg write function
 409  *
 410  * @adev: amdgpu device pointer
 411  * @block: offset of instance
 412  * @reg: offset of register
 413  * @v: value to write to the register
 414  *
 415  * Dummy register read function.  Used for register blocks
 416  * that certain asics don't have (all asics).
 417  */
 418 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 419                                       uint32_t block,
 420                                       uint32_t reg, uint32_t v)
 421 {
 422         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 423                   reg, block, v);
 424         BUG();
 425 }
 426
 427 /**
 428  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
 429  *
 430  * @adev: amdgpu device pointer
 431  *
 432  * Allocates a scratch page of VRAM for use by various things in the
 433  * driver.
 434  */
 435 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 436 {
 437         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
 438                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 439                                        &adev->vram_scratch.robj,
 440                                        &adev->vram_scratch.gpu_addr,
 441                                        (void **)&adev->vram_scratch.ptr);
 442 }
 443
 444 /**
 445  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
 446  *
 447  * @adev: amdgpu device pointer
 448  *
 449  * Frees the VRAM scratch page.
 450  */
 451 static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 452 {
 453         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
 454 }
 455
 456 /**
 457  * amdgpu_device_program_register_sequence - program an array of registers.
 458  *
 459  * @adev: amdgpu_device pointer
 460  * @registers: pointer to the register array
 461  * @array_size: size of the register array
 462  *
 463  * Programs an array or registers with and and or masks.
 464  * This is a helper for setting golden registers.
 465  */
 466 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
 467                                              const u32 *registers,
 468                                              const u32 array_size)
 469 {
 470         u32 tmp, reg, and_mask, or_mask;
 471         int i;
 472
 473         if (array_size % 3)
 474                 return;
 475
 476         for (i = 0; i < array_size; i +=3) {
 477                 reg = registers[i + 0];
 478                 and_mask = registers[i + 1];
 479                 or_mask = registers[i + 2];
 480
 481                 if (and_mask == 0xffffffff) {
 482                         tmp = or_mask;
 483                 } else {
 484                         tmp = RREG32(reg);
 485                         tmp &= ~and_mask;
 486                         tmp |= or_mask;
 487                 }
 488                 WREG32(reg, tmp);
 489         }
 490 }
 491
 492 /**
 493  * amdgpu_device_pci_config_reset - reset the GPU
 494  *
 495  * @adev: amdgpu_device pointer
 496  *
 497  * Resets the GPU using the pci config reset sequence.
 498  * Only applicable to asics prior to vega10.
 499  */
 500 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
 501 {
 502         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 503 }
 504
 505 /*
 506  * GPU doorbell aperture helpers function.
 507  */
 508 /**
 509  * amdgpu_device_doorbell_init - Init doorbell driver information.
 510  *
 511  * @adev: amdgpu_device pointer
 512  *
 513  * Init doorbell driver information (CIK)
 514  * Returns 0 on success, error on failure.
 515  */
 516 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
 517 {
 518
 519         /* No doorbell on SI hardware generation */
 520         if (adev->asic_type < CHIP_BONAIRE) {
 521                 adev->doorbell.base = 0;
 522                 adev->doorbell.size = 0;
 523                 adev->doorbell.num_doorbells = 0;
 524                 adev->doorbell.ptr = NULL;
 525                 return 0;
 526         }
 527
 528         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
 529                 return -EINVAL;
 530
 531         amdgpu_asic_init_doorbell_index(adev);
 532
 533         /* doorbell bar mapping */
 534         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 535         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 536
 537         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 538                                              adev->doorbell_index.max_assignment+1);
 539         if (adev->doorbell.num_doorbells == 0)
 540                 return -EINVAL;
 541
 542         /* For Vega, reserve and map two pages on doorbell BAR since SDMA
 543          * paging queue doorbell use the second page. The
 544          * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
 545          * doorbells are in the first page. So with paging queue enabled,
 546          * the max num_doorbells should + 1 page (0x400 in dword)
 547          */
 548         if (adev->asic_type >= CHIP_VEGA10)
 549                 adev->doorbell.num_doorbells += 0x400;
 550
 551         adev->doorbell.ptr = ioremap(adev->doorbell.base,
 552                                      adev->doorbell.num_doorbells *
 553                                      sizeof(u32));
 554         if (adev->doorbell.ptr == NULL)
 555                 return -ENOMEM;
 556
 557         return 0;
 558 }
 559
 560 /**
 561  * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
 562  *
 563  * @adev: amdgpu_device pointer
 564  *
 565  * Tear down doorbell driver information (CIK)
 566  */
 567 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
 568 {
 569         iounmap(adev->doorbell.ptr);
 570         adev->doorbell.ptr = NULL;
 571 }
 572
 573
 574
 575 /*
 576  * amdgpu_device_wb_*()
 577  * Writeback is the method by which the GPU updates special pages in memory
 578  * with the status of certain GPU events (fences, ring pointers,etc.).
 579  */
 580
 581 /**
 582  * amdgpu_device_wb_fini - Disable Writeback and free memory
 583  *
 584  * @adev: amdgpu_device pointer
 585  *
 586  * Disables Writeback and frees the Writeback memory (all asics).
 587  * Used at driver shutdown.
 588  */
 589 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
 590 {
 591         if (adev->wb.wb_obj) {
 592                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 593                                       &adev->wb.gpu_addr,
 594                                       (void **)&adev->wb.wb);
 595                 adev->wb.wb_obj = NULL;
 596         }
 597 }
 598
 599 /**
 600  * amdgpu_device_wb_init- Init Writeback driver info and allocate memory
 601  *
 602  * @adev: amdgpu_device pointer
 603  *
 604  * Initializes writeback and allocates writeback memory (all asics).
 605  * Used at driver startup.
 606  * Returns 0 on success or an -error on failure.
 607  */
 608 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
 609 {
 610         int r;
 611
 612         if (adev->wb.wb_obj == NULL) {
 613                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
 614                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
 615                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 616                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 617                                             (void **)&adev->wb.wb);
 618                 if (r) {
 619                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 620                         return r;
 621                 }
 622
 623                 adev->wb.num_wb = AMDGPU_MAX_WB;
 624                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 625
 626                 /* clear wb memory */
 627                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
 628         }
 629
 630         return 0;
 631 }
 632
 633 /**
 634  * amdgpu_device_wb_get - Allocate a wb entry
 635  *
 636  * @adev: amdgpu_device pointer
 637  * @wb: wb index
 638  *
 639  * Allocate a wb slot for use by the driver (all asics).
 640  * Returns 0 on success or -EINVAL on failure.
 641  */
 642 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
 643 {
 644         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 645
 646         if (offset < adev->wb.num_wb) {
 647                 __set_bit(offset, adev->wb.used);
 648                 *wb = offset << 3; /* convert to dw offset */
 649                 return 0;
 650         } else {
 651                 return -EINVAL;
 652         }
 653 }
 654
 655 /**
 656  * amdgpu_device_wb_free - Free a wb entry
 657  *
 658  * @adev: amdgpu_device pointer
 659  * @wb: wb index
 660  *
 661  * Free a wb slot allocated for use by the driver (all asics)
 662  */
 663 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 664 {
 665         wb >>= 3;
 666         if (wb < adev->wb.num_wb)
 667                 __clear_bit(wb, adev->wb.used);
 668 }
 669
 670 /**
 671  * amdgpu_device_resize_fb_bar - try to resize FB BAR
 672  *
 673  * @adev: amdgpu_device pointer
 674  *
 675  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
 676  * to fail, but if any of the BARs is not accessible after the size we abort
 677  * driver loading by returning -ENODEV.
 678  */
 679 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
 680 {
 681         u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
 682         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
 683         struct pci_bus *root;
 684         struct resource *res;
 685         unsigned i;
 686         u16 cmd;
 687         int r;
 688
 689         /* Bypass for VF */
 690         if (amdgpu_sriov_vf(adev))
 691                 return 0;
 692
 693         /* Check if the root BUS has 64bit memory resources */
 694         root = adev->pdev->bus;
 695         while (root->parent)
 696                 root = root->parent;
 697
 698         pci_bus_for_each_resource(root, res, i) {
 699                 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
 700                     res->start > 0x100000000ull)
 701                         break;
 702         }
 703
 704         /* Trying to resize is pointless without a root hub window above 4GB */
 705         if (!res)
 706                 return 0;
 707
 708         /* Disable memory decoding while we change the BAR addresses and size */
 709         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
 710         pci_write_config_word(adev->pdev, PCI_COMMAND,
 711                               cmd & ~PCI_COMMAND_MEMORY);
 712
 713         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
 714         amdgpu_device_doorbell_fini(adev);
 715         if (adev->asic_type >= CHIP_BONAIRE)
 716                 pci_release_resource(adev->pdev, 2);
 717
 718         pci_release_resource(adev->pdev, 0);
 719
 720         r = pci_resize_resource(adev->pdev, 0, rbar_size);
 721         if (r == -ENOSPC)
 722                 DRM_INFO("Not enough PCI address space for a large BAR.");
 723         else if (r && r != -ENOTSUPP)
 724                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
 725
 726         pci_assign_unassigned_bus_resources(adev->pdev->bus);
 727
 728         /* When the doorbell or fb BAR isn't available we have no chance of
 729          * using the device.
 730          */
 731         r = amdgpu_device_doorbell_init(adev);
 732         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
 733                 return -ENODEV;
 734
 735         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
 736
 737         return 0;
 738 }
 739
 740 /*
 741  * GPU helpers function.
 742  */
 743 /**
 744  * amdgpu_device_need_post - check if the hw need post or not
 745  *
 746  * @adev: amdgpu_device pointer
 747  *
 748  * Check if the asic has been initialized (all asics) at driver startup
 749  * or post is needed if  hw reset is performed.
 750  * Returns true if need or false if not.
 751  */
 752 bool amdgpu_device_need_post(struct amdgpu_device *adev)
 753 {
 754         uint32_t reg;
 755
 756         if (amdgpu_sriov_vf(adev))
 757                 return false;
 758
 759         if (amdgpu_passthrough(adev)) {
 760                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
 761                  * some old smc fw still need driver do vPost otherwise gpu hang, while
 762                  * those smc fw version above 22.15 doesn't have this flaw, so we force
 763                  * vpost executed for smc version below 22.15
 764                  */
 765                 if (adev->asic_type == CHIP_FIJI) {
 766                         int err;
 767                         uint32_t fw_ver;
 768                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 769                         /* force vPost if error occured */
 770                         if (err)
 771                                 return true;
 772
 773                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 774                         if (fw_ver < 0x00160e00)
 775                                 return true;
 776                 }
 777         }
 778
 779         if (adev->has_hw_reset) {
 780                 adev->has_hw_reset = false;
 781                 return true;
 782         }
 783
 784         /* bios scratch used on CIK+ */
 785         if (adev->asic_type >= CHIP_BONAIRE)
 786                 return amdgpu_atombios_scratch_need_asic_init(adev);
 787
 788         /* check MEM_SIZE for older asics */
 789         reg = amdgpu_asic_get_config_memsize(adev);
 790
 791         if ((reg != 0) && (reg != 0xffffffff))
 792                 return false;
 793
 794         return true;
 795 }
 796
 797 /* if we get transitioned to only one device, take VGA back */
 798 /**
 799  * amdgpu_device_vga_set_decode - enable/disable vga decode
 800  *
 801  * @cookie: amdgpu_device pointer
 802  * @state: enable/disable vga decode
 803  *
 804  * Enable/disable vga decode (all asics).
 805  * Returns VGA resource flags.
 806  */
 807 static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state)
 808 {
 809         struct amdgpu_device *adev = cookie;
 810         amdgpu_asic_set_vga_state(adev, state);
 811         if (state)
 812                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 813                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 814         else
 815                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 816 }
 817
 818 /**
 819  * amdgpu_device_check_block_size - validate the vm block size
 820  *
 821  * @adev: amdgpu_device pointer
 822  *
 823  * Validates the vm block size specified via module parameter.
 824  * The vm block size defines number of bits in page table versus page directory,
 825  * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 826  * page table and the remaining bits are in the page directory.
 827  */
 828 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
 829 {
 830         /* defines number of bits in page table versus page directory,
 831          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 832          * page table and the remaining bits are in the page directory */
 833         if (amdgpu_vm_block_size == -1)
 834                 return;
 835
 836         if (amdgpu_vm_block_size < 9) {
 837                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 838                          amdgpu_vm_block_size);
 839                 amdgpu_vm_block_size = -1;
 840         }
 841 }
 842
 843 /**
 844  * amdgpu_device_check_vm_size - validate the vm size
 845  *
 846  * @adev: amdgpu_device pointer
 847  *
 848  * Validates the vm size in GB specified via module parameter.
 849  * The VM size is the size of the GPU virtual memory space in GB.
 850  */
 851 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
 852 {
 853         /* no need to check the default value */
 854         if (amdgpu_vm_size == -1)
 855                 return;
 856
 857         if (amdgpu_vm_size < 1) {
 858                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 859                          amdgpu_vm_size);
 860                 amdgpu_vm_size = -1;
 861         }
 862 }
 863
 864 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
 865 {
 866         struct sysinfo si;
 867         bool is_os_64 = (sizeof(void *) == 8) ? true : false;
 868         uint64_t total_memory;
 869         uint64_t dram_size_seven_GB = 0x1B8000000;
 870         uint64_t dram_size_three_GB = 0xB8000000;
 871
 872         if (amdgpu_smu_memory_pool_size == 0)
 873                 return;
 874
 875         if (!is_os_64) {
 876                 DRM_WARN("Not 64-bit OS, feature not supported\n");
 877                 goto def_value;
 878         }
 879         si_meminfo(&si);
 880         total_memory = (uint64_t)si.totalram * si.mem_unit;
 881
 882         if ((amdgpu_smu_memory_pool_size == 1) ||
 883                 (amdgpu_smu_memory_pool_size == 2)) {
 884                 if (total_memory < dram_size_three_GB)
 885                         goto def_value1;
 886         } else if ((amdgpu_smu_memory_pool_size == 4) ||
 887                 (amdgpu_smu_memory_pool_size == 8)) {
 888                 if (total_memory < dram_size_seven_GB)
 889                         goto def_value1;
 890         } else {
 891                 DRM_WARN("Smu memory pool size not supported\n");
 892                 goto def_value;
 893         }
 894         adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
 895
 896         return;
 897
 898 def_value1:
 899         DRM_WARN("No enough system memory\n");
 900 def_value:
 901         adev->pm.smu_prv_buffer_size = 0;
 902 }
 903
 904 /**
 905  * amdgpu_device_check_arguments - validate module params
 906  *
 907  * @adev: amdgpu_device pointer
 908  *
 909  * Validates certain module parameters and updates
 910  * the associated values used by the driver (all asics).
 911  */
 912 static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
 913 {
 914         if (amdgpu_sched_jobs < 4) {
 915                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 916                          amdgpu_sched_jobs);
 917                 amdgpu_sched_jobs = 4;
 918         } else if (!is_power_of_2(amdgpu_sched_jobs)){
 919                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 920                          amdgpu_sched_jobs);
 921                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 922         }
 923
 924         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
 925                 /* gart size must be greater or equal to 32M */
 926                 dev_warn(adev->dev, "gart size (%d) too small\n",
 927                          amdgpu_gart_size);
 928                 amdgpu_gart_size = -1;
 929         }
 930
 931         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
 932                 /* gtt size must be greater or equal to 32M */
 933                 dev_warn(adev->dev, "gtt size (%d) too small\n",
 934                                  amdgpu_gtt_size);
 935                 amdgpu_gtt_size = -1;
 936         }
 937
 938         /* valid range is between 4 and 9 inclusive */
 939         if (amdgpu_vm_fragment_size != -1 &&
 940             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
 941                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
 942                 amdgpu_vm_fragment_size = -1;
 943         }
 944
 945         amdgpu_device_check_smu_prv_buffer_size(adev);
 946
 947         amdgpu_device_check_vm_size(adev);
 948
 949         amdgpu_device_check_block_size(adev);
 950
 951         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
 952             !is_power_of_2(amdgpu_vram_page_split))) {
 953                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
 954                          amdgpu_vram_page_split);
 955                 amdgpu_vram_page_split = 1024;
 956         }
 957
 958         if (amdgpu_lockup_timeout == 0) {
 959                 dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
 960                 amdgpu_lockup_timeout = 10000;
 961         }
 962
 963         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 964 }
 965
 966 /**
 967  * amdgpu_switcheroo_set_state - set switcheroo state
 968  *
 969  * @pdev: pci dev pointer
 970  * @state: vga_switcheroo state
 971  *
 972  * Callback for the switcheroo driver.  Suspends or resumes the
 973  * the asics before or after it is powered up using ACPI methods.
 974  */
 975 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 976 {
 977         struct drm_device *dev = pci_get_drvdata(pdev);
 978
 979         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
 980                 return;
 981
 982         if (state == VGA_SWITCHEROO_ON) {
 983                 pr_info("amdgpu: switched on\n");
 984                 /* don't suspend or resume card normally */
 985                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 986
 987                 amdgpu_device_resume(dev, true, true);
 988
 989                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 990                 drm_kms_helper_poll_enable(dev);
 991         } else {
 992                 pr_info("amdgpu: switched off\n");
 993                 drm_kms_helper_poll_disable(dev);
 994                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 995                 amdgpu_device_suspend(dev, true, true);
 996                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 997         }
 998 }
 999
1000 /**
1001  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1002  *
1003  * @pdev: pci dev pointer
1004  *
1005  * Callback for the switcheroo driver.  Check of the switcheroo
1006  * state can be changed.
1007  * Returns true if the state can be changed, false if not.
1008  */
1009 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1010 {
1011         struct drm_device *dev = pci_get_drvdata(pdev);
1012
1013         /*
1014         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1015         * locking inversion with the driver load path. And the access here is
1016         * completely racy anyway. So don't bother with locking for now.
1017         */
1018         return dev->open_count == 0;
1019 }
1020
1021 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1022         .set_gpu_state = amdgpu_switcheroo_set_state,
1023         .reprobe = NULL,
1024         .can_switch = amdgpu_switcheroo_can_switch,
1025 };
1026
1027 /**
1028  * amdgpu_device_ip_set_clockgating_state - set the CG state
1029  *
1030  * @dev: amdgpu_device pointer
1031  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1032  * @state: clockgating state (gate or ungate)
1033  *
1034  * Sets the requested clockgating state for all instances of
1035  * the hardware IP specified.
1036  * Returns the error code from the last instance.
1037  */
1038 int amdgpu_device_ip_set_clockgating_state(void *dev,
1039                                            enum amd_ip_block_type block_type,
1040                                            enum amd_clockgating_state state)
1041 {
1042         struct amdgpu_device *adev = dev;
1043         int i, r = 0;
1044
1045         for (i = 0; i < adev->num_ip_blocks; i++) {
1046                 if (!adev->ip_blocks[i].status.valid)
1047                         continue;
1048                 if (adev->ip_blocks[i].version->type != block_type)
1049                         continue;
1050                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1051                         continue;
1052                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1053                         (void *)adev, state);
1054                 if (r)
1055                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1056                                   adev->ip_blocks[i].version->funcs->name, r);
1057         }
1058         return r;
1059 }
1060
1061 /**
1062  * amdgpu_device_ip_set_powergating_state - set the PG state
1063  *
1064  * @dev: amdgpu_device pointer
1065  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1066  * @state: powergating state (gate or ungate)
1067  *
1068  * Sets the requested powergating state for all instances of
1069  * the hardware IP specified.
1070  * Returns the error code from the last instance.
1071  */
1072 int amdgpu_device_ip_set_powergating_state(void *dev,
1073                                            enum amd_ip_block_type block_type,
1074                                            enum amd_powergating_state state)
1075 {
1076         struct amdgpu_device *adev = dev;
1077         int i, r = 0;
1078
1079         for (i = 0; i < adev->num_ip_blocks; i++) {
1080                 if (!adev->ip_blocks[i].status.valid)
1081                         continue;
1082                 if (adev->ip_blocks[i].version->type != block_type)
1083                         continue;
1084                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1085                         continue;
1086                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1087                         (void *)adev, state);
1088                 if (r)
1089                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1090                                   adev->ip_blocks[i].version->funcs->name, r);
1091         }
1092         return r;
1093 }
1094
1095 /**
1096  * amdgpu_device_ip_get_clockgating_state - get the CG state
1097  *
1098  * @adev: amdgpu_device pointer
1099  * @flags: clockgating feature flags
1100  *
1101  * Walks the list of IPs on the device and updates the clockgating
1102  * flags for each IP.
1103  * Updates @flags with the feature flags for each hardware IP where
1104  * clockgating is enabled.
1105  */
1106 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1107                                             u32 *flags)
1108 {
1109         int i;
1110
1111         for (i = 0; i < adev->num_ip_blocks; i++) {
1112                 if (!adev->ip_blocks[i].status.valid)
1113                         continue;
1114                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1115                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1116         }
1117 }
1118
1119 /**
1120  * amdgpu_device_ip_wait_for_idle - wait for idle
1121  *
1122  * @adev: amdgpu_device pointer
1123  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1124  *
1125  * Waits for the request hardware IP to be idle.
1126  * Returns 0 for success or a negative error code on failure.
1127  */
1128 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1129                                    enum amd_ip_block_type block_type)
1130 {
1131         int i, r;
1132
1133         for (i = 0; i < adev->num_ip_blocks; i++) {
1134                 if (!adev->ip_blocks[i].status.valid)
1135                         continue;
1136                 if (adev->ip_blocks[i].version->type == block_type) {
1137                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1138                         if (r)
1139                                 return r;
1140                         break;
1141                 }
1142         }
1143         return 0;
1144
1145 }
1146
1147 /**
1148  * amdgpu_device_ip_is_idle - is the hardware IP idle
1149  *
1150  * @adev: amdgpu_device pointer
1151  * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1152  *
1153  * Check if the hardware IP is idle or not.
1154  * Returns true if it the IP is idle, false if not.
1155  */
1156 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1157                               enum amd_ip_block_type block_type)
1158 {
1159         int i;
1160
1161         for (i = 0; i < adev->num_ip_blocks; i++) {
1162                 if (!adev->ip_blocks[i].status.valid)
1163                         continue;
1164                 if (adev->ip_blocks[i].version->type == block_type)
1165                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1166         }
1167         return true;
1168
1169 }
1170
1171 /**
1172  * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1173  *
1174  * @adev: amdgpu_device pointer
1175  * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1176  *
1177  * Returns a pointer to the hardware IP block structure
1178  * if it exists for the asic, otherwise NULL.
1179  */
1180 struct amdgpu_ip_block *
1181 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1182                               enum amd_ip_block_type type)
1183 {
1184         int i;
1185
1186         for (i = 0; i < adev->num_ip_blocks; i++)
1187                 if (adev->ip_blocks[i].version->type == type)
1188                         return &adev->ip_blocks[i];
1189
1190         return NULL;
1191 }
1192
1193 /**
1194  * amdgpu_device_ip_block_version_cmp
1195  *
1196  * @adev: amdgpu_device pointer
1197  * @type: enum amd_ip_block_type
1198  * @major: major version
1199  * @minor: minor version
1200  *
1201  * return 0 if equal or greater
1202  * return 1 if smaller or the ip_block doesn't exist
1203  */
1204 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1205                                        enum amd_ip_block_type type,
1206                                        u32 major, u32 minor)
1207 {
1208         struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1209
1210         if (ip_block && ((ip_block->version->major > major) ||
1211                         ((ip_block->version->major == major) &&
1212                         (ip_block->version->minor >= minor))))
1213                 return 0;
1214
1215         return 1;
1216 }
1217
1218 /**
1219  * amdgpu_device_ip_block_add
1220  *
1221  * @adev: amdgpu_device pointer
1222  * @ip_block_version: pointer to the IP to add
1223  *
1224  * Adds the IP block driver information to the collection of IPs
1225  * on the asic.
1226  */
1227 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1228                                const struct amdgpu_ip_block_version *ip_block_version)
1229 {
1230         if (!ip_block_version)
1231                 return -EINVAL;
1232
1233         DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1234                   ip_block_version->funcs->name);
1235
1236         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1237
1238         return 0;
1239 }
1240
1241 /**
1242  * amdgpu_device_enable_virtual_display - enable virtual display feature
1243  *
1244  * @adev: amdgpu_device pointer
1245  *
1246  * Enabled the virtual display feature if the user has enabled it via
1247  * the module parameter virtual_display.  This feature provides a virtual
1248  * display hardware on headless boards or in virtualized environments.
1249  * This function parses and validates the configuration string specified by
1250  * the user and configues the virtual display configuration (number of
1251  * virtual connectors, crtcs, etc.) specified.
1252  */
1253 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1254 {
1255         adev->enable_virtual_display = false;
1256
1257         if (amdgpu_virtual_display) {
1258                 struct drm_device *ddev = adev->ddev;
1259                 const char *pci_address_name = pci_name(ddev->pdev);
1260                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1261
1262                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1263                 pciaddstr_tmp = pciaddstr;
1264                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1265                         pciaddname = strsep(&pciaddname_tmp, ",");
1266                         if (!strcmp("all", pciaddname)
1267                             || !strcmp(pci_address_name, pciaddname)) {
1268                                 long num_crtc;
1269                                 int res = -1;
1270
1271                                 adev->enable_virtual_display = true;
1272
1273                                 if (pciaddname_tmp)
1274                                         res = kstrtol(pciaddname_tmp, 10,
1275                                                       &num_crtc);
1276
1277                                 if (!res) {
1278                                         if (num_crtc < 1)
1279                                                 num_crtc = 1;
1280                                         if (num_crtc > 6)
1281                                                 num_crtc = 6;
1282                                         adev->mode_info.num_crtc = num_crtc;
1283                                 } else {
1284                                         adev->mode_info.num_crtc = 1;
1285                                 }
1286                                 break;
1287                         }
1288                 }
1289
1290                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1291                          amdgpu_virtual_display, pci_address_name,
1292                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1293
1294                 kfree(pciaddstr);
1295         }
1296 }
1297
1298 /**
1299  * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1300  *
1301  * @adev: amdgpu_device pointer
1302  *
1303  * Parses the asic configuration parameters specified in the gpu info
1304  * firmware and makes them availale to the driver for use in configuring
1305  * the asic.
1306  * Returns 0 on success, -EINVAL on failure.
1307  */
1308 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1309 {
1310         const char *chip_name;
1311         char fw_name[30];
1312         int err;
1313         const struct gpu_info_firmware_header_v1_0 *hdr;
1314
1315         adev->firmware.gpu_info_fw = NULL;
1316
1317         switch (adev->asic_type) {
1318         case CHIP_TOPAZ:
1319         case CHIP_TONGA:
1320         case CHIP_FIJI:
1321         case CHIP_POLARIS10:
1322         case CHIP_POLARIS11:
1323         case CHIP_POLARIS12:
1324         case CHIP_VEGAM:
1325         case CHIP_CARRIZO:
1326         case CHIP_STONEY:
1327 #ifdef CONFIG_DRM_AMDGPU_SI
1328         case CHIP_VERDE:
1329         case CHIP_TAHITI:
1330         case CHIP_PITCAIRN:
1331         case CHIP_OLAND:
1332         case CHIP_HAINAN:
1333 #endif
1334 #ifdef CONFIG_DRM_AMDGPU_CIK
1335         case CHIP_BONAIRE:
1336         case CHIP_HAWAII:
1337         case CHIP_KAVERI:
1338         case CHIP_KABINI:
1339         case CHIP_MULLINS:
1340 #endif
1341         case CHIP_VEGA20:
1342         default:
1343                 return 0;
1344         case CHIP_VEGA10:
1345                 chip_name = "vega10";
1346                 break;
1347         case CHIP_VEGA12:
1348                 chip_name = "vega12";
1349                 break;
1350         case CHIP_RAVEN:
1351                 if (adev->rev_id >= 8)
1352                         chip_name = "raven2";
1353                 else if (adev->pdev->device == 0x15d8)
1354                         chip_name = "picasso";
1355                 else
1356                         chip_name = "raven";
1357                 break;
1358         }
1359
1360         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1361         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1362         if (err) {
1363                 dev_err(adev->dev,
1364                         "Failed to load gpu_info firmware \"%s\"\n",
1365                         fw_name);
1366                 goto out;
1367         }
1368         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1369         if (err) {
1370                 dev_err(adev->dev,
1371                         "Failed to validate gpu_info firmware \"%s\"\n",
1372                         fw_name);
1373                 goto out;
1374         }
1375
1376         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1377         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1378
1379         switch (hdr->version_major) {
1380         case 1:
1381         {
1382                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1383                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1384                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1385
1386                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1387                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1388                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1389                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1390                 adev->gfx.config.max_texture_channel_caches =
1391                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1392                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1393                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1394                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1395                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1396                 adev->gfx.config.double_offchip_lds_buf =
1397                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1398                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1399                 adev->gfx.cu_info.max_waves_per_simd =
1400                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1401                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1402                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1403                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1404                 break;
1405         }
1406         default:
1407                 dev_err(adev->dev,
1408                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1409                 err = -EINVAL;
1410                 goto out;
1411         }
1412 out:
1413         return err;
1414 }
1415
1416 /**
1417  * amdgpu_device_ip_early_init - run early init for hardware IPs
1418  *
1419  * @adev: amdgpu_device pointer
1420  *
1421  * Early initialization pass for hardware IPs.  The hardware IPs that make
1422  * up each asic are discovered each IP's early_init callback is run.  This
1423  * is the first stage in initializing the asic.
1424  * Returns 0 on success, negative error code on failure.
1425  */
1426 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
1427 {
1428         int i, r;
1429
1430         amdgpu_device_enable_virtual_display(adev);
1431
1432         switch (adev->asic_type) {
1433         case CHIP_TOPAZ:
1434         case CHIP_TONGA:
1435         case CHIP_FIJI:
1436         case CHIP_POLARIS10:
1437         case CHIP_POLARIS11:
1438         case CHIP_POLARIS12:
1439         case CHIP_VEGAM:
1440         case CHIP_CARRIZO:
1441         case CHIP_STONEY:
1442                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1443                         adev->family = AMDGPU_FAMILY_CZ;
1444                 else
1445                         adev->family = AMDGPU_FAMILY_VI;
1446
1447                 r = vi_set_ip_blocks(adev);
1448                 if (r)
1449                         return r;
1450                 break;
1451 #ifdef CONFIG_DRM_AMDGPU_SI
1452         case CHIP_VERDE:
1453         case CHIP_TAHITI:
1454         case CHIP_PITCAIRN:
1455         case CHIP_OLAND:
1456         case CHIP_HAINAN:
1457                 adev->family = AMDGPU_FAMILY_SI;
1458                 r = si_set_ip_blocks(adev);
1459                 if (r)
1460                         return r;
1461                 break;
1462 #endif
1463 #ifdef CONFIG_DRM_AMDGPU_CIK
1464         case CHIP_BONAIRE:
1465         case CHIP_HAWAII:
1466         case CHIP_KAVERI:
1467         case CHIP_KABINI:
1468         case CHIP_MULLINS:
1469                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1470                         adev->family = AMDGPU_FAMILY_CI;
1471                 else
1472                         adev->family = AMDGPU_FAMILY_KV;
1473
1474                 r = cik_set_ip_blocks(adev);
1475                 if (r)
1476                         return r;
1477                 break;
1478 #endif
1479         case CHIP_VEGA10:
1480         case CHIP_VEGA12:
1481         case CHIP_VEGA20:
1482         case CHIP_RAVEN:
1483                 if (adev->asic_type == CHIP_RAVEN)
1484                         adev->family = AMDGPU_FAMILY_RV;
1485                 else
1486                         adev->family = AMDGPU_FAMILY_AI;
1487
1488                 r = soc15_set_ip_blocks(adev);
1489                 if (r)
1490                         return r;
1491                 break;
1492         default:
1493                 /* FIXME: not supported yet */
1494                 return -EINVAL;
1495         }
1496
1497         r = amdgpu_device_parse_gpu_info_fw(adev);
1498         if (r)
1499                 return r;
1500
1501         amdgpu_amdkfd_device_probe(adev);
1502
1503         if (amdgpu_sriov_vf(adev)) {
1504                 r = amdgpu_virt_request_full_gpu(adev, true);
1505                 if (r)
1506                         return -EAGAIN;
1507         }
1508
1509         adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1510
1511         for (i = 0; i < adev->num_ip_blocks; i++) {
1512                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1513                         DRM_ERROR("disabled ip block: %d <%s>\n",
1514                                   i, adev->ip_blocks[i].version->funcs->name);
1515                         adev->ip_blocks[i].status.valid = false;
1516                 } else {
1517                         if (adev->ip_blocks[i].version->funcs->early_init) {
1518                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1519                                 if (r == -ENOENT) {
1520                                         adev->ip_blocks[i].status.valid = false;
1521                                 } else if (r) {
1522                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1523                                                   adev->ip_blocks[i].version->funcs->name, r);
1524                                         return r;
1525                                 } else {
1526                                         adev->ip_blocks[i].status.valid = true;
1527                                 }
1528                         } else {
1529                                 adev->ip_blocks[i].status.valid = true;
1530                         }
1531                 }
1532         }
1533
1534         adev->cg_flags &= amdgpu_cg_mask;
1535         adev->pg_flags &= amdgpu_pg_mask;
1536
1537         return 0;
1538 }
1539
1540 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
1541 {
1542         int i, r;
1543
1544         for (i = 0; i < adev->num_ip_blocks; i++) {
1545                 if (!adev->ip_blocks[i].status.sw)
1546                         continue;
1547                 if (adev->ip_blocks[i].status.hw)
1548                         continue;
1549                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1550                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
1551                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1552                         if (r) {
1553                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1554                                           adev->ip_blocks[i].version->funcs->name, r);
1555                                 return r;
1556                         }
1557                         adev->ip_blocks[i].status.hw = true;
1558                 }
1559         }
1560
1561         return 0;
1562 }
1563
1564 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
1565 {
1566         int i, r;
1567
1568         for (i = 0; i < adev->num_ip_blocks; i++) {
1569                 if (!adev->ip_blocks[i].status.sw)
1570                         continue;
1571                 if (adev->ip_blocks[i].status.hw)
1572                         continue;
1573                 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1574                 if (r) {
1575                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1576                                   adev->ip_blocks[i].version->funcs->name, r);
1577                         return r;
1578                 }
1579                 adev->ip_blocks[i].status.hw = true;
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
1586 {
1587         int r = 0;
1588         int i;
1589
1590         if (adev->asic_type >= CHIP_VEGA10) {
1591                 for (i = 0; i < adev->num_ip_blocks; i++) {
1592                         if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
1593                                 if (adev->in_gpu_reset || adev->in_suspend) {
1594                                         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
1595                                                 break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
1596                                         r = adev->ip_blocks[i].version->funcs->resume(adev);
1597                                         if (r) {
1598                                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
1599                                                           adev->ip_blocks[i].version->funcs->name, r);
1600                                                 return r;
1601                                         }
1602                                 } else {
1603                                         r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1604                                         if (r) {
1605                                                 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1606                                                   adev->ip_blocks[i].version->funcs->name, r);
1607                                                 return r;
1608                                         }
1609                                 }
1610                                 adev->ip_blocks[i].status.hw = true;
1611                         }
1612                 }
1613         }
1614
1615         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
1616                 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
1617                 if (r) {
1618                         pr_err("firmware loading failed\n");
1619                         return r;
1620                 }
1621         }
1622
1623         return 0;
1624 }
1625
1626 /**
1627  * amdgpu_device_ip_init - run init for hardware IPs
1628  *
1629  * @adev: amdgpu_device pointer
1630  *
1631  * Main initialization pass for hardware IPs.  The list of all the hardware
1632  * IPs that make up the asic is walked and the sw_init and hw_init callbacks
1633  * are run.  sw_init initializes the software state associated with each IP
1634  * and hw_init initializes the hardware associated with each IP.
1635  * Returns 0 on success, negative error code on failure.
1636  */
1637 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
1638 {
1639         int i, r;
1640
1641         for (i = 0; i < adev->num_ip_blocks; i++) {
1642                 if (!adev->ip_blocks[i].status.valid)
1643                         continue;
1644                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1645                 if (r) {
1646                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1647                                   adev->ip_blocks[i].version->funcs->name, r);
1648                         goto init_failed;
1649                 }
1650                 adev->ip_blocks[i].status.sw = true;
1651
1652                 /* need to do gmc hw init early so we can allocate gpu mem */
1653                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1654                         r = amdgpu_device_vram_scratch_init(adev);
1655                         if (r) {
1656                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1657                                 goto init_failed;
1658                         }
1659                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1660                         if (r) {
1661                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1662                                 goto init_failed;
1663                         }
1664                         r = amdgpu_device_wb_init(adev);
1665                         if (r) {
1666                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
1667                                 goto init_failed;
1668                         }
1669                         adev->ip_blocks[i].status.hw = true;
1670
1671                         /* right after GMC hw init, we create CSA */
1672                         if (amdgpu_sriov_vf(adev)) {
1673                                 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
1674                                                                 AMDGPU_GEM_DOMAIN_VRAM,
1675                                                                 AMDGPU_CSA_SIZE);
1676                                 if (r) {
1677                                         DRM_ERROR("allocate CSA failed %d\n", r);
1678                                         goto init_failed;
1679                                 }
1680                         }
1681                 }
1682         }
1683
1684         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
1685         if (r)
1686                 goto init_failed;
1687
1688         r = amdgpu_device_ip_hw_init_phase1(adev);
1689         if (r)
1690                 goto init_failed;
1691
1692         r = amdgpu_device_fw_loading(adev);
1693         if (r)
1694                 goto init_failed;
1695
1696         r = amdgpu_device_ip_hw_init_phase2(adev);
1697         if (r)
1698                 goto init_failed;
1699
1700         if (adev->gmc.xgmi.num_physical_nodes > 1)
1701                 amdgpu_xgmi_add_device(adev);
1702         amdgpu_amdkfd_device_init(adev);
1703
1704 init_failed:
1705         if (amdgpu_sriov_vf(adev)) {
1706                 if (!r)
1707                         amdgpu_virt_init_data_exchange(adev);
1708                 amdgpu_virt_release_full_gpu(adev, true);
1709         }
1710
1711         return r;
1712 }
1713
1714 /**
1715  * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
1716  *
1717  * @adev: amdgpu_device pointer
1718  *
1719  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
1720  * this function before a GPU reset.  If the value is retained after a
1721  * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM contents.
1722  */
1723 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
1724 {
1725         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1726 }
1727
1728 /**
1729  * amdgpu_device_check_vram_lost - check if vram is valid
1730  *
1731  * @adev: amdgpu_device pointer
1732  *
1733  * Checks the reset magic value written to the gart pointer in VRAM.
1734  * The driver calls this after a GPU reset to see if the contents of
1735  * VRAM is lost or now.
1736  * returns true if vram is lost, false if not.
1737  */
1738 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
1739 {
1740         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1741                         AMDGPU_RESET_MAGIC_NUM);
1742 }
1743
1744 /**
1745  * amdgpu_device_set_cg_state - set clockgating for amdgpu device
1746  *
1747  * @adev: amdgpu_device pointer
1748  *
1749  * The list of all the hardware IPs that make up the asic is walked and the
1750  * set_clockgating_state callbacks are run.
1751  * Late initialization pass enabling clockgating for hardware IPs.
1752  * Fini or suspend, pass disabling clockgating for hardware IPs.
1753  * Returns 0 on success, negative error code on failure.
1754  */
1755
1756 static int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1757                                                 enum amd_clockgating_state state)
1758 {
1759         int i, j, r;
1760
1761         if (amdgpu_emu_mode == 1)
1762                 return 0;
1763
1764         for (j = 0; j < adev->num_ip_blocks; j++) {
1765                 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1766                 if (!adev->ip_blocks[i].status.late_initialized)
1767                         continue;
1768                 /* skip CG for VCE/UVD, it's handled specially */
1769                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1770                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1771                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1772                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
1773                         /* enable clockgating to save power */
1774                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1775                                                                                      state);
1776                         if (r) {
1777                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1778                                           adev->ip_blocks[i].version->funcs->name, r);
1779                                 return r;
1780                         }
1781                 }
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state)
1788 {
1789         int i, j, r;
1790
1791         if (amdgpu_emu_mode == 1)
1792                 return 0;
1793
1794         for (j = 0; j < adev->num_ip_blocks; j++) {
1795                 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
1796                 if (!adev->ip_blocks[i].status.late_initialized)
1797                         continue;
1798                 /* skip CG for VCE/UVD, it's handled specially */
1799                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1800                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
1801                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
1802                     adev->ip_blocks[i].version->funcs->set_powergating_state) {
1803                         /* enable powergating to save power */
1804                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1805                                                                                         state);
1806                         if (r) {
1807                                 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
1808                                           adev->ip_blocks[i].version->funcs->name, r);
1809                                 return r;
1810                         }
1811                 }
1812         }
1813         return 0;
1814 }
1815
1816 /**
1817  * amdgpu_device_ip_late_init - run late init for hardware IPs
1818  *
1819  * @adev: amdgpu_device pointer
1820  *
1821  * Late initialization pass for hardware IPs.  The list of all the hardware
1822  * IPs that make up the asic is walked and the late_init callbacks are run.
1823  * late_init covers any special initialization that an IP requires
1824  * after all of the have been initialized or something that needs to happen
1825  * late in the init process.
1826  * Returns 0 on success, negative error code on failure.
1827  */
1828 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
1829 {
1830         int i = 0, r;
1831
1832         for (i = 0; i < adev->num_ip_blocks; i++) {
1833                 if (!adev->ip_blocks[i].status.hw)
1834                         continue;
1835                 if (adev->ip_blocks[i].version->funcs->late_init) {
1836                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1837                         if (r) {
1838                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1839                                           adev->ip_blocks[i].version->funcs->name, r);
1840                                 return r;
1841                         }
1842                 }
1843                 adev->ip_blocks[i].status.late_initialized = true;
1844         }
1845
1846         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
1847         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
1848
1849         queue_delayed_work(system_wq, &adev->late_init_work,
1850                            msecs_to_jiffies(AMDGPU_RESUME_MS));
1851
1852         amdgpu_device_fill_reset_magic(adev);
1853
1854         return 0;
1855 }
1856
1857 /**
1858  * amdgpu_device_ip_fini - run fini for hardware IPs
1859  *
1860  * @adev: amdgpu_device pointer
1861  *
1862  * Main teardown pass for hardware IPs.  The list of all the hardware
1863  * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
1864  * are run.  hw_fini tears down the hardware associated with each IP
1865  * and sw_fini tears down any software state associated with each IP.
1866  * Returns 0 on success, negative error code on failure.
1867  */
1868 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
1869 {
1870         int i, r;
1871
1872         if (adev->gmc.xgmi.num_physical_nodes > 1)
1873                 amdgpu_xgmi_remove_device(adev);
1874
1875         amdgpu_amdkfd_device_fini(adev);
1876
1877         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
1878         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
1879
1880         /* need to disable SMC first */
1881         for (i = 0; i < adev->num_ip_blocks; i++) {
1882                 if (!adev->ip_blocks[i].status.hw)
1883                         continue;
1884                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1885                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1886                         /* XXX handle errors */
1887                         if (r) {
1888                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1889                                           adev->ip_blocks[i].version->funcs->name, r);
1890                         }
1891                         adev->ip_blocks[i].status.hw = false;
1892                         break;
1893                 }
1894         }
1895
1896         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1897                 if (!adev->ip_blocks[i].status.hw)
1898                         continue;
1899
1900                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1901                 /* XXX handle errors */
1902                 if (r) {
1903                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1904                                   adev->ip_blocks[i].version->funcs->name, r);
1905                 }
1906
1907                 adev->ip_blocks[i].status.hw = false;
1908         }
1909
1910
1911         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1912                 if (!adev->ip_blocks[i].status.sw)
1913                         continue;
1914
1915                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1916                         amdgpu_ucode_free_bo(adev);
1917                         amdgpu_free_static_csa(&adev->virt.csa_obj);
1918                         amdgpu_device_wb_fini(adev);
1919                         amdgpu_device_vram_scratch_fini(adev);
1920                 }
1921
1922                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1923                 /* XXX handle errors */
1924                 if (r) {
1925                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1926                                   adev->ip_blocks[i].version->funcs->name, r);
1927                 }
1928                 adev->ip_blocks[i].status.sw = false;
1929                 adev->ip_blocks[i].status.valid = false;
1930         }
1931
1932         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1933                 if (!adev->ip_blocks[i].status.late_initialized)
1934                         continue;
1935                 if (adev->ip_blocks[i].version->funcs->late_fini)
1936                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1937                 adev->ip_blocks[i].status.late_initialized = false;
1938         }
1939
1940         if (amdgpu_sriov_vf(adev))
1941                 if (amdgpu_virt_release_full_gpu(adev, false))
1942                         DRM_ERROR("failed to release exclusive mode on fini\n");
1943
1944         return 0;
1945 }
1946
1947 static int amdgpu_device_enable_mgpu_fan_boost(void)
1948 {
1949         struct amdgpu_gpu_instance *gpu_ins;
1950         struct amdgpu_device *adev;
1951         int i, ret = 0;
1952
1953         mutex_lock(&mgpu_info.mutex);
1954
1955         /*
1956          * MGPU fan boost feature should be enabled
1957          * only when there are two or more dGPUs in
1958          * the system
1959          */
1960         if (mgpu_info.num_dgpu < 2)
1961                 goto out;
1962
1963         for (i = 0; i < mgpu_info.num_dgpu; i++) {
1964                 gpu_ins = &(mgpu_info.gpu_ins[i]);
1965                 adev = gpu_ins->adev;
1966                 if (!(adev->flags & AMD_IS_APU) &&
1967                     !gpu_ins->mgpu_fan_enabled &&
1968                     adev->powerplay.pp_funcs &&
1969                     adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
1970                         ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
1971                         if (ret)
1972                                 break;
1973
1974                         gpu_ins->mgpu_fan_enabled = 1;
1975                 }
1976         }
1977
1978 out:
1979         mutex_unlock(&mgpu_info.mutex);
1980
1981         return ret;
1982 }
1983
1984 /**
1985  * amdgpu_device_ip_late_init_func_handler - work handler for ib test
1986  *
1987  * @work: work_struct.
1988  */
1989 static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
1990 {
1991         struct amdgpu_device *adev =
1992                 container_of(work, struct amdgpu_device, late_init_work.work);
1993         int r;
1994
1995         r = amdgpu_ib_ring_tests(adev);
1996         if (r)
1997                 DRM_ERROR("ib ring test failed (%d).\n", r);
1998
1999         r = amdgpu_device_enable_mgpu_fan_boost();
2000         if (r)
2001                 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2002 }
2003
2004 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2005 {
2006         struct amdgpu_device *adev =
2007                 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2008
2009         mutex_lock(&adev->gfx.gfx_off_mutex);
2010         if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
2011                 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2012                         adev->gfx.gfx_off_state = true;
2013         }
2014         mutex_unlock(&adev->gfx.gfx_off_mutex);
2015 }
2016
2017 /**
2018  * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2019  *
2020  * @adev: amdgpu_device pointer
2021  *
2022  * Main suspend function for hardware IPs.  The list of all the hardware
2023  * IPs that make up the asic is walked, clockgating is disabled and the
2024  * suspend callbacks are run.  suspend puts the hardware and software state
2025  * in each IP into a state suitable for suspend.
2026  * Returns 0 on success, negative error code on failure.
2027  */
2028 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2029 {
2030         int i, r;
2031
2032         amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2033         amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2034
2035         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2036                 if (!adev->ip_blocks[i].status.valid)
2037                         continue;
2038                 /* displays are handled separately */
2039                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
2040                         /* XXX handle errors */
2041                         r = adev->ip_blocks[i].version->funcs->suspend(adev);
2042                         /* XXX handle errors */
2043                         if (r) {
2044                                 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2045                                           adev->ip_blocks[i].version->funcs->name, r);
2046                         }
2047                 }
2048         }
2049
2050         return 0;
2051 }
2052
2053 /**
2054  * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2055  *
2056  * @adev: amdgpu_device pointer
2057  *
2058  * Main suspend function for hardware IPs.  The list of all the hardware
2059  * IPs that make up the asic is walked, clockgating is disabled and the
2060  * suspend callbacks are run.  suspend puts the hardware and software state
2061  * in each IP into a state suitable for suspend.
2062  * Returns 0 on success, negative error code on failure.
2063  */
2064 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2065 {
2066         int i, r;
2067
2068         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2069                 if (!adev->ip_blocks[i].status.valid)
2070                         continue;
2071                 /* displays are handled in phase1 */
2072                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
2073                         continue;
2074                 /* XXX handle errors */
2075                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2076                 /* XXX handle errors */
2077                 if (r) {
2078                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
2079                                   adev->ip_blocks[i].version->funcs->name, r);
2080                 }
2081         }
2082
2083         return 0;
2084 }
2085
2086 /**
2087  * amdgpu_device_ip_suspend - run suspend for hardware IPs
2088  *
2089  * @adev: amdgpu_device pointer
2090  *
2091  * Main suspend function for hardware IPs.  The list of all the hardware
2092  * IPs that make up the asic is walked, clockgating is disabled and the
2093  * suspend callbacks are run.  suspend puts the hardware and software state
2094  * in each IP into a state suitable for suspend.
2095  * Returns 0 on success, negative error code on failure.
2096  */
2097 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
2098 {
2099         int r;
2100
2101         if (amdgpu_sriov_vf(adev))
2102                 amdgpu_virt_request_full_gpu(adev, false);
2103
2104         r = amdgpu_device_ip_suspend_phase1(adev);
2105         if (r)
2106                 return r;
2107         r = amdgpu_device_ip_suspend_phase2(adev);
2108
2109         if (amdgpu_sriov_vf(adev))
2110                 amdgpu_virt_release_full_gpu(adev, false);
2111
2112         return r;
2113 }
2114
2115 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
2116 {
2117         int i, r;
2118
2119         static enum amd_ip_block_type ip_order[] = {
2120                 AMD_IP_BLOCK_TYPE_GMC,
2121                 AMD_IP_BLOCK_TYPE_COMMON,
2122                 AMD_IP_BLOCK_TYPE_PSP,
2123                 AMD_IP_BLOCK_TYPE_IH,
2124         };
2125
2126         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2127                 int j;
2128                 struct amdgpu_ip_block *block;
2129
2130                 for (j = 0; j < adev->num_ip_blocks; j++) {
2131                         block = &adev->ip_blocks[j];
2132
2133                         if (block->version->type != ip_order[i] ||
2134                                 !block->status.valid)
2135                                 continue;
2136
2137                         r = block->version->funcs->hw_init(adev);
2138                         DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2139                         if (r)
2140                                 return r;
2141                 }
2142         }
2143
2144         return 0;
2145 }
2146
2147 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
2148 {
2149         int i, r;
2150
2151         static enum amd_ip_block_type ip_order[] = {
2152                 AMD_IP_BLOCK_TYPE_SMC,
2153                 AMD_IP_BLOCK_TYPE_DCE,
2154                 AMD_IP_BLOCK_TYPE_GFX,
2155                 AMD_IP_BLOCK_TYPE_SDMA,
2156                 AMD_IP_BLOCK_TYPE_UVD,
2157                 AMD_IP_BLOCK_TYPE_VCE
2158         };
2159
2160         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2161                 int j;
2162                 struct amdgpu_ip_block *block;
2163
2164                 for (j = 0; j < adev->num_ip_blocks; j++) {
2165                         block = &adev->ip_blocks[j];
2166
2167                         if (block->version->type != ip_order[i] ||
2168                                 !block->status.valid)
2169                                 continue;
2170
2171                         r = block->version->funcs->hw_init(adev);
2172                         DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
2173                         if (r)
2174                                 return r;
2175                 }
2176         }
2177
2178         return 0;
2179 }
2180
2181 /**
2182  * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
2183  *
2184  * @adev: amdgpu_device pointer
2185  *
2186  * First resume function for hardware IPs.  The list of all the hardware
2187  * IPs that make up the asic is walked and the resume callbacks are run for
2188  * COMMON, GMC, and IH.  resume puts the hardware into a functional state
2189  * after a suspend and updates the software state as necessary.  This
2190  * function is also used for restoring the GPU after a GPU reset.
2191  * Returns 0 on success, negative error code on failure.
2192  */
2193 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
2194 {
2195         int i, r;
2196
2197         for (i = 0; i < adev->num_ip_blocks; i++) {
2198                 if (!adev->ip_blocks[i].status.valid)
2199                         continue;
2200                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2201                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2202                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2203                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2204                         if (r) {
2205                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2206                                           adev->ip_blocks[i].version->funcs->name, r);
2207                                 return r;
2208                         }
2209                 }
2210         }
2211
2212         return 0;
2213 }
2214
2215 /**
2216  * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
2217  *
2218  * @adev: amdgpu_device pointer
2219  *
2220  * First resume function for hardware IPs.  The list of all the hardware
2221  * IPs that make up the asic is walked and the resume callbacks are run for
2222  * all blocks except COMMON, GMC, and IH.  resume puts the hardware into a
2223  * functional state after a suspend and updates the software state as
2224  * necessary.  This function is also used for restoring the GPU after a GPU
2225  * reset.
2226  * Returns 0 on success, negative error code on failure.
2227  */
2228 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
2229 {
2230         int i, r;
2231
2232         for (i = 0; i < adev->num_ip_blocks; i++) {
2233                 if (!adev->ip_blocks[i].status.valid)
2234                         continue;
2235                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2236                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2237                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
2238                     adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
2239                         continue;
2240                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2241                 if (r) {
2242                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2243                                   adev->ip_blocks[i].version->funcs->name, r);
2244                         return r;
2245                 }
2246         }
2247
2248         return 0;
2249 }
2250
2251 /**
2252  * amdgpu_device_ip_resume - run resume for hardware IPs
2253  *
2254  * @adev: amdgpu_device pointer
2255  *
2256  * Main resume function for hardware IPs.  The hardware IPs
2257  * are split into two resume functions because they are
2258  * are also used in in recovering from a GPU reset and some additional
2259  * steps need to be take between them.  In this case (S3/S4) they are
2260  * run sequentially.
2261  * Returns 0 on success, negative error code on failure.
2262  */
2263 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
2264 {
2265         int r;
2266
2267         r = amdgpu_device_ip_resume_phase1(adev);
2268         if (r)
2269                 return r;
2270
2271         r = amdgpu_device_fw_loading(adev);
2272         if (r)
2273                 return r;
2274
2275         r = amdgpu_device_ip_resume_phase2(adev);
2276
2277         return r;
2278 }
2279
2280 /**
2281  * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
2282  *
2283  * @adev: amdgpu_device pointer
2284  *
2285  * Query the VBIOS data tables to determine if the board supports SR-IOV.
2286  */
2287 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2288 {
2289         if (amdgpu_sriov_vf(adev)) {
2290                 if (adev->is_atom_fw) {
2291                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2292                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2293                 } else {
2294                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2295                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2296                 }
2297
2298                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2299                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2300         }
2301 }
2302
2303 /**
2304  * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
2305  *
2306  * @asic_type: AMD asic type
2307  *
2308  * Check if there is DC (new modesetting infrastructre) support for an asic.
2309  * returns true if DC has support, false if not.
2310  */
2311 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2312 {
2313         switch (asic_type) {
2314 #if defined(CONFIG_DRM_AMD_DC)
2315         case CHIP_BONAIRE:
2316         case CHIP_KAVERI:
2317         case CHIP_KABINI:
2318         case CHIP_MULLINS:
2319                 /*
2320                  * We have systems in the wild with these ASICs that require
2321                  * LVDS and VGA support which is not supported with DC.
2322                  *
2323                  * Fallback to the non-DC driver here by default so as not to
2324                  * cause regressions.
2325                  */
2326                 return amdgpu_dc > 0;
2327         case CHIP_HAWAII:
2328         case CHIP_CARRIZO:
2329         case CHIP_STONEY:
2330         case CHIP_POLARIS10:
2331         case CHIP_POLARIS11:
2332         case CHIP_POLARIS12:
2333         case CHIP_VEGAM:
2334         case CHIP_TONGA:
2335         case CHIP_FIJI:
2336         case CHIP_VEGA10:
2337         case CHIP_VEGA12:
2338         case CHIP_VEGA20:
2339 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2340         case CHIP_RAVEN:
2341 #endif
2342                 return amdgpu_dc != 0;
2343 #endif
2344         default:
2345                 return false;
2346         }
2347 }
2348
2349 /**
2350  * amdgpu_device_has_dc_support - check if dc is supported
2351  *
2352  * @adev: amdgpu_device_pointer
2353  *
2354  * Returns true for supported, false for not supported
2355  */
2356 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2357 {
2358         if (amdgpu_sriov_vf(adev))
2359                 return false;
2360
2361         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2362 }
2363
2364
2365 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
2366 {
2367         struct amdgpu_device *adev =
2368                 container_of(__work, struct amdgpu_device, xgmi_reset_work);
2369
2370         adev->asic_reset_res =  amdgpu_asic_reset(adev);
2371         if (adev->asic_reset_res)
2372                 DRM_WARN("ASIC reset failed with err r, %d for drm dev, %s",
2373                          adev->asic_reset_res, adev->ddev->unique);
2374 }
2375
2376
2377 /**
2378  * amdgpu_device_init - initialize the driver
2379  *
2380  * @adev: amdgpu_device pointer
2381  * @ddev: drm dev pointer
2382  * @pdev: pci dev pointer
2383  * @flags: driver flags
2384  *
2385  * Initializes the driver info and hw (all asics).
2386  * Returns 0 for success or an error on failure.
2387  * Called at driver startup.
2388  */
2389 int amdgpu_device_init(struct amdgpu_device *adev,
2390                        struct drm_device *ddev,
2391                        struct pci_dev *pdev,
2392                        uint32_t flags)
2393 {
2394         int r, i;
2395         bool runtime = false;
2396         u32 max_MBps;
2397
2398         adev->shutdown = false;
2399         adev->dev = &pdev->dev;
2400         adev->ddev = ddev;
2401         adev->pdev = pdev;
2402         adev->flags = flags;
2403         adev->asic_type = flags & AMD_ASIC_MASK;
2404         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2405         if (amdgpu_emu_mode == 1)
2406                 adev->usec_timeout *= 2;
2407         adev->gmc.gart_size = 512 * 1024 * 1024;
2408         adev->accel_working = false;
2409         adev->num_rings = 0;
2410         adev->mman.buffer_funcs = NULL;
2411         adev->mman.buffer_funcs_ring = NULL;
2412         adev->vm_manager.vm_pte_funcs = NULL;
2413         adev->vm_manager.vm_pte_num_rqs = 0;
2414         adev->gmc.gmc_funcs = NULL;
2415         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2416         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2417
2418         adev->smc_rreg = &amdgpu_invalid_rreg;
2419         adev->smc_wreg = &amdgpu_invalid_wreg;
2420         adev->pcie_rreg = &amdgpu_invalid_rreg;
2421         adev->pcie_wreg = &amdgpu_invalid_wreg;
2422         adev->pciep_rreg = &amdgpu_invalid_rreg;
2423         adev->pciep_wreg = &amdgpu_invalid_wreg;
2424         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2425         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2426         adev->didt_rreg = &amdgpu_invalid_rreg;
2427         adev->didt_wreg = &amdgpu_invalid_wreg;
2428         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2429         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2430         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2431         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2432
2433         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2434                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2435                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2436
2437         /* mutex initialization are all done here so we
2438          * can recall function without having locking issues */
2439         atomic_set(&adev->irq.ih.lock, 0);
2440         mutex_init(&adev->firmware.mutex);
2441         mutex_init(&adev->pm.mutex);
2442         mutex_init(&adev->gfx.gpu_clock_mutex);
2443         mutex_init(&adev->srbm_mutex);
2444         mutex_init(&adev->gfx.pipe_reserve_mutex);
2445         mutex_init(&adev->gfx.gfx_off_mutex);
2446         mutex_init(&adev->grbm_idx_mutex);
2447         mutex_init(&adev->mn_lock);
2448         mutex_init(&adev->virt.vf_errors.lock);
2449         hash_init(adev->mn_hash);
2450         mutex_init(&adev->lock_reset);
2451
2452         amdgpu_device_check_arguments(adev);
2453
2454         spin_lock_init(&adev->mmio_idx_lock);
2455         spin_lock_init(&adev->smc_idx_lock);
2456         spin_lock_init(&adev->pcie_idx_lock);
2457         spin_lock_init(&adev->uvd_ctx_idx_lock);
2458         spin_lock_init(&adev->didt_idx_lock);
2459         spin_lock_init(&adev->gc_cac_idx_lock);
2460         spin_lock_init(&adev->se_cac_idx_lock);
2461         spin_lock_init(&adev->audio_endpt_idx_lock);
2462         spin_lock_init(&adev->mm_stats.lock);
2463
2464         INIT_LIST_HEAD(&adev->shadow_list);
2465         mutex_init(&adev->shadow_list_lock);
2466
2467         INIT_LIST_HEAD(&adev->ring_lru_list);
2468         spin_lock_init(&adev->ring_lru_list_lock);
2469
2470         INIT_DELAYED_WORK(&adev->late_init_work,
2471                           amdgpu_device_ip_late_init_func_handler);
2472         INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
2473                           amdgpu_device_delay_enable_gfx_off);
2474
2475         INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
2476
2477         adev->gfx.gfx_off_req_count = 1;
2478         adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false;
2479
2480         /* Registers mapping */
2481         /* TODO: block userspace mapping of io register */
2482         if (adev->asic_type >= CHIP_BONAIRE) {
2483                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2484                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2485         } else {
2486                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2487                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2488         }
2489
2490         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2491         if (adev->rmmio == NULL) {
2492                 return -ENOMEM;
2493         }
2494         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2495         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2496
2497         /* io port mapping */
2498         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2499                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2500                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2501                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2502                         break;
2503                 }
2504         }
2505         if (adev->rio_mem == NULL)
2506                 DRM_INFO("PCI I/O BAR is not found.\n");
2507
2508         amdgpu_device_get_pcie_info(adev);
2509
2510         /* early init functions */
2511         r = amdgpu_device_ip_early_init(adev);
2512         if (r)
2513                 return r;
2514
2515         /* doorbell bar mapping and doorbell index init*/
2516         amdgpu_device_doorbell_init(adev);
2517
2518         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2519         /* this will fail for cards that aren't VGA class devices, just
2520          * ignore it */
2521         vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode);
2522
2523         if (amdgpu_device_is_px(ddev))
2524                 runtime = true;
2525         if (!pci_is_thunderbolt_attached(adev->pdev))
2526                 vga_switcheroo_register_client(adev->pdev,
2527                                                &amdgpu_switcheroo_ops, runtime);
2528         if (runtime)
2529                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2530
2531         if (amdgpu_emu_mode == 1) {
2532                 /* post the asic on emulation mode */
2533                 emu_soc_asic_init(adev);
2534                 goto fence_driver_init;
2535         }
2536
2537         /* Read BIOS */
2538         if (!amdgpu_get_bios(adev)) {
2539                 r = -EINVAL;
2540                 goto failed;
2541         }
2542
2543         r = amdgpu_atombios_init(adev);
2544         if (r) {
2545                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2546                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2547                 goto failed;
2548         }
2549
2550         /* detect if we are with an SRIOV vbios */
2551         amdgpu_device_detect_sriov_bios(adev);
2552
2553         /* check if we need to reset the asic
2554          *  E.g., driver was not cleanly unloaded previously, etc.
2555          */
2556         if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
2557                 r = amdgpu_asic_reset(adev);
2558                 if (r) {
2559                         dev_err(adev->dev, "asic reset on init failed\n");
2560                         goto failed;
2561                 }
2562         }
2563
2564         /* Post card if necessary */
2565         if (amdgpu_device_need_post(adev)) {
2566                 if (!adev->bios) {
2567                         dev_err(adev->dev, "no vBIOS found\n");
2568                         r = -EINVAL;
2569                         goto failed;
2570                 }
2571                 DRM_INFO("GPU posting now...\n");
2572                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2573                 if (r) {
2574                         dev_err(adev->dev, "gpu post error!\n");
2575                         goto failed;
2576                 }
2577         }
2578
2579         if (adev->is_atom_fw) {
2580                 /* Initialize clocks */
2581                 r = amdgpu_atomfirmware_get_clock_info(adev);
2582                 if (r) {
2583                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2584                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2585                         goto failed;
2586                 }
2587         } else {
2588                 /* Initialize clocks */
2589                 r = amdgpu_atombios_get_clock_info(adev);
2590                 if (r) {
2591                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2592                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2593                         goto failed;
2594                 }
2595                 /* init i2c buses */
2596                 if (!amdgpu_device_has_dc_support(adev))
2597                         amdgpu_atombios_i2c_init(adev);
2598         }
2599
2600 fence_driver_init:
2601         /* Fence driver */
2602         r = amdgpu_fence_driver_init(adev);
2603         if (r) {
2604                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2605                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2606                 goto failed;
2607         }
2608
2609         /* init the mode config */
2610         drm_mode_config_init(adev->ddev);
2611
2612         r = amdgpu_device_ip_init(adev);
2613         if (r) {
2614                 /* failed in exclusive mode due to timeout */
2615                 if (amdgpu_sriov_vf(adev) &&
2616                     !amdgpu_sriov_runtime(adev) &&
2617                     amdgpu_virt_mmio_blocked(adev) &&
2618                     !amdgpu_virt_wait_reset(adev)) {
2619                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2620                         /* Don't send request since VF is inactive. */
2621                         adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
2622                         adev->virt.ops = NULL;
2623                         r = -EAGAIN;
2624                         goto failed;
2625                 }
2626                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
2627                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2628                 if (amdgpu_virt_request_full_gpu(adev, false))
2629                         amdgpu_virt_release_full_gpu(adev, false);
2630                 goto failed;
2631         }
2632
2633         adev->accel_working = true;
2634
2635         amdgpu_vm_check_compute_bug(adev);
2636
2637         /* Initialize the buffer migration limit. */
2638         if (amdgpu_moverate >= 0)
2639                 max_MBps = amdgpu_moverate;
2640         else
2641                 max_MBps = 8; /* Allow 8 MB/s. */
2642         /* Get a log2 for easy divisions. */
2643         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2644
2645         r = amdgpu_ib_pool_init(adev);
2646         if (r) {
2647                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2648                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2649                 goto failed;
2650         }
2651
2652         amdgpu_fbdev_init(adev);
2653
2654         r = amdgpu_pm_sysfs_init(adev);
2655         if (r)
2656                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2657
2658         r = amdgpu_debugfs_gem_init(adev);
2659         if (r)
2660                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2661
2662         r = amdgpu_debugfs_regs_init(adev);
2663         if (r)
2664                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2665
2666         r = amdgpu_debugfs_firmware_init(adev);
2667         if (r)
2668                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2669
2670         r = amdgpu_debugfs_init(adev);
2671         if (r)
2672                 DRM_ERROR("Creating debugfs files failed (%d).\n", r);
2673
2674         if ((amdgpu_testing & 1)) {
2675                 if (adev->accel_working)
2676                         amdgpu_test_moves(adev);
2677                 else
2678                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2679         }
2680         if (amdgpu_benchmarking) {
2681                 if (adev->accel_working)
2682                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2683                 else
2684                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2685         }
2686
2687         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2688          * explicit gating rather than handling it automatically.
2689          */
2690         r = amdgpu_device_ip_late_init(adev);
2691         if (r) {
2692                 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
2693                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2694                 goto failed;
2695         }
2696
2697         return 0;
2698
2699 failed:
2700         amdgpu_vf_error_trans_all(adev);
2701         if (runtime)
2702                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2703
2704         return r;
2705 }
2706
2707 /**
2708  * amdgpu_device_fini - tear down the driver
2709  *
2710  * @adev: amdgpu_device pointer
2711  *
2712  * Tear down the driver info (all asics).
2713  * Called at driver shutdown.
2714  */
2715 void amdgpu_device_fini(struct amdgpu_device *adev)
2716 {
2717         int r;
2718
2719         DRM_INFO("amdgpu: finishing device.\n");
2720         adev->shutdown = true;
2721         /* disable all interrupts */
2722         amdgpu_irq_disable_all(adev);
2723         if (adev->mode_info.mode_config_initialized){
2724                 if (!amdgpu_device_has_dc_support(adev))
2725                         drm_helper_force_disable_all(adev->ddev);
2726                 else
2727                         drm_atomic_helper_shutdown(adev->ddev);
2728         }
2729         amdgpu_ib_pool_fini(adev);
2730         amdgpu_fence_driver_fini(adev);
2731         amdgpu_pm_sysfs_fini(adev);
2732         amdgpu_fbdev_fini(adev);
2733         r = amdgpu_device_ip_fini(adev);
2734         if (adev->firmware.gpu_info_fw) {
2735                 release_firmware(adev->firmware.gpu_info_fw);
2736                 adev->firmware.gpu_info_fw = NULL;
2737         }
2738         adev->accel_working = false;
2739         cancel_delayed_work_sync(&adev->late_init_work);
2740         /* free i2c buses */
2741         if (!amdgpu_device_has_dc_support(adev))
2742                 amdgpu_i2c_fini(adev);
2743
2744         if (amdgpu_emu_mode != 1)
2745                 amdgpu_atombios_fini(adev);
2746
2747         kfree(adev->bios);
2748         adev->bios = NULL;
2749         if (!pci_is_thunderbolt_attached(adev->pdev))
2750                 vga_switcheroo_unregister_client(adev->pdev);
2751         if (adev->flags & AMD_IS_PX)
2752                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2753         vga_client_register(adev->pdev, NULL, NULL, NULL);
2754         if (adev->rio_mem)
2755                 pci_iounmap(adev->pdev, adev->rio_mem);
2756         adev->rio_mem = NULL;
2757         iounmap(adev->rmmio);
2758         adev->rmmio = NULL;
2759         amdgpu_device_doorbell_fini(adev);
2760         amdgpu_debugfs_regs_cleanup(adev);
2761 }
2762
2763
2764 /*
2765  * Suspend & resume.
2766  */
2767 /**
2768  * amdgpu_device_suspend - initiate device suspend
2769  *
2770  * @dev: drm dev pointer
2771  * @suspend: suspend state
2772  * @fbcon : notify the fbdev of suspend
2773  *
2774  * Puts the hw in the suspend state (all asics).
2775  * Returns 0 for success or an error on failure.
2776  * Called at driver suspend.
2777  */
2778 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2779 {
2780         struct amdgpu_device *adev;
2781         struct drm_crtc *crtc;
2782         struct drm_connector *connector;
2783         int r;
2784
2785         if (dev == NULL || dev->dev_private == NULL) {
2786                 return -ENODEV;
2787         }
2788
2789         adev = dev->dev_private;
2790
2791         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2792                 return 0;
2793
2794         adev->in_suspend = true;
2795         drm_kms_helper_poll_disable(dev);
2796
2797         if (fbcon)
2798                 amdgpu_fbdev_set_suspend(adev, 1);
2799
2800         cancel_delayed_work_sync(&adev->late_init_work);
2801
2802         if (!amdgpu_device_has_dc_support(adev)) {
2803                 /* turn off display hw */
2804                 drm_modeset_lock_all(dev);
2805                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2806                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2807                 }
2808                 drm_modeset_unlock_all(dev);
2809                         /* unpin the front buffers and cursors */
2810                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2811                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2812                         struct drm_framebuffer *fb = crtc->primary->fb;
2813                         struct amdgpu_bo *robj;
2814
2815                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2816                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2817                                 r = amdgpu_bo_reserve(aobj, true);
2818                                 if (r == 0) {
2819                                         amdgpu_bo_unpin(aobj);
2820                                         amdgpu_bo_unreserve(aobj);
2821                                 }
2822                         }
2823
2824                         if (fb == NULL || fb->obj[0] == NULL) {
2825                                 continue;
2826                         }
2827                         robj = gem_to_amdgpu_bo(fb->obj[0]);
2828                         /* don't unpin kernel fb objects */
2829                         if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2830                                 r = amdgpu_bo_reserve(robj, true);
2831                                 if (r == 0) {
2832                                         amdgpu_bo_unpin(robj);
2833                                         amdgpu_bo_unreserve(robj);
2834                                 }
2835                         }
2836                 }
2837         }
2838
2839         amdgpu_amdkfd_suspend(adev);
2840
2841         r = amdgpu_device_ip_suspend_phase1(adev);
2842
2843         /* evict vram memory */
2844         amdgpu_bo_evict_vram(adev);
2845
2846         amdgpu_fence_driver_suspend(adev);
2847
2848         r = amdgpu_device_ip_suspend_phase2(adev);
2849
2850         /* evict remaining vram memory
2851          * This second call to evict vram is to evict the gart page table
2852          * using the CPU.
2853          */
2854         amdgpu_bo_evict_vram(adev);
2855
2856         pci_save_state(dev->pdev);
2857         if (suspend) {
2858                 /* Shut down the device */
2859                 pci_disable_device(dev->pdev);
2860                 pci_set_power_state(dev->pdev, PCI_D3hot);
2861         } else {
2862                 r = amdgpu_asic_reset(adev);
2863                 if (r)
2864                         DRM_ERROR("amdgpu asic reset failed\n");
2865         }
2866
2867         return 0;
2868 }
2869
2870 /**
2871  * amdgpu_device_resume - initiate device resume
2872  *
2873  * @dev: drm dev pointer
2874  * @resume: resume state
2875  * @fbcon : notify the fbdev of resume
2876  *
2877  * Bring the hw back to operating state (all asics).
2878  * Returns 0 for success or an error on failure.
2879  * Called at driver resume.
2880  */
2881 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2882 {
2883         struct drm_connector *connector;
2884         struct amdgpu_device *adev = dev->dev_private;
2885         struct drm_crtc *crtc;
2886         int r = 0;
2887
2888         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2889                 return 0;
2890
2891         if (resume) {
2892                 pci_set_power_state(dev->pdev, PCI_D0);
2893                 pci_restore_state(dev->pdev);
2894                 r = pci_enable_device(dev->pdev);
2895                 if (r)
2896                         return r;
2897         }
2898
2899         /* post card */
2900         if (amdgpu_device_need_post(adev)) {
2901                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2902                 if (r)
2903                         DRM_ERROR("amdgpu asic init failed\n");
2904         }
2905
2906         r = amdgpu_device_ip_resume(adev);
2907         if (r) {
2908                 DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
2909                 return r;
2910         }
2911         amdgpu_fence_driver_resume(adev);
2912
2913
2914         r = amdgpu_device_ip_late_init(adev);
2915         if (r)
2916                 return r;
2917
2918         if (!amdgpu_device_has_dc_support(adev)) {
2919                 /* pin cursors */
2920                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2921                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2922
2923                         if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
2924                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2925                                 r = amdgpu_bo_reserve(aobj, true);
2926                                 if (r == 0) {
2927                                         r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2928                                         if (r != 0)
2929                                                 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2930                                         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2931                                         amdgpu_bo_unreserve(aobj);
2932                                 }
2933                         }
2934                 }
2935         }
2936         r = amdgpu_amdkfd_resume(adev);
2937         if (r)
2938                 return r;
2939
2940         /* Make sure IB tests flushed */
2941         flush_delayed_work(&adev->late_init_work);
2942
2943         /* blat the mode back in */
2944         if (fbcon) {
2945                 if (!amdgpu_device_has_dc_support(adev)) {
2946                         /* pre DCE11 */
2947                         drm_helper_resume_force_mode(dev);
2948
2949                         /* turn on display hw */
2950                         drm_modeset_lock_all(dev);
2951                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2952                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2953                         }
2954                         drm_modeset_unlock_all(dev);
2955                 }
2956                 amdgpu_fbdev_set_suspend(adev, 0);
2957         }
2958
2959         drm_kms_helper_poll_enable(dev);
2960
2961         /*
2962          * Most of the connector probing functions try to acquire runtime pm
2963          * refs to ensure that the GPU is powered on when connector polling is
2964          * performed. Since we're calling this from a runtime PM callback,
2965          * trying to acquire rpm refs will cause us to deadlock.
2966          *
2967          * Since we're guaranteed to be holding the rpm lock, it's safe to
2968          * temporarily disable the rpm helpers so this doesn't deadlock us.
2969          */
2970 #ifdef CONFIG_PM
2971         dev->dev->power.disable_depth++;
2972 #endif
2973         if (!amdgpu_device_has_dc_support(adev))
2974                 drm_helper_hpd_irq_event(dev);
2975         else
2976                 drm_kms_helper_hotplug_event(dev);
2977 #ifdef CONFIG_PM
2978         dev->dev->power.disable_depth--;
2979 #endif
2980         adev->in_suspend = false;
2981
2982         return 0;
2983 }
2984
2985 /**
2986  * amdgpu_device_ip_check_soft_reset - did soft reset succeed
2987  *
2988  * @adev: amdgpu_device pointer
2989  *
2990  * The list of all the hardware IPs that make up the asic is walked and
2991  * the check_soft_reset callbacks are run.  check_soft_reset determines
2992  * if the asic is still hung or not.
2993  * Returns true if any of the IPs are still in a hung state, false if not.
2994  */
2995 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
2996 {
2997         int i;
2998         bool asic_hang = false;
2999
3000         if (amdgpu_sriov_vf(adev))
3001                 return true;
3002
3003         if (amdgpu_asic_need_full_reset(adev))
3004                 return true;
3005
3006         for (i = 0; i < adev->num_ip_blocks; i++) {
3007                 if (!adev->ip_blocks[i].status.valid)
3008                         continue;
3009                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
3010                         adev->ip_blocks[i].status.hang =
3011                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
3012                 if (adev->ip_blocks[i].status.hang) {
3013                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
3014                         asic_hang = true;
3015                 }
3016         }
3017         return asic_hang;
3018 }
3019
3020 /**
3021  * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
3022  *
3023  * @adev: amdgpu_device pointer
3024  *
3025  * The list of all the hardware IPs that make up the asic is walked and the
3026  * pre_soft_reset callbacks are run if the block is hung.  pre_soft_reset
3027  * handles any IP specific hardware or software state changes that are
3028  * necessary for a soft reset to succeed.
3029  * Returns 0 on success, negative error code on failure.
3030  */
3031 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
3032 {
3033         int i, r = 0;
3034
3035         for (i = 0; i < adev->num_ip_blocks; i++) {
3036                 if (!adev->ip_blocks[i].status.valid)
3037                         continue;
3038                 if (adev->ip_blocks[i].status.hang &&
3039                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
3040                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
3041                         if (r)
3042                                 return r;
3043                 }
3044         }
3045
3046         return 0;
3047 }
3048
3049 /**
3050  * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
3051  *
3052  * @adev: amdgpu_device pointer
3053  *
3054  * Some hardware IPs cannot be soft reset.  If they are hung, a full gpu
3055  * reset is necessary to recover.
3056  * Returns true if a full asic reset is required, false if not.
3057  */
3058 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
3059 {
3060         int i;
3061
3062         if (amdgpu_asic_need_full_reset(adev))
3063                 return true;
3064
3065         for (i = 0; i < adev->num_ip_blocks; i++) {
3066                 if (!adev->ip_blocks[i].status.valid)
3067                         continue;
3068                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
3069                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
3070                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
3071                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
3072                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3073                         if (adev->ip_blocks[i].status.hang) {
3074                                 DRM_INFO("Some block need full reset!\n");
3075                                 return true;
3076                         }
3077                 }
3078         }
3079         return false;
3080 }
3081
3082 /**
3083  * amdgpu_device_ip_soft_reset - do a soft reset
3084  *
3085  * @adev: amdgpu_device pointer
3086  *
3087  * The list of all the hardware IPs that make up the asic is walked and the
3088  * soft_reset callbacks are run if the block is hung.  soft_reset handles any
3089  * IP specific hardware or software state changes that are necessary to soft
3090  * reset the IP.
3091  * Returns 0 on success, negative error code on failure.
3092  */
3093 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
3094 {
3095         int i, r = 0;
3096
3097         for (i = 0; i < adev->num_ip_blocks; i++) {
3098                 if (!adev->ip_blocks[i].status.valid)
3099                         continue;
3100                 if (adev->ip_blocks[i].status.hang &&
3101                     adev->ip_blocks[i].version->funcs->soft_reset) {
3102                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
3103                         if (r)
3104                                 return r;
3105                 }
3106         }
3107
3108         return 0;
3109 }
3110
3111 /**
3112  * amdgpu_device_ip_post_soft_reset - clean up from soft reset
3113  *
3114  * @adev: amdgpu_device pointer
3115  *
3116  * The list of all the hardware IPs that make up the asic is walked and the
3117  * post_soft_reset callbacks are run if the asic was hung.  post_soft_reset
3118  * handles any IP specific hardware or software state changes that are
3119  * necessary after the IP has been soft reset.
3120  * Returns 0 on success, negative error code on failure.
3121  */
3122 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
3123 {
3124         int i, r = 0;
3125
3126         for (i = 0; i < adev->num_ip_blocks; i++) {
3127                 if (!adev->ip_blocks[i].status.valid)
3128                         continue;
3129                 if (adev->ip_blocks[i].status.hang &&
3130                     adev->ip_blocks[i].version->funcs->post_soft_reset)
3131                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
3132                 if (r)
3133                         return r;
3134         }
3135
3136         return 0;
3137 }
3138
3139 /**
3140  * amdgpu_device_recover_vram - Recover some VRAM contents
3141  *
3142  * @adev: amdgpu_device pointer
3143  *
3144  * Restores the contents of VRAM buffers from the shadows in GTT.  Used to
3145  * restore things like GPUVM page tables after a GPU reset where
3146  * the contents of VRAM might be lost.
3147  *
3148  * Returns:
3149  * 0 on success, negative error code on failure.
3150  */
3151 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
3152 {
3153         struct dma_fence *fence = NULL, *next = NULL;
3154         struct amdgpu_bo *shadow;
3155         long r = 1, tmo;
3156
3157         if (amdgpu_sriov_runtime(adev))
3158                 tmo = msecs_to_jiffies(8000);
3159         else
3160                 tmo = msecs_to_jiffies(100);
3161
3162         DRM_INFO("recover vram bo from shadow start\n");
3163         mutex_lock(&adev->shadow_list_lock);
3164         list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {
3165
3166                 /* No need to recover an evicted BO */
3167                 if (shadow->tbo.mem.mem_type != TTM_PL_TT ||
3168                     shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET ||
3169                     shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM)
3170                         continue;
3171
3172                 r = amdgpu_bo_restore_shadow(shadow, &next);
3173                 if (r)
3174                         break;
3175
3176                 if (fence) {
3177                         tmo = dma_fence_wait_timeout(fence, false, tmo);
3178                         dma_fence_put(fence);
3179                         fence = next;
3180                         if (tmo == 0) {
3181                                 r = -ETIMEDOUT;
3182                                 break;
3183                         } else if (tmo < 0) {
3184                                 r = tmo;
3185                                 break;
3186                         }
3187                 } else {
3188                         fence = next;
3189                 }
3190         }
3191         mutex_unlock(&adev->shadow_list_lock);
3192
3193         if (fence)
3194                 tmo = dma_fence_wait_timeout(fence, false, tmo);
3195         dma_fence_put(fence);
3196
3197         if (r < 0 || tmo <= 0) {
3198                 DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
3199                 return -EIO;
3200         }
3201
3202         DRM_INFO("recover vram bo from shadow done\n");
3203         return 0;
3204 }
3205
3206
3207 /**
3208  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
3209  *
3210  * @adev: amdgpu device pointer
3211  * @from_hypervisor: request from hypervisor
3212  *
3213  * do VF FLR and reinitialize Asic
3214  * return 0 means succeeded otherwise failed
3215  */
3216 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
3217                                      bool from_hypervisor)
3218 {
3219         int r;
3220
3221         if (from_hypervisor)
3222                 r = amdgpu_virt_request_full_gpu(adev, true);
3223         else
3224                 r = amdgpu_virt_reset_gpu(adev);
3225         if (r)
3226                 return r;
3227
3228         /* Resume IP prior to SMC */
3229         r = amdgpu_device_ip_reinit_early_sriov(adev);
3230         if (r)
3231                 goto error;
3232
3233         /* we need recover gart prior to run SMC/CP/SDMA resume */
3234         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3235
3236         r = amdgpu_device_fw_loading(adev);
3237         if (r)
3238                 return r;
3239
3240         /* now we are okay to resume SMC/CP/SDMA */
3241         r = amdgpu_device_ip_reinit_late_sriov(adev);
3242         if (r)
3243                 goto error;
3244
3245         amdgpu_irq_gpu_reset_resume_helper(adev);
3246         r = amdgpu_ib_ring_tests(adev);
3247
3248 error:
3249         amdgpu_virt_init_data_exchange(adev);
3250         amdgpu_virt_release_full_gpu(adev, true);
3251         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
3252                 atomic_inc(&adev->vram_lost_counter);
3253                 r = amdgpu_device_recover_vram(adev);
3254         }
3255
3256         return r;
3257 }
3258
3259 /**
3260  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
3261  *
3262  * @adev: amdgpu device pointer
3263  *
3264  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
3265  * a hung GPU.
3266  */
3267 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
3268 {
3269         if (!amdgpu_device_ip_check_soft_reset(adev)) {
3270                 DRM_INFO("Timeout, but no hardware hang detected.\n");
3271                 return false;
3272         }
3273
3274         if (amdgpu_gpu_recovery == 0)
3275                 goto disabled;
3276
3277         if (amdgpu_sriov_vf(adev))
3278                 return true;
3279
3280         if (amdgpu_gpu_recovery == -1) {
3281                 switch (adev->asic_type) {
3282                 case CHIP_BONAIRE:
3283                 case CHIP_HAWAII:
3284                 case CHIP_TOPAZ:
3285                 case CHIP_TONGA:
3286                 case CHIP_FIJI:
3287                 case CHIP_POLARIS10:
3288                 case CHIP_POLARIS11:
3289                 case CHIP_POLARIS12:
3290                 case CHIP_VEGAM:
3291                 case CHIP_VEGA20:
3292                 case CHIP_VEGA10:
3293                 case CHIP_VEGA12:
3294                         break;
3295                 default:
3296                         goto disabled;
3297                 }
3298         }
3299
3300         return true;
3301
3302 disabled:
3303                 DRM_INFO("GPU recovery disabled.\n");
3304                 return false;
3305 }
3306
3307
3308 static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
3309                                         struct amdgpu_job *job,
3310                                         bool *need_full_reset_arg)
3311 {
3312         int i, r = 0;
3313         bool need_full_reset  = *need_full_reset_arg;
3314
3315         /* block all schedulers and reset given job's ring */
3316         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3317                 struct amdgpu_ring *ring = adev->rings[i];
3318
3319                 if (!ring || !ring->sched.thread)
3320                         continue;
3321
3322                 drm_sched_stop(&ring->sched);
3323
3324                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3325                 amdgpu_fence_driver_force_completion(ring);
3326         }
3327
3328         if(job)
3329                 drm_sched_increase_karma(&job->base);
3330
3331
3332
3333         if (!amdgpu_sriov_vf(adev)) {
3334
3335                 if (!need_full_reset)
3336                         need_full_reset = amdgpu_device_ip_need_full_reset(adev);
3337
3338                 if (!need_full_reset) {
3339                         amdgpu_device_ip_pre_soft_reset(adev);
3340                         r = amdgpu_device_ip_soft_reset(adev);
3341                         amdgpu_device_ip_post_soft_reset(adev);
3342                         if (r || amdgpu_device_ip_check_soft_reset(adev)) {
3343                                 DRM_INFO("soft reset failed, will fallback to full reset!\n");
3344                                 need_full_reset = true;
3345                         }
3346                 }
3347
3348                 if (need_full_reset)
3349                         r = amdgpu_device_ip_suspend(adev);
3350
3351                 *need_full_reset_arg = need_full_reset;
3352         }
3353
3354         return r;
3355 }
3356
3357 static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
3358                                struct list_head *device_list_handle,
3359                                bool *need_full_reset_arg)
3360 {
3361         struct amdgpu_device *tmp_adev = NULL;
3362         bool need_full_reset = *need_full_reset_arg, vram_lost = false;
3363         int r = 0;
3364
3365         /*
3366          * ASIC reset has to be done on all HGMI hive nodes ASAP
3367          * to allow proper links negotiation in FW (within 1 sec)
3368          */
3369         if (need_full_reset) {
3370                 list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3371                         /* For XGMI run all resets in parallel to speed up the process */
3372                         if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3373                                 if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work))
3374                                         r = -EALREADY;
3375                         } else
3376                                 r = amdgpu_asic_reset(tmp_adev);
3377
3378                         if (r) {
3379                                 DRM_ERROR("ASIC reset failed with err r, %d for drm dev, %s",
3380                                          r, tmp_adev->ddev->unique);
3381                                 break;
3382                         }
3383                 }
3384
3385                 /* For XGMI wait for all PSP resets to complete before proceed */
3386                 if (!r) {
3387                         list_for_each_entry(tmp_adev, device_list_handle,
3388                                             gmc.xgmi.head) {
3389                                 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
3390                                         flush_work(&tmp_adev->xgmi_reset_work);
3391                                         r = tmp_adev->asic_reset_res;
3392                                         if (r)
3393                                                 break;
3394                                 }
3395                         }
3396                 }
3397         }
3398
3399
3400         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3401                 if (need_full_reset) {
3402                         /* post card */
3403                         if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context))
3404                                 DRM_WARN("asic atom init failed!");
3405
3406                         if (!r) {
3407                                 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
3408                                 r = amdgpu_device_ip_resume_phase1(tmp_adev);
3409                                 if (r)
3410                                         goto out;
3411
3412                                 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
3413                                 if (vram_lost) {
3414                                         DRM_ERROR("VRAM is lost!\n");
3415                                         atomic_inc(&tmp_adev->vram_lost_counter);
3416                                 }
3417
3418                                 r = amdgpu_gtt_mgr_recover(
3419                                         &tmp_adev->mman.bdev.man[TTM_PL_TT]);
3420                                 if (r)
3421                                         goto out;
3422
3423                                 r = amdgpu_device_fw_loading(tmp_adev);
3424                                 if (r)
3425                                         return r;
3426
3427                                 r = amdgpu_device_ip_resume_phase2(tmp_adev);
3428                                 if (r)
3429                                         goto out;
3430
3431                                 if (vram_lost)
3432                                         amdgpu_device_fill_reset_magic(tmp_adev);
3433
3434                                 /* Update PSP FW topology after reset */
3435                                 if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1)
3436                                         r = amdgpu_xgmi_update_topology(hive, tmp_adev);
3437                         }
3438                 }
3439
3440
3441 out:
3442                 if (!r) {
3443                         amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
3444                         r = amdgpu_ib_ring_tests(tmp_adev);
3445                         if (r) {
3446                                 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
3447                                 r = amdgpu_device_ip_suspend(tmp_adev);
3448                                 need_full_reset = true;
3449                                 r = -EAGAIN;
3450                                 goto end;
3451                         }
3452                 }
3453
3454                 if (!r)
3455                         r = amdgpu_device_recover_vram(tmp_adev);
3456                 else
3457                         tmp_adev->asic_reset_res = r;
3458         }
3459
3460 end:
3461         *need_full_reset_arg = need_full_reset;
3462         return r;
3463 }
3464
3465 static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
3466                                           struct amdgpu_job *job)
3467 {
3468         int i;
3469
3470         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3471                 struct amdgpu_ring *ring = adev->rings[i];
3472
3473                 if (!ring || !ring->sched.thread)
3474                         continue;
3475
3476                 if (!adev->asic_reset_res)
3477                         drm_sched_resubmit_jobs(&ring->sched);
3478
3479                 drm_sched_start(&ring->sched, !adev->asic_reset_res);
3480         }
3481
3482         if (!amdgpu_device_has_dc_support(adev)) {
3483                 drm_helper_resume_force_mode(adev->ddev);
3484         }
3485
3486         adev->asic_reset_res = 0;
3487 }
3488
3489 static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
3490 {
3491         mutex_lock(&adev->lock_reset);
3492         atomic_inc(&adev->gpu_reset_counter);
3493         adev->in_gpu_reset = 1;
3494         /* Block kfd: SRIOV would do it separately */
3495         if (!amdgpu_sriov_vf(adev))
3496                 amdgpu_amdkfd_pre_reset(adev);
3497 }
3498
3499 static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
3500 {
3501         /*unlock kfd: SRIOV would do it separately */
3502         if (!amdgpu_sriov_vf(adev))
3503                 amdgpu_amdkfd_post_reset(adev);
3504         amdgpu_vf_error_trans_all(adev);
3505         adev->in_gpu_reset = 0;
3506         mutex_unlock(&adev->lock_reset);
3507 }
3508
3509
3510 /**
3511  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
3512  *
3513  * @adev: amdgpu device pointer
3514  * @job: which job trigger hang
3515  *
3516  * Attempt to reset the GPU if it has hung (all asics).
3517  * Attempt to do soft-reset or full-reset and reinitialize Asic
3518  * Returns 0 for success or an error on failure.
3519  */
3520
3521 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
3522                               struct amdgpu_job *job)
3523 {
3524         int r;
3525         struct amdgpu_hive_info *hive = NULL;
3526         bool need_full_reset = false;
3527         struct amdgpu_device *tmp_adev = NULL;
3528         struct list_head device_list, *device_list_handle =  NULL;
3529
3530         INIT_LIST_HEAD(&device_list);
3531
3532         dev_info(adev->dev, "GPU reset begin!\n");
3533
3534         /*
3535          * In case of XGMI hive disallow concurrent resets to be triggered
3536          * by different nodes. No point also since the one node already executing
3537          * reset will also reset all the other nodes in the hive.
3538          */
3539         hive = amdgpu_get_xgmi_hive(adev, 0);
3540         if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
3541             !mutex_trylock(&hive->reset_lock))
3542                 return 0;
3543
3544         /* Start with adev pre asic reset first for soft reset check.*/
3545         amdgpu_device_lock_adev(adev);
3546         r = amdgpu_device_pre_asic_reset(adev,
3547                                          job,
3548                                          &need_full_reset);
3549         if (r) {
3550                 /*TODO Should we stop ?*/
3551                 DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3552                           r, adev->ddev->unique);
3553                 adev->asic_reset_res = r;
3554         }
3555
3556         /* Build list of devices to reset */
3557         if  (need_full_reset && adev->gmc.xgmi.num_physical_nodes > 1) {
3558                 if (!hive) {
3559                         amdgpu_device_unlock_adev(adev);
3560                         return -ENODEV;
3561                 }
3562
3563                 /*
3564                  * In case we are in XGMI hive mode device reset is done for all the
3565                  * nodes in the hive to retrain all XGMI links and hence the reset
3566                  * sequence is executed in loop on all nodes.
3567                  */
3568                 device_list_handle = &hive->device_list;
3569         } else {
3570                 list_add_tail(&adev->gmc.xgmi.head, &device_list);
3571                 device_list_handle = &device_list;
3572         }
3573
3574 retry:  /* Rest of adevs pre asic reset from XGMI hive. */
3575         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3576
3577                 if (tmp_adev == adev)
3578                         continue;
3579
3580                 amdgpu_device_lock_adev(tmp_adev);
3581                 r = amdgpu_device_pre_asic_reset(tmp_adev,
3582                                                  NULL,
3583                                                  &need_full_reset);
3584                 /*TODO Should we stop ?*/
3585                 if (r) {
3586                         DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
3587                                   r, tmp_adev->ddev->unique);
3588                         tmp_adev->asic_reset_res = r;
3589                 }
3590         }
3591
3592         /* Actual ASIC resets if needed.*/
3593         /* TODO Implement XGMI hive reset logic for SRIOV */
3594         if (amdgpu_sriov_vf(adev)) {
3595                 r = amdgpu_device_reset_sriov(adev, job ? false : true);
3596                 if (r)
3597                         adev->asic_reset_res = r;
3598         } else {
3599                 r  = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset);
3600                 if (r && r == -EAGAIN)
3601                         goto retry;
3602         }
3603
3604         /* Post ASIC reset for all devs .*/
3605         list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
3606                 amdgpu_device_post_asic_reset(tmp_adev, tmp_adev == adev ? job : NULL);
3607
3608                 if (r) {
3609                         /* bad news, how to tell it to userspace ? */
3610                         dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3611                         amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3612                 } else {
3613                         dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter));
3614                 }
3615
3616                 amdgpu_device_unlock_adev(tmp_adev);
3617         }
3618
3619         if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
3620                 mutex_unlock(&hive->reset_lock);
3621
3622         if (r)
3623                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
3624         return r;
3625 }
3626
3627 static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
3628                                                   enum pci_bus_speed *speed,
3629                                                   enum pcie_link_width *width)
3630 {
3631         struct pci_dev *pdev = adev->pdev;
3632         enum pci_bus_speed cur_speed;
3633         enum pcie_link_width cur_width;
3634         u32 ret = 1;
3635
3636         *speed = PCI_SPEED_UNKNOWN;
3637         *width = PCIE_LNK_WIDTH_UNKNOWN;
3638
3639         while (pdev) {
3640                 cur_speed = pcie_get_speed_cap(pdev);
3641                 cur_width = pcie_get_width_cap(pdev);
3642                 ret = pcie_bandwidth_available(adev->pdev, NULL,
3643                                                        NULL, &cur_width);
3644                 if (!ret)
3645                         cur_width = PCIE_LNK_WIDTH_RESRV;
3646
3647                 if (cur_speed != PCI_SPEED_UNKNOWN) {
3648                         if (*speed == PCI_SPEED_UNKNOWN)
3649                                 *speed = cur_speed;
3650                         else if (cur_speed < *speed)
3651                                 *speed = cur_speed;
3652                 }
3653
3654                 if (cur_width != PCIE_LNK_WIDTH_UNKNOWN) {
3655                         if (*width == PCIE_LNK_WIDTH_UNKNOWN)
3656                                 *width = cur_width;
3657                         else if (cur_width < *width)
3658                                 *width = cur_width;
3659                 }
3660                 pdev = pci_upstream_bridge(pdev);
3661         }
3662 }
3663
3664 /**
3665  * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
3666  *
3667  * @adev: amdgpu_device pointer
3668  *
3669  * Fetchs and stores in the driver the PCIE capabilities (gen speed
3670  * and lanes) of the slot the device is in. Handles APUs and
3671  * virtualized environments where PCIE config space may not be available.
3672  */
3673 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
3674 {
3675         struct pci_dev *pdev;
3676         enum pci_bus_speed speed_cap, platform_speed_cap;
3677         enum pcie_link_width platform_link_width;
3678
3679         if (amdgpu_pcie_gen_cap)
3680                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3681
3682         if (amdgpu_pcie_lane_cap)
3683                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3684
3685         /* covers APUs as well */
3686         if (pci_is_root_bus(adev->pdev->bus)) {
3687                 if (adev->pm.pcie_gen_mask == 0)
3688                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3689                 if (adev->pm.pcie_mlw_mask == 0)
3690                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3691                 return;
3692         }
3693
3694         if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
3695                 return;
3696
3697         amdgpu_device_get_min_pci_speed_width(adev, &platform_speed_cap,
3698                                               &platform_link_width);
3699
3700         if (adev->pm.pcie_gen_mask == 0) {
3701                 /* asic caps */
3702                 pdev = adev->pdev;
3703                 speed_cap = pcie_get_speed_cap(pdev);
3704                 if (speed_cap == PCI_SPEED_UNKNOWN) {
3705                         adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3706                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3707                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3708                 } else {
3709                         if (speed_cap == PCIE_SPEED_16_0GT)
3710                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3711                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3712                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3713                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
3714                         else if (speed_cap == PCIE_SPEED_8_0GT)
3715                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3716                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3717                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3718                         else if (speed_cap == PCIE_SPEED_5_0GT)
3719                                 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3720                                                           CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
3721                         else
3722                                 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
3723                 }
3724                 /* platform caps */
3725                 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
3726                         adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3727                                                    CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3728                 } else {
3729                         if (platform_speed_cap == PCIE_SPEED_16_0GT)
3730                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3731                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3732                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
3733                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
3734                         else if (platform_speed_cap == PCIE_SPEED_8_0GT)
3735                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3736                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3737                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
3738                         else if (platform_speed_cap == PCIE_SPEED_5_0GT)
3739                                 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3740                                                            CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
3741                         else
3742                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3743
3744                 }
3745         }
3746         if (adev->pm.pcie_mlw_mask == 0) {
3747                 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
3748                         adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
3749                 } else {
3750                         switch (platform_link_width) {
3751                         case PCIE_LNK_X32:
3752                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3753                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3754                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3755                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3756                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3757                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3758                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3759                                 break;
3760                         case PCIE_LNK_X16:
3761                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3762                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3763                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3764                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3765                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3766                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3767                                 break;
3768                         case PCIE_LNK_X12:
3769                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3770                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3771                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3772                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3773                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3774                                 break;
3775                         case PCIE_LNK_X8:
3776                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3777                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3778                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3779                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3780                                 break;
3781                         case PCIE_LNK_X4:
3782                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3783                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3784                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3785                                 break;
3786                         case PCIE_LNK_X2:
3787                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3788                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3789                                 break;
3790                         case PCIE_LNK_X1:
3791                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3792                                 break;
3793                         default:
3794                                 break;
3795                         }
3796                 }
3797         }
3798 }
3799