2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
56 #include "amdgpu_pm.h"
58 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
59 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
61 static const char *amdgpu_asic_name[] = {
84 bool amdgpu_device_is_px(struct drm_device *dev)
86 struct amdgpu_device *adev = dev->dev_private;
88 if (adev->flags & AMD_IS_PX)
94 * MMIO register access helper functions.
96 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
101 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
102 BUG_ON(in_interrupt());
103 return amdgpu_virt_kiq_rreg(adev, reg);
106 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
107 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
111 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
112 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
113 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
114 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
116 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
120 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
123 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
125 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
126 BUG_ON(in_interrupt());
127 return amdgpu_virt_kiq_wreg(adev, reg, v);
130 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
131 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
135 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
136 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
137 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
138 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
142 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
144 if ((reg * 4) < adev->rio_mem_size)
145 return ioread32(adev->rio_mem + (reg * 4));
147 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
148 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
152 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
155 if ((reg * 4) < adev->rio_mem_size)
156 iowrite32(v, adev->rio_mem + (reg * 4));
158 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
159 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
164 * amdgpu_mm_rdoorbell - read a doorbell dword
166 * @adev: amdgpu_device pointer
167 * @index: doorbell index
169 * Returns the value in the doorbell aperture at the
170 * requested doorbell index (CIK).
172 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
174 if (index < adev->doorbell.num_doorbells) {
175 return readl(adev->doorbell.ptr + index);
177 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
183 * amdgpu_mm_wdoorbell - write a doorbell dword
185 * @adev: amdgpu_device pointer
186 * @index: doorbell index
189 * Writes @v to the doorbell aperture at the
190 * requested doorbell index (CIK).
192 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
194 if (index < adev->doorbell.num_doorbells) {
195 writel(v, adev->doorbell.ptr + index);
197 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
202 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
204 * @adev: amdgpu_device pointer
205 * @index: doorbell index
207 * Returns the value in the doorbell aperture at the
208 * requested doorbell index (VEGA10+).
210 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
212 if (index < adev->doorbell.num_doorbells) {
213 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
215 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
221 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
223 * @adev: amdgpu_device pointer
224 * @index: doorbell index
227 * Writes @v to the doorbell aperture at the
228 * requested doorbell index (VEGA10+).
230 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
232 if (index < adev->doorbell.num_doorbells) {
233 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
235 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
240 * amdgpu_invalid_rreg - dummy reg read function
242 * @adev: amdgpu device pointer
243 * @reg: offset of register
245 * Dummy register read function. Used for register blocks
246 * that certain asics don't have (all asics).
247 * Returns the value in the register.
249 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
251 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
257 * amdgpu_invalid_wreg - dummy reg write function
259 * @adev: amdgpu device pointer
260 * @reg: offset of register
261 * @v: value to write to the register
263 * Dummy register read function. Used for register blocks
264 * that certain asics don't have (all asics).
266 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
268 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
274 * amdgpu_block_invalid_rreg - dummy reg read function
276 * @adev: amdgpu device pointer
277 * @block: offset of instance
278 * @reg: offset of register
280 * Dummy register read function. Used for register blocks
281 * that certain asics don't have (all asics).
282 * Returns the value in the register.
284 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
285 uint32_t block, uint32_t reg)
287 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
294 * amdgpu_block_invalid_wreg - dummy reg write function
296 * @adev: amdgpu device pointer
297 * @block: offset of instance
298 * @reg: offset of register
299 * @v: value to write to the register
301 * Dummy register read function. Used for register blocks
302 * that certain asics don't have (all asics).
304 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
306 uint32_t reg, uint32_t v)
308 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
313 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
317 if (adev->vram_scratch.robj == NULL) {
318 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
319 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
320 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
321 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
322 NULL, NULL, &adev->vram_scratch.robj);
328 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
329 if (unlikely(r != 0))
331 r = amdgpu_bo_pin(adev->vram_scratch.robj,
332 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
334 amdgpu_bo_unreserve(adev->vram_scratch.robj);
337 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
338 (void **)&adev->vram_scratch.ptr);
340 amdgpu_bo_unpin(adev->vram_scratch.robj);
341 amdgpu_bo_unreserve(adev->vram_scratch.robj);
346 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
350 if (adev->vram_scratch.robj == NULL) {
353 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
354 if (likely(r == 0)) {
355 amdgpu_bo_kunmap(adev->vram_scratch.robj);
356 amdgpu_bo_unpin(adev->vram_scratch.robj);
357 amdgpu_bo_unreserve(adev->vram_scratch.robj);
359 amdgpu_bo_unref(&adev->vram_scratch.robj);
363 * amdgpu_program_register_sequence - program an array of registers.
365 * @adev: amdgpu_device pointer
366 * @registers: pointer to the register array
367 * @array_size: size of the register array
369 * Programs an array or registers with and and or masks.
370 * This is a helper for setting golden registers.
372 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
373 const u32 *registers,
374 const u32 array_size)
376 u32 tmp, reg, and_mask, or_mask;
382 for (i = 0; i < array_size; i +=3) {
383 reg = registers[i + 0];
384 and_mask = registers[i + 1];
385 or_mask = registers[i + 2];
387 if (and_mask == 0xffffffff) {
398 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
400 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
404 * GPU doorbell aperture helpers function.
407 * amdgpu_doorbell_init - Init doorbell driver information.
409 * @adev: amdgpu_device pointer
411 * Init doorbell driver information (CIK)
412 * Returns 0 on success, error on failure.
414 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
416 /* doorbell bar mapping */
417 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
418 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
420 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
421 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
422 if (adev->doorbell.num_doorbells == 0)
425 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
426 if (adev->doorbell.ptr == NULL) {
429 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
430 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
436 * amdgpu_doorbell_fini - Tear down doorbell driver information.
438 * @adev: amdgpu_device pointer
440 * Tear down doorbell driver information (CIK)
442 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
444 iounmap(adev->doorbell.ptr);
445 adev->doorbell.ptr = NULL;
449 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
452 * @adev: amdgpu_device pointer
453 * @aperture_base: output returning doorbell aperture base physical address
454 * @aperture_size: output returning doorbell aperture size in bytes
455 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
457 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
458 * takes doorbells required for its own rings and reports the setup to amdkfd.
459 * amdgpu reserved doorbells are at the start of the doorbell aperture.
461 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
462 phys_addr_t *aperture_base,
463 size_t *aperture_size,
464 size_t *start_offset)
467 * The first num_doorbells are used by amdgpu.
468 * amdkfd takes whatever's left in the aperture.
470 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
471 *aperture_base = adev->doorbell.base;
472 *aperture_size = adev->doorbell.size;
473 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
483 * Writeback is the the method by which the the GPU updates special pages
484 * in memory with the status of certain GPU events (fences, ring pointers,
489 * amdgpu_wb_fini - Disable Writeback and free memory
491 * @adev: amdgpu_device pointer
493 * Disables Writeback and frees the Writeback memory (all asics).
494 * Used at driver shutdown.
496 static void amdgpu_wb_fini(struct amdgpu_device *adev)
498 if (adev->wb.wb_obj) {
499 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
501 (void **)&adev->wb.wb);
502 adev->wb.wb_obj = NULL;
507 * amdgpu_wb_init- Init Writeback driver info and allocate memory
509 * @adev: amdgpu_device pointer
511 * Disables Writeback and frees the Writeback memory (all asics).
512 * Used at driver startup.
513 * Returns 0 on success or an -error on failure.
515 static int amdgpu_wb_init(struct amdgpu_device *adev)
519 if (adev->wb.wb_obj == NULL) {
520 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t),
521 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
522 &adev->wb.wb_obj, &adev->wb.gpu_addr,
523 (void **)&adev->wb.wb);
525 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
529 adev->wb.num_wb = AMDGPU_MAX_WB;
530 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
532 /* clear wb memory */
533 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
540 * amdgpu_wb_get - Allocate a wb entry
542 * @adev: amdgpu_device pointer
545 * Allocate a wb slot for use by the driver (all asics).
546 * Returns 0 on success or -EINVAL on failure.
548 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
550 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
551 if (offset < adev->wb.num_wb) {
552 __set_bit(offset, adev->wb.used);
561 * amdgpu_wb_get_64bit - Allocate a wb entry
563 * @adev: amdgpu_device pointer
566 * Allocate a wb slot for use by the driver (all asics).
567 * Returns 0 on success or -EINVAL on failure.
569 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
571 unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
572 adev->wb.num_wb, 0, 2, 7, 0);
573 if ((offset + 1) < adev->wb.num_wb) {
574 __set_bit(offset, adev->wb.used);
575 __set_bit(offset + 1, adev->wb.used);
584 * amdgpu_wb_free - Free a wb entry
586 * @adev: amdgpu_device pointer
589 * Free a wb slot allocated for use by the driver (all asics)
591 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
593 if (wb < adev->wb.num_wb)
594 __clear_bit(wb, adev->wb.used);
598 * amdgpu_wb_free_64bit - Free a wb entry
600 * @adev: amdgpu_device pointer
603 * Free a wb slot allocated for use by the driver (all asics)
605 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
607 if ((wb + 1) < adev->wb.num_wb) {
608 __clear_bit(wb, adev->wb.used);
609 __clear_bit(wb + 1, adev->wb.used);
614 * amdgpu_vram_location - try to find VRAM location
615 * @adev: amdgpu device structure holding all necessary informations
616 * @mc: memory controller structure holding memory informations
617 * @base: base address at which to put VRAM
619 * Function will place try to place VRAM at base address provided
620 * as parameter (which is so far either PCI aperture address or
621 * for IGP TOM base address).
623 * If there is not enough space to fit the unvisible VRAM in the 32bits
624 * address space then we limit the VRAM size to the aperture.
626 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
627 * this shouldn't be a problem as we are using the PCI aperture as a reference.
628 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
631 * Note: we use mc_vram_size as on some board we need to program the mc to
632 * cover the whole aperture even if VRAM size is inferior to aperture size
633 * Novell bug 204882 + along with lots of ubuntu ones
635 * Note: when limiting vram it's safe to overwritte real_vram_size because
636 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
637 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
640 * Note: IGP TOM addr should be the same as the aperture addr, we don't
641 * explicitly check for that thought.
643 * FIXME: when reducing VRAM size align new size on power of 2.
645 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
647 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
649 mc->vram_start = base;
650 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
651 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
652 mc->real_vram_size = mc->aper_size;
653 mc->mc_vram_size = mc->aper_size;
655 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
656 if (limit && limit < mc->real_vram_size)
657 mc->real_vram_size = limit;
658 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
659 mc->mc_vram_size >> 20, mc->vram_start,
660 mc->vram_end, mc->real_vram_size >> 20);
664 * amdgpu_gtt_location - try to find GTT location
665 * @adev: amdgpu device structure holding all necessary informations
666 * @mc: memory controller structure holding memory informations
668 * Function will place try to place GTT before or after VRAM.
670 * If GTT size is bigger than space left then we ajust GTT size.
671 * Thus function will never fails.
673 * FIXME: when reducing GTT size align new size on power of 2.
675 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
677 u64 size_af, size_bf;
679 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
680 size_bf = mc->vram_start & ~mc->gtt_base_align;
681 if (size_bf > size_af) {
682 if (mc->gtt_size > size_bf) {
683 dev_warn(adev->dev, "limiting GTT\n");
684 mc->gtt_size = size_bf;
688 if (mc->gtt_size > size_af) {
689 dev_warn(adev->dev, "limiting GTT\n");
690 mc->gtt_size = size_af;
692 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
694 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
695 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
696 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
700 * GPU helpers function.
703 * amdgpu_need_post - check if the hw need post or not
705 * @adev: amdgpu_device pointer
707 * Check if the asic has been initialized (all asics) at driver startup
708 * or post is needed if hw reset is performed.
709 * Returns true if need or false if not.
711 bool amdgpu_need_post(struct amdgpu_device *adev)
715 if (adev->has_hw_reset) {
716 adev->has_hw_reset = false;
719 /* then check MEM_SIZE, in case the crtcs are off */
720 reg = amdgpu_asic_get_config_memsize(adev);
722 if ((reg != 0) && (reg != 0xffffffff))
729 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
731 if (amdgpu_sriov_vf(adev))
734 if (amdgpu_passthrough(adev)) {
735 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
736 * some old smc fw still need driver do vPost otherwise gpu hang, while
737 * those smc fw version above 22.15 doesn't have this flaw, so we force
738 * vpost executed for smc version below 22.15
740 if (adev->asic_type == CHIP_FIJI) {
743 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
744 /* force vPost if error occured */
748 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
749 if (fw_ver < 0x00160e00)
753 return amdgpu_need_post(adev);
757 * amdgpu_dummy_page_init - init dummy page used by the driver
759 * @adev: amdgpu_device pointer
761 * Allocate the dummy page used by the driver (all asics).
762 * This dummy page is used by the driver as a filler for gart entries
763 * when pages are taken out of the GART
764 * Returns 0 on sucess, -ENOMEM on failure.
766 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
768 if (adev->dummy_page.page)
770 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
771 if (adev->dummy_page.page == NULL)
773 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
774 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
775 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
776 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
777 __free_page(adev->dummy_page.page);
778 adev->dummy_page.page = NULL;
785 * amdgpu_dummy_page_fini - free dummy page used by the driver
787 * @adev: amdgpu_device pointer
789 * Frees the dummy page used by the driver (all asics).
791 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
793 if (adev->dummy_page.page == NULL)
795 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
796 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
797 __free_page(adev->dummy_page.page);
798 adev->dummy_page.page = NULL;
802 /* ATOM accessor methods */
804 * ATOM is an interpreted byte code stored in tables in the vbios. The
805 * driver registers callbacks to access registers and the interpreter
806 * in the driver parses the tables and executes then to program specific
807 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
808 * atombios.h, and atom.c
812 * cail_pll_read - read PLL register
814 * @info: atom card_info pointer
815 * @reg: PLL register offset
817 * Provides a PLL register accessor for the atom interpreter (r4xx+).
818 * Returns the value of the PLL register.
820 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
826 * cail_pll_write - write PLL register
828 * @info: atom card_info pointer
829 * @reg: PLL register offset
830 * @val: value to write to the pll register
832 * Provides a PLL register accessor for the atom interpreter (r4xx+).
834 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
840 * cail_mc_read - read MC (Memory Controller) register
842 * @info: atom card_info pointer
843 * @reg: MC register offset
845 * Provides an MC register accessor for the atom interpreter (r4xx+).
846 * Returns the value of the MC register.
848 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
854 * cail_mc_write - write MC (Memory Controller) register
856 * @info: atom card_info pointer
857 * @reg: MC register offset
858 * @val: value to write to the pll register
860 * Provides a MC register accessor for the atom interpreter (r4xx+).
862 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
868 * cail_reg_write - write MMIO register
870 * @info: atom card_info pointer
871 * @reg: MMIO register offset
872 * @val: value to write to the pll register
874 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
876 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
878 struct amdgpu_device *adev = info->dev->dev_private;
884 * cail_reg_read - read MMIO register
886 * @info: atom card_info pointer
887 * @reg: MMIO register offset
889 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
890 * Returns the value of the MMIO register.
892 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
894 struct amdgpu_device *adev = info->dev->dev_private;
902 * cail_ioreg_write - write IO register
904 * @info: atom card_info pointer
905 * @reg: IO register offset
906 * @val: value to write to the pll register
908 * Provides a IO register accessor for the atom interpreter (r4xx+).
910 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
912 struct amdgpu_device *adev = info->dev->dev_private;
918 * cail_ioreg_read - read IO register
920 * @info: atom card_info pointer
921 * @reg: IO register offset
923 * Provides an IO register accessor for the atom interpreter (r4xx+).
924 * Returns the value of the IO register.
926 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
928 struct amdgpu_device *adev = info->dev->dev_private;
936 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
938 * @adev: amdgpu_device pointer
940 * Frees the driver info and register access callbacks for the ATOM
941 * interpreter (r4xx+).
942 * Called at driver shutdown.
944 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
946 if (adev->mode_info.atom_context) {
947 kfree(adev->mode_info.atom_context->scratch);
948 kfree(adev->mode_info.atom_context->iio);
950 kfree(adev->mode_info.atom_context);
951 adev->mode_info.atom_context = NULL;
952 kfree(adev->mode_info.atom_card_info);
953 adev->mode_info.atom_card_info = NULL;
957 * amdgpu_atombios_init - init the driver info and callbacks for atombios
959 * @adev: amdgpu_device pointer
961 * Initializes the driver info and register access callbacks for the
962 * ATOM interpreter (r4xx+).
963 * Returns 0 on sucess, -ENOMEM on failure.
964 * Called at driver startup.
966 static int amdgpu_atombios_init(struct amdgpu_device *adev)
968 struct card_info *atom_card_info =
969 kzalloc(sizeof(struct card_info), GFP_KERNEL);
974 adev->mode_info.atom_card_info = atom_card_info;
975 atom_card_info->dev = adev->ddev;
976 atom_card_info->reg_read = cail_reg_read;
977 atom_card_info->reg_write = cail_reg_write;
978 /* needed for iio ops */
980 atom_card_info->ioreg_read = cail_ioreg_read;
981 atom_card_info->ioreg_write = cail_ioreg_write;
983 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
984 atom_card_info->ioreg_read = cail_reg_read;
985 atom_card_info->ioreg_write = cail_reg_write;
987 atom_card_info->mc_read = cail_mc_read;
988 atom_card_info->mc_write = cail_mc_write;
989 atom_card_info->pll_read = cail_pll_read;
990 atom_card_info->pll_write = cail_pll_write;
992 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
993 if (!adev->mode_info.atom_context) {
994 amdgpu_atombios_fini(adev);
998 mutex_init(&adev->mode_info.atom_context->mutex);
999 if (adev->is_atom_fw) {
1000 amdgpu_atomfirmware_scratch_regs_init(adev);
1001 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1003 amdgpu_atombios_scratch_regs_init(adev);
1004 amdgpu_atombios_allocate_fb_scratch(adev);
1009 /* if we get transitioned to only one device, take VGA back */
1011 * amdgpu_vga_set_decode - enable/disable vga decode
1013 * @cookie: amdgpu_device pointer
1014 * @state: enable/disable vga decode
1016 * Enable/disable vga decode (all asics).
1017 * Returns VGA resource flags.
1019 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1021 struct amdgpu_device *adev = cookie;
1022 amdgpu_asic_set_vga_state(adev, state);
1024 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1025 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1027 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1031 * amdgpu_check_pot_argument - check that argument is a power of two
1033 * @arg: value to check
1035 * Validates that a certain argument is a power of two (all asics).
1036 * Returns true if argument is valid.
1038 static bool amdgpu_check_pot_argument(int arg)
1040 return (arg & (arg - 1)) == 0;
1043 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1045 /* defines number of bits in page table versus page directory,
1046 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1047 * page table and the remaining bits are in the page directory */
1048 if (amdgpu_vm_block_size == -1)
1051 if (amdgpu_vm_block_size < 9) {
1052 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1053 amdgpu_vm_block_size);
1057 if (amdgpu_vm_block_size > 24 ||
1058 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1059 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1060 amdgpu_vm_block_size);
1067 amdgpu_vm_block_size = -1;
1070 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1072 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1073 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1078 if (amdgpu_vm_size < 1) {
1079 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1085 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1087 if (amdgpu_vm_size > 1024) {
1088 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1096 amdgpu_vm_size = -1;
1100 * amdgpu_check_arguments - validate module params
1102 * @adev: amdgpu_device pointer
1104 * Validates certain module parameters and updates
1105 * the associated values used by the driver (all asics).
1107 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1109 if (amdgpu_sched_jobs < 4) {
1110 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1112 amdgpu_sched_jobs = 4;
1113 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
1114 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1116 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1119 if (amdgpu_gart_size != -1) {
1120 /* gtt size must be greater or equal to 32M */
1121 if (amdgpu_gart_size < 32) {
1122 dev_warn(adev->dev, "gart size (%d) too small\n",
1124 amdgpu_gart_size = -1;
1128 amdgpu_check_vm_size(adev);
1130 amdgpu_check_block_size(adev);
1132 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1133 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1134 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1135 amdgpu_vram_page_split);
1136 amdgpu_vram_page_split = 1024;
1141 * amdgpu_switcheroo_set_state - set switcheroo state
1143 * @pdev: pci dev pointer
1144 * @state: vga_switcheroo state
1146 * Callback for the switcheroo driver. Suspends or resumes the
1147 * the asics before or after it is powered up using ACPI methods.
1149 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1151 struct drm_device *dev = pci_get_drvdata(pdev);
1153 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1156 if (state == VGA_SWITCHEROO_ON) {
1157 unsigned d3_delay = dev->pdev->d3_delay;
1159 pr_info("amdgpu: switched on\n");
1160 /* don't suspend or resume card normally */
1161 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1163 amdgpu_device_resume(dev, true, true);
1165 dev->pdev->d3_delay = d3_delay;
1167 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1168 drm_kms_helper_poll_enable(dev);
1170 pr_info("amdgpu: switched off\n");
1171 drm_kms_helper_poll_disable(dev);
1172 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1173 amdgpu_device_suspend(dev, true, true);
1174 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1179 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1181 * @pdev: pci dev pointer
1183 * Callback for the switcheroo driver. Check of the switcheroo
1184 * state can be changed.
1185 * Returns true if the state can be changed, false if not.
1187 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1189 struct drm_device *dev = pci_get_drvdata(pdev);
1192 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1193 * locking inversion with the driver load path. And the access here is
1194 * completely racy anyway. So don't bother with locking for now.
1196 return dev->open_count == 0;
1199 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1200 .set_gpu_state = amdgpu_switcheroo_set_state,
1202 .can_switch = amdgpu_switcheroo_can_switch,
1205 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1206 enum amd_ip_block_type block_type,
1207 enum amd_clockgating_state state)
1211 for (i = 0; i < adev->num_ip_blocks; i++) {
1212 if (!adev->ip_blocks[i].status.valid)
1214 if (adev->ip_blocks[i].version->type != block_type)
1216 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1218 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1219 (void *)adev, state);
1221 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1222 adev->ip_blocks[i].version->funcs->name, r);
1227 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1228 enum amd_ip_block_type block_type,
1229 enum amd_powergating_state state)
1233 for (i = 0; i < adev->num_ip_blocks; i++) {
1234 if (!adev->ip_blocks[i].status.valid)
1236 if (adev->ip_blocks[i].version->type != block_type)
1238 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1240 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1241 (void *)adev, state);
1243 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1244 adev->ip_blocks[i].version->funcs->name, r);
1249 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1253 for (i = 0; i < adev->num_ip_blocks; i++) {
1254 if (!adev->ip_blocks[i].status.valid)
1256 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1257 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1261 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1262 enum amd_ip_block_type block_type)
1266 for (i = 0; i < adev->num_ip_blocks; i++) {
1267 if (!adev->ip_blocks[i].status.valid)
1269 if (adev->ip_blocks[i].version->type == block_type) {
1270 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1280 bool amdgpu_is_idle(struct amdgpu_device *adev,
1281 enum amd_ip_block_type block_type)
1285 for (i = 0; i < adev->num_ip_blocks; i++) {
1286 if (!adev->ip_blocks[i].status.valid)
1288 if (adev->ip_blocks[i].version->type == block_type)
1289 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1295 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1296 enum amd_ip_block_type type)
1300 for (i = 0; i < adev->num_ip_blocks; i++)
1301 if (adev->ip_blocks[i].version->type == type)
1302 return &adev->ip_blocks[i];
1308 * amdgpu_ip_block_version_cmp
1310 * @adev: amdgpu_device pointer
1311 * @type: enum amd_ip_block_type
1312 * @major: major version
1313 * @minor: minor version
1315 * return 0 if equal or greater
1316 * return 1 if smaller or the ip_block doesn't exist
1318 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1319 enum amd_ip_block_type type,
1320 u32 major, u32 minor)
1322 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1324 if (ip_block && ((ip_block->version->major > major) ||
1325 ((ip_block->version->major == major) &&
1326 (ip_block->version->minor >= minor))))
1333 * amdgpu_ip_block_add
1335 * @adev: amdgpu_device pointer
1336 * @ip_block_version: pointer to the IP to add
1338 * Adds the IP block driver information to the collection of IPs
1341 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1342 const struct amdgpu_ip_block_version *ip_block_version)
1344 if (!ip_block_version)
1347 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1352 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1354 adev->enable_virtual_display = false;
1356 if (amdgpu_virtual_display) {
1357 struct drm_device *ddev = adev->ddev;
1358 const char *pci_address_name = pci_name(ddev->pdev);
1359 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1361 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1362 pciaddstr_tmp = pciaddstr;
1363 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1364 pciaddname = strsep(&pciaddname_tmp, ",");
1365 if (!strcmp("all", pciaddname)
1366 || !strcmp(pci_address_name, pciaddname)) {
1370 adev->enable_virtual_display = true;
1373 res = kstrtol(pciaddname_tmp, 10,
1381 adev->mode_info.num_crtc = num_crtc;
1383 adev->mode_info.num_crtc = 1;
1389 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1390 amdgpu_virtual_display, pci_address_name,
1391 adev->enable_virtual_display, adev->mode_info.num_crtc);
1397 static int amdgpu_early_init(struct amdgpu_device *adev)
1401 amdgpu_device_enable_virtual_display(adev);
1403 switch (adev->asic_type) {
1407 case CHIP_POLARIS11:
1408 case CHIP_POLARIS10:
1409 case CHIP_POLARIS12:
1412 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1413 adev->family = AMDGPU_FAMILY_CZ;
1415 adev->family = AMDGPU_FAMILY_VI;
1417 r = vi_set_ip_blocks(adev);
1421 #ifdef CONFIG_DRM_AMDGPU_SI
1427 adev->family = AMDGPU_FAMILY_SI;
1428 r = si_set_ip_blocks(adev);
1433 #ifdef CONFIG_DRM_AMDGPU_CIK
1439 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1440 adev->family = AMDGPU_FAMILY_CI;
1442 adev->family = AMDGPU_FAMILY_KV;
1444 r = cik_set_ip_blocks(adev);
1450 adev->family = AMDGPU_FAMILY_AI;
1452 r = soc15_set_ip_blocks(adev);
1457 /* FIXME: not supported yet */
1461 if (amdgpu_sriov_vf(adev)) {
1462 r = amdgpu_virt_request_full_gpu(adev, true);
1467 for (i = 0; i < adev->num_ip_blocks; i++) {
1468 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1469 DRM_ERROR("disabled ip block: %d\n", i);
1470 adev->ip_blocks[i].status.valid = false;
1472 if (adev->ip_blocks[i].version->funcs->early_init) {
1473 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1475 adev->ip_blocks[i].status.valid = false;
1477 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1478 adev->ip_blocks[i].version->funcs->name, r);
1481 adev->ip_blocks[i].status.valid = true;
1484 adev->ip_blocks[i].status.valid = true;
1489 adev->cg_flags &= amdgpu_cg_mask;
1490 adev->pg_flags &= amdgpu_pg_mask;
1495 static int amdgpu_init(struct amdgpu_device *adev)
1499 for (i = 0; i < adev->num_ip_blocks; i++) {
1500 if (!adev->ip_blocks[i].status.valid)
1502 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1504 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1505 adev->ip_blocks[i].version->funcs->name, r);
1508 adev->ip_blocks[i].status.sw = true;
1509 /* need to do gmc hw init early so we can allocate gpu mem */
1510 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1511 r = amdgpu_vram_scratch_init(adev);
1513 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1516 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1518 DRM_ERROR("hw_init %d failed %d\n", i, r);
1521 r = amdgpu_wb_init(adev);
1523 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1526 adev->ip_blocks[i].status.hw = true;
1528 /* right after GMC hw init, we create CSA */
1529 if (amdgpu_sriov_vf(adev)) {
1530 r = amdgpu_allocate_static_csa(adev);
1532 DRM_ERROR("allocate CSA failed %d\n", r);
1539 for (i = 0; i < adev->num_ip_blocks; i++) {
1540 if (!adev->ip_blocks[i].status.sw)
1542 /* gmc hw init is done early */
1543 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1545 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1547 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1548 adev->ip_blocks[i].version->funcs->name, r);
1551 adev->ip_blocks[i].status.hw = true;
1557 static int amdgpu_late_init(struct amdgpu_device *adev)
1561 for (i = 0; i < adev->num_ip_blocks; i++) {
1562 if (!adev->ip_blocks[i].status.valid)
1564 if (adev->ip_blocks[i].version->funcs->late_init) {
1565 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1567 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1568 adev->ip_blocks[i].version->funcs->name, r);
1571 adev->ip_blocks[i].status.late_initialized = true;
1573 /* skip CG for VCE/UVD, it's handled specially */
1574 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1575 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1576 /* enable clockgating to save power */
1577 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1580 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1581 adev->ip_blocks[i].version->funcs->name, r);
1587 amdgpu_dpm_enable_uvd(adev, false);
1588 amdgpu_dpm_enable_vce(adev, false);
1593 static int amdgpu_fini(struct amdgpu_device *adev)
1597 /* need to disable SMC first */
1598 for (i = 0; i < adev->num_ip_blocks; i++) {
1599 if (!adev->ip_blocks[i].status.hw)
1601 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1602 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1603 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1604 AMD_CG_STATE_UNGATE);
1606 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1607 adev->ip_blocks[i].version->funcs->name, r);
1610 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1611 /* XXX handle errors */
1613 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1614 adev->ip_blocks[i].version->funcs->name, r);
1616 adev->ip_blocks[i].status.hw = false;
1621 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1622 if (!adev->ip_blocks[i].status.hw)
1624 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1625 amdgpu_wb_fini(adev);
1626 amdgpu_vram_scratch_fini(adev);
1629 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1630 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1631 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1632 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1633 AMD_CG_STATE_UNGATE);
1635 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1636 adev->ip_blocks[i].version->funcs->name, r);
1641 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1642 /* XXX handle errors */
1644 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1645 adev->ip_blocks[i].version->funcs->name, r);
1648 adev->ip_blocks[i].status.hw = false;
1651 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1652 if (!adev->ip_blocks[i].status.sw)
1654 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1655 /* XXX handle errors */
1657 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1658 adev->ip_blocks[i].version->funcs->name, r);
1660 adev->ip_blocks[i].status.sw = false;
1661 adev->ip_blocks[i].status.valid = false;
1664 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1665 if (!adev->ip_blocks[i].status.late_initialized)
1667 if (adev->ip_blocks[i].version->funcs->late_fini)
1668 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1669 adev->ip_blocks[i].status.late_initialized = false;
1672 if (amdgpu_sriov_vf(adev)) {
1673 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
1674 amdgpu_virt_release_full_gpu(adev, false);
1680 int amdgpu_suspend(struct amdgpu_device *adev)
1684 if (amdgpu_sriov_vf(adev))
1685 amdgpu_virt_request_full_gpu(adev, false);
1687 /* ungate SMC block first */
1688 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1689 AMD_CG_STATE_UNGATE);
1691 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1694 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1695 if (!adev->ip_blocks[i].status.valid)
1697 /* ungate blocks so that suspend can properly shut them down */
1698 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1699 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1700 AMD_CG_STATE_UNGATE);
1702 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1703 adev->ip_blocks[i].version->funcs->name, r);
1706 /* XXX handle errors */
1707 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1708 /* XXX handle errors */
1710 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1711 adev->ip_blocks[i].version->funcs->name, r);
1715 if (amdgpu_sriov_vf(adev))
1716 amdgpu_virt_release_full_gpu(adev, false);
1721 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1725 for (i = 0; i < adev->num_ip_blocks; i++) {
1726 if (!adev->ip_blocks[i].status.valid)
1729 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1730 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1731 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
1732 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1735 DRM_ERROR("resume of IP block <%s> failed %d\n",
1736 adev->ip_blocks[i].version->funcs->name, r);
1744 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1748 for (i = 0; i < adev->num_ip_blocks; i++) {
1749 if (!adev->ip_blocks[i].status.valid)
1752 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1753 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1754 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1757 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
1759 DRM_ERROR("resume of IP block <%s> failed %d\n",
1760 adev->ip_blocks[i].version->funcs->name, r);
1768 static int amdgpu_resume(struct amdgpu_device *adev)
1772 for (i = 0; i < adev->num_ip_blocks; i++) {
1773 if (!adev->ip_blocks[i].status.valid)
1775 r = adev->ip_blocks[i].version->funcs->resume(adev);
1777 DRM_ERROR("resume of IP block <%s> failed %d\n",
1778 adev->ip_blocks[i].version->funcs->name, r);
1786 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1788 if (adev->is_atom_fw) {
1789 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1790 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1792 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1793 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1798 * amdgpu_device_init - initialize the driver
1800 * @adev: amdgpu_device pointer
1801 * @pdev: drm dev pointer
1802 * @pdev: pci dev pointer
1803 * @flags: driver flags
1805 * Initializes the driver info and hw (all asics).
1806 * Returns 0 for success or an error on failure.
1807 * Called at driver startup.
1809 int amdgpu_device_init(struct amdgpu_device *adev,
1810 struct drm_device *ddev,
1811 struct pci_dev *pdev,
1815 bool runtime = false;
1818 adev->shutdown = false;
1819 adev->dev = &pdev->dev;
1822 adev->flags = flags;
1823 adev->asic_type = flags & AMD_ASIC_MASK;
1824 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1825 adev->mc.gtt_size = 512 * 1024 * 1024;
1826 adev->accel_working = false;
1827 adev->num_rings = 0;
1828 adev->mman.buffer_funcs = NULL;
1829 adev->mman.buffer_funcs_ring = NULL;
1830 adev->vm_manager.vm_pte_funcs = NULL;
1831 adev->vm_manager.vm_pte_num_rings = 0;
1832 adev->gart.gart_funcs = NULL;
1833 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1835 adev->smc_rreg = &amdgpu_invalid_rreg;
1836 adev->smc_wreg = &amdgpu_invalid_wreg;
1837 adev->pcie_rreg = &amdgpu_invalid_rreg;
1838 adev->pcie_wreg = &amdgpu_invalid_wreg;
1839 adev->pciep_rreg = &amdgpu_invalid_rreg;
1840 adev->pciep_wreg = &amdgpu_invalid_wreg;
1841 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1842 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1843 adev->didt_rreg = &amdgpu_invalid_rreg;
1844 adev->didt_wreg = &amdgpu_invalid_wreg;
1845 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1846 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1847 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1848 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1851 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1852 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1853 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1855 /* mutex initialization are all done here so we
1856 * can recall function without having locking issues */
1857 mutex_init(&adev->vm_manager.lock);
1858 atomic_set(&adev->irq.ih.lock, 0);
1859 mutex_init(&adev->firmware.mutex);
1860 mutex_init(&adev->pm.mutex);
1861 mutex_init(&adev->gfx.gpu_clock_mutex);
1862 mutex_init(&adev->srbm_mutex);
1863 mutex_init(&adev->grbm_idx_mutex);
1864 mutex_init(&adev->mn_lock);
1865 hash_init(adev->mn_hash);
1867 amdgpu_check_arguments(adev);
1869 /* Registers mapping */
1870 /* TODO: block userspace mapping of io register */
1871 spin_lock_init(&adev->mmio_idx_lock);
1872 spin_lock_init(&adev->smc_idx_lock);
1873 spin_lock_init(&adev->pcie_idx_lock);
1874 spin_lock_init(&adev->uvd_ctx_idx_lock);
1875 spin_lock_init(&adev->didt_idx_lock);
1876 spin_lock_init(&adev->gc_cac_idx_lock);
1877 spin_lock_init(&adev->audio_endpt_idx_lock);
1878 spin_lock_init(&adev->mm_stats.lock);
1880 INIT_LIST_HEAD(&adev->shadow_list);
1881 mutex_init(&adev->shadow_list_lock);
1883 INIT_LIST_HEAD(&adev->gtt_list);
1884 spin_lock_init(&adev->gtt_list_lock);
1886 if (adev->asic_type >= CHIP_BONAIRE) {
1887 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1888 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1890 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1891 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1894 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1895 if (adev->rmmio == NULL) {
1898 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1899 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1901 if (adev->asic_type >= CHIP_BONAIRE)
1902 /* doorbell bar mapping */
1903 amdgpu_doorbell_init(adev);
1905 /* io port mapping */
1906 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1907 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1908 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1909 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1913 if (adev->rio_mem == NULL)
1914 DRM_INFO("PCI I/O BAR is not found.\n");
1916 /* early init functions */
1917 r = amdgpu_early_init(adev);
1921 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1922 /* this will fail for cards that aren't VGA class devices, just
1924 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1926 if (amdgpu_runtime_pm == 1)
1928 if (amdgpu_device_is_px(ddev))
1930 if (!pci_is_thunderbolt_attached(adev->pdev))
1931 vga_switcheroo_register_client(adev->pdev,
1932 &amdgpu_switcheroo_ops, runtime);
1934 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1937 if (!amdgpu_get_bios(adev)) {
1942 r = amdgpu_atombios_init(adev);
1944 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1948 /* detect if we are with an SRIOV vbios */
1949 amdgpu_device_detect_sriov_bios(adev);
1951 /* Post card if necessary */
1952 if (amdgpu_vpost_needed(adev)) {
1954 dev_err(adev->dev, "no vBIOS found\n");
1958 DRM_INFO("GPU posting now...\n");
1959 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1961 dev_err(adev->dev, "gpu post error!\n");
1965 DRM_INFO("GPU post is not needed\n");
1968 if (!adev->is_atom_fw) {
1969 /* Initialize clocks */
1970 r = amdgpu_atombios_get_clock_info(adev);
1972 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1975 /* init i2c buses */
1976 amdgpu_atombios_i2c_init(adev);
1980 r = amdgpu_fence_driver_init(adev);
1982 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1986 /* init the mode config */
1987 drm_mode_config_init(adev->ddev);
1989 r = amdgpu_init(adev);
1991 dev_err(adev->dev, "amdgpu_init failed\n");
1996 adev->accel_working = true;
1998 /* Initialize the buffer migration limit. */
1999 if (amdgpu_moverate >= 0)
2000 max_MBps = amdgpu_moverate;
2002 max_MBps = 8; /* Allow 8 MB/s. */
2003 /* Get a log2 for easy divisions. */
2004 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2006 r = amdgpu_ib_pool_init(adev);
2008 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2012 r = amdgpu_ib_ring_tests(adev);
2014 DRM_ERROR("ib ring test failed (%d).\n", r);
2016 amdgpu_fbdev_init(adev);
2018 r = amdgpu_gem_debugfs_init(adev);
2020 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2022 r = amdgpu_debugfs_regs_init(adev);
2024 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2026 r = amdgpu_debugfs_firmware_init(adev);
2028 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2030 if ((amdgpu_testing & 1)) {
2031 if (adev->accel_working)
2032 amdgpu_test_moves(adev);
2034 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2036 if (amdgpu_benchmarking) {
2037 if (adev->accel_working)
2038 amdgpu_benchmark(adev, amdgpu_benchmarking);
2040 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2043 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2044 * explicit gating rather than handling it automatically.
2046 r = amdgpu_late_init(adev);
2048 dev_err(adev->dev, "amdgpu_late_init failed\n");
2056 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2061 * amdgpu_device_fini - tear down the driver
2063 * @adev: amdgpu_device pointer
2065 * Tear down the driver info (all asics).
2066 * Called at driver shutdown.
2068 void amdgpu_device_fini(struct amdgpu_device *adev)
2072 DRM_INFO("amdgpu: finishing device.\n");
2073 adev->shutdown = true;
2074 drm_crtc_force_disable_all(adev->ddev);
2075 /* evict vram memory */
2076 amdgpu_bo_evict_vram(adev);
2077 amdgpu_ib_pool_fini(adev);
2078 amdgpu_fence_driver_fini(adev);
2079 amdgpu_fbdev_fini(adev);
2080 r = amdgpu_fini(adev);
2081 adev->accel_working = false;
2082 /* free i2c buses */
2083 amdgpu_i2c_fini(adev);
2084 amdgpu_atombios_fini(adev);
2087 if (!pci_is_thunderbolt_attached(adev->pdev))
2088 vga_switcheroo_unregister_client(adev->pdev);
2089 if (adev->flags & AMD_IS_PX)
2090 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2091 vga_client_register(adev->pdev, NULL, NULL, NULL);
2093 pci_iounmap(adev->pdev, adev->rio_mem);
2094 adev->rio_mem = NULL;
2095 iounmap(adev->rmmio);
2097 if (adev->asic_type >= CHIP_BONAIRE)
2098 amdgpu_doorbell_fini(adev);
2099 amdgpu_debugfs_regs_cleanup(adev);
2107 * amdgpu_device_suspend - initiate device suspend
2109 * @pdev: drm dev pointer
2110 * @state: suspend state
2112 * Puts the hw in the suspend state (all asics).
2113 * Returns 0 for success or an error on failure.
2114 * Called at driver suspend.
2116 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2118 struct amdgpu_device *adev;
2119 struct drm_crtc *crtc;
2120 struct drm_connector *connector;
2123 if (dev == NULL || dev->dev_private == NULL) {
2127 adev = dev->dev_private;
2129 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2132 drm_kms_helper_poll_disable(dev);
2134 /* turn off display hw */
2135 drm_modeset_lock_all(dev);
2136 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2137 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2139 drm_modeset_unlock_all(dev);
2141 /* unpin the front buffers and cursors */
2142 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2143 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2144 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2145 struct amdgpu_bo *robj;
2147 if (amdgpu_crtc->cursor_bo) {
2148 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2149 r = amdgpu_bo_reserve(aobj, false);
2151 amdgpu_bo_unpin(aobj);
2152 amdgpu_bo_unreserve(aobj);
2156 if (rfb == NULL || rfb->obj == NULL) {
2159 robj = gem_to_amdgpu_bo(rfb->obj);
2160 /* don't unpin kernel fb objects */
2161 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2162 r = amdgpu_bo_reserve(robj, false);
2164 amdgpu_bo_unpin(robj);
2165 amdgpu_bo_unreserve(robj);
2169 /* evict vram memory */
2170 amdgpu_bo_evict_vram(adev);
2172 amdgpu_fence_driver_suspend(adev);
2174 r = amdgpu_suspend(adev);
2176 /* evict remaining vram memory
2177 * This second call to evict vram is to evict the gart page table
2180 amdgpu_bo_evict_vram(adev);
2182 if (adev->is_atom_fw)
2183 amdgpu_atomfirmware_scratch_regs_save(adev);
2185 amdgpu_atombios_scratch_regs_save(adev);
2186 pci_save_state(dev->pdev);
2188 /* Shut down the device */
2189 pci_disable_device(dev->pdev);
2190 pci_set_power_state(dev->pdev, PCI_D3hot);
2192 r = amdgpu_asic_reset(adev);
2194 DRM_ERROR("amdgpu asic reset failed\n");
2199 amdgpu_fbdev_set_suspend(adev, 1);
2206 * amdgpu_device_resume - initiate device resume
2208 * @pdev: drm dev pointer
2210 * Bring the hw back to operating state (all asics).
2211 * Returns 0 for success or an error on failure.
2212 * Called at driver resume.
2214 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2216 struct drm_connector *connector;
2217 struct amdgpu_device *adev = dev->dev_private;
2218 struct drm_crtc *crtc;
2221 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2228 pci_set_power_state(dev->pdev, PCI_D0);
2229 pci_restore_state(dev->pdev);
2230 r = pci_enable_device(dev->pdev);
2237 if (adev->is_atom_fw)
2238 amdgpu_atomfirmware_scratch_regs_restore(adev);
2240 amdgpu_atombios_scratch_regs_restore(adev);
2243 if (amdgpu_need_post(adev)) {
2244 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2246 DRM_ERROR("amdgpu asic init failed\n");
2249 r = amdgpu_resume(adev);
2251 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2254 amdgpu_fence_driver_resume(adev);
2257 r = amdgpu_ib_ring_tests(adev);
2259 DRM_ERROR("ib ring test failed (%d).\n", r);
2262 r = amdgpu_late_init(adev);
2270 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2271 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2273 if (amdgpu_crtc->cursor_bo) {
2274 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2275 r = amdgpu_bo_reserve(aobj, false);
2277 r = amdgpu_bo_pin(aobj,
2278 AMDGPU_GEM_DOMAIN_VRAM,
2279 &amdgpu_crtc->cursor_addr);
2281 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2282 amdgpu_bo_unreserve(aobj);
2287 /* blat the mode back in */
2289 drm_helper_resume_force_mode(dev);
2290 /* turn on display hw */
2291 drm_modeset_lock_all(dev);
2292 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2293 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2295 drm_modeset_unlock_all(dev);
2298 drm_kms_helper_poll_enable(dev);
2301 * Most of the connector probing functions try to acquire runtime pm
2302 * refs to ensure that the GPU is powered on when connector polling is
2303 * performed. Since we're calling this from a runtime PM callback,
2304 * trying to acquire rpm refs will cause us to deadlock.
2306 * Since we're guaranteed to be holding the rpm lock, it's safe to
2307 * temporarily disable the rpm helpers so this doesn't deadlock us.
2310 dev->dev->power.disable_depth++;
2312 drm_helper_hpd_irq_event(dev);
2314 dev->dev->power.disable_depth--;
2318 amdgpu_fbdev_set_suspend(adev, 0);
2325 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2328 bool asic_hang = false;
2330 for (i = 0; i < adev->num_ip_blocks; i++) {
2331 if (!adev->ip_blocks[i].status.valid)
2333 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2334 adev->ip_blocks[i].status.hang =
2335 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2336 if (adev->ip_blocks[i].status.hang) {
2337 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2344 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2348 for (i = 0; i < adev->num_ip_blocks; i++) {
2349 if (!adev->ip_blocks[i].status.valid)
2351 if (adev->ip_blocks[i].status.hang &&
2352 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2353 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2362 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2366 for (i = 0; i < adev->num_ip_blocks; i++) {
2367 if (!adev->ip_blocks[i].status.valid)
2369 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2370 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2371 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2372 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2373 if (adev->ip_blocks[i].status.hang) {
2374 DRM_INFO("Some block need full reset!\n");
2382 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2386 for (i = 0; i < adev->num_ip_blocks; i++) {
2387 if (!adev->ip_blocks[i].status.valid)
2389 if (adev->ip_blocks[i].status.hang &&
2390 adev->ip_blocks[i].version->funcs->soft_reset) {
2391 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2400 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2404 for (i = 0; i < adev->num_ip_blocks; i++) {
2405 if (!adev->ip_blocks[i].status.valid)
2407 if (adev->ip_blocks[i].status.hang &&
2408 adev->ip_blocks[i].version->funcs->post_soft_reset)
2409 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2417 bool amdgpu_need_backup(struct amdgpu_device *adev)
2419 if (adev->flags & AMD_IS_APU)
2422 return amdgpu_lockup_timeout > 0 ? true : false;
2425 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2426 struct amdgpu_ring *ring,
2427 struct amdgpu_bo *bo,
2428 struct dma_fence **fence)
2436 r = amdgpu_bo_reserve(bo, false);
2439 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2440 /* if bo has been evicted, then no need to recover */
2441 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2442 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2445 DRM_ERROR("recover page table failed!\n");
2450 amdgpu_bo_unreserve(bo);
2455 * amdgpu_sriov_gpu_reset - reset the asic
2457 * @adev: amdgpu device pointer
2458 * @voluntary: if this reset is requested by guest.
2459 * (true means by guest and false means by HYPERVISOR )
2461 * Attempt the reset the GPU if it has hung (all asics).
2463 * Returns 0 for success or an error on failure.
2465 int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, bool voluntary)
2469 struct amdgpu_bo *bo, *tmp;
2470 struct amdgpu_ring *ring;
2471 struct dma_fence *fence = NULL, *next = NULL;
2473 mutex_lock(&adev->virt.lock_reset);
2474 atomic_inc(&adev->gpu_reset_counter);
2475 adev->gfx.in_reset = true;
2478 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2480 /* block scheduler */
2481 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2482 ring = adev->rings[i];
2484 if (!ring || !ring->sched.thread)
2487 kthread_park(ring->sched.thread);
2488 amd_sched_hw_job_reset(&ring->sched);
2491 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2492 amdgpu_fence_driver_force_completion(adev);
2494 /* request to take full control of GPU before re-initialization */
2496 amdgpu_virt_reset_gpu(adev);
2498 amdgpu_virt_request_full_gpu(adev, true);
2501 /* Resume IP prior to SMC */
2502 amdgpu_sriov_reinit_early(adev);
2504 /* we need recover gart prior to run SMC/CP/SDMA resume */
2505 amdgpu_ttm_recover_gart(adev);
2507 /* now we are okay to resume SMC/CP/SDMA */
2508 amdgpu_sriov_reinit_late(adev);
2510 amdgpu_irq_gpu_reset_resume_helper(adev);
2512 if (amdgpu_ib_ring_tests(adev))
2513 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2515 /* release full control of GPU after ib test */
2516 amdgpu_virt_release_full_gpu(adev, true);
2518 DRM_INFO("recover vram bo from shadow\n");
2520 ring = adev->mman.buffer_funcs_ring;
2521 mutex_lock(&adev->shadow_list_lock);
2522 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2523 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2525 r = dma_fence_wait(fence, false);
2527 WARN(r, "recovery from shadow isn't completed\n");
2532 dma_fence_put(fence);
2535 mutex_unlock(&adev->shadow_list_lock);
2538 r = dma_fence_wait(fence, false);
2540 WARN(r, "recovery from shadow isn't completed\n");
2542 dma_fence_put(fence);
2544 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2545 struct amdgpu_ring *ring = adev->rings[i];
2546 if (!ring || !ring->sched.thread)
2549 amd_sched_job_recovery(&ring->sched);
2550 kthread_unpark(ring->sched.thread);
2553 drm_helper_resume_force_mode(adev->ddev);
2554 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2556 /* bad news, how to tell it to userspace ? */
2557 dev_info(adev->dev, "GPU reset failed\n");
2560 adev->gfx.in_reset = false;
2561 mutex_unlock(&adev->virt.lock_reset);
2566 * amdgpu_gpu_reset - reset the asic
2568 * @adev: amdgpu device pointer
2570 * Attempt the reset the GPU if it has hung (all asics).
2571 * Returns 0 for success or an error on failure.
2573 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2577 bool need_full_reset;
2579 if (amdgpu_sriov_vf(adev))
2580 return amdgpu_sriov_gpu_reset(adev, true);
2582 if (!amdgpu_check_soft_reset(adev)) {
2583 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2587 atomic_inc(&adev->gpu_reset_counter);
2590 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2592 /* block scheduler */
2593 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2594 struct amdgpu_ring *ring = adev->rings[i];
2598 kthread_park(ring->sched.thread);
2599 amd_sched_hw_job_reset(&ring->sched);
2601 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2602 amdgpu_fence_driver_force_completion(adev);
2604 need_full_reset = amdgpu_need_full_reset(adev);
2606 if (!need_full_reset) {
2607 amdgpu_pre_soft_reset(adev);
2608 r = amdgpu_soft_reset(adev);
2609 amdgpu_post_soft_reset(adev);
2610 if (r || amdgpu_check_soft_reset(adev)) {
2611 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2612 need_full_reset = true;
2616 if (need_full_reset) {
2617 r = amdgpu_suspend(adev);
2620 /* Disable fb access */
2621 if (adev->mode_info.num_crtc) {
2622 struct amdgpu_mode_mc_save save;
2623 amdgpu_display_stop_mc_access(adev, &save);
2624 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2626 if (adev->is_atom_fw)
2627 amdgpu_atomfirmware_scratch_regs_save(adev);
2629 amdgpu_atombios_scratch_regs_save(adev);
2630 r = amdgpu_asic_reset(adev);
2631 if (adev->is_atom_fw)
2632 amdgpu_atomfirmware_scratch_regs_restore(adev);
2634 amdgpu_atombios_scratch_regs_restore(adev);
2636 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2639 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2640 r = amdgpu_resume(adev);
2644 amdgpu_irq_gpu_reset_resume_helper(adev);
2645 if (need_full_reset && amdgpu_need_backup(adev)) {
2646 r = amdgpu_ttm_recover_gart(adev);
2648 DRM_ERROR("gart recovery failed!!!\n");
2650 r = amdgpu_ib_ring_tests(adev);
2652 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2653 r = amdgpu_suspend(adev);
2654 need_full_reset = true;
2658 * recovery vm page tables, since we cannot depend on VRAM is
2659 * consistent after gpu full reset.
2661 if (need_full_reset && amdgpu_need_backup(adev)) {
2662 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2663 struct amdgpu_bo *bo, *tmp;
2664 struct dma_fence *fence = NULL, *next = NULL;
2666 DRM_INFO("recover vram bo from shadow\n");
2667 mutex_lock(&adev->shadow_list_lock);
2668 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2669 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2671 r = dma_fence_wait(fence, false);
2673 WARN(r, "recovery from shadow isn't completed\n");
2678 dma_fence_put(fence);
2681 mutex_unlock(&adev->shadow_list_lock);
2683 r = dma_fence_wait(fence, false);
2685 WARN(r, "recovery from shadow isn't completed\n");
2687 dma_fence_put(fence);
2689 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2690 struct amdgpu_ring *ring = adev->rings[i];
2694 amd_sched_job_recovery(&ring->sched);
2695 kthread_unpark(ring->sched.thread);
2698 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2699 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2700 if (adev->rings[i]) {
2701 kthread_unpark(adev->rings[i]->sched.thread);
2706 drm_helper_resume_force_mode(adev->ddev);
2708 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2710 /* bad news, how to tell it to userspace ? */
2711 dev_info(adev->dev, "GPU reset failed\n");
2717 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2722 if (amdgpu_pcie_gen_cap)
2723 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2725 if (amdgpu_pcie_lane_cap)
2726 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2728 /* covers APUs as well */
2729 if (pci_is_root_bus(adev->pdev->bus)) {
2730 if (adev->pm.pcie_gen_mask == 0)
2731 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2732 if (adev->pm.pcie_mlw_mask == 0)
2733 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2737 if (adev->pm.pcie_gen_mask == 0) {
2738 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2740 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2741 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2742 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2744 if (mask & DRM_PCIE_SPEED_25)
2745 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2746 if (mask & DRM_PCIE_SPEED_50)
2747 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2748 if (mask & DRM_PCIE_SPEED_80)
2749 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2751 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2754 if (adev->pm.pcie_mlw_mask == 0) {
2755 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2759 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2760 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2761 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2762 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2763 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2764 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2765 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2768 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2769 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2770 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2771 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2772 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2773 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2776 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2777 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2778 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2779 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2780 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2783 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2784 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2785 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2786 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2789 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2790 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2791 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2794 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2795 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2798 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2804 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2812 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2813 const struct drm_info_list *files,
2818 for (i = 0; i < adev->debugfs_count; i++) {
2819 if (adev->debugfs[i].files == files) {
2820 /* Already registered */
2825 i = adev->debugfs_count + 1;
2826 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2827 DRM_ERROR("Reached maximum number of debugfs components.\n");
2828 DRM_ERROR("Report so we increase "
2829 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2832 adev->debugfs[adev->debugfs_count].files = files;
2833 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2834 adev->debugfs_count = i;
2835 #if defined(CONFIG_DEBUG_FS)
2836 drm_debugfs_create_files(files, nfiles,
2837 adev->ddev->primary->debugfs_root,
2838 adev->ddev->primary);
2843 #if defined(CONFIG_DEBUG_FS)
2845 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2846 size_t size, loff_t *pos)
2848 struct amdgpu_device *adev = file_inode(f)->i_private;
2851 bool pm_pg_lock, use_bank;
2852 unsigned instance_bank, sh_bank, se_bank;
2854 if (size & 0x3 || *pos & 0x3)
2857 /* are we reading registers for which a PG lock is necessary? */
2858 pm_pg_lock = (*pos >> 23) & 1;
2860 if (*pos & (1ULL << 62)) {
2861 se_bank = (*pos >> 24) & 0x3FF;
2862 sh_bank = (*pos >> 34) & 0x3FF;
2863 instance_bank = (*pos >> 44) & 0x3FF;
2865 if (se_bank == 0x3FF)
2866 se_bank = 0xFFFFFFFF;
2867 if (sh_bank == 0x3FF)
2868 sh_bank = 0xFFFFFFFF;
2869 if (instance_bank == 0x3FF)
2870 instance_bank = 0xFFFFFFFF;
2876 *pos &= (1UL << 22) - 1;
2879 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2880 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2882 mutex_lock(&adev->grbm_idx_mutex);
2883 amdgpu_gfx_select_se_sh(adev, se_bank,
2884 sh_bank, instance_bank);
2888 mutex_lock(&adev->pm.mutex);
2893 if (*pos > adev->rmmio_size)
2896 value = RREG32(*pos >> 2);
2897 r = put_user(value, (uint32_t *)buf);
2911 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2912 mutex_unlock(&adev->grbm_idx_mutex);
2916 mutex_unlock(&adev->pm.mutex);
2921 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2922 size_t size, loff_t *pos)
2924 struct amdgpu_device *adev = file_inode(f)->i_private;
2927 bool pm_pg_lock, use_bank;
2928 unsigned instance_bank, sh_bank, se_bank;
2930 if (size & 0x3 || *pos & 0x3)
2933 /* are we reading registers for which a PG lock is necessary? */
2934 pm_pg_lock = (*pos >> 23) & 1;
2936 if (*pos & (1ULL << 62)) {
2937 se_bank = (*pos >> 24) & 0x3FF;
2938 sh_bank = (*pos >> 34) & 0x3FF;
2939 instance_bank = (*pos >> 44) & 0x3FF;
2941 if (se_bank == 0x3FF)
2942 se_bank = 0xFFFFFFFF;
2943 if (sh_bank == 0x3FF)
2944 sh_bank = 0xFFFFFFFF;
2945 if (instance_bank == 0x3FF)
2946 instance_bank = 0xFFFFFFFF;
2952 *pos &= (1UL << 22) - 1;
2955 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2956 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2958 mutex_lock(&adev->grbm_idx_mutex);
2959 amdgpu_gfx_select_se_sh(adev, se_bank,
2960 sh_bank, instance_bank);
2964 mutex_lock(&adev->pm.mutex);
2969 if (*pos > adev->rmmio_size)
2972 r = get_user(value, (uint32_t *)buf);
2976 WREG32(*pos >> 2, value);
2985 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2986 mutex_unlock(&adev->grbm_idx_mutex);
2990 mutex_unlock(&adev->pm.mutex);
2995 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2996 size_t size, loff_t *pos)
2998 struct amdgpu_device *adev = file_inode(f)->i_private;
3002 if (size & 0x3 || *pos & 0x3)
3008 value = RREG32_PCIE(*pos >> 2);
3009 r = put_user(value, (uint32_t *)buf);
3022 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3023 size_t size, loff_t *pos)
3025 struct amdgpu_device *adev = file_inode(f)->i_private;
3029 if (size & 0x3 || *pos & 0x3)
3035 r = get_user(value, (uint32_t *)buf);
3039 WREG32_PCIE(*pos >> 2, value);
3050 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3051 size_t size, loff_t *pos)
3053 struct amdgpu_device *adev = file_inode(f)->i_private;
3057 if (size & 0x3 || *pos & 0x3)
3063 value = RREG32_DIDT(*pos >> 2);
3064 r = put_user(value, (uint32_t *)buf);
3077 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3078 size_t size, loff_t *pos)
3080 struct amdgpu_device *adev = file_inode(f)->i_private;
3084 if (size & 0x3 || *pos & 0x3)
3090 r = get_user(value, (uint32_t *)buf);
3094 WREG32_DIDT(*pos >> 2, value);
3105 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3106 size_t size, loff_t *pos)
3108 struct amdgpu_device *adev = file_inode(f)->i_private;
3112 if (size & 0x3 || *pos & 0x3)
3118 value = RREG32_SMC(*pos);
3119 r = put_user(value, (uint32_t *)buf);
3132 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3133 size_t size, loff_t *pos)
3135 struct amdgpu_device *adev = file_inode(f)->i_private;
3139 if (size & 0x3 || *pos & 0x3)
3145 r = get_user(value, (uint32_t *)buf);
3149 WREG32_SMC(*pos, value);
3160 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3161 size_t size, loff_t *pos)
3163 struct amdgpu_device *adev = file_inode(f)->i_private;
3166 uint32_t *config, no_regs = 0;
3168 if (size & 0x3 || *pos & 0x3)
3171 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3175 /* version, increment each time something is added */
3176 config[no_regs++] = 3;
3177 config[no_regs++] = adev->gfx.config.max_shader_engines;
3178 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3179 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3180 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3181 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3182 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3183 config[no_regs++] = adev->gfx.config.max_gprs;
3184 config[no_regs++] = adev->gfx.config.max_gs_threads;
3185 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3186 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3187 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3188 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3189 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3190 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3191 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3192 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3193 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3194 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3195 config[no_regs++] = adev->gfx.config.num_gpus;
3196 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3197 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3198 config[no_regs++] = adev->gfx.config.gb_addr_config;
3199 config[no_regs++] = adev->gfx.config.num_rbs;
3202 config[no_regs++] = adev->rev_id;
3203 config[no_regs++] = adev->pg_flags;
3204 config[no_regs++] = adev->cg_flags;
3207 config[no_regs++] = adev->family;
3208 config[no_regs++] = adev->external_rev_id;
3211 config[no_regs++] = adev->pdev->device;
3212 config[no_regs++] = adev->pdev->revision;
3213 config[no_regs++] = adev->pdev->subsystem_device;
3214 config[no_regs++] = adev->pdev->subsystem_vendor;
3216 while (size && (*pos < no_regs * 4)) {
3219 value = config[*pos >> 2];
3220 r = put_user(value, (uint32_t *)buf);
3236 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3237 size_t size, loff_t *pos)
3239 struct amdgpu_device *adev = file_inode(f)->i_private;
3240 int idx, x, outsize, r, valuesize;
3241 uint32_t values[16];
3243 if (size & 3 || *pos & 0x3)
3246 if (amdgpu_dpm == 0)
3249 /* convert offset to sensor number */
3252 valuesize = sizeof(values);
3253 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3254 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
3255 else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
3256 r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
3261 if (size > valuesize)
3268 r = put_user(values[x++], (int32_t *)buf);
3275 return !r ? outsize : r;
3278 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3279 size_t size, loff_t *pos)
3281 struct amdgpu_device *adev = f->f_inode->i_private;
3284 uint32_t offset, se, sh, cu, wave, simd, data[32];
3286 if (size & 3 || *pos & 3)
3290 offset = (*pos & 0x7F);
3291 se = ((*pos >> 7) & 0xFF);
3292 sh = ((*pos >> 15) & 0xFF);
3293 cu = ((*pos >> 23) & 0xFF);
3294 wave = ((*pos >> 31) & 0xFF);
3295 simd = ((*pos >> 37) & 0xFF);
3297 /* switch to the specific se/sh/cu */
3298 mutex_lock(&adev->grbm_idx_mutex);
3299 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3302 if (adev->gfx.funcs->read_wave_data)
3303 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3305 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3306 mutex_unlock(&adev->grbm_idx_mutex);
3311 while (size && (offset < x * 4)) {
3314 value = data[offset >> 2];
3315 r = put_user(value, (uint32_t *)buf);
3328 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3329 size_t size, loff_t *pos)
3331 struct amdgpu_device *adev = f->f_inode->i_private;
3334 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3336 if (size & 3 || *pos & 3)
3340 offset = (*pos & 0xFFF); /* in dwords */
3341 se = ((*pos >> 12) & 0xFF);
3342 sh = ((*pos >> 20) & 0xFF);
3343 cu = ((*pos >> 28) & 0xFF);
3344 wave = ((*pos >> 36) & 0xFF);
3345 simd = ((*pos >> 44) & 0xFF);
3346 thread = ((*pos >> 52) & 0xFF);
3347 bank = ((*pos >> 60) & 1);
3349 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3353 /* switch to the specific se/sh/cu */
3354 mutex_lock(&adev->grbm_idx_mutex);
3355 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3358 if (adev->gfx.funcs->read_wave_vgprs)
3359 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3361 if (adev->gfx.funcs->read_wave_sgprs)
3362 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3365 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3366 mutex_unlock(&adev->grbm_idx_mutex);
3371 value = data[offset++];
3372 r = put_user(value, (uint32_t *)buf);
3388 static const struct file_operations amdgpu_debugfs_regs_fops = {
3389 .owner = THIS_MODULE,
3390 .read = amdgpu_debugfs_regs_read,
3391 .write = amdgpu_debugfs_regs_write,
3392 .llseek = default_llseek
3394 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3395 .owner = THIS_MODULE,
3396 .read = amdgpu_debugfs_regs_didt_read,
3397 .write = amdgpu_debugfs_regs_didt_write,
3398 .llseek = default_llseek
3400 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3401 .owner = THIS_MODULE,
3402 .read = amdgpu_debugfs_regs_pcie_read,
3403 .write = amdgpu_debugfs_regs_pcie_write,
3404 .llseek = default_llseek
3406 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3407 .owner = THIS_MODULE,
3408 .read = amdgpu_debugfs_regs_smc_read,
3409 .write = amdgpu_debugfs_regs_smc_write,
3410 .llseek = default_llseek
3413 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3414 .owner = THIS_MODULE,
3415 .read = amdgpu_debugfs_gca_config_read,
3416 .llseek = default_llseek
3419 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3420 .owner = THIS_MODULE,
3421 .read = amdgpu_debugfs_sensor_read,
3422 .llseek = default_llseek
3425 static const struct file_operations amdgpu_debugfs_wave_fops = {
3426 .owner = THIS_MODULE,
3427 .read = amdgpu_debugfs_wave_read,
3428 .llseek = default_llseek
3430 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3431 .owner = THIS_MODULE,
3432 .read = amdgpu_debugfs_gpr_read,
3433 .llseek = default_llseek
3436 static const struct file_operations *debugfs_regs[] = {
3437 &amdgpu_debugfs_regs_fops,
3438 &amdgpu_debugfs_regs_didt_fops,
3439 &amdgpu_debugfs_regs_pcie_fops,
3440 &amdgpu_debugfs_regs_smc_fops,
3441 &amdgpu_debugfs_gca_config_fops,
3442 &amdgpu_debugfs_sensors_fops,
3443 &amdgpu_debugfs_wave_fops,
3444 &amdgpu_debugfs_gpr_fops,
3447 static const char *debugfs_regs_names[] = {
3452 "amdgpu_gca_config",
3458 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3460 struct drm_minor *minor = adev->ddev->primary;
3461 struct dentry *ent, *root = minor->debugfs_root;
3464 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3465 ent = debugfs_create_file(debugfs_regs_names[i],
3466 S_IFREG | S_IRUGO, root,
3467 adev, debugfs_regs[i]);
3469 for (j = 0; j < i; j++) {
3470 debugfs_remove(adev->debugfs_regs[i]);
3471 adev->debugfs_regs[i] = NULL;
3473 return PTR_ERR(ent);
3477 i_size_write(ent->d_inode, adev->rmmio_size);
3478 adev->debugfs_regs[i] = ent;
3484 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3488 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3489 if (adev->debugfs_regs[i]) {
3490 debugfs_remove(adev->debugfs_regs[i]);
3491 adev->debugfs_regs[i] = NULL;
3496 int amdgpu_debugfs_init(struct drm_minor *minor)
3501 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3505 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }