drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34
  35 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  36                                       struct drm_amdgpu_cs_chunk_fence *data,
  37                                       uint32_t *offset)
  38 {
  39         struct drm_gem_object *gobj;
  40         unsigned long size;
  41
  42         gobj = drm_gem_object_lookup(p->filp, data->handle);
  43         if (gobj == NULL)
  44                 return -EINVAL;
  45
  46         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  47         p->uf_entry.priority = 0;
  48         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  49         p->uf_entry.tv.shared = true;
  50         p->uf_entry.user_pages = NULL;
  51
  52         size = amdgpu_bo_size(p->uf_entry.robj);
  53         if (size != PAGE_SIZE || (data->offset + 8) > size)
  54                 return -EINVAL;
  55
  56         *offset = data->offset;
  57
  58         drm_gem_object_put_unlocked(gobj);
  59
  60         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  61                 amdgpu_bo_unref(&p->uf_entry.robj);
  62                 return -EINVAL;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  69 {
  70         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  71         struct amdgpu_vm *vm = &fpriv->vm;
  72         union drm_amdgpu_cs *cs = data;
  73         uint64_t *chunk_array_user;
  74         uint64_t *chunk_array;
  75         unsigned size, num_ibs = 0;
  76         uint32_t uf_offset = 0;
  77         int i;
  78         int ret;
  79
  80         if (cs->in.num_chunks == 0)
  81                 return 0;
  82
  83         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  84         if (!chunk_array)
  85                 return -ENOMEM;
  86
  87         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  88         if (!p->ctx) {
  89                 ret = -EINVAL;
  90                 goto free_chunk;
  91         }
  92
  93         mutex_lock(&p->ctx->lock);
  94
  95         /* get chunks */
  96         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
  97         if (copy_from_user(chunk_array, chunk_array_user,
  98                            sizeof(uint64_t)*cs->in.num_chunks)) {
  99                 ret = -EFAULT;
 100                 goto free_chunk;
 101         }
 102
 103         p->nchunks = cs->in.num_chunks;
 104         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 105                             GFP_KERNEL);
 106         if (!p->chunks) {
 107                 ret = -ENOMEM;
 108                 goto free_chunk;
 109         }
 110
 111         for (i = 0; i < p->nchunks; i++) {
 112                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 113                 struct drm_amdgpu_cs_chunk user_chunk;
 114                 uint32_t __user *cdata;
 115
 116                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 117                 if (copy_from_user(&user_chunk, chunk_ptr,
 118                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 119                         ret = -EFAULT;
 120                         i--;
 121                         goto free_partial_kdata;
 122                 }
 123                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 124                 p->chunks[i].length_dw = user_chunk.length_dw;
 125
 126                 size = p->chunks[i].length_dw;
 127                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 128
 129                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 130                 if (p->chunks[i].kdata == NULL) {
 131                         ret = -ENOMEM;
 132                         i--;
 133                         goto free_partial_kdata;
 134                 }
 135                 size *= sizeof(uint32_t);
 136                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 137                         ret = -EFAULT;
 138                         goto free_partial_kdata;
 139                 }
 140
 141                 switch (p->chunks[i].chunk_id) {
 142                 case AMDGPU_CHUNK_ID_IB:
 143                         ++num_ibs;
 144                         break;
 145
 146                 case AMDGPU_CHUNK_ID_FENCE:
 147                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 148                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 149                                 ret = -EINVAL;
 150                                 goto free_partial_kdata;
 151                         }
 152
 153                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 154                                                          &uf_offset);
 155                         if (ret)
 156                                 goto free_partial_kdata;
 157
 158                         break;
 159
 160                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 161                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 162                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 163                         break;
 164
 165                 default:
 166                         ret = -EINVAL;
 167                         goto free_partial_kdata;
 168                 }
 169         }
 170
 171         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 172         if (ret)
 173                 goto free_all_kdata;
 174
 175         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 176                 ret = -ECANCELED;
 177                 goto free_all_kdata;
 178         }
 179
 180         if (p->uf_entry.robj)
 181                 p->job->uf_addr = uf_offset;
 182         kfree(chunk_array);
 183         return 0;
 184
 185 free_all_kdata:
 186         i = p->nchunks - 1;
 187 free_partial_kdata:
 188         for (; i >= 0; i--)
 189                 kvfree(p->chunks[i].kdata);
 190         kfree(p->chunks);
 191         p->chunks = NULL;
 192         p->nchunks = 0;
 193 free_chunk:
 194         kfree(chunk_array);
 195
 196         return ret;
 197 }
 198
 199 /* Convert microseconds to bytes. */
 200 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 201 {
 202         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 203                 return 0;
 204
 205         /* Since accum_us is incremented by a million per second, just
 206          * multiply it by the number of MB/s to get the number of bytes.
 207          */
 208         return us << adev->mm_stats.log2_max_MBps;
 209 }
 210
 211 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 212 {
 213         if (!adev->mm_stats.log2_max_MBps)
 214                 return 0;
 215
 216         return bytes >> adev->mm_stats.log2_max_MBps;
 217 }
 218
 219 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 220  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 221  * which means it can go over the threshold once. If that happens, the driver
 222  * will be in debt and no other buffer migrations can be done until that debt
 223  * is repaid.
 224  *
 225  * This approach allows moving a buffer of any size (it's important to allow
 226  * that).
 227  *
 228  * The currency is simply time in microseconds and it increases as the clock
 229  * ticks. The accumulated microseconds (us) are converted to bytes and
 230  * returned.
 231  */
 232 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 233                                               u64 *max_bytes,
 234                                               u64 *max_vis_bytes)
 235 {
 236         s64 time_us, increment_us;
 237         u64 free_vram, total_vram, used_vram;
 238
 239         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 240          * throttling.
 241          *
 242          * It means that in order to get full max MBps, at least 5 IBs per
 243          * second must be submitted and not more than 200ms apart from each
 244          * other.
 245          */
 246         const s64 us_upper_bound = 200000;
 247
 248         if (!adev->mm_stats.log2_max_MBps) {
 249                 *max_bytes = 0;
 250                 *max_vis_bytes = 0;
 251                 return;
 252         }
 253
 254         total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
 255         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 256         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 257
 258         spin_lock(&adev->mm_stats.lock);
 259
 260         /* Increase the amount of accumulated us. */
 261         time_us = ktime_to_us(ktime_get());
 262         increment_us = time_us - adev->mm_stats.last_update_us;
 263         adev->mm_stats.last_update_us = time_us;
 264         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 265                                       us_upper_bound);
 266
 267         /* This prevents the short period of low performance when the VRAM
 268          * usage is low and the driver is in debt or doesn't have enough
 269          * accumulated us to fill VRAM quickly.
 270          *
 271          * The situation can occur in these cases:
 272          * - a lot of VRAM is freed by userspace
 273          * - the presence of a big buffer causes a lot of evictions
 274          *   (solution: split buffers into smaller ones)
 275          *
 276          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 277          * accum_us to a positive number.
 278          */
 279         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 280                 s64 min_us;
 281
 282                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 283                  * VRAM now.
 284                  */
 285                 if (!(adev->flags & AMD_IS_APU))
 286                         min_us = bytes_to_us(adev, free_vram / 4);
 287                 else
 288                         min_us = 0; /* Reset accum_us on APUs. */
 289
 290                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 291         }
 292
 293         /* This is set to 0 if the driver is in debt to disallow (optional)
 294          * buffer moves.
 295          */
 296         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 297
 298         /* Do the same for visible VRAM if half of it is free */
 299         if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 300                 u64 total_vis_vram = adev->mc.visible_vram_size;
 301                 u64 used_vis_vram =
 302                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 303
 304                 if (used_vis_vram < total_vis_vram) {
 305                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 306                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 307                                                           increment_us, us_upper_bound);
 308
 309                         if (free_vis_vram >= total_vis_vram / 2)
 310                                 adev->mm_stats.accum_us_vis =
 311                                         max(bytes_to_us(adev, free_vis_vram / 2),
 312                                             adev->mm_stats.accum_us_vis);
 313                 }
 314
 315                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 316         } else {
 317                 *max_vis_bytes = 0;
 318         }
 319
 320         spin_unlock(&adev->mm_stats.lock);
 321 }
 322
 323 /* Report how many bytes have really been moved for the last command
 324  * submission. This can result in a debt that can stop buffer migrations
 325  * temporarily.
 326  */
 327 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 328                                   u64 num_vis_bytes)
 329 {
 330         spin_lock(&adev->mm_stats.lock);
 331         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 332         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 333         spin_unlock(&adev->mm_stats.lock);
 334 }
 335
 336 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 337                                  struct amdgpu_bo *bo)
 338 {
 339         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 340         u64 initial_bytes_moved, bytes_moved;
 341         uint32_t domain;
 342         int r;
 343
 344         if (bo->pin_count)
 345                 return 0;
 346
 347         /* Don't move this buffer if we have depleted our allowance
 348          * to move it. Don't move anything if the threshold is zero.
 349          */
 350         if (p->bytes_moved < p->bytes_moved_threshold) {
 351                 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 352                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 353                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 354                          * visible VRAM if we've depleted our allowance to do
 355                          * that.
 356                          */
 357                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 358                                 domain = bo->preferred_domains;
 359                         else
 360                                 domain = bo->allowed_domains;
 361                 } else {
 362                         domain = bo->preferred_domains;
 363                 }
 364         } else {
 365                 domain = bo->allowed_domains;
 366         }
 367
 368 retry:
 369         amdgpu_ttm_placement_from_domain(bo, domain);
 370         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 371         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 372         bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 373                       initial_bytes_moved;
 374         p->bytes_moved += bytes_moved;
 375         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 376             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 377             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 378                 p->bytes_moved_vis += bytes_moved;
 379
 380         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 381                 domain = bo->allowed_domains;
 382                 goto retry;
 383         }
 384
 385         return r;
 386 }
 387
 388 /* Last resort, try to evict something from the current working set */
 389 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 390                                 struct amdgpu_bo *validated)
 391 {
 392         uint32_t domain = validated->allowed_domains;
 393         int r;
 394
 395         if (!p->evictable)
 396                 return false;
 397
 398         for (;&p->evictable->tv.head != &p->validated;
 399              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 400
 401                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 402                 struct amdgpu_bo *bo = candidate->robj;
 403                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 404                 u64 initial_bytes_moved, bytes_moved;
 405                 bool update_bytes_moved_vis;
 406                 uint32_t other;
 407
 408                 /* If we reached our current BO we can forget it */
 409                 if (candidate->robj == validated)
 410                         break;
 411
 412                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 413
 414                 /* Check if this BO is in one of the domains we need space for */
 415                 if (!(other & domain))
 416                         continue;
 417
 418                 /* Check if we can move this BO somewhere else */
 419                 other = bo->allowed_domains & ~domain;
 420                 if (!other)
 421                         continue;
 422
 423                 /* Good we can try to move this BO somewhere else */
 424                 amdgpu_ttm_placement_from_domain(bo, other);
 425                 update_bytes_moved_vis =
 426                         adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 427                         bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 428                         bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;
 429                 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 430                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 431                 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 432                         initial_bytes_moved;
 433                 p->bytes_moved += bytes_moved;
 434                 if (update_bytes_moved_vis)
 435                         p->bytes_moved_vis += bytes_moved;
 436
 437                 if (unlikely(r))
 438                         break;
 439
 440                 p->evictable = list_prev_entry(p->evictable, tv.head);
 441                 list_move(&candidate->tv.head, &p->validated);
 442
 443                 return true;
 444         }
 445
 446         return false;
 447 }
 448
 449 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 450 {
 451         struct amdgpu_cs_parser *p = param;
 452         int r;
 453
 454         do {
 455                 r = amdgpu_cs_bo_validate(p, bo);
 456         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 457         if (r)
 458                 return r;
 459
 460         if (bo->shadow)
 461                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 462
 463         return r;
 464 }
 465
 466 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 467                             struct list_head *validated)
 468 {
 469         struct amdgpu_bo_list_entry *lobj;
 470         int r;
 471
 472         list_for_each_entry(lobj, validated, tv.head) {
 473                 struct amdgpu_bo *bo = lobj->robj;
 474                 bool binding_userptr = false;
 475                 struct mm_struct *usermm;
 476
 477                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 478                 if (usermm && usermm != current->mm)
 479                         return -EPERM;
 480
 481                 /* Check if we have user pages and nobody bound the BO already */
 482                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 483                     lobj->user_pages) {
 484                         amdgpu_ttm_placement_from_domain(bo,
 485                                                          AMDGPU_GEM_DOMAIN_CPU);
 486                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true,
 487                                             false);
 488                         if (r)
 489                                 return r;
 490                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 491                                                      lobj->user_pages);
 492                         binding_userptr = true;
 493                 }
 494
 495                 if (p->evictable == lobj)
 496                         p->evictable = NULL;
 497
 498                 r = amdgpu_cs_validate(p, bo);
 499                 if (r)
 500                         return r;
 501
 502                 if (binding_userptr) {
 503                         kvfree(lobj->user_pages);
 504                         lobj->user_pages = NULL;
 505                 }
 506         }
 507         return 0;
 508 }
 509
 510 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 511                                 union drm_amdgpu_cs *cs)
 512 {
 513         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 514         struct amdgpu_bo_list_entry *e;
 515         struct list_head duplicates;
 516         unsigned i, tries = 10;
 517         int r;
 518
 519         INIT_LIST_HEAD(&p->validated);
 520
 521         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 522         if (p->bo_list) {
 523                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 524                 if (p->bo_list->first_userptr != p->bo_list->num_entries)
 525                         p->mn = amdgpu_mn_get(p->adev);
 526         }
 527
 528         INIT_LIST_HEAD(&duplicates);
 529         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 530
 531         if (p->uf_entry.robj)
 532                 list_add(&p->uf_entry.tv.head, &p->validated);
 533
 534         while (1) {
 535                 struct list_head need_pages;
 536                 unsigned i;
 537
 538                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 539                                            &duplicates);
 540                 if (unlikely(r != 0)) {
 541                         if (r != -ERESTARTSYS)
 542                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 543                         goto error_free_pages;
 544                 }
 545
 546                 /* Without a BO list we don't have userptr BOs */
 547                 if (!p->bo_list)
 548                         break;
 549
 550                 INIT_LIST_HEAD(&need_pages);
 551                 for (i = p->bo_list->first_userptr;
 552                      i < p->bo_list->num_entries; ++i) {
 553                         struct amdgpu_bo *bo;
 554
 555                         e = &p->bo_list->array[i];
 556                         bo = e->robj;
 557
 558                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 559                                  &e->user_invalidated) && e->user_pages) {
 560
 561                                 /* We acquired a page array, but somebody
 562                                  * invalidated it. Free it and try again
 563                                  */
 564                                 release_pages(e->user_pages,
 565                                               bo->tbo.ttm->num_pages,
 566                                               false);
 567                                 kvfree(e->user_pages);
 568                                 e->user_pages = NULL;
 569                         }
 570
 571                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 572                             !e->user_pages) {
 573                                 list_del(&e->tv.head);
 574                                 list_add(&e->tv.head, &need_pages);
 575
 576                                 amdgpu_bo_unreserve(e->robj);
 577                         }
 578                 }
 579
 580                 if (list_empty(&need_pages))
 581                         break;
 582
 583                 /* Unreserve everything again. */
 584                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 585
 586                 /* We tried too many times, just abort */
 587                 if (!--tries) {
 588                         r = -EDEADLK;
 589                         DRM_ERROR("deadlock in %s\n", __func__);
 590                         goto error_free_pages;
 591                 }
 592
 593                 /* Fill the page arrays for all userptrs. */
 594                 list_for_each_entry(e, &need_pages, tv.head) {
 595                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 596
 597                         e->user_pages = kvmalloc_array(ttm->num_pages,
 598                                                          sizeof(struct page*),
 599                                                          GFP_KERNEL | __GFP_ZERO);
 600                         if (!e->user_pages) {
 601                                 r = -ENOMEM;
 602                                 DRM_ERROR("calloc failure in %s\n", __func__);
 603                                 goto error_free_pages;
 604                         }
 605
 606                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 607                         if (r) {
 608                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 609                                 kvfree(e->user_pages);
 610                                 e->user_pages = NULL;
 611                                 goto error_free_pages;
 612                         }
 613                 }
 614
 615                 /* And try again. */
 616                 list_splice(&need_pages, &p->validated);
 617         }
 618
 619         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 620                                           &p->bytes_moved_vis_threshold);
 621         p->bytes_moved = 0;
 622         p->bytes_moved_vis = 0;
 623         p->evictable = list_last_entry(&p->validated,
 624                                        struct amdgpu_bo_list_entry,
 625                                        tv.head);
 626
 627         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 628                                       amdgpu_cs_validate, p);
 629         if (r) {
 630                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 631                 goto error_validate;
 632         }
 633
 634         r = amdgpu_cs_list_validate(p, &duplicates);
 635         if (r) {
 636                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 637                 goto error_validate;
 638         }
 639
 640         r = amdgpu_cs_list_validate(p, &p->validated);
 641         if (r) {
 642                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 643                 goto error_validate;
 644         }
 645
 646         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 647                                      p->bytes_moved_vis);
 648         if (p->bo_list) {
 649                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 650                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 651                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 652                 struct amdgpu_vm *vm = &fpriv->vm;
 653                 unsigned i;
 654
 655                 for (i = 0; i < p->bo_list->num_entries; i++) {
 656                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 657
 658                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 659                 }
 660
 661                 if (gds) {
 662                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 663                         p->job->gds_size = amdgpu_bo_size(gds);
 664                 }
 665                 if (gws) {
 666                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 667                         p->job->gws_size = amdgpu_bo_size(gws);
 668                 }
 669                 if (oa) {
 670                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 671                         p->job->oa_size = amdgpu_bo_size(oa);
 672                 }
 673         }
 674
 675         if (!r && p->uf_entry.robj) {
 676                 struct amdgpu_bo *uf = p->uf_entry.robj;
 677
 678                 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
 679                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 680         }
 681
 682 error_validate:
 683         if (r)
 684                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 685
 686 error_free_pages:
 687
 688         if (p->bo_list) {
 689                 for (i = p->bo_list->first_userptr;
 690                      i < p->bo_list->num_entries; ++i) {
 691                         e = &p->bo_list->array[i];
 692
 693                         if (!e->user_pages)
 694                                 continue;
 695
 696                         release_pages(e->user_pages,
 697                                       e->robj->tbo.ttm->num_pages,
 698                                       false);
 699                         kvfree(e->user_pages);
 700                 }
 701         }
 702
 703         return r;
 704 }
 705
 706 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 707 {
 708         struct amdgpu_bo_list_entry *e;
 709         int r;
 710
 711         list_for_each_entry(e, &p->validated, tv.head) {
 712                 struct reservation_object *resv = e->robj->tbo.resv;
 713                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 714                                      amdgpu_bo_explicit_sync(e->robj));
 715
 716                 if (r)
 717                         return r;
 718         }
 719         return 0;
 720 }
 721
 722 /**
 723  * cs_parser_fini() - clean parser states
 724  * @parser:     parser structure holding parsing context.
 725  * @error:      error number
 726  *
 727  * If error is set than unvalidate buffer, otherwise just free memory
 728  * used by parsing context.
 729  **/
 730 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 731                                   bool backoff)
 732 {
 733         unsigned i;
 734
 735         if (error && backoff)
 736                 ttm_eu_backoff_reservation(&parser->ticket,
 737                                            &parser->validated);
 738
 739         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 740                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 741         kfree(parser->post_dep_syncobjs);
 742
 743         dma_fence_put(parser->fence);
 744
 745         if (parser->ctx) {
 746                 mutex_unlock(&parser->ctx->lock);
 747                 amdgpu_ctx_put(parser->ctx);
 748         }
 749         if (parser->bo_list)
 750                 amdgpu_bo_list_put(parser->bo_list);
 751
 752         for (i = 0; i < parser->nchunks; i++)
 753                 kvfree(parser->chunks[i].kdata);
 754         kfree(parser->chunks);
 755         if (parser->job)
 756                 amdgpu_job_free(parser->job);
 757         amdgpu_bo_unref(&parser->uf_entry.robj);
 758 }
 759
 760 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 761 {
 762         struct amdgpu_device *adev = p->adev;
 763         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 764         struct amdgpu_vm *vm = &fpriv->vm;
 765         struct amdgpu_bo_va *bo_va;
 766         struct amdgpu_bo *bo;
 767         int i, r;
 768
 769         r = amdgpu_vm_update_directories(adev, vm);
 770         if (r)
 771                 return r;
 772
 773         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 774         if (r)
 775                 return r;
 776
 777         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 778         if (r)
 779                 return r;
 780
 781         r = amdgpu_sync_fence(adev, &p->job->sync,
 782                               fpriv->prt_va->last_pt_update);
 783         if (r)
 784                 return r;
 785
 786         if (amdgpu_sriov_vf(adev)) {
 787                 struct dma_fence *f;
 788
 789                 bo_va = fpriv->csa_va;
 790                 BUG_ON(!bo_va);
 791                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 792                 if (r)
 793                         return r;
 794
 795                 f = bo_va->last_pt_update;
 796                 r = amdgpu_sync_fence(adev, &p->job->sync, f);
 797                 if (r)
 798                         return r;
 799         }
 800
 801         if (p->bo_list) {
 802                 for (i = 0; i < p->bo_list->num_entries; i++) {
 803                         struct dma_fence *f;
 804
 805                         /* ignore duplicates */
 806                         bo = p->bo_list->array[i].robj;
 807                         if (!bo)
 808                                 continue;
 809
 810                         bo_va = p->bo_list->array[i].bo_va;
 811                         if (bo_va == NULL)
 812                                 continue;
 813
 814                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 815                         if (r)
 816                                 return r;
 817
 818                         f = bo_va->last_pt_update;
 819                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 820                         if (r)
 821                                 return r;
 822                 }
 823
 824         }
 825
 826         r = amdgpu_vm_handle_moved(adev, vm);
 827         if (r)
 828                 return r;
 829
 830         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update);
 831         if (r)
 832                 return r;
 833
 834         if (amdgpu_vm_debug && p->bo_list) {
 835                 /* Invalidate all BOs to test for userspace bugs */
 836                 for (i = 0; i < p->bo_list->num_entries; i++) {
 837                         /* ignore duplicates */
 838                         bo = p->bo_list->array[i].robj;
 839                         if (!bo)
 840                                 continue;
 841
 842                         amdgpu_vm_bo_invalidate(adev, bo, false);
 843                 }
 844         }
 845
 846         return r;
 847 }
 848
 849 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 850                                  struct amdgpu_cs_parser *p)
 851 {
 852         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 853         struct amdgpu_vm *vm = &fpriv->vm;
 854         struct amdgpu_ring *ring = p->job->ring;
 855         int r;
 856
 857         /* Only for UVD/VCE VM emulation */
 858         if (p->job->ring->funcs->parse_cs) {
 859                 unsigned i, j;
 860
 861                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 862                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 863                         struct amdgpu_bo_va_mapping *m;
 864                         struct amdgpu_bo *aobj = NULL;
 865                         struct amdgpu_cs_chunk *chunk;
 866                         struct amdgpu_ib *ib;
 867                         uint64_t offset;
 868                         uint8_t *kptr;
 869
 870                         chunk = &p->chunks[i];
 871                         ib = &p->job->ibs[j];
 872                         chunk_ib = chunk->kdata;
 873
 874                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 875                                 continue;
 876
 877                         r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
 878                                                    &aobj, &m);
 879                         if (r) {
 880                                 DRM_ERROR("IB va_start is invalid\n");
 881                                 return r;
 882                         }
 883
 884                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 885                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 886                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 887                                 return -EINVAL;
 888                         }
 889
 890                         /* the IB should be reserved at this point */
 891                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 892                         if (r) {
 893                                 return r;
 894                         }
 895
 896                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 897                         kptr += chunk_ib->va_start - offset;
 898
 899                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 900                         amdgpu_bo_kunmap(aobj);
 901
 902                         r = amdgpu_ring_parse_cs(ring, p, j);
 903                         if (r)
 904                                 return r;
 905
 906                         j++;
 907                 }
 908         }
 909
 910         if (p->job->vm) {
 911                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
 912
 913                 r = amdgpu_bo_vm_update_pte(p);
 914                 if (r)
 915                         return r;
 916         }
 917
 918         return amdgpu_cs_sync_rings(p);
 919 }
 920
 921 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 922                              struct amdgpu_cs_parser *parser)
 923 {
 924         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 925         struct amdgpu_vm *vm = &fpriv->vm;
 926         int i, j;
 927         int r, ce_preempt = 0, de_preempt = 0;
 928
 929         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 930                 struct amdgpu_cs_chunk *chunk;
 931                 struct amdgpu_ib *ib;
 932                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 933                 struct amdgpu_ring *ring;
 934
 935                 chunk = &parser->chunks[i];
 936                 ib = &parser->job->ibs[j];
 937                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 938
 939                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 940                         continue;
 941
 942                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 943                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 944                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 945                                         ce_preempt++;
 946                                 else
 947                                         de_preempt++;
 948                         }
 949
 950                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 951                         if (ce_preempt > 1 || de_preempt > 1)
 952                                 return -EINVAL;
 953                 }
 954
 955                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 956                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 957                 if (r)
 958                         return r;
 959
 960                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 961                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 962                         if (!parser->ctx->preamble_presented) {
 963                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 964                                 parser->ctx->preamble_presented = true;
 965                         }
 966                 }
 967
 968                 if (parser->job->ring && parser->job->ring != ring)
 969                         return -EINVAL;
 970
 971                 parser->job->ring = ring;
 972
 973                 r =  amdgpu_ib_get(adev, vm,
 974                                         ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
 975                                         ib);
 976                 if (r) {
 977                         DRM_ERROR("Failed to get ib !\n");
 978                         return r;
 979                 }
 980
 981                 ib->gpu_addr = chunk_ib->va_start;
 982                 ib->length_dw = chunk_ib->ib_bytes / 4;
 983                 ib->flags = chunk_ib->flags;
 984
 985                 j++;
 986         }
 987
 988         /* UVD & VCE fw doesn't support user fences */
 989         if (parser->job->uf_addr && (
 990             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 991             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
 992                 return -EINVAL;
 993
 994         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
 995 }
 996
 997 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 998                                        struct amdgpu_cs_chunk *chunk)
 999 {
1000         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1001         unsigned num_deps;
1002         int i, r;
1003         struct drm_amdgpu_cs_chunk_dep *deps;
1004
1005         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1006         num_deps = chunk->length_dw * 4 /
1007                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1008
1009         for (i = 0; i < num_deps; ++i) {
1010                 struct amdgpu_ring *ring;
1011                 struct amdgpu_ctx *ctx;
1012                 struct dma_fence *fence;
1013
1014                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1015                 if (ctx == NULL)
1016                         return -EINVAL;
1017
1018                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1019                                          deps[i].ip_type,
1020                                          deps[i].ip_instance,
1021                                          deps[i].ring, &ring);
1022                 if (r) {
1023                         amdgpu_ctx_put(ctx);
1024                         return r;
1025                 }
1026
1027                 fence = amdgpu_ctx_get_fence(ctx, ring,
1028                                              deps[i].handle);
1029                 if (IS_ERR(fence)) {
1030                         r = PTR_ERR(fence);
1031                         amdgpu_ctx_put(ctx);
1032                         return r;
1033                 } else if (fence) {
1034                         r = amdgpu_sync_fence(p->adev, &p->job->sync,
1035                                               fence);
1036                         dma_fence_put(fence);
1037                         amdgpu_ctx_put(ctx);
1038                         if (r)
1039                                 return r;
1040                 }
1041         }
1042         return 0;
1043 }
1044
1045 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1046                                                  uint32_t handle)
1047 {
1048         int r;
1049         struct dma_fence *fence;
1050         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1051         if (r)
1052                 return r;
1053
1054         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
1055         dma_fence_put(fence);
1056
1057         return r;
1058 }
1059
1060 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1061                                             struct amdgpu_cs_chunk *chunk)
1062 {
1063         unsigned num_deps;
1064         int i, r;
1065         struct drm_amdgpu_cs_chunk_sem *deps;
1066
1067         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1068         num_deps = chunk->length_dw * 4 /
1069                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1070
1071         for (i = 0; i < num_deps; ++i) {
1072                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1073                 if (r)
1074                         return r;
1075         }
1076         return 0;
1077 }
1078
1079 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1080                                              struct amdgpu_cs_chunk *chunk)
1081 {
1082         unsigned num_deps;
1083         int i;
1084         struct drm_amdgpu_cs_chunk_sem *deps;
1085         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1086         num_deps = chunk->length_dw * 4 /
1087                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1088
1089         p->post_dep_syncobjs = kmalloc_array(num_deps,
1090                                              sizeof(struct drm_syncobj *),
1091                                              GFP_KERNEL);
1092         p->num_post_dep_syncobjs = 0;
1093
1094         if (!p->post_dep_syncobjs)
1095                 return -ENOMEM;
1096
1097         for (i = 0; i < num_deps; ++i) {
1098                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1099                 if (!p->post_dep_syncobjs[i])
1100                         return -EINVAL;
1101                 p->num_post_dep_syncobjs++;
1102         }
1103         return 0;
1104 }
1105
1106 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1107                                   struct amdgpu_cs_parser *p)
1108 {
1109         int i, r;
1110
1111         for (i = 0; i < p->nchunks; ++i) {
1112                 struct amdgpu_cs_chunk *chunk;
1113
1114                 chunk = &p->chunks[i];
1115
1116                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1117                         r = amdgpu_cs_process_fence_dep(p, chunk);
1118                         if (r)
1119                                 return r;
1120                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1121                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1122                         if (r)
1123                                 return r;
1124                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1125                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1126                         if (r)
1127                                 return r;
1128                 }
1129         }
1130
1131         return 0;
1132 }
1133
1134 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1135 {
1136         int i;
1137
1138         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1139                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1140 }
1141
1142 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1143                             union drm_amdgpu_cs *cs)
1144 {
1145         struct amdgpu_ring *ring = p->job->ring;
1146         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1147         struct amdgpu_job *job;
1148         unsigned i;
1149         uint64_t seq;
1150
1151         int r;
1152
1153         amdgpu_mn_lock(p->mn);
1154         if (p->bo_list) {
1155                 for (i = p->bo_list->first_userptr;
1156                      i < p->bo_list->num_entries; ++i) {
1157                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1158
1159                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1160                                 amdgpu_mn_unlock(p->mn);
1161                                 return -ERESTARTSYS;
1162                         }
1163                 }
1164         }
1165
1166         job = p->job;
1167         p->job = NULL;
1168
1169         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1170         if (r) {
1171                 amdgpu_job_free(job);
1172                 amdgpu_mn_unlock(p->mn);
1173                 return r;
1174         }
1175
1176         job->owner = p->filp;
1177         job->fence_ctx = entity->fence_context;
1178         p->fence = dma_fence_get(&job->base.s_fence->finished);
1179
1180         r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1181         if (r) {
1182                 dma_fence_put(p->fence);
1183                 dma_fence_put(&job->base.s_fence->finished);
1184                 amdgpu_job_free(job);
1185                 amdgpu_mn_unlock(p->mn);
1186                 return r;
1187         }
1188
1189         amdgpu_cs_post_dependencies(p);
1190
1191         cs->out.handle = seq;
1192         job->uf_sequence = seq;
1193
1194         amdgpu_job_free_resources(job);
1195         amdgpu_ring_priority_get(job->ring,
1196                                  amd_sched_get_job_priority(&job->base));
1197
1198         trace_amdgpu_cs_ioctl(job);
1199         amd_sched_entity_push_job(&job->base);
1200
1201         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1202         amdgpu_mn_unlock(p->mn);
1203
1204         return 0;
1205 }
1206
1207 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1208 {
1209         struct amdgpu_device *adev = dev->dev_private;
1210         union drm_amdgpu_cs *cs = data;
1211         struct amdgpu_cs_parser parser = {};
1212         bool reserved_buffers = false;
1213         int i, r;
1214
1215         if (!adev->accel_working)
1216                 return -EBUSY;
1217
1218         parser.adev = adev;
1219         parser.filp = filp;
1220
1221         r = amdgpu_cs_parser_init(&parser, data);
1222         if (r) {
1223                 DRM_ERROR("Failed to initialize parser !\n");
1224                 goto out;
1225         }
1226
1227         r = amdgpu_cs_ib_fill(adev, &parser);
1228         if (r)
1229                 goto out;
1230
1231         r = amdgpu_cs_parser_bos(&parser, data);
1232         if (r) {
1233                 if (r == -ENOMEM)
1234                         DRM_ERROR("Not enough memory for command submission!\n");
1235                 else if (r != -ERESTARTSYS)
1236                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1237                 goto out;
1238         }
1239
1240         reserved_buffers = true;
1241
1242         r = amdgpu_cs_dependencies(adev, &parser);
1243         if (r) {
1244                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1245                 goto out;
1246         }
1247
1248         for (i = 0; i < parser.job->num_ibs; i++)
1249                 trace_amdgpu_cs(&parser, i);
1250
1251         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1252         if (r)
1253                 goto out;
1254
1255         r = amdgpu_cs_submit(&parser, cs);
1256
1257 out:
1258         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1259         return r;
1260 }
1261
1262 /**
1263  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1264  *
1265  * @dev: drm device
1266  * @data: data from userspace
1267  * @filp: file private
1268  *
1269  * Wait for the command submission identified by handle to finish.
1270  */
1271 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1272                          struct drm_file *filp)
1273 {
1274         union drm_amdgpu_wait_cs *wait = data;
1275         struct amdgpu_device *adev = dev->dev_private;
1276         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1277         struct amdgpu_ring *ring = NULL;
1278         struct amdgpu_ctx *ctx;
1279         struct dma_fence *fence;
1280         long r;
1281
1282         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1283         if (ctx == NULL)
1284                 return -EINVAL;
1285
1286         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1287                                  wait->in.ip_type, wait->in.ip_instance,
1288                                  wait->in.ring, &ring);
1289         if (r) {
1290                 amdgpu_ctx_put(ctx);
1291                 return r;
1292         }
1293
1294         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1295         if (IS_ERR(fence))
1296                 r = PTR_ERR(fence);
1297         else if (fence) {
1298                 r = dma_fence_wait_timeout(fence, true, timeout);
1299                 if (r > 0 && fence->error)
1300                         r = fence->error;
1301                 dma_fence_put(fence);
1302         } else
1303                 r = 1;
1304
1305         amdgpu_ctx_put(ctx);
1306         if (r < 0)
1307                 return r;
1308
1309         memset(wait, 0, sizeof(*wait));
1310         wait->out.status = (r == 0);
1311
1312         return 0;
1313 }
1314
1315 /**
1316  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1317  *
1318  * @adev: amdgpu device
1319  * @filp: file private
1320  * @user: drm_amdgpu_fence copied from user space
1321  */
1322 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1323                                              struct drm_file *filp,
1324                                              struct drm_amdgpu_fence *user)
1325 {
1326         struct amdgpu_ring *ring;
1327         struct amdgpu_ctx *ctx;
1328         struct dma_fence *fence;
1329         int r;
1330
1331         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1332         if (ctx == NULL)
1333                 return ERR_PTR(-EINVAL);
1334
1335         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1336                                  user->ip_instance, user->ring, &ring);
1337         if (r) {
1338                 amdgpu_ctx_put(ctx);
1339                 return ERR_PTR(r);
1340         }
1341
1342         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1343         amdgpu_ctx_put(ctx);
1344
1345         return fence;
1346 }
1347
1348 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1349                                     struct drm_file *filp)
1350 {
1351         struct amdgpu_device *adev = dev->dev_private;
1352         union drm_amdgpu_fence_to_handle *info = data;
1353         struct dma_fence *fence;
1354         struct drm_syncobj *syncobj;
1355         struct sync_file *sync_file;
1356         int fd, r;
1357
1358         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1359         if (IS_ERR(fence))
1360                 return PTR_ERR(fence);
1361
1362         switch (info->in.what) {
1363         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1364                 r = drm_syncobj_create(&syncobj, 0, fence);
1365                 dma_fence_put(fence);
1366                 if (r)
1367                         return r;
1368                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1369                 drm_syncobj_put(syncobj);
1370                 return r;
1371
1372         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1373                 r = drm_syncobj_create(&syncobj, 0, fence);
1374                 dma_fence_put(fence);
1375                 if (r)
1376                         return r;
1377                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1378                 drm_syncobj_put(syncobj);
1379                 return r;
1380
1381         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1382                 fd = get_unused_fd_flags(O_CLOEXEC);
1383                 if (fd < 0) {
1384                         dma_fence_put(fence);
1385                         return fd;
1386                 }
1387
1388                 sync_file = sync_file_create(fence);
1389                 dma_fence_put(fence);
1390                 if (!sync_file) {
1391                         put_unused_fd(fd);
1392                         return -ENOMEM;
1393                 }
1394
1395                 fd_install(fd, sync_file->file);
1396                 info->out.handle = fd;
1397                 return 0;
1398
1399         default:
1400                 return -EINVAL;
1401         }
1402 }
1403
1404 /**
1405  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1406  *
1407  * @adev: amdgpu device
1408  * @filp: file private
1409  * @wait: wait parameters
1410  * @fences: array of drm_amdgpu_fence
1411  */
1412 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1413                                      struct drm_file *filp,
1414                                      union drm_amdgpu_wait_fences *wait,
1415                                      struct drm_amdgpu_fence *fences)
1416 {
1417         uint32_t fence_count = wait->in.fence_count;
1418         unsigned int i;
1419         long r = 1;
1420
1421         for (i = 0; i < fence_count; i++) {
1422                 struct dma_fence *fence;
1423                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1424
1425                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1426                 if (IS_ERR(fence))
1427                         return PTR_ERR(fence);
1428                 else if (!fence)
1429                         continue;
1430
1431                 r = dma_fence_wait_timeout(fence, true, timeout);
1432                 dma_fence_put(fence);
1433                 if (r < 0)
1434                         return r;
1435
1436                 if (r == 0)
1437                         break;
1438
1439                 if (fence->error)
1440                         return fence->error;
1441         }
1442
1443         memset(wait, 0, sizeof(*wait));
1444         wait->out.status = (r > 0);
1445
1446         return 0;
1447 }
1448
1449 /**
1450  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1451  *
1452  * @adev: amdgpu device
1453  * @filp: file private
1454  * @wait: wait parameters
1455  * @fences: array of drm_amdgpu_fence
1456  */
1457 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1458                                     struct drm_file *filp,
1459                                     union drm_amdgpu_wait_fences *wait,
1460                                     struct drm_amdgpu_fence *fences)
1461 {
1462         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1463         uint32_t fence_count = wait->in.fence_count;
1464         uint32_t first = ~0;
1465         struct dma_fence **array;
1466         unsigned int i;
1467         long r;
1468
1469         /* Prepare the fence array */
1470         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1471
1472         if (array == NULL)
1473                 return -ENOMEM;
1474
1475         for (i = 0; i < fence_count; i++) {
1476                 struct dma_fence *fence;
1477
1478                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1479                 if (IS_ERR(fence)) {
1480                         r = PTR_ERR(fence);
1481                         goto err_free_fence_array;
1482                 } else if (fence) {
1483                         array[i] = fence;
1484                 } else { /* NULL, the fence has been already signaled */
1485                         r = 1;
1486                         first = i;
1487                         goto out;
1488                 }
1489         }
1490
1491         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1492                                        &first);
1493         if (r < 0)
1494                 goto err_free_fence_array;
1495
1496 out:
1497         memset(wait, 0, sizeof(*wait));
1498         wait->out.status = (r > 0);
1499         wait->out.first_signaled = first;
1500
1501         if (first < fence_count && array[first])
1502                 r = array[first]->error;
1503         else
1504                 r = 0;
1505
1506 err_free_fence_array:
1507         for (i = 0; i < fence_count; i++)
1508                 dma_fence_put(array[i]);
1509         kfree(array);
1510
1511         return r;
1512 }
1513
1514 /**
1515  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1516  *
1517  * @dev: drm device
1518  * @data: data from userspace
1519  * @filp: file private
1520  */
1521 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1522                                 struct drm_file *filp)
1523 {
1524         struct amdgpu_device *adev = dev->dev_private;
1525         union drm_amdgpu_wait_fences *wait = data;
1526         uint32_t fence_count = wait->in.fence_count;
1527         struct drm_amdgpu_fence *fences_user;
1528         struct drm_amdgpu_fence *fences;
1529         int r;
1530
1531         /* Get the fences from userspace */
1532         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1533                         GFP_KERNEL);
1534         if (fences == NULL)
1535                 return -ENOMEM;
1536
1537         fences_user = u64_to_user_ptr(wait->in.fences);
1538         if (copy_from_user(fences, fences_user,
1539                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1540                 r = -EFAULT;
1541                 goto err_free_fences;
1542         }
1543
1544         if (wait->in.wait_all)
1545                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1546         else
1547                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1548
1549 err_free_fences:
1550         kfree(fences);
1551
1552         return r;
1553 }
1554
1555 /**
1556  * amdgpu_cs_find_bo_va - find bo_va for VM address
1557  *
1558  * @parser: command submission parser context
1559  * @addr: VM address
1560  * @bo: resulting BO of the mapping found
1561  *
1562  * Search the buffer objects in the command submission context for a certain
1563  * virtual memory address. Returns allocation structure when found, NULL
1564  * otherwise.
1565  */
1566 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1567                            uint64_t addr, struct amdgpu_bo **bo,
1568                            struct amdgpu_bo_va_mapping **map)
1569 {
1570         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1571         struct amdgpu_vm *vm = &fpriv->vm;
1572         struct amdgpu_bo_va_mapping *mapping;
1573         int r;
1574
1575         addr /= AMDGPU_GPU_PAGE_SIZE;
1576
1577         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1578         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1579                 return -EINVAL;
1580
1581         *bo = mapping->bo_va->base.bo;
1582         *map = mapping;
1583
1584         /* Double check that the BO is reserved by this CS */
1585         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1586                 return -EINVAL;
1587
1588         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1589                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1590                 amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1591                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false,
1592                                     false);
1593                 if (r)
1594                         return r;
1595         }
1596
1597         return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem);
1598 }