drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/display/drm_dp_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_modeset_helper_vtables.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include "amdgpu.h"
  34 #include "atom.h"
  35 #include "atombios_encoders.h"
  36 #include "atombios_dp.h"
  37 #include "amdgpu_connectors.h"
  38 #include "amdgpu_i2c.h"
  39 #include "amdgpu_display.h"
  40
  41 #include <linux/pm_runtime.h>
  42
  43 void amdgpu_connector_hotplug(struct drm_connector *connector)
  44 {
  45         struct drm_device *dev = connector->dev;
  46         struct amdgpu_device *adev = drm_to_adev(dev);
  47         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  48
  49         /* bail if the connector does not have hpd pin, e.g.,
  50          * VGA, TV, etc.
  51          */
  52         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  53                 return;
  54
  55         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  56
  57         /* if the connector is already off, don't turn it back on */
  58         if (connector->dpms != DRM_MODE_DPMS_ON)
  59                 return;
  60
  61         /* just deal with DP (not eDP) here. */
  62         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  63                 struct amdgpu_connector_atom_dig *dig_connector =
  64                         amdgpu_connector->con_priv;
  65
  66                 /* if existing sink type was not DP no need to retrain */
  67                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  68                         return;
  69
  70                 /* first get sink type as it may be reset after (un)plug */
  71                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  72                 /* don't do anything if sink is not display port, i.e.,
  73                  * passive dp->(dvi|hdmi) adaptor
  74                  */
  75                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  76                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  77                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  78                         /* Don't start link training before we have the DPCD */
  79                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  80                                 return;
  81
  82                         /* Turn the connector off and back on immediately, which
  83                          * will trigger link training
  84                          */
  85                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  86                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  92 {
  93         struct drm_crtc *crtc = encoder->crtc;
  94
  95         if (crtc && crtc->enabled) {
  96                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  97                                          crtc->x, crtc->y, crtc->primary->fb);
  98         }
  99 }
 100
 101 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 102 {
 103         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 104         struct amdgpu_connector_atom_dig *dig_connector;
 105         int bpc = 8;
 106         unsigned int mode_clock, max_tmds_clock;
 107
 108         switch (connector->connector_type) {
 109         case DRM_MODE_CONNECTOR_DVII:
 110         case DRM_MODE_CONNECTOR_HDMIB:
 111                 if (amdgpu_connector->use_digital) {
 112                         if (connector->display_info.is_hdmi) {
 113                                 if (connector->display_info.bpc)
 114                                         bpc = connector->display_info.bpc;
 115                         }
 116                 }
 117                 break;
 118         case DRM_MODE_CONNECTOR_DVID:
 119         case DRM_MODE_CONNECTOR_HDMIA:
 120                 if (connector->display_info.is_hdmi) {
 121                         if (connector->display_info.bpc)
 122                                 bpc = connector->display_info.bpc;
 123                 }
 124                 break;
 125         case DRM_MODE_CONNECTOR_DisplayPort:
 126                 dig_connector = amdgpu_connector->con_priv;
 127                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 128                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 129                     connector->display_info.is_hdmi) {
 130                         if (connector->display_info.bpc)
 131                                 bpc = connector->display_info.bpc;
 132                 }
 133                 break;
 134         case DRM_MODE_CONNECTOR_eDP:
 135         case DRM_MODE_CONNECTOR_LVDS:
 136                 if (connector->display_info.bpc)
 137                         bpc = connector->display_info.bpc;
 138                 else {
 139                         const struct drm_connector_helper_funcs *connector_funcs =
 140                                 connector->helper_private;
 141                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 142                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 143                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 144
 145                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 146                                 bpc = 6;
 147                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 148                                 bpc = 8;
 149                 }
 150                 break;
 151         }
 152
 153         if (connector->display_info.is_hdmi) {
 154                 /*
 155                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 156                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 157                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 158                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 159                  */
 160                 if (bpc > 12) {
 161                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 162                                   connector->name, bpc);
 163                         bpc = 12;
 164                 }
 165
 166                 /* Any defined maximum tmds clock limit we must not exceed? */
 167                 if (connector->display_info.max_tmds_clock > 0) {
 168                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 169                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 170
 171                         /* Maximum allowable input clock in kHz */
 172                         max_tmds_clock = connector->display_info.max_tmds_clock;
 173
 174                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 175                                   connector->name, mode_clock, max_tmds_clock);
 176
 177                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 178                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 179                                 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
 180                                     (mode_clock * 5/4 <= max_tmds_clock))
 181                                         bpc = 10;
 182                                 else
 183                                         bpc = 8;
 184
 185                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 186                                           connector->name, bpc);
 187                         }
 188
 189                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 190                                 bpc = 8;
 191                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 192                                           connector->name, bpc);
 193                         }
 194                 } else if (bpc > 8) {
 195                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 196                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 197                                   connector->name);
 198                         bpc = 8;
 199                 }
 200         }
 201
 202         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 203                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 204                           connector->name);
 205                 bpc = 8;
 206         }
 207
 208         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 209                   connector->name, connector->display_info.bpc, bpc);
 210
 211         return bpc;
 212 }
 213
 214 static void
 215 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 216                                       enum drm_connector_status status)
 217 {
 218         struct drm_encoder *best_encoder;
 219         struct drm_encoder *encoder;
 220         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 221         bool connected;
 222
 223         best_encoder = connector_funcs->best_encoder(connector);
 224
 225         drm_connector_for_each_possible_encoder(connector, encoder) {
 226                 if ((encoder == best_encoder) && (status == connector_status_connected))
 227                         connected = true;
 228                 else
 229                         connected = false;
 230
 231                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 232         }
 233 }
 234
 235 static struct drm_encoder *
 236 amdgpu_connector_find_encoder(struct drm_connector *connector,
 237                                int encoder_type)
 238 {
 239         struct drm_encoder *encoder;
 240
 241         drm_connector_for_each_possible_encoder(connector, encoder) {
 242                 if (encoder->encoder_type == encoder_type)
 243                         return encoder;
 244         }
 245
 246         return NULL;
 247 }
 248
 249 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 250 {
 251         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 252         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 253
 254         if (amdgpu_connector->edid) {
 255                 return amdgpu_connector->edid;
 256         } else if (edid_blob) {
 257                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 258
 259                 if (edid)
 260                         amdgpu_connector->edid = edid;
 261         }
 262         return amdgpu_connector->edid;
 263 }
 264
 265 static struct edid *
 266 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 267 {
 268         if (adev->mode_info.bios_hardcoded_edid) {
 269                 return kmemdup((unsigned char *)adev->mode_info.bios_hardcoded_edid,
 270                                adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 271         }
 272         return NULL;
 273 }
 274
 275 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 276 {
 277         struct drm_device *dev = connector->dev;
 278         struct amdgpu_device *adev = drm_to_adev(dev);
 279         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 280
 281         if (amdgpu_connector->edid)
 282                 return;
 283
 284         /* on hw with routers, select right port */
 285         if (amdgpu_connector->router.ddc_valid)
 286                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 287
 288         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 289              ENCODER_OBJECT_ID_NONE) &&
 290             amdgpu_connector->ddc_bus->has_aux) {
 291                 amdgpu_connector->edid = drm_get_edid(connector,
 292                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 293         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 294                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 295                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 296
 297                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 298                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 299                     amdgpu_connector->ddc_bus->has_aux)
 300                         amdgpu_connector->edid = drm_get_edid(connector,
 301                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 302                 else if (amdgpu_connector->ddc_bus)
 303                         amdgpu_connector->edid = drm_get_edid(connector,
 304                                                               &amdgpu_connector->ddc_bus->adapter);
 305         } else if (amdgpu_connector->ddc_bus) {
 306                 amdgpu_connector->edid = drm_get_edid(connector,
 307                                                       &amdgpu_connector->ddc_bus->adapter);
 308         }
 309
 310         if (!amdgpu_connector->edid) {
 311                 /* some laptops provide a hardcoded edid in rom for LCDs */
 312                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 313                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) {
 314                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 315                         drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 316                 }
 317         }
 318 }
 319
 320 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 321 {
 322         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 323
 324         kfree(amdgpu_connector->edid);
 325         amdgpu_connector->edid = NULL;
 326 }
 327
 328 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 329 {
 330         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 331         int ret;
 332
 333         if (amdgpu_connector->edid) {
 334                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
 335                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 336                 return ret;
 337         }
 338         drm_connector_update_edid_property(connector, NULL);
 339         return 0;
 340 }
 341
 342 static struct drm_encoder *
 343 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 344 {
 345         struct drm_encoder *encoder;
 346
 347         /* pick the first one */
 348         drm_connector_for_each_possible_encoder(connector, encoder)
 349                 return encoder;
 350
 351         return NULL;
 352 }
 353
 354 static void amdgpu_get_native_mode(struct drm_connector *connector)
 355 {
 356         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 357         struct amdgpu_encoder *amdgpu_encoder;
 358
 359         if (encoder == NULL)
 360                 return;
 361
 362         amdgpu_encoder = to_amdgpu_encoder(encoder);
 363
 364         if (!list_empty(&connector->probed_modes)) {
 365                 struct drm_display_mode *preferred_mode =
 366                         list_first_entry(&connector->probed_modes,
 367                                          struct drm_display_mode, head);
 368
 369                 amdgpu_encoder->native_mode = *preferred_mode;
 370         } else {
 371                 amdgpu_encoder->native_mode.clock = 0;
 372         }
 373 }
 374
 375 static struct drm_display_mode *
 376 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 377 {
 378         struct drm_device *dev = encoder->dev;
 379         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 380         struct drm_display_mode *mode = NULL;
 381         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 382
 383         if (native_mode->hdisplay != 0 &&
 384             native_mode->vdisplay != 0 &&
 385             native_mode->clock != 0) {
 386                 mode = drm_mode_duplicate(dev, native_mode);
 387                 if (!mode)
 388                         return NULL;
 389
 390                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 391                 drm_mode_set_name(mode);
 392
 393                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 394         } else if (native_mode->hdisplay != 0 &&
 395                    native_mode->vdisplay != 0) {
 396                 /* mac laptops without an edid */
 397                 /* Note that this is not necessarily the exact panel mode,
 398                  * but an approximation based on the cvt formula.  For these
 399                  * systems we should ideally read the mode info out of the
 400                  * registers or add a mode table, but this works and is much
 401                  * simpler.
 402                  */
 403                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 404                 if (!mode)
 405                         return NULL;
 406
 407                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 408                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 409         }
 410         return mode;
 411 }
 412
 413 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 414                                                struct drm_connector *connector)
 415 {
 416         struct drm_device *dev = encoder->dev;
 417         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 418         struct drm_display_mode *mode = NULL;
 419         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 420         int i;
 421         static const struct mode_size {
 422                 int w;
 423                 int h;
 424         } common_modes[17] = {
 425                 { 640,  480},
 426                 { 720,  480},
 427                 { 800,  600},
 428                 { 848,  480},
 429                 {1024,  768},
 430                 {1152,  768},
 431                 {1280,  720},
 432                 {1280,  800},
 433                 {1280,  854},
 434                 {1280,  960},
 435                 {1280, 1024},
 436                 {1440,  900},
 437                 {1400, 1050},
 438                 {1680, 1050},
 439                 {1600, 1200},
 440                 {1920, 1080},
 441                 {1920, 1200}
 442         };
 443
 444         for (i = 0; i < 17; i++) {
 445                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 446                         if (common_modes[i].w > 1024 ||
 447                             common_modes[i].h > 768)
 448                                 continue;
 449                 }
 450                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 451                         if (common_modes[i].w > native_mode->hdisplay ||
 452                             common_modes[i].h > native_mode->vdisplay ||
 453                             (common_modes[i].w == native_mode->hdisplay &&
 454                              common_modes[i].h == native_mode->vdisplay))
 455                                 continue;
 456                 }
 457                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 458                         continue;
 459
 460                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 461                 drm_mode_probed_add(connector, mode);
 462         }
 463 }
 464
 465 static int amdgpu_connector_set_property(struct drm_connector *connector,
 466                                           struct drm_property *property,
 467                                           uint64_t val)
 468 {
 469         struct drm_device *dev = connector->dev;
 470         struct amdgpu_device *adev = drm_to_adev(dev);
 471         struct drm_encoder *encoder;
 472         struct amdgpu_encoder *amdgpu_encoder;
 473
 474         if (property == adev->mode_info.coherent_mode_property) {
 475                 struct amdgpu_encoder_atom_dig *dig;
 476                 bool new_coherent_mode;
 477
 478                 /* need to find digital encoder on connector */
 479                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 480                 if (!encoder)
 481                         return 0;
 482
 483                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 484
 485                 if (!amdgpu_encoder->enc_priv)
 486                         return 0;
 487
 488                 dig = amdgpu_encoder->enc_priv;
 489                 new_coherent_mode = val ? true : false;
 490                 if (dig->coherent_mode != new_coherent_mode) {
 491                         dig->coherent_mode = new_coherent_mode;
 492                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 493                 }
 494         }
 495
 496         if (property == adev->mode_info.audio_property) {
 497                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 498                 /* need to find digital encoder on connector */
 499                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 500                 if (!encoder)
 501                         return 0;
 502
 503                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 504
 505                 if (amdgpu_connector->audio != val) {
 506                         amdgpu_connector->audio = val;
 507                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 508                 }
 509         }
 510
 511         if (property == adev->mode_info.dither_property) {
 512                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 513                 /* need to find digital encoder on connector */
 514                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 515                 if (!encoder)
 516                         return 0;
 517
 518                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 519
 520                 if (amdgpu_connector->dither != val) {
 521                         amdgpu_connector->dither = val;
 522                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 523                 }
 524         }
 525
 526         if (property == adev->mode_info.underscan_property) {
 527                 /* need to find digital encoder on connector */
 528                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 529                 if (!encoder)
 530                         return 0;
 531
 532                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 533
 534                 if (amdgpu_encoder->underscan_type != val) {
 535                         amdgpu_encoder->underscan_type = val;
 536                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 537                 }
 538         }
 539
 540         if (property == adev->mode_info.underscan_hborder_property) {
 541                 /* need to find digital encoder on connector */
 542                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 543                 if (!encoder)
 544                         return 0;
 545
 546                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 547
 548                 if (amdgpu_encoder->underscan_hborder != val) {
 549                         amdgpu_encoder->underscan_hborder = val;
 550                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 551                 }
 552         }
 553
 554         if (property == adev->mode_info.underscan_vborder_property) {
 555                 /* need to find digital encoder on connector */
 556                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 557                 if (!encoder)
 558                         return 0;
 559
 560                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 561
 562                 if (amdgpu_encoder->underscan_vborder != val) {
 563                         amdgpu_encoder->underscan_vborder = val;
 564                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 565                 }
 566         }
 567
 568         if (property == adev->mode_info.load_detect_property) {
 569                 struct amdgpu_connector *amdgpu_connector =
 570                         to_amdgpu_connector(connector);
 571
 572                 if (val == 0)
 573                         amdgpu_connector->dac_load_detect = false;
 574                 else
 575                         amdgpu_connector->dac_load_detect = true;
 576         }
 577
 578         if (property == dev->mode_config.scaling_mode_property) {
 579                 enum amdgpu_rmx_type rmx_type;
 580
 581                 if (connector->encoder) {
 582                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 583                 } else {
 584                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 585
 586                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 587                 }
 588
 589                 switch (val) {
 590                 default:
 591                 case DRM_MODE_SCALE_NONE:
 592                         rmx_type = RMX_OFF;
 593                         break;
 594                 case DRM_MODE_SCALE_CENTER:
 595                         rmx_type = RMX_CENTER;
 596                         break;
 597                 case DRM_MODE_SCALE_ASPECT:
 598                         rmx_type = RMX_ASPECT;
 599                         break;
 600                 case DRM_MODE_SCALE_FULLSCREEN:
 601                         rmx_type = RMX_FULL;
 602                         break;
 603                 }
 604
 605                 if (amdgpu_encoder->rmx_type == rmx_type)
 606                         return 0;
 607
 608                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 609                     (amdgpu_encoder->native_mode.clock == 0))
 610                         return 0;
 611
 612                 amdgpu_encoder->rmx_type = rmx_type;
 613
 614                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 615         }
 616
 617         return 0;
 618 }
 619
 620 static void
 621 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 622                                         struct drm_connector *connector)
 623 {
 624         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 625         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 626         struct drm_display_mode *t, *mode;
 627
 628         /* If the EDID preferred mode doesn't match the native mode, use it */
 629         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 630                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 631                         if (mode->hdisplay != native_mode->hdisplay ||
 632                             mode->vdisplay != native_mode->vdisplay)
 633                                 drm_mode_copy(native_mode, mode);
 634                 }
 635         }
 636
 637         /* Try to get native mode details from EDID if necessary */
 638         if (!native_mode->clock) {
 639                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 640                         if (mode->hdisplay == native_mode->hdisplay &&
 641                             mode->vdisplay == native_mode->vdisplay) {
 642                                 drm_mode_copy(native_mode, mode);
 643                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 644                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 645                                 break;
 646                         }
 647                 }
 648         }
 649
 650         if (!native_mode->clock) {
 651                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 652                 amdgpu_encoder->rmx_type = RMX_OFF;
 653         }
 654 }
 655
 656 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 657 {
 658         struct drm_encoder *encoder;
 659         int ret = 0;
 660         struct drm_display_mode *mode;
 661
 662         amdgpu_connector_get_edid(connector);
 663         ret = amdgpu_connector_ddc_get_modes(connector);
 664         if (ret > 0) {
 665                 encoder = amdgpu_connector_best_single_encoder(connector);
 666                 if (encoder) {
 667                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 668                         /* add scaled modes */
 669                         amdgpu_connector_add_common_modes(encoder, connector);
 670                 }
 671                 return ret;
 672         }
 673
 674         encoder = amdgpu_connector_best_single_encoder(connector);
 675         if (!encoder)
 676                 return 0;
 677
 678         /* we have no EDID modes */
 679         mode = amdgpu_connector_lcd_native_mode(encoder);
 680         if (mode) {
 681                 ret = 1;
 682                 drm_mode_probed_add(connector, mode);
 683                 /* add the width/height from vbios tables if available */
 684                 connector->display_info.width_mm = mode->width_mm;
 685                 connector->display_info.height_mm = mode->height_mm;
 686                 /* add scaled modes */
 687                 amdgpu_connector_add_common_modes(encoder, connector);
 688         }
 689
 690         return ret;
 691 }
 692
 693 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 694                                              struct drm_display_mode *mode)
 695 {
 696         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 697
 698         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 699                 return MODE_PANEL;
 700
 701         if (encoder) {
 702                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 703                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 704
 705                 /* AVIVO hardware supports downscaling modes larger than the panel
 706                  * to the panel size, but I'm not sure this is desirable.
 707                  */
 708                 if ((mode->hdisplay > native_mode->hdisplay) ||
 709                     (mode->vdisplay > native_mode->vdisplay))
 710                         return MODE_PANEL;
 711
 712                 /* if scaling is disabled, block non-native modes */
 713                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 714                         if ((mode->hdisplay != native_mode->hdisplay) ||
 715                             (mode->vdisplay != native_mode->vdisplay))
 716                                 return MODE_PANEL;
 717                 }
 718         }
 719
 720         return MODE_OK;
 721 }
 722
 723 static enum drm_connector_status
 724 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 725 {
 726         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 727         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 728         enum drm_connector_status ret = connector_status_disconnected;
 729         int r;
 730
 731         if (!drm_kms_helper_is_poll_worker()) {
 732                 r = pm_runtime_get_sync(connector->dev->dev);
 733                 if (r < 0) {
 734                         pm_runtime_put_autosuspend(connector->dev->dev);
 735                         return connector_status_disconnected;
 736                 }
 737         }
 738
 739         if (encoder) {
 740                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 741                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 742
 743                 /* check if panel is valid */
 744                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 745                         ret = connector_status_connected;
 746
 747         }
 748
 749         /* check for edid as well */
 750         amdgpu_connector_get_edid(connector);
 751         if (amdgpu_connector->edid)
 752                 ret = connector_status_connected;
 753         /* check acpi lid status ??? */
 754
 755         amdgpu_connector_update_scratch_regs(connector, ret);
 756
 757         if (!drm_kms_helper_is_poll_worker()) {
 758                 pm_runtime_mark_last_busy(connector->dev->dev);
 759                 pm_runtime_put_autosuspend(connector->dev->dev);
 760         }
 761
 762         return ret;
 763 }
 764
 765 static void amdgpu_connector_unregister(struct drm_connector *connector)
 766 {
 767         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 768
 769         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 770                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 771                 amdgpu_connector->ddc_bus->has_aux = false;
 772         }
 773 }
 774
 775 static void amdgpu_connector_destroy(struct drm_connector *connector)
 776 {
 777         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 778
 779         amdgpu_connector_free_edid(connector);
 780         kfree(amdgpu_connector->con_priv);
 781         drm_connector_unregister(connector);
 782         drm_connector_cleanup(connector);
 783         kfree(connector);
 784 }
 785
 786 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 787                                               struct drm_property *property,
 788                                               uint64_t value)
 789 {
 790         struct drm_device *dev = connector->dev;
 791         struct amdgpu_encoder *amdgpu_encoder;
 792         enum amdgpu_rmx_type rmx_type;
 793
 794         DRM_DEBUG_KMS("\n");
 795         if (property != dev->mode_config.scaling_mode_property)
 796                 return 0;
 797
 798         if (connector->encoder)
 799                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 800         else {
 801                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 802
 803                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 804         }
 805
 806         switch (value) {
 807         case DRM_MODE_SCALE_NONE:
 808                 rmx_type = RMX_OFF;
 809                 break;
 810         case DRM_MODE_SCALE_CENTER:
 811                 rmx_type = RMX_CENTER;
 812                 break;
 813         case DRM_MODE_SCALE_ASPECT:
 814                 rmx_type = RMX_ASPECT;
 815                 break;
 816         default:
 817         case DRM_MODE_SCALE_FULLSCREEN:
 818                 rmx_type = RMX_FULL;
 819                 break;
 820         }
 821
 822         if (amdgpu_encoder->rmx_type == rmx_type)
 823                 return 0;
 824
 825         amdgpu_encoder->rmx_type = rmx_type;
 826
 827         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 828         return 0;
 829 }
 830
 831
 832 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 833         .get_modes = amdgpu_connector_lvds_get_modes,
 834         .mode_valid = amdgpu_connector_lvds_mode_valid,
 835         .best_encoder = amdgpu_connector_best_single_encoder,
 836 };
 837
 838 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 839         .dpms = drm_helper_connector_dpms,
 840         .detect = amdgpu_connector_lvds_detect,
 841         .fill_modes = drm_helper_probe_single_connector_modes,
 842         .early_unregister = amdgpu_connector_unregister,
 843         .destroy = amdgpu_connector_destroy,
 844         .set_property = amdgpu_connector_set_lcd_property,
 845 };
 846
 847 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 848 {
 849         int ret;
 850
 851         amdgpu_connector_get_edid(connector);
 852         ret = amdgpu_connector_ddc_get_modes(connector);
 853         amdgpu_get_native_mode(connector);
 854
 855         return ret;
 856 }
 857
 858 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 859                                             struct drm_display_mode *mode)
 860 {
 861         struct drm_device *dev = connector->dev;
 862         struct amdgpu_device *adev = drm_to_adev(dev);
 863
 864         /* XXX check mode bandwidth */
 865
 866         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 867                 return MODE_CLOCK_HIGH;
 868
 869         return MODE_OK;
 870 }
 871
 872 static enum drm_connector_status
 873 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 874 {
 875         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 876         struct drm_encoder *encoder;
 877         const struct drm_encoder_helper_funcs *encoder_funcs;
 878         bool dret = false;
 879         enum drm_connector_status ret = connector_status_disconnected;
 880         int r;
 881
 882         if (!drm_kms_helper_is_poll_worker()) {
 883                 r = pm_runtime_get_sync(connector->dev->dev);
 884                 if (r < 0) {
 885                         pm_runtime_put_autosuspend(connector->dev->dev);
 886                         return connector_status_disconnected;
 887                 }
 888         }
 889
 890         encoder = amdgpu_connector_best_single_encoder(connector);
 891         if (!encoder)
 892                 ret = connector_status_disconnected;
 893
 894         if (amdgpu_connector->ddc_bus)
 895                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 896         if (dret) {
 897                 amdgpu_connector->detected_by_load = false;
 898                 amdgpu_connector_free_edid(connector);
 899                 amdgpu_connector_get_edid(connector);
 900
 901                 if (!amdgpu_connector->edid) {
 902                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 903                                         connector->name);
 904                         ret = connector_status_connected;
 905                 } else {
 906                         amdgpu_connector->use_digital =
 907                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 908
 909                         /* some oems have boards with separate digital and analog connectors
 910                          * with a shared ddc line (often vga + hdmi)
 911                          */
 912                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 913                                 amdgpu_connector_free_edid(connector);
 914                                 ret = connector_status_disconnected;
 915                         } else {
 916                                 ret = connector_status_connected;
 917                         }
 918                 }
 919         } else {
 920
 921                 /* if we aren't forcing don't do destructive polling */
 922                 if (!force) {
 923                         /* only return the previous status if we last
 924                          * detected a monitor via load.
 925                          */
 926                         if (amdgpu_connector->detected_by_load)
 927                                 ret = connector->status;
 928                         goto out;
 929                 }
 930
 931                 if (amdgpu_connector->dac_load_detect && encoder) {
 932                         encoder_funcs = encoder->helper_private;
 933                         ret = encoder_funcs->detect(encoder, connector);
 934                         if (ret != connector_status_disconnected)
 935                                 amdgpu_connector->detected_by_load = true;
 936                 }
 937         }
 938
 939         amdgpu_connector_update_scratch_regs(connector, ret);
 940
 941 out:
 942         if (!drm_kms_helper_is_poll_worker()) {
 943                 pm_runtime_mark_last_busy(connector->dev->dev);
 944                 pm_runtime_put_autosuspend(connector->dev->dev);
 945         }
 946
 947         return ret;
 948 }
 949
 950 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 951         .get_modes = amdgpu_connector_vga_get_modes,
 952         .mode_valid = amdgpu_connector_vga_mode_valid,
 953         .best_encoder = amdgpu_connector_best_single_encoder,
 954 };
 955
 956 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 957         .dpms = drm_helper_connector_dpms,
 958         .detect = amdgpu_connector_vga_detect,
 959         .fill_modes = drm_helper_probe_single_connector_modes,
 960         .early_unregister = amdgpu_connector_unregister,
 961         .destroy = amdgpu_connector_destroy,
 962         .set_property = amdgpu_connector_set_property,
 963 };
 964
 965 static bool
 966 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 967 {
 968         struct drm_device *dev = connector->dev;
 969         struct amdgpu_device *adev = drm_to_adev(dev);
 970         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 971         enum drm_connector_status status;
 972
 973         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 974                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 975                         status = connector_status_connected;
 976                 else
 977                         status = connector_status_disconnected;
 978                 if (connector->status == status)
 979                         return true;
 980         }
 981
 982         return false;
 983 }
 984
 985 static void amdgpu_connector_shared_ddc(enum drm_connector_status *status,
 986                                         struct drm_connector *connector,
 987                                         struct amdgpu_connector *amdgpu_connector)
 988 {
 989         struct drm_connector *list_connector;
 990         struct drm_connector_list_iter iter;
 991         struct amdgpu_connector *list_amdgpu_connector;
 992         struct drm_device *dev = connector->dev;
 993         struct amdgpu_device *adev = drm_to_adev(dev);
 994
 995         if (amdgpu_connector->shared_ddc && *status == connector_status_connected) {
 996                 drm_connector_list_iter_begin(dev, &iter);
 997                 drm_for_each_connector_iter(list_connector,
 998                                             &iter) {
 999                         if (connector == list_connector)
1000                                 continue;
1001                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1002                         if (list_amdgpu_connector->shared_ddc &&
1003                             list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1004                              amdgpu_connector->ddc_bus->rec.i2c_id) {
1005                                 /* cases where both connectors are digital */
1006                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1007                                         /* hpd is our only option in this case */
1008                                         if (!amdgpu_display_hpd_sense(adev,
1009                                                                       amdgpu_connector->hpd.hpd)) {
1010                                                 amdgpu_connector_free_edid(connector);
1011                                                 *status = connector_status_disconnected;
1012                                         }
1013                                 }
1014                         }
1015                 }
1016                 drm_connector_list_iter_end(&iter);
1017         }
1018 }
1019
1020 /*
1021  * DVI is complicated
1022  * Do a DDC probe, if DDC probe passes, get the full EDID so
1023  * we can do analog/digital monitor detection at this point.
1024  * If the monitor is an analog monitor or we got no DDC,
1025  * we need to find the DAC encoder object for this connector.
1026  * If we got no DDC, we do load detection on the DAC encoder object.
1027  * If we got analog DDC or load detection passes on the DAC encoder
1028  * we have to check if this analog encoder is shared with anyone else (TV)
1029  * if its shared we have to set the other connector to disconnected.
1030  */
1031 static enum drm_connector_status
1032 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
1033 {
1034         struct drm_device *dev = connector->dev;
1035         struct amdgpu_device *adev = drm_to_adev(dev);
1036         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1037         const struct drm_encoder_helper_funcs *encoder_funcs;
1038         int r;
1039         enum drm_connector_status ret = connector_status_disconnected;
1040         bool dret = false, broken_edid = false;
1041
1042         if (!drm_kms_helper_is_poll_worker()) {
1043                 r = pm_runtime_get_sync(connector->dev->dev);
1044                 if (r < 0) {
1045                         pm_runtime_put_autosuspend(connector->dev->dev);
1046                         return connector_status_disconnected;
1047                 }
1048         }
1049
1050         if (amdgpu_connector->detected_hpd_without_ddc) {
1051                 force = true;
1052                 amdgpu_connector->detected_hpd_without_ddc = false;
1053         }
1054
1055         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1056                 ret = connector->status;
1057                 goto exit;
1058         }
1059
1060         if (amdgpu_connector->ddc_bus) {
1061                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1062
1063                 /* Sometimes the pins required for the DDC probe on DVI
1064                  * connectors don't make contact at the same time that the ones
1065                  * for HPD do. If the DDC probe fails even though we had an HPD
1066                  * signal, try again later
1067                  */
1068                 if (!dret && !force &&
1069                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1070                         DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1071                         amdgpu_connector->detected_hpd_without_ddc = true;
1072                         schedule_delayed_work(&adev->hotplug_work,
1073                                               msecs_to_jiffies(1000));
1074                         goto exit;
1075                 }
1076         }
1077         if (dret) {
1078                 amdgpu_connector->detected_by_load = false;
1079                 amdgpu_connector_free_edid(connector);
1080                 amdgpu_connector_get_edid(connector);
1081
1082                 if (!amdgpu_connector->edid) {
1083                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1084                                         connector->name);
1085                         ret = connector_status_connected;
1086                         broken_edid = true; /* defer use_digital to later */
1087                 } else {
1088                         amdgpu_connector->use_digital =
1089                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1090
1091                         /* some oems have boards with separate digital and analog connectors
1092                          * with a shared ddc line (often vga + hdmi)
1093                          */
1094                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1095                                 amdgpu_connector_free_edid(connector);
1096                                 ret = connector_status_disconnected;
1097                         } else {
1098                                 ret = connector_status_connected;
1099                         }
1100
1101                         /* This gets complicated.  We have boards with VGA + HDMI with a
1102                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1103                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1104                          * you don't really know what's connected to which port as both are digital.
1105                          */
1106                         amdgpu_connector_shared_ddc(&ret, connector, amdgpu_connector);
1107                 }
1108         }
1109
1110         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1111                 goto out;
1112
1113         /* DVI-D and HDMI-A are digital only */
1114         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1115             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1116                 goto out;
1117
1118         /* if we aren't forcing don't do destructive polling */
1119         if (!force) {
1120                 /* only return the previous status if we last
1121                  * detected a monitor via load.
1122                  */
1123                 if (amdgpu_connector->detected_by_load)
1124                         ret = connector->status;
1125                 goto out;
1126         }
1127
1128         /* find analog encoder */
1129         if (amdgpu_connector->dac_load_detect) {
1130                 struct drm_encoder *encoder;
1131
1132                 drm_connector_for_each_possible_encoder(connector, encoder) {
1133                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1134                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1135                                 continue;
1136
1137                         encoder_funcs = encoder->helper_private;
1138                         if (encoder_funcs->detect) {
1139                                 if (!broken_edid) {
1140                                         if (ret != connector_status_connected) {
1141                                                 /* deal with analog monitors without DDC */
1142                                                 ret = encoder_funcs->detect(encoder, connector);
1143                                                 if (ret == connector_status_connected) {
1144                                                         amdgpu_connector->use_digital = false;
1145                                                 }
1146                                                 if (ret != connector_status_disconnected)
1147                                                         amdgpu_connector->detected_by_load = true;
1148                                         }
1149                                 } else {
1150                                         enum drm_connector_status lret;
1151                                         /* assume digital unless load detected otherwise */
1152                                         amdgpu_connector->use_digital = true;
1153                                         lret = encoder_funcs->detect(encoder, connector);
1154                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",
1155                                                       encoder->encoder_type, lret);
1156                                         if (lret == connector_status_connected)
1157                                                 amdgpu_connector->use_digital = false;
1158                                 }
1159                                 break;
1160                         }
1161                 }
1162         }
1163
1164 out:
1165         /* updated in get modes as well since we need to know if it's analog or digital */
1166         amdgpu_connector_update_scratch_regs(connector, ret);
1167
1168 exit:
1169         if (!drm_kms_helper_is_poll_worker()) {
1170                 pm_runtime_mark_last_busy(connector->dev->dev);
1171                 pm_runtime_put_autosuspend(connector->dev->dev);
1172         }
1173
1174         return ret;
1175 }
1176
1177 /* okay need to be smart in here about which encoder to pick */
1178 static struct drm_encoder *
1179 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1180 {
1181         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1182         struct drm_encoder *encoder;
1183
1184         drm_connector_for_each_possible_encoder(connector, encoder) {
1185                 if (amdgpu_connector->use_digital == true) {
1186                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1187                                 return encoder;
1188                 } else {
1189                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1190                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1191                                 return encoder;
1192                 }
1193         }
1194
1195         /* see if we have a default encoder  TODO */
1196
1197         /* then check use digitial */
1198         /* pick the first one */
1199         drm_connector_for_each_possible_encoder(connector, encoder)
1200                 return encoder;
1201
1202         return NULL;
1203 }
1204
1205 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1206 {
1207         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1208
1209         if (connector->force == DRM_FORCE_ON)
1210                 amdgpu_connector->use_digital = false;
1211         if (connector->force == DRM_FORCE_ON_DIGITAL)
1212                 amdgpu_connector->use_digital = true;
1213 }
1214
1215 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1216                                             struct drm_display_mode *mode)
1217 {
1218         struct drm_device *dev = connector->dev;
1219         struct amdgpu_device *adev = drm_to_adev(dev);
1220         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1221
1222         /* XXX check mode bandwidth */
1223
1224         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1225                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1226                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1227                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1228                         return MODE_OK;
1229                 } else if (connector->display_info.is_hdmi) {
1230                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1231                         if (mode->clock > 340000)
1232                                 return MODE_CLOCK_HIGH;
1233                         else
1234                                 return MODE_OK;
1235                 } else {
1236                         return MODE_CLOCK_HIGH;
1237                 }
1238         }
1239
1240         /* check against the max pixel clock */
1241         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1242                 return MODE_CLOCK_HIGH;
1243
1244         return MODE_OK;
1245 }
1246
1247 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1248         .get_modes = amdgpu_connector_vga_get_modes,
1249         .mode_valid = amdgpu_connector_dvi_mode_valid,
1250         .best_encoder = amdgpu_connector_dvi_encoder,
1251 };
1252
1253 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1254         .dpms = drm_helper_connector_dpms,
1255         .detect = amdgpu_connector_dvi_detect,
1256         .fill_modes = drm_helper_probe_single_connector_modes,
1257         .set_property = amdgpu_connector_set_property,
1258         .early_unregister = amdgpu_connector_unregister,
1259         .destroy = amdgpu_connector_destroy,
1260         .force = amdgpu_connector_dvi_force,
1261 };
1262
1263 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1264 {
1265         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1266         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1267         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1268         int ret;
1269
1270         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1271             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1272                 struct drm_display_mode *mode;
1273
1274                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1275                         if (!amdgpu_dig_connector->edp_on)
1276                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1277                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1278                         amdgpu_connector_get_edid(connector);
1279                         ret = amdgpu_connector_ddc_get_modes(connector);
1280                         if (!amdgpu_dig_connector->edp_on)
1281                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1282                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1283                 } else {
1284                         /* need to setup ddc on the bridge */
1285                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1286                             ENCODER_OBJECT_ID_NONE) {
1287                                 if (encoder)
1288                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1289                         }
1290                         amdgpu_connector_get_edid(connector);
1291                         ret = amdgpu_connector_ddc_get_modes(connector);
1292                 }
1293
1294                 if (ret > 0) {
1295                         if (encoder) {
1296                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1297                                 /* add scaled modes */
1298                                 amdgpu_connector_add_common_modes(encoder, connector);
1299                         }
1300                         return ret;
1301                 }
1302
1303                 if (!encoder)
1304                         return 0;
1305
1306                 /* we have no EDID modes */
1307                 mode = amdgpu_connector_lcd_native_mode(encoder);
1308                 if (mode) {
1309                         ret = 1;
1310                         drm_mode_probed_add(connector, mode);
1311                         /* add the width/height from vbios tables if available */
1312                         connector->display_info.width_mm = mode->width_mm;
1313                         connector->display_info.height_mm = mode->height_mm;
1314                         /* add scaled modes */
1315                         amdgpu_connector_add_common_modes(encoder, connector);
1316                 }
1317         } else {
1318                 /* need to setup ddc on the bridge */
1319                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1320                         ENCODER_OBJECT_ID_NONE) {
1321                         if (encoder)
1322                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1323                 }
1324                 amdgpu_connector_get_edid(connector);
1325                 ret = amdgpu_connector_ddc_get_modes(connector);
1326
1327                 amdgpu_get_native_mode(connector);
1328         }
1329
1330         return ret;
1331 }
1332
1333 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1334 {
1335         struct drm_encoder *encoder;
1336         struct amdgpu_encoder *amdgpu_encoder;
1337
1338         drm_connector_for_each_possible_encoder(connector, encoder) {
1339                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1340
1341                 switch (amdgpu_encoder->encoder_id) {
1342                 case ENCODER_OBJECT_ID_TRAVIS:
1343                 case ENCODER_OBJECT_ID_NUTMEG:
1344                         return amdgpu_encoder->encoder_id;
1345                 default:
1346                         break;
1347                 }
1348         }
1349
1350         return ENCODER_OBJECT_ID_NONE;
1351 }
1352
1353 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1354 {
1355         struct drm_encoder *encoder;
1356         struct amdgpu_encoder *amdgpu_encoder;
1357         bool found = false;
1358
1359         drm_connector_for_each_possible_encoder(connector, encoder) {
1360                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1361                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1362                         found = true;
1363         }
1364
1365         return found;
1366 }
1367
1368 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1369 {
1370         struct drm_device *dev = connector->dev;
1371         struct amdgpu_device *adev = drm_to_adev(dev);
1372
1373         if ((adev->clock.default_dispclk >= 53900) &&
1374             amdgpu_connector_encoder_is_hbr2(connector)) {
1375                 return true;
1376         }
1377
1378         return false;
1379 }
1380
1381 static enum drm_connector_status
1382 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1383 {
1384         struct drm_device *dev = connector->dev;
1385         struct amdgpu_device *adev = drm_to_adev(dev);
1386         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1387         enum drm_connector_status ret = connector_status_disconnected;
1388         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1389         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1390         int r;
1391
1392         if (!drm_kms_helper_is_poll_worker()) {
1393                 r = pm_runtime_get_sync(connector->dev->dev);
1394                 if (r < 0) {
1395                         pm_runtime_put_autosuspend(connector->dev->dev);
1396                         return connector_status_disconnected;
1397                 }
1398         }
1399
1400         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1401                 ret = connector->status;
1402                 goto out;
1403         }
1404
1405         amdgpu_connector_free_edid(connector);
1406
1407         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1408             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1409                 if (encoder) {
1410                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1411                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1412
1413                         /* check if panel is valid */
1414                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1415                                 ret = connector_status_connected;
1416                 }
1417                 /* eDP is always DP */
1418                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1419                 if (!amdgpu_dig_connector->edp_on)
1420                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1421                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1422                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1423                         ret = connector_status_connected;
1424                 if (!amdgpu_dig_connector->edp_on)
1425                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1426                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1427         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1428                    ENCODER_OBJECT_ID_NONE) {
1429                 /* DP bridges are always DP */
1430                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1431                 /* get the DPCD from the bridge */
1432                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1433
1434                 if (encoder) {
1435                         /* setup ddc on the bridge */
1436                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1437                         /* bridge chips are always aux */
1438                         /* try DDC */
1439                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1440                                 ret = connector_status_connected;
1441                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1442                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1443
1444                                 ret = encoder_funcs->detect(encoder, connector);
1445                         }
1446                 }
1447         } else {
1448                 amdgpu_dig_connector->dp_sink_type =
1449                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1450                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1451                         ret = connector_status_connected;
1452                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1453                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1454                 } else {
1455                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1456                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1457                                         ret = connector_status_connected;
1458                         } else {
1459                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1460                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1461                                                              false))
1462                                         ret = connector_status_connected;
1463                         }
1464                 }
1465         }
1466
1467         amdgpu_connector_update_scratch_regs(connector, ret);
1468 out:
1469         if (!drm_kms_helper_is_poll_worker()) {
1470                 pm_runtime_mark_last_busy(connector->dev->dev);
1471                 pm_runtime_put_autosuspend(connector->dev->dev);
1472         }
1473
1474         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
1475             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1476                 drm_dp_set_subconnector_property(&amdgpu_connector->base,
1477                                                  ret,
1478                                                  amdgpu_dig_connector->dpcd,
1479                                                  amdgpu_dig_connector->downstream_ports);
1480         return ret;
1481 }
1482
1483 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1484                                            struct drm_display_mode *mode)
1485 {
1486         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1487         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1488
1489         /* XXX check mode bandwidth */
1490
1491         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1492             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1493                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1494
1495                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1496                         return MODE_PANEL;
1497
1498                 if (encoder) {
1499                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1500                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1501
1502                         /* AVIVO hardware supports downscaling modes larger than the panel
1503                          * to the panel size, but I'm not sure this is desirable.
1504                          */
1505                         if ((mode->hdisplay > native_mode->hdisplay) ||
1506                             (mode->vdisplay > native_mode->vdisplay))
1507                                 return MODE_PANEL;
1508
1509                         /* if scaling is disabled, block non-native modes */
1510                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1511                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1512                                     (mode->vdisplay != native_mode->vdisplay))
1513                                         return MODE_PANEL;
1514                         }
1515                 }
1516                 return MODE_OK;
1517         } else {
1518                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1519                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1520                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1521                 } else {
1522                         if (connector->display_info.is_hdmi) {
1523                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1524                                 if (mode->clock > 340000)
1525                                         return MODE_CLOCK_HIGH;
1526                         } else {
1527                                 if (mode->clock > 165000)
1528                                         return MODE_CLOCK_HIGH;
1529                         }
1530                 }
1531         }
1532
1533         return MODE_OK;
1534 }
1535
1536 static int
1537 amdgpu_connector_late_register(struct drm_connector *connector)
1538 {
1539         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1540         int r = 0;
1541
1542         if (amdgpu_connector->ddc_bus->has_aux) {
1543                 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
1544                 r = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
1545         }
1546
1547         return r;
1548 }
1549
1550 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1551         .get_modes = amdgpu_connector_dp_get_modes,
1552         .mode_valid = amdgpu_connector_dp_mode_valid,
1553         .best_encoder = amdgpu_connector_dvi_encoder,
1554 };
1555
1556 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1557         .dpms = drm_helper_connector_dpms,
1558         .detect = amdgpu_connector_dp_detect,
1559         .fill_modes = drm_helper_probe_single_connector_modes,
1560         .set_property = amdgpu_connector_set_property,
1561         .early_unregister = amdgpu_connector_unregister,
1562         .destroy = amdgpu_connector_destroy,
1563         .force = amdgpu_connector_dvi_force,
1564         .late_register = amdgpu_connector_late_register,
1565 };
1566
1567 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1568         .dpms = drm_helper_connector_dpms,
1569         .detect = amdgpu_connector_dp_detect,
1570         .fill_modes = drm_helper_probe_single_connector_modes,
1571         .set_property = amdgpu_connector_set_lcd_property,
1572         .early_unregister = amdgpu_connector_unregister,
1573         .destroy = amdgpu_connector_destroy,
1574         .force = amdgpu_connector_dvi_force,
1575         .late_register = amdgpu_connector_late_register,
1576 };
1577
1578 void
1579 amdgpu_connector_add(struct amdgpu_device *adev,
1580                       uint32_t connector_id,
1581                       uint32_t supported_device,
1582                       int connector_type,
1583                       struct amdgpu_i2c_bus_rec *i2c_bus,
1584                       uint16_t connector_object_id,
1585                       struct amdgpu_hpd *hpd,
1586                       struct amdgpu_router *router)
1587 {
1588         struct drm_device *dev = adev_to_drm(adev);
1589         struct drm_connector *connector;
1590         struct drm_connector_list_iter iter;
1591         struct amdgpu_connector *amdgpu_connector;
1592         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1593         struct drm_encoder *encoder;
1594         struct amdgpu_encoder *amdgpu_encoder;
1595         struct i2c_adapter *ddc = NULL;
1596         uint32_t subpixel_order = SubPixelNone;
1597         bool shared_ddc = false;
1598         bool is_dp_bridge = false;
1599         bool has_aux = false;
1600
1601         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1602                 return;
1603
1604         /* see if we already added it */
1605         drm_connector_list_iter_begin(dev, &iter);
1606         drm_for_each_connector_iter(connector, &iter) {
1607                 amdgpu_connector = to_amdgpu_connector(connector);
1608                 if (amdgpu_connector->connector_id == connector_id) {
1609                         amdgpu_connector->devices |= supported_device;
1610                         drm_connector_list_iter_end(&iter);
1611                         return;
1612                 }
1613                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1614                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1615                                 amdgpu_connector->shared_ddc = true;
1616                                 shared_ddc = true;
1617                         }
1618                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1619                             (amdgpu_connector->router.router_id == router->router_id)) {
1620                                 amdgpu_connector->shared_ddc = false;
1621                                 shared_ddc = false;
1622                         }
1623                 }
1624         }
1625         drm_connector_list_iter_end(&iter);
1626
1627         /* check if it's a dp bridge */
1628         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1629                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1630                 if (amdgpu_encoder->devices & supported_device) {
1631                         switch (amdgpu_encoder->encoder_id) {
1632                         case ENCODER_OBJECT_ID_TRAVIS:
1633                         case ENCODER_OBJECT_ID_NUTMEG:
1634                                 is_dp_bridge = true;
1635                                 break;
1636                         default:
1637                                 break;
1638                         }
1639                 }
1640         }
1641
1642         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1643         if (!amdgpu_connector)
1644                 return;
1645
1646         connector = &amdgpu_connector->base;
1647
1648         amdgpu_connector->connector_id = connector_id;
1649         amdgpu_connector->devices = supported_device;
1650         amdgpu_connector->shared_ddc = shared_ddc;
1651         amdgpu_connector->connector_object_id = connector_object_id;
1652         amdgpu_connector->hpd = *hpd;
1653
1654         amdgpu_connector->router = *router;
1655         if (router->ddc_valid || router->cd_valid) {
1656                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1657                 if (!amdgpu_connector->router_bus)
1658                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1659         }
1660
1661         if (is_dp_bridge) {
1662                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1663                 if (!amdgpu_dig_connector)
1664                         goto failed;
1665                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1666                 if (i2c_bus->valid) {
1667                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1668                         if (amdgpu_connector->ddc_bus) {
1669                                 has_aux = true;
1670                                 ddc = &amdgpu_connector->ddc_bus->adapter;
1671                         } else {
1672                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1673                         }
1674                 }
1675                 switch (connector_type) {
1676                 case DRM_MODE_CONNECTOR_VGA:
1677                 case DRM_MODE_CONNECTOR_DVIA:
1678                 default:
1679                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1680                                                     &amdgpu_connector_dp_funcs,
1681                                                     connector_type,
1682                                                     ddc);
1683                         drm_connector_helper_add(&amdgpu_connector->base,
1684                                                  &amdgpu_connector_dp_helper_funcs);
1685                         connector->interlace_allowed = true;
1686                         connector->doublescan_allowed = true;
1687                         amdgpu_connector->dac_load_detect = true;
1688                         drm_object_attach_property(&amdgpu_connector->base.base,
1689                                                       adev->mode_info.load_detect_property,
1690                                                       1);
1691                         drm_object_attach_property(&amdgpu_connector->base.base,
1692                                                    dev->mode_config.scaling_mode_property,
1693                                                    DRM_MODE_SCALE_NONE);
1694                         break;
1695                 case DRM_MODE_CONNECTOR_DVII:
1696                 case DRM_MODE_CONNECTOR_DVID:
1697                 case DRM_MODE_CONNECTOR_HDMIA:
1698                 case DRM_MODE_CONNECTOR_HDMIB:
1699                 case DRM_MODE_CONNECTOR_DisplayPort:
1700                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1701                                                     &amdgpu_connector_dp_funcs,
1702                                                     connector_type,
1703                                                     ddc);
1704                         drm_connector_helper_add(&amdgpu_connector->base,
1705                                                  &amdgpu_connector_dp_helper_funcs);
1706                         drm_object_attach_property(&amdgpu_connector->base.base,
1707                                                       adev->mode_info.underscan_property,
1708                                                       UNDERSCAN_OFF);
1709                         drm_object_attach_property(&amdgpu_connector->base.base,
1710                                                       adev->mode_info.underscan_hborder_property,
1711                                                       0);
1712                         drm_object_attach_property(&amdgpu_connector->base.base,
1713                                                       adev->mode_info.underscan_vborder_property,
1714                                                       0);
1715
1716                         drm_object_attach_property(&amdgpu_connector->base.base,
1717                                                    dev->mode_config.scaling_mode_property,
1718                                                    DRM_MODE_SCALE_NONE);
1719
1720                         drm_object_attach_property(&amdgpu_connector->base.base,
1721                                                    adev->mode_info.dither_property,
1722                                                    AMDGPU_FMT_DITHER_DISABLE);
1723
1724                         if (amdgpu_audio != 0) {
1725                                 drm_object_attach_property(&amdgpu_connector->base.base,
1726                                                            adev->mode_info.audio_property,
1727                                                            AMDGPU_AUDIO_AUTO);
1728                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1729                         }
1730
1731                         subpixel_order = SubPixelHorizontalRGB;
1732                         connector->interlace_allowed = true;
1733                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1734                                 connector->doublescan_allowed = true;
1735                         else
1736                                 connector->doublescan_allowed = false;
1737                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1738                                 amdgpu_connector->dac_load_detect = true;
1739                                 drm_object_attach_property(&amdgpu_connector->base.base,
1740                                                               adev->mode_info.load_detect_property,
1741                                                               1);
1742                         }
1743                         break;
1744                 case DRM_MODE_CONNECTOR_LVDS:
1745                 case DRM_MODE_CONNECTOR_eDP:
1746                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1747                                                     &amdgpu_connector_edp_funcs,
1748                                                     connector_type,
1749                                                     ddc);
1750                         drm_connector_helper_add(&amdgpu_connector->base,
1751                                                  &amdgpu_connector_dp_helper_funcs);
1752                         drm_object_attach_property(&amdgpu_connector->base.base,
1753                                                       dev->mode_config.scaling_mode_property,
1754                                                       DRM_MODE_SCALE_FULLSCREEN);
1755                         subpixel_order = SubPixelHorizontalRGB;
1756                         connector->interlace_allowed = false;
1757                         connector->doublescan_allowed = false;
1758                         break;
1759                 }
1760         } else {
1761                 switch (connector_type) {
1762                 case DRM_MODE_CONNECTOR_VGA:
1763                         if (i2c_bus->valid) {
1764                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1765                                 if (!amdgpu_connector->ddc_bus)
1766                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1767                                 else
1768                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1769                         }
1770                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1771                                                     &amdgpu_connector_vga_funcs,
1772                                                     connector_type,
1773                                                     ddc);
1774                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1775                         amdgpu_connector->dac_load_detect = true;
1776                         drm_object_attach_property(&amdgpu_connector->base.base,
1777                                                       adev->mode_info.load_detect_property,
1778                                                       1);
1779                         drm_object_attach_property(&amdgpu_connector->base.base,
1780                                                    dev->mode_config.scaling_mode_property,
1781                                                    DRM_MODE_SCALE_NONE);
1782                         /* no HPD on analog connectors */
1783                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1784                         connector->interlace_allowed = true;
1785                         connector->doublescan_allowed = true;
1786                         break;
1787                 case DRM_MODE_CONNECTOR_DVIA:
1788                         if (i2c_bus->valid) {
1789                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1790                                 if (!amdgpu_connector->ddc_bus)
1791                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1792                                 else
1793                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1794                         }
1795                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1796                                                     &amdgpu_connector_vga_funcs,
1797                                                     connector_type,
1798                                                     ddc);
1799                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1800                         amdgpu_connector->dac_load_detect = true;
1801                         drm_object_attach_property(&amdgpu_connector->base.base,
1802                                                       adev->mode_info.load_detect_property,
1803                                                       1);
1804                         drm_object_attach_property(&amdgpu_connector->base.base,
1805                                                    dev->mode_config.scaling_mode_property,
1806                                                    DRM_MODE_SCALE_NONE);
1807                         /* no HPD on analog connectors */
1808                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1809                         connector->interlace_allowed = true;
1810                         connector->doublescan_allowed = true;
1811                         break;
1812                 case DRM_MODE_CONNECTOR_DVII:
1813                 case DRM_MODE_CONNECTOR_DVID:
1814                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1815                         if (!amdgpu_dig_connector)
1816                                 goto failed;
1817                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1818                         if (i2c_bus->valid) {
1819                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1820                                 if (!amdgpu_connector->ddc_bus)
1821                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1822                                 else
1823                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1824                         }
1825                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1826                                                     &amdgpu_connector_dvi_funcs,
1827                                                     connector_type,
1828                                                     ddc);
1829                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1830                         subpixel_order = SubPixelHorizontalRGB;
1831                         drm_object_attach_property(&amdgpu_connector->base.base,
1832                                                       adev->mode_info.coherent_mode_property,
1833                                                       1);
1834                         drm_object_attach_property(&amdgpu_connector->base.base,
1835                                                    adev->mode_info.underscan_property,
1836                                                    UNDERSCAN_OFF);
1837                         drm_object_attach_property(&amdgpu_connector->base.base,
1838                                                    adev->mode_info.underscan_hborder_property,
1839                                                    0);
1840                         drm_object_attach_property(&amdgpu_connector->base.base,
1841                                                    adev->mode_info.underscan_vborder_property,
1842                                                    0);
1843                         drm_object_attach_property(&amdgpu_connector->base.base,
1844                                                    dev->mode_config.scaling_mode_property,
1845                                                    DRM_MODE_SCALE_NONE);
1846
1847                         if (amdgpu_audio != 0) {
1848                                 drm_object_attach_property(&amdgpu_connector->base.base,
1849                                                            adev->mode_info.audio_property,
1850                                                            AMDGPU_AUDIO_AUTO);
1851                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1852                         }
1853                         drm_object_attach_property(&amdgpu_connector->base.base,
1854                                                    adev->mode_info.dither_property,
1855                                                    AMDGPU_FMT_DITHER_DISABLE);
1856                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1857                                 amdgpu_connector->dac_load_detect = true;
1858                                 drm_object_attach_property(&amdgpu_connector->base.base,
1859                                                            adev->mode_info.load_detect_property,
1860                                                            1);
1861                         }
1862                         connector->interlace_allowed = true;
1863                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1864                                 connector->doublescan_allowed = true;
1865                         else
1866                                 connector->doublescan_allowed = false;
1867                         break;
1868                 case DRM_MODE_CONNECTOR_HDMIA:
1869                 case DRM_MODE_CONNECTOR_HDMIB:
1870                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1871                         if (!amdgpu_dig_connector)
1872                                 goto failed;
1873                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1874                         if (i2c_bus->valid) {
1875                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1876                                 if (!amdgpu_connector->ddc_bus)
1877                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1878                                 else
1879                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1880                         }
1881                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1882                                                     &amdgpu_connector_dvi_funcs,
1883                                                     connector_type,
1884                                                     ddc);
1885                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1886                         drm_object_attach_property(&amdgpu_connector->base.base,
1887                                                       adev->mode_info.coherent_mode_property,
1888                                                       1);
1889                         drm_object_attach_property(&amdgpu_connector->base.base,
1890                                                    adev->mode_info.underscan_property,
1891                                                    UNDERSCAN_OFF);
1892                         drm_object_attach_property(&amdgpu_connector->base.base,
1893                                                    adev->mode_info.underscan_hborder_property,
1894                                                    0);
1895                         drm_object_attach_property(&amdgpu_connector->base.base,
1896                                                    adev->mode_info.underscan_vborder_property,
1897                                                    0);
1898                         drm_object_attach_property(&amdgpu_connector->base.base,
1899                                                    dev->mode_config.scaling_mode_property,
1900                                                    DRM_MODE_SCALE_NONE);
1901                         if (amdgpu_audio != 0) {
1902                                 drm_object_attach_property(&amdgpu_connector->base.base,
1903                                                            adev->mode_info.audio_property,
1904                                                            AMDGPU_AUDIO_AUTO);
1905                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1906                         }
1907                         drm_object_attach_property(&amdgpu_connector->base.base,
1908                                                    adev->mode_info.dither_property,
1909                                                    AMDGPU_FMT_DITHER_DISABLE);
1910                         subpixel_order = SubPixelHorizontalRGB;
1911                         connector->interlace_allowed = true;
1912                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1913                                 connector->doublescan_allowed = true;
1914                         else
1915                                 connector->doublescan_allowed = false;
1916                         break;
1917                 case DRM_MODE_CONNECTOR_DisplayPort:
1918                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1919                         if (!amdgpu_dig_connector)
1920                                 goto failed;
1921                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1922                         if (i2c_bus->valid) {
1923                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1924                                 if (amdgpu_connector->ddc_bus) {
1925                                         has_aux = true;
1926                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1927                                 } else {
1928                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1929                                 }
1930                         }
1931                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1932                                                     &amdgpu_connector_dp_funcs,
1933                                                     connector_type,
1934                                                     ddc);
1935                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1936                         subpixel_order = SubPixelHorizontalRGB;
1937                         drm_object_attach_property(&amdgpu_connector->base.base,
1938                                                       adev->mode_info.coherent_mode_property,
1939                                                       1);
1940                         drm_object_attach_property(&amdgpu_connector->base.base,
1941                                                    adev->mode_info.underscan_property,
1942                                                    UNDERSCAN_OFF);
1943                         drm_object_attach_property(&amdgpu_connector->base.base,
1944                                                    adev->mode_info.underscan_hborder_property,
1945                                                    0);
1946                         drm_object_attach_property(&amdgpu_connector->base.base,
1947                                                    adev->mode_info.underscan_vborder_property,
1948                                                    0);
1949                         drm_object_attach_property(&amdgpu_connector->base.base,
1950                                                    dev->mode_config.scaling_mode_property,
1951                                                    DRM_MODE_SCALE_NONE);
1952                         if (amdgpu_audio != 0) {
1953                                 drm_object_attach_property(&amdgpu_connector->base.base,
1954                                                            adev->mode_info.audio_property,
1955                                                            AMDGPU_AUDIO_AUTO);
1956                                 amdgpu_connector->audio = AMDGPU_AUDIO_AUTO;
1957                         }
1958                         drm_object_attach_property(&amdgpu_connector->base.base,
1959                                                    adev->mode_info.dither_property,
1960                                                    AMDGPU_FMT_DITHER_DISABLE);
1961                         connector->interlace_allowed = true;
1962                         /* in theory with a DP to VGA converter... */
1963                         connector->doublescan_allowed = false;
1964                         break;
1965                 case DRM_MODE_CONNECTOR_eDP:
1966                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1967                         if (!amdgpu_dig_connector)
1968                                 goto failed;
1969                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1970                         if (i2c_bus->valid) {
1971                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1972                                 if (amdgpu_connector->ddc_bus) {
1973                                         has_aux = true;
1974                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1975                                 } else {
1976                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1977                                 }
1978                         }
1979                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1980                                                     &amdgpu_connector_edp_funcs,
1981                                                     connector_type,
1982                                                     ddc);
1983                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1984                         drm_object_attach_property(&amdgpu_connector->base.base,
1985                                                       dev->mode_config.scaling_mode_property,
1986                                                       DRM_MODE_SCALE_FULLSCREEN);
1987                         subpixel_order = SubPixelHorizontalRGB;
1988                         connector->interlace_allowed = false;
1989                         connector->doublescan_allowed = false;
1990                         break;
1991                 case DRM_MODE_CONNECTOR_LVDS:
1992                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1993                         if (!amdgpu_dig_connector)
1994                                 goto failed;
1995                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1996                         if (i2c_bus->valid) {
1997                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1998                                 if (!amdgpu_connector->ddc_bus)
1999                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2000                                 else
2001                                         ddc = &amdgpu_connector->ddc_bus->adapter;
2002                         }
2003                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
2004                                                     &amdgpu_connector_lvds_funcs,
2005                                                     connector_type,
2006                                                     ddc);
2007                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
2008                         drm_object_attach_property(&amdgpu_connector->base.base,
2009                                                       dev->mode_config.scaling_mode_property,
2010                                                       DRM_MODE_SCALE_FULLSCREEN);
2011                         subpixel_order = SubPixelHorizontalRGB;
2012                         connector->interlace_allowed = false;
2013                         connector->doublescan_allowed = false;
2014                         break;
2015                 }
2016         }
2017
2018         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
2019                 if (i2c_bus->valid) {
2020                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2021                                                 DRM_CONNECTOR_POLL_DISCONNECT;
2022                 }
2023         } else
2024                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2025
2026         connector->display_info.subpixel_order = subpixel_order;
2027
2028         if (has_aux)
2029                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
2030
2031         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2032             connector_type == DRM_MODE_CONNECTOR_eDP) {
2033                 drm_connector_attach_dp_subconnector_property(&amdgpu_connector->base);
2034         }
2035
2036         return;
2037
2038 failed:
2039         drm_connector_cleanup(connector);
2040         kfree(connector);
2041 }