drm/connector: Allow max possible encoders to attach to a connector
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_connectors.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26
27 #include <drm/drm_edid.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/drm_probe_helper.h>
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu.h"
32 #include "atom.h"
33 #include "atombios_encoders.h"
34 #include "atombios_dp.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_i2c.h"
37 #include "amdgpu_display.h"
38
39 #include <linux/pm_runtime.h>
40
41 void amdgpu_connector_hotplug(struct drm_connector *connector)
42 {
43         struct drm_device *dev = connector->dev;
44         struct amdgpu_device *adev = dev->dev_private;
45         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
46
47         /* bail if the connector does not have hpd pin, e.g.,
48          * VGA, TV, etc.
49          */
50         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
51                 return;
52
53         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
54
55         /* if the connector is already off, don't turn it back on */
56         if (connector->dpms != DRM_MODE_DPMS_ON)
57                 return;
58
59         /* just deal with DP (not eDP) here. */
60         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
61                 struct amdgpu_connector_atom_dig *dig_connector =
62                         amdgpu_connector->con_priv;
63
64                 /* if existing sink type was not DP no need to retrain */
65                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
66                         return;
67
68                 /* first get sink type as it may be reset after (un)plug */
69                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
70                 /* don't do anything if sink is not display port, i.e.,
71                  * passive dp->(dvi|hdmi) adaptor
72                  */
73                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
74                     amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
75                     amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
76                         /* Don't start link training before we have the DPCD */
77                         if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
78                                 return;
79
80                         /* Turn the connector off and back on immediately, which
81                          * will trigger link training
82                          */
83                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
84                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
85                 }
86         }
87 }
88
89 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
90 {
91         struct drm_crtc *crtc = encoder->crtc;
92
93         if (crtc && crtc->enabled) {
94                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
95                                          crtc->x, crtc->y, crtc->primary->fb);
96         }
97 }
98
99 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
100 {
101         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
102         struct amdgpu_connector_atom_dig *dig_connector;
103         int bpc = 8;
104         unsigned mode_clock, max_tmds_clock;
105
106         switch (connector->connector_type) {
107         case DRM_MODE_CONNECTOR_DVII:
108         case DRM_MODE_CONNECTOR_HDMIB:
109                 if (amdgpu_connector->use_digital) {
110                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
111                                 if (connector->display_info.bpc)
112                                         bpc = connector->display_info.bpc;
113                         }
114                 }
115                 break;
116         case DRM_MODE_CONNECTOR_DVID:
117         case DRM_MODE_CONNECTOR_HDMIA:
118                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
119                         if (connector->display_info.bpc)
120                                 bpc = connector->display_info.bpc;
121                 }
122                 break;
123         case DRM_MODE_CONNECTOR_DisplayPort:
124                 dig_connector = amdgpu_connector->con_priv;
125                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
126                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
127                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
128                         if (connector->display_info.bpc)
129                                 bpc = connector->display_info.bpc;
130                 }
131                 break;
132         case DRM_MODE_CONNECTOR_eDP:
133         case DRM_MODE_CONNECTOR_LVDS:
134                 if (connector->display_info.bpc)
135                         bpc = connector->display_info.bpc;
136                 else {
137                         const struct drm_connector_helper_funcs *connector_funcs =
138                                 connector->helper_private;
139                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
140                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
141                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
142
143                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
144                                 bpc = 6;
145                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
146                                 bpc = 8;
147                 }
148                 break;
149         }
150
151         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
152                 /*
153                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
154                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
155                  * 12 bpc is always supported on hdmi deep color sinks, as this is
156                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
157                  */
158                 if (bpc > 12) {
159                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
160                                   connector->name, bpc);
161                         bpc = 12;
162                 }
163
164                 /* Any defined maximum tmds clock limit we must not exceed? */
165                 if (connector->display_info.max_tmds_clock > 0) {
166                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
167                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
168
169                         /* Maximum allowable input clock in kHz */
170                         max_tmds_clock = connector->display_info.max_tmds_clock;
171
172                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
173                                   connector->name, mode_clock, max_tmds_clock);
174
175                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
176                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
177                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
178                                     (mode_clock * 5/4 <= max_tmds_clock))
179                                         bpc = 10;
180                                 else
181                                         bpc = 8;
182
183                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
184                                           connector->name, bpc);
185                         }
186
187                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
188                                 bpc = 8;
189                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
190                                           connector->name, bpc);
191                         }
192                 } else if (bpc > 8) {
193                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
194                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
195                                   connector->name);
196                         bpc = 8;
197                 }
198         }
199
200         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
201                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
202                           connector->name);
203                 bpc = 8;
204         }
205
206         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
207                   connector->name, connector->display_info.bpc, bpc);
208
209         return bpc;
210 }
211
212 static void
213 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
214                                       enum drm_connector_status status)
215 {
216         struct drm_encoder *best_encoder;
217         struct drm_encoder *encoder;
218         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
219         bool connected;
220
221         best_encoder = connector_funcs->best_encoder(connector);
222
223         drm_connector_for_each_possible_encoder(connector, encoder) {
224                 if ((encoder == best_encoder) && (status == connector_status_connected))
225                         connected = true;
226                 else
227                         connected = false;
228
229                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
230         }
231 }
232
233 static struct drm_encoder *
234 amdgpu_connector_find_encoder(struct drm_connector *connector,
235                                int encoder_type)
236 {
237         struct drm_encoder *encoder;
238
239         drm_connector_for_each_possible_encoder(connector, encoder) {
240                 if (encoder->encoder_type == encoder_type)
241                         return encoder;
242         }
243
244         return NULL;
245 }
246
247 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
248 {
249         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
250         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
251
252         if (amdgpu_connector->edid) {
253                 return amdgpu_connector->edid;
254         } else if (edid_blob) {
255                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
256                 if (edid)
257                         amdgpu_connector->edid = edid;
258         }
259         return amdgpu_connector->edid;
260 }
261
262 static struct edid *
263 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
264 {
265         struct edid *edid;
266
267         if (adev->mode_info.bios_hardcoded_edid) {
268                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
269                 if (edid) {
270                         memcpy((unsigned char *)edid,
271                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
272                                adev->mode_info.bios_hardcoded_edid_size);
273                         return edid;
274                 }
275         }
276         return NULL;
277 }
278
279 static void amdgpu_connector_get_edid(struct drm_connector *connector)
280 {
281         struct drm_device *dev = connector->dev;
282         struct amdgpu_device *adev = dev->dev_private;
283         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
284
285         if (amdgpu_connector->edid)
286                 return;
287
288         /* on hw with routers, select right port */
289         if (amdgpu_connector->router.ddc_valid)
290                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
291
292         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
293              ENCODER_OBJECT_ID_NONE) &&
294             amdgpu_connector->ddc_bus->has_aux) {
295                 amdgpu_connector->edid = drm_get_edid(connector,
296                                                       &amdgpu_connector->ddc_bus->aux.ddc);
297         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
298                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
299                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
300
301                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
302                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
303                     amdgpu_connector->ddc_bus->has_aux)
304                         amdgpu_connector->edid = drm_get_edid(connector,
305                                                               &amdgpu_connector->ddc_bus->aux.ddc);
306                 else if (amdgpu_connector->ddc_bus)
307                         amdgpu_connector->edid = drm_get_edid(connector,
308                                                               &amdgpu_connector->ddc_bus->adapter);
309         } else if (amdgpu_connector->ddc_bus) {
310                 amdgpu_connector->edid = drm_get_edid(connector,
311                                                       &amdgpu_connector->ddc_bus->adapter);
312         }
313
314         if (!amdgpu_connector->edid) {
315                 /* some laptops provide a hardcoded edid in rom for LCDs */
316                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
317                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
318                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
319         }
320 }
321
322 static void amdgpu_connector_free_edid(struct drm_connector *connector)
323 {
324         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
325
326         kfree(amdgpu_connector->edid);
327         amdgpu_connector->edid = NULL;
328 }
329
330 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
331 {
332         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
333         int ret;
334
335         if (amdgpu_connector->edid) {
336                 drm_connector_update_edid_property(connector, amdgpu_connector->edid);
337                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
338                 return ret;
339         }
340         drm_connector_update_edid_property(connector, NULL);
341         return 0;
342 }
343
344 static struct drm_encoder *
345 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
346 {
347         struct drm_encoder *encoder;
348
349         /* pick the first one */
350         drm_connector_for_each_possible_encoder(connector, encoder)
351                 return encoder;
352
353         return NULL;
354 }
355
356 static void amdgpu_get_native_mode(struct drm_connector *connector)
357 {
358         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
359         struct amdgpu_encoder *amdgpu_encoder;
360
361         if (encoder == NULL)
362                 return;
363
364         amdgpu_encoder = to_amdgpu_encoder(encoder);
365
366         if (!list_empty(&connector->probed_modes)) {
367                 struct drm_display_mode *preferred_mode =
368                         list_first_entry(&connector->probed_modes,
369                                          struct drm_display_mode, head);
370
371                 amdgpu_encoder->native_mode = *preferred_mode;
372         } else {
373                 amdgpu_encoder->native_mode.clock = 0;
374         }
375 }
376
377 static struct drm_display_mode *
378 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
379 {
380         struct drm_device *dev = encoder->dev;
381         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
382         struct drm_display_mode *mode = NULL;
383         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
384
385         if (native_mode->hdisplay != 0 &&
386             native_mode->vdisplay != 0 &&
387             native_mode->clock != 0) {
388                 mode = drm_mode_duplicate(dev, native_mode);
389                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
390                 drm_mode_set_name(mode);
391
392                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
393         } else if (native_mode->hdisplay != 0 &&
394                    native_mode->vdisplay != 0) {
395                 /* mac laptops without an edid */
396                 /* Note that this is not necessarily the exact panel mode,
397                  * but an approximation based on the cvt formula.  For these
398                  * systems we should ideally read the mode info out of the
399                  * registers or add a mode table, but this works and is much
400                  * simpler.
401                  */
402                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
403                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
404                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
405         }
406         return mode;
407 }
408
409 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
410                                                struct drm_connector *connector)
411 {
412         struct drm_device *dev = encoder->dev;
413         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
414         struct drm_display_mode *mode = NULL;
415         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
416         int i;
417         static const struct mode_size {
418                 int w;
419                 int h;
420         } common_modes[17] = {
421                 { 640,  480},
422                 { 720,  480},
423                 { 800,  600},
424                 { 848,  480},
425                 {1024,  768},
426                 {1152,  768},
427                 {1280,  720},
428                 {1280,  800},
429                 {1280,  854},
430                 {1280,  960},
431                 {1280, 1024},
432                 {1440,  900},
433                 {1400, 1050},
434                 {1680, 1050},
435                 {1600, 1200},
436                 {1920, 1080},
437                 {1920, 1200}
438         };
439
440         for (i = 0; i < 17; i++) {
441                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
442                         if (common_modes[i].w > 1024 ||
443                             common_modes[i].h > 768)
444                                 continue;
445                 }
446                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
447                         if (common_modes[i].w > native_mode->hdisplay ||
448                             common_modes[i].h > native_mode->vdisplay ||
449                             (common_modes[i].w == native_mode->hdisplay &&
450                              common_modes[i].h == native_mode->vdisplay))
451                                 continue;
452                 }
453                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
454                         continue;
455
456                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
457                 drm_mode_probed_add(connector, mode);
458         }
459 }
460
461 static int amdgpu_connector_set_property(struct drm_connector *connector,
462                                           struct drm_property *property,
463                                           uint64_t val)
464 {
465         struct drm_device *dev = connector->dev;
466         struct amdgpu_device *adev = dev->dev_private;
467         struct drm_encoder *encoder;
468         struct amdgpu_encoder *amdgpu_encoder;
469
470         if (property == adev->mode_info.coherent_mode_property) {
471                 struct amdgpu_encoder_atom_dig *dig;
472                 bool new_coherent_mode;
473
474                 /* need to find digital encoder on connector */
475                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
476                 if (!encoder)
477                         return 0;
478
479                 amdgpu_encoder = to_amdgpu_encoder(encoder);
480
481                 if (!amdgpu_encoder->enc_priv)
482                         return 0;
483
484                 dig = amdgpu_encoder->enc_priv;
485                 new_coherent_mode = val ? true : false;
486                 if (dig->coherent_mode != new_coherent_mode) {
487                         dig->coherent_mode = new_coherent_mode;
488                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
489                 }
490         }
491
492         if (property == adev->mode_info.audio_property) {
493                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
494                 /* need to find digital encoder on connector */
495                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
496                 if (!encoder)
497                         return 0;
498
499                 amdgpu_encoder = to_amdgpu_encoder(encoder);
500
501                 if (amdgpu_connector->audio != val) {
502                         amdgpu_connector->audio = val;
503                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
504                 }
505         }
506
507         if (property == adev->mode_info.dither_property) {
508                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
509                 /* need to find digital encoder on connector */
510                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
511                 if (!encoder)
512                         return 0;
513
514                 amdgpu_encoder = to_amdgpu_encoder(encoder);
515
516                 if (amdgpu_connector->dither != val) {
517                         amdgpu_connector->dither = val;
518                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
519                 }
520         }
521
522         if (property == adev->mode_info.underscan_property) {
523                 /* need to find digital encoder on connector */
524                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
525                 if (!encoder)
526                         return 0;
527
528                 amdgpu_encoder = to_amdgpu_encoder(encoder);
529
530                 if (amdgpu_encoder->underscan_type != val) {
531                         amdgpu_encoder->underscan_type = val;
532                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
533                 }
534         }
535
536         if (property == adev->mode_info.underscan_hborder_property) {
537                 /* need to find digital encoder on connector */
538                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
539                 if (!encoder)
540                         return 0;
541
542                 amdgpu_encoder = to_amdgpu_encoder(encoder);
543
544                 if (amdgpu_encoder->underscan_hborder != val) {
545                         amdgpu_encoder->underscan_hborder = val;
546                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
547                 }
548         }
549
550         if (property == adev->mode_info.underscan_vborder_property) {
551                 /* need to find digital encoder on connector */
552                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
553                 if (!encoder)
554                         return 0;
555
556                 amdgpu_encoder = to_amdgpu_encoder(encoder);
557
558                 if (amdgpu_encoder->underscan_vborder != val) {
559                         amdgpu_encoder->underscan_vborder = val;
560                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
561                 }
562         }
563
564         if (property == adev->mode_info.load_detect_property) {
565                 struct amdgpu_connector *amdgpu_connector =
566                         to_amdgpu_connector(connector);
567
568                 if (val == 0)
569                         amdgpu_connector->dac_load_detect = false;
570                 else
571                         amdgpu_connector->dac_load_detect = true;
572         }
573
574         if (property == dev->mode_config.scaling_mode_property) {
575                 enum amdgpu_rmx_type rmx_type;
576
577                 if (connector->encoder) {
578                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
579                 } else {
580                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
581                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
582                 }
583
584                 switch (val) {
585                 default:
586                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
587                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
588                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
589                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
590                 }
591                 if (amdgpu_encoder->rmx_type == rmx_type)
592                         return 0;
593
594                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
595                     (amdgpu_encoder->native_mode.clock == 0))
596                         return 0;
597
598                 amdgpu_encoder->rmx_type = rmx_type;
599
600                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
601         }
602
603         return 0;
604 }
605
606 static void
607 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
608                                         struct drm_connector *connector)
609 {
610         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
611         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
612         struct drm_display_mode *t, *mode;
613
614         /* If the EDID preferred mode doesn't match the native mode, use it */
615         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
616                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
617                         if (mode->hdisplay != native_mode->hdisplay ||
618                             mode->vdisplay != native_mode->vdisplay)
619                                 memcpy(native_mode, mode, sizeof(*mode));
620                 }
621         }
622
623         /* Try to get native mode details from EDID if necessary */
624         if (!native_mode->clock) {
625                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
626                         if (mode->hdisplay == native_mode->hdisplay &&
627                             mode->vdisplay == native_mode->vdisplay) {
628                                 *native_mode = *mode;
629                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
630                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
631                                 break;
632                         }
633                 }
634         }
635
636         if (!native_mode->clock) {
637                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
638                 amdgpu_encoder->rmx_type = RMX_OFF;
639         }
640 }
641
642 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
643 {
644         struct drm_encoder *encoder;
645         int ret = 0;
646         struct drm_display_mode *mode;
647
648         amdgpu_connector_get_edid(connector);
649         ret = amdgpu_connector_ddc_get_modes(connector);
650         if (ret > 0) {
651                 encoder = amdgpu_connector_best_single_encoder(connector);
652                 if (encoder) {
653                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
654                         /* add scaled modes */
655                         amdgpu_connector_add_common_modes(encoder, connector);
656                 }
657                 return ret;
658         }
659
660         encoder = amdgpu_connector_best_single_encoder(connector);
661         if (!encoder)
662                 return 0;
663
664         /* we have no EDID modes */
665         mode = amdgpu_connector_lcd_native_mode(encoder);
666         if (mode) {
667                 ret = 1;
668                 drm_mode_probed_add(connector, mode);
669                 /* add the width/height from vbios tables if available */
670                 connector->display_info.width_mm = mode->width_mm;
671                 connector->display_info.height_mm = mode->height_mm;
672                 /* add scaled modes */
673                 amdgpu_connector_add_common_modes(encoder, connector);
674         }
675
676         return ret;
677 }
678
679 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
680                                              struct drm_display_mode *mode)
681 {
682         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
683
684         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
685                 return MODE_PANEL;
686
687         if (encoder) {
688                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
689                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
690
691                 /* AVIVO hardware supports downscaling modes larger than the panel
692                  * to the panel size, but I'm not sure this is desirable.
693                  */
694                 if ((mode->hdisplay > native_mode->hdisplay) ||
695                     (mode->vdisplay > native_mode->vdisplay))
696                         return MODE_PANEL;
697
698                 /* if scaling is disabled, block non-native modes */
699                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
700                         if ((mode->hdisplay != native_mode->hdisplay) ||
701                             (mode->vdisplay != native_mode->vdisplay))
702                                 return MODE_PANEL;
703                 }
704         }
705
706         return MODE_OK;
707 }
708
709 static enum drm_connector_status
710 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
711 {
712         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
713         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
714         enum drm_connector_status ret = connector_status_disconnected;
715         int r;
716
717         if (!drm_kms_helper_is_poll_worker()) {
718                 r = pm_runtime_get_sync(connector->dev->dev);
719                 if (r < 0)
720                         return connector_status_disconnected;
721         }
722
723         if (encoder) {
724                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
725                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
726
727                 /* check if panel is valid */
728                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
729                         ret = connector_status_connected;
730
731         }
732
733         /* check for edid as well */
734         amdgpu_connector_get_edid(connector);
735         if (amdgpu_connector->edid)
736                 ret = connector_status_connected;
737         /* check acpi lid status ??? */
738
739         amdgpu_connector_update_scratch_regs(connector, ret);
740
741         if (!drm_kms_helper_is_poll_worker()) {
742                 pm_runtime_mark_last_busy(connector->dev->dev);
743                 pm_runtime_put_autosuspend(connector->dev->dev);
744         }
745
746         return ret;
747 }
748
749 static void amdgpu_connector_unregister(struct drm_connector *connector)
750 {
751         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
752
753         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
754                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
755                 amdgpu_connector->ddc_bus->has_aux = false;
756         }
757 }
758
759 static void amdgpu_connector_destroy(struct drm_connector *connector)
760 {
761         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
762
763         amdgpu_connector_free_edid(connector);
764         kfree(amdgpu_connector->con_priv);
765         drm_connector_unregister(connector);
766         drm_connector_cleanup(connector);
767         kfree(connector);
768 }
769
770 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
771                                               struct drm_property *property,
772                                               uint64_t value)
773 {
774         struct drm_device *dev = connector->dev;
775         struct amdgpu_encoder *amdgpu_encoder;
776         enum amdgpu_rmx_type rmx_type;
777
778         DRM_DEBUG_KMS("\n");
779         if (property != dev->mode_config.scaling_mode_property)
780                 return 0;
781
782         if (connector->encoder)
783                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
784         else {
785                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
786                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
787         }
788
789         switch (value) {
790         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
791         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
792         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
793         default:
794         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
795         }
796         if (amdgpu_encoder->rmx_type == rmx_type)
797                 return 0;
798
799         amdgpu_encoder->rmx_type = rmx_type;
800
801         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
802         return 0;
803 }
804
805
806 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
807         .get_modes = amdgpu_connector_lvds_get_modes,
808         .mode_valid = amdgpu_connector_lvds_mode_valid,
809         .best_encoder = amdgpu_connector_best_single_encoder,
810 };
811
812 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
813         .dpms = drm_helper_connector_dpms,
814         .detect = amdgpu_connector_lvds_detect,
815         .fill_modes = drm_helper_probe_single_connector_modes,
816         .early_unregister = amdgpu_connector_unregister,
817         .destroy = amdgpu_connector_destroy,
818         .set_property = amdgpu_connector_set_lcd_property,
819 };
820
821 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
822 {
823         int ret;
824
825         amdgpu_connector_get_edid(connector);
826         ret = amdgpu_connector_ddc_get_modes(connector);
827
828         return ret;
829 }
830
831 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
832                                             struct drm_display_mode *mode)
833 {
834         struct drm_device *dev = connector->dev;
835         struct amdgpu_device *adev = dev->dev_private;
836
837         /* XXX check mode bandwidth */
838
839         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
840                 return MODE_CLOCK_HIGH;
841
842         return MODE_OK;
843 }
844
845 static enum drm_connector_status
846 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
847 {
848         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
849         struct drm_encoder *encoder;
850         const struct drm_encoder_helper_funcs *encoder_funcs;
851         bool dret = false;
852         enum drm_connector_status ret = connector_status_disconnected;
853         int r;
854
855         if (!drm_kms_helper_is_poll_worker()) {
856                 r = pm_runtime_get_sync(connector->dev->dev);
857                 if (r < 0)
858                         return connector_status_disconnected;
859         }
860
861         encoder = amdgpu_connector_best_single_encoder(connector);
862         if (!encoder)
863                 ret = connector_status_disconnected;
864
865         if (amdgpu_connector->ddc_bus)
866                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
867         if (dret) {
868                 amdgpu_connector->detected_by_load = false;
869                 amdgpu_connector_free_edid(connector);
870                 amdgpu_connector_get_edid(connector);
871
872                 if (!amdgpu_connector->edid) {
873                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
874                                         connector->name);
875                         ret = connector_status_connected;
876                 } else {
877                         amdgpu_connector->use_digital =
878                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
879
880                         /* some oems have boards with separate digital and analog connectors
881                          * with a shared ddc line (often vga + hdmi)
882                          */
883                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
884                                 amdgpu_connector_free_edid(connector);
885                                 ret = connector_status_disconnected;
886                         } else {
887                                 ret = connector_status_connected;
888                         }
889                 }
890         } else {
891
892                 /* if we aren't forcing don't do destructive polling */
893                 if (!force) {
894                         /* only return the previous status if we last
895                          * detected a monitor via load.
896                          */
897                         if (amdgpu_connector->detected_by_load)
898                                 ret = connector->status;
899                         goto out;
900                 }
901
902                 if (amdgpu_connector->dac_load_detect && encoder) {
903                         encoder_funcs = encoder->helper_private;
904                         ret = encoder_funcs->detect(encoder, connector);
905                         if (ret != connector_status_disconnected)
906                                 amdgpu_connector->detected_by_load = true;
907                 }
908         }
909
910         amdgpu_connector_update_scratch_regs(connector, ret);
911
912 out:
913         if (!drm_kms_helper_is_poll_worker()) {
914                 pm_runtime_mark_last_busy(connector->dev->dev);
915                 pm_runtime_put_autosuspend(connector->dev->dev);
916         }
917
918         return ret;
919 }
920
921 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
922         .get_modes = amdgpu_connector_vga_get_modes,
923         .mode_valid = amdgpu_connector_vga_mode_valid,
924         .best_encoder = amdgpu_connector_best_single_encoder,
925 };
926
927 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
928         .dpms = drm_helper_connector_dpms,
929         .detect = amdgpu_connector_vga_detect,
930         .fill_modes = drm_helper_probe_single_connector_modes,
931         .early_unregister = amdgpu_connector_unregister,
932         .destroy = amdgpu_connector_destroy,
933         .set_property = amdgpu_connector_set_property,
934 };
935
936 static bool
937 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
938 {
939         struct drm_device *dev = connector->dev;
940         struct amdgpu_device *adev = dev->dev_private;
941         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
942         enum drm_connector_status status;
943
944         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
945                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
946                         status = connector_status_connected;
947                 else
948                         status = connector_status_disconnected;
949                 if (connector->status == status)
950                         return true;
951         }
952
953         return false;
954 }
955
956 /*
957  * DVI is complicated
958  * Do a DDC probe, if DDC probe passes, get the full EDID so
959  * we can do analog/digital monitor detection at this point.
960  * If the monitor is an analog monitor or we got no DDC,
961  * we need to find the DAC encoder object for this connector.
962  * If we got no DDC, we do load detection on the DAC encoder object.
963  * If we got analog DDC or load detection passes on the DAC encoder
964  * we have to check if this analog encoder is shared with anyone else (TV)
965  * if its shared we have to set the other connector to disconnected.
966  */
967 static enum drm_connector_status
968 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
969 {
970         struct drm_device *dev = connector->dev;
971         struct amdgpu_device *adev = dev->dev_private;
972         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
973         const struct drm_encoder_helper_funcs *encoder_funcs;
974         int r;
975         enum drm_connector_status ret = connector_status_disconnected;
976         bool dret = false, broken_edid = false;
977
978         if (!drm_kms_helper_is_poll_worker()) {
979                 r = pm_runtime_get_sync(connector->dev->dev);
980                 if (r < 0)
981                         return connector_status_disconnected;
982         }
983
984         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
985                 ret = connector->status;
986                 goto exit;
987         }
988
989         if (amdgpu_connector->ddc_bus)
990                 dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
991         if (dret) {
992                 amdgpu_connector->detected_by_load = false;
993                 amdgpu_connector_free_edid(connector);
994                 amdgpu_connector_get_edid(connector);
995
996                 if (!amdgpu_connector->edid) {
997                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
998                                         connector->name);
999                         ret = connector_status_connected;
1000                         broken_edid = true; /* defer use_digital to later */
1001                 } else {
1002                         amdgpu_connector->use_digital =
1003                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1004
1005                         /* some oems have boards with separate digital and analog connectors
1006                          * with a shared ddc line (often vga + hdmi)
1007                          */
1008                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1009                                 amdgpu_connector_free_edid(connector);
1010                                 ret = connector_status_disconnected;
1011                         } else {
1012                                 ret = connector_status_connected;
1013                         }
1014
1015                         /* This gets complicated.  We have boards with VGA + HDMI with a
1016                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1017                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1018                          * you don't really know what's connected to which port as both are digital.
1019                          */
1020                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1021                                 struct drm_connector *list_connector;
1022                                 struct amdgpu_connector *list_amdgpu_connector;
1023                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1024                                         if (connector == list_connector)
1025                                                 continue;
1026                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1027                                         if (list_amdgpu_connector->shared_ddc &&
1028                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1029                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1030                                                 /* cases where both connectors are digital */
1031                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1032                                                         /* hpd is our only option in this case */
1033                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1034                                                                 amdgpu_connector_free_edid(connector);
1035                                                                 ret = connector_status_disconnected;
1036                                                         }
1037                                                 }
1038                                         }
1039                                 }
1040                         }
1041                 }
1042         }
1043
1044         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1045                 goto out;
1046
1047         /* DVI-D and HDMI-A are digital only */
1048         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1049             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1050                 goto out;
1051
1052         /* if we aren't forcing don't do destructive polling */
1053         if (!force) {
1054                 /* only return the previous status if we last
1055                  * detected a monitor via load.
1056                  */
1057                 if (amdgpu_connector->detected_by_load)
1058                         ret = connector->status;
1059                 goto out;
1060         }
1061
1062         /* find analog encoder */
1063         if (amdgpu_connector->dac_load_detect) {
1064                 struct drm_encoder *encoder;
1065
1066                 drm_connector_for_each_possible_encoder(connector, encoder) {
1067                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1068                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1069                                 continue;
1070
1071                         encoder_funcs = encoder->helper_private;
1072                         if (encoder_funcs->detect) {
1073                                 if (!broken_edid) {
1074                                         if (ret != connector_status_connected) {
1075                                                 /* deal with analog monitors without DDC */
1076                                                 ret = encoder_funcs->detect(encoder, connector);
1077                                                 if (ret == connector_status_connected) {
1078                                                         amdgpu_connector->use_digital = false;
1079                                                 }
1080                                                 if (ret != connector_status_disconnected)
1081                                                         amdgpu_connector->detected_by_load = true;
1082                                         }
1083                                 } else {
1084                                         enum drm_connector_status lret;
1085                                         /* assume digital unless load detected otherwise */
1086                                         amdgpu_connector->use_digital = true;
1087                                         lret = encoder_funcs->detect(encoder, connector);
1088                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1089                                         if (lret == connector_status_connected)
1090                                                 amdgpu_connector->use_digital = false;
1091                                 }
1092                                 break;
1093                         }
1094                 }
1095         }
1096
1097 out:
1098         /* updated in get modes as well since we need to know if it's analog or digital */
1099         amdgpu_connector_update_scratch_regs(connector, ret);
1100
1101 exit:
1102         if (!drm_kms_helper_is_poll_worker()) {
1103                 pm_runtime_mark_last_busy(connector->dev->dev);
1104                 pm_runtime_put_autosuspend(connector->dev->dev);
1105         }
1106
1107         return ret;
1108 }
1109
1110 /* okay need to be smart in here about which encoder to pick */
1111 static struct drm_encoder *
1112 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1113 {
1114         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1115         struct drm_encoder *encoder;
1116
1117         drm_connector_for_each_possible_encoder(connector, encoder) {
1118                 if (amdgpu_connector->use_digital == true) {
1119                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1120                                 return encoder;
1121                 } else {
1122                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1123                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1124                                 return encoder;
1125                 }
1126         }
1127
1128         /* see if we have a default encoder  TODO */
1129
1130         /* then check use digitial */
1131         /* pick the first one */
1132         drm_connector_for_each_possible_encoder(connector, encoder)
1133                 return encoder;
1134
1135         return NULL;
1136 }
1137
1138 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1139 {
1140         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1141         if (connector->force == DRM_FORCE_ON)
1142                 amdgpu_connector->use_digital = false;
1143         if (connector->force == DRM_FORCE_ON_DIGITAL)
1144                 amdgpu_connector->use_digital = true;
1145 }
1146
1147 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1148                                             struct drm_display_mode *mode)
1149 {
1150         struct drm_device *dev = connector->dev;
1151         struct amdgpu_device *adev = dev->dev_private;
1152         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1153
1154         /* XXX check mode bandwidth */
1155
1156         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1157                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1158                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1159                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1160                         return MODE_OK;
1161                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1162                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1163                         if (mode->clock > 340000)
1164                                 return MODE_CLOCK_HIGH;
1165                         else
1166                                 return MODE_OK;
1167                 } else {
1168                         return MODE_CLOCK_HIGH;
1169                 }
1170         }
1171
1172         /* check against the max pixel clock */
1173         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1174                 return MODE_CLOCK_HIGH;
1175
1176         return MODE_OK;
1177 }
1178
1179 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1180         .get_modes = amdgpu_connector_vga_get_modes,
1181         .mode_valid = amdgpu_connector_dvi_mode_valid,
1182         .best_encoder = amdgpu_connector_dvi_encoder,
1183 };
1184
1185 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1186         .dpms = drm_helper_connector_dpms,
1187         .detect = amdgpu_connector_dvi_detect,
1188         .fill_modes = drm_helper_probe_single_connector_modes,
1189         .set_property = amdgpu_connector_set_property,
1190         .early_unregister = amdgpu_connector_unregister,
1191         .destroy = amdgpu_connector_destroy,
1192         .force = amdgpu_connector_dvi_force,
1193 };
1194
1195 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1196 {
1197         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1198         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1199         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1200         int ret;
1201
1202         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1203             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1204                 struct drm_display_mode *mode;
1205
1206                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1207                         if (!amdgpu_dig_connector->edp_on)
1208                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1209                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1210                         amdgpu_connector_get_edid(connector);
1211                         ret = amdgpu_connector_ddc_get_modes(connector);
1212                         if (!amdgpu_dig_connector->edp_on)
1213                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1214                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1215                 } else {
1216                         /* need to setup ddc on the bridge */
1217                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1218                             ENCODER_OBJECT_ID_NONE) {
1219                                 if (encoder)
1220                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1221                         }
1222                         amdgpu_connector_get_edid(connector);
1223                         ret = amdgpu_connector_ddc_get_modes(connector);
1224                 }
1225
1226                 if (ret > 0) {
1227                         if (encoder) {
1228                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1229                                 /* add scaled modes */
1230                                 amdgpu_connector_add_common_modes(encoder, connector);
1231                         }
1232                         return ret;
1233                 }
1234
1235                 if (!encoder)
1236                         return 0;
1237
1238                 /* we have no EDID modes */
1239                 mode = amdgpu_connector_lcd_native_mode(encoder);
1240                 if (mode) {
1241                         ret = 1;
1242                         drm_mode_probed_add(connector, mode);
1243                         /* add the width/height from vbios tables if available */
1244                         connector->display_info.width_mm = mode->width_mm;
1245                         connector->display_info.height_mm = mode->height_mm;
1246                         /* add scaled modes */
1247                         amdgpu_connector_add_common_modes(encoder, connector);
1248                 }
1249         } else {
1250                 /* need to setup ddc on the bridge */
1251                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1252                         ENCODER_OBJECT_ID_NONE) {
1253                         if (encoder)
1254                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1255                 }
1256                 amdgpu_connector_get_edid(connector);
1257                 ret = amdgpu_connector_ddc_get_modes(connector);
1258
1259                 amdgpu_get_native_mode(connector);
1260         }
1261
1262         return ret;
1263 }
1264
1265 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1266 {
1267         struct drm_encoder *encoder;
1268         struct amdgpu_encoder *amdgpu_encoder;
1269
1270         drm_connector_for_each_possible_encoder(connector, encoder) {
1271                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1272
1273                 switch (amdgpu_encoder->encoder_id) {
1274                 case ENCODER_OBJECT_ID_TRAVIS:
1275                 case ENCODER_OBJECT_ID_NUTMEG:
1276                         return amdgpu_encoder->encoder_id;
1277                 default:
1278                         break;
1279                 }
1280         }
1281
1282         return ENCODER_OBJECT_ID_NONE;
1283 }
1284
1285 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1286 {
1287         struct drm_encoder *encoder;
1288         struct amdgpu_encoder *amdgpu_encoder;
1289         bool found = false;
1290
1291         drm_connector_for_each_possible_encoder(connector, encoder) {
1292                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1293                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1294                         found = true;
1295         }
1296
1297         return found;
1298 }
1299
1300 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1301 {
1302         struct drm_device *dev = connector->dev;
1303         struct amdgpu_device *adev = dev->dev_private;
1304
1305         if ((adev->clock.default_dispclk >= 53900) &&
1306             amdgpu_connector_encoder_is_hbr2(connector)) {
1307                 return true;
1308         }
1309
1310         return false;
1311 }
1312
1313 static enum drm_connector_status
1314 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1315 {
1316         struct drm_device *dev = connector->dev;
1317         struct amdgpu_device *adev = dev->dev_private;
1318         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1319         enum drm_connector_status ret = connector_status_disconnected;
1320         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1321         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1322         int r;
1323
1324         if (!drm_kms_helper_is_poll_worker()) {
1325                 r = pm_runtime_get_sync(connector->dev->dev);
1326                 if (r < 0)
1327                         return connector_status_disconnected;
1328         }
1329
1330         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1331                 ret = connector->status;
1332                 goto out;
1333         }
1334
1335         amdgpu_connector_free_edid(connector);
1336
1337         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1338             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1339                 if (encoder) {
1340                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1341                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1342
1343                         /* check if panel is valid */
1344                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1345                                 ret = connector_status_connected;
1346                 }
1347                 /* eDP is always DP */
1348                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1349                 if (!amdgpu_dig_connector->edp_on)
1350                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1351                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1352                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1353                         ret = connector_status_connected;
1354                 if (!amdgpu_dig_connector->edp_on)
1355                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1356                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1357         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1358                    ENCODER_OBJECT_ID_NONE) {
1359                 /* DP bridges are always DP */
1360                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1361                 /* get the DPCD from the bridge */
1362                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1363
1364                 if (encoder) {
1365                         /* setup ddc on the bridge */
1366                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1367                         /* bridge chips are always aux */
1368                         /* try DDC */
1369                         if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1370                                 ret = connector_status_connected;
1371                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1372                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1373                                 ret = encoder_funcs->detect(encoder, connector);
1374                         }
1375                 }
1376         } else {
1377                 amdgpu_dig_connector->dp_sink_type =
1378                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1379                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1380                         ret = connector_status_connected;
1381                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1382                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1383                 } else {
1384                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1385                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1386                                         ret = connector_status_connected;
1387                         } else {
1388                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1389                                 if (amdgpu_display_ddc_probe(amdgpu_connector,
1390                                                              false))
1391                                         ret = connector_status_connected;
1392                         }
1393                 }
1394         }
1395
1396         amdgpu_connector_update_scratch_regs(connector, ret);
1397 out:
1398         if (!drm_kms_helper_is_poll_worker()) {
1399                 pm_runtime_mark_last_busy(connector->dev->dev);
1400                 pm_runtime_put_autosuspend(connector->dev->dev);
1401         }
1402
1403         return ret;
1404 }
1405
1406 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1407                                            struct drm_display_mode *mode)
1408 {
1409         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1410         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1411
1412         /* XXX check mode bandwidth */
1413
1414         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1415             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1416                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1417
1418                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1419                         return MODE_PANEL;
1420
1421                 if (encoder) {
1422                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1423                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1424
1425                         /* AVIVO hardware supports downscaling modes larger than the panel
1426                          * to the panel size, but I'm not sure this is desirable.
1427                          */
1428                         if ((mode->hdisplay > native_mode->hdisplay) ||
1429                             (mode->vdisplay > native_mode->vdisplay))
1430                                 return MODE_PANEL;
1431
1432                         /* if scaling is disabled, block non-native modes */
1433                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1434                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1435                                     (mode->vdisplay != native_mode->vdisplay))
1436                                         return MODE_PANEL;
1437                         }
1438                 }
1439                 return MODE_OK;
1440         } else {
1441                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1442                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1443                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1444                 } else {
1445                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1446                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1447                                 if (mode->clock > 340000)
1448                                         return MODE_CLOCK_HIGH;
1449                         } else {
1450                                 if (mode->clock > 165000)
1451                                         return MODE_CLOCK_HIGH;
1452                         }
1453                 }
1454         }
1455
1456         return MODE_OK;
1457 }
1458
1459 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1460         .get_modes = amdgpu_connector_dp_get_modes,
1461         .mode_valid = amdgpu_connector_dp_mode_valid,
1462         .best_encoder = amdgpu_connector_dvi_encoder,
1463 };
1464
1465 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1466         .dpms = drm_helper_connector_dpms,
1467         .detect = amdgpu_connector_dp_detect,
1468         .fill_modes = drm_helper_probe_single_connector_modes,
1469         .set_property = amdgpu_connector_set_property,
1470         .early_unregister = amdgpu_connector_unregister,
1471         .destroy = amdgpu_connector_destroy,
1472         .force = amdgpu_connector_dvi_force,
1473 };
1474
1475 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1476         .dpms = drm_helper_connector_dpms,
1477         .detect = amdgpu_connector_dp_detect,
1478         .fill_modes = drm_helper_probe_single_connector_modes,
1479         .set_property = amdgpu_connector_set_lcd_property,
1480         .early_unregister = amdgpu_connector_unregister,
1481         .destroy = amdgpu_connector_destroy,
1482         .force = amdgpu_connector_dvi_force,
1483 };
1484
1485 void
1486 amdgpu_connector_add(struct amdgpu_device *adev,
1487                       uint32_t connector_id,
1488                       uint32_t supported_device,
1489                       int connector_type,
1490                       struct amdgpu_i2c_bus_rec *i2c_bus,
1491                       uint16_t connector_object_id,
1492                       struct amdgpu_hpd *hpd,
1493                       struct amdgpu_router *router)
1494 {
1495         struct drm_device *dev = adev->ddev;
1496         struct drm_connector *connector;
1497         struct amdgpu_connector *amdgpu_connector;
1498         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1499         struct drm_encoder *encoder;
1500         struct amdgpu_encoder *amdgpu_encoder;
1501         struct i2c_adapter *ddc = NULL;
1502         uint32_t subpixel_order = SubPixelNone;
1503         bool shared_ddc = false;
1504         bool is_dp_bridge = false;
1505         bool has_aux = false;
1506
1507         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1508                 return;
1509
1510         /* see if we already added it */
1511         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1512                 amdgpu_connector = to_amdgpu_connector(connector);
1513                 if (amdgpu_connector->connector_id == connector_id) {
1514                         amdgpu_connector->devices |= supported_device;
1515                         return;
1516                 }
1517                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1518                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1519                                 amdgpu_connector->shared_ddc = true;
1520                                 shared_ddc = true;
1521                         }
1522                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1523                             (amdgpu_connector->router.router_id == router->router_id)) {
1524                                 amdgpu_connector->shared_ddc = false;
1525                                 shared_ddc = false;
1526                         }
1527                 }
1528         }
1529
1530         /* check if it's a dp bridge */
1531         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1532                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1533                 if (amdgpu_encoder->devices & supported_device) {
1534                         switch (amdgpu_encoder->encoder_id) {
1535                         case ENCODER_OBJECT_ID_TRAVIS:
1536                         case ENCODER_OBJECT_ID_NUTMEG:
1537                                 is_dp_bridge = true;
1538                                 break;
1539                         default:
1540                                 break;
1541                         }
1542                 }
1543         }
1544
1545         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1546         if (!amdgpu_connector)
1547                 return;
1548
1549         connector = &amdgpu_connector->base;
1550
1551         amdgpu_connector->connector_id = connector_id;
1552         amdgpu_connector->devices = supported_device;
1553         amdgpu_connector->shared_ddc = shared_ddc;
1554         amdgpu_connector->connector_object_id = connector_object_id;
1555         amdgpu_connector->hpd = *hpd;
1556
1557         amdgpu_connector->router = *router;
1558         if (router->ddc_valid || router->cd_valid) {
1559                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1560                 if (!amdgpu_connector->router_bus)
1561                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1562         }
1563
1564         if (is_dp_bridge) {
1565                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1566                 if (!amdgpu_dig_connector)
1567                         goto failed;
1568                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1569                 if (i2c_bus->valid) {
1570                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1571                         if (amdgpu_connector->ddc_bus) {
1572                                 has_aux = true;
1573                                 ddc = &amdgpu_connector->ddc_bus->adapter;
1574                         } else {
1575                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1576                         }
1577                 }
1578                 switch (connector_type) {
1579                 case DRM_MODE_CONNECTOR_VGA:
1580                 case DRM_MODE_CONNECTOR_DVIA:
1581                 default:
1582                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1583                                                     &amdgpu_connector_dp_funcs,
1584                                                     connector_type,
1585                                                     ddc);
1586                         drm_connector_helper_add(&amdgpu_connector->base,
1587                                                  &amdgpu_connector_dp_helper_funcs);
1588                         connector->interlace_allowed = true;
1589                         connector->doublescan_allowed = true;
1590                         amdgpu_connector->dac_load_detect = true;
1591                         drm_object_attach_property(&amdgpu_connector->base.base,
1592                                                       adev->mode_info.load_detect_property,
1593                                                       1);
1594                         drm_object_attach_property(&amdgpu_connector->base.base,
1595                                                    dev->mode_config.scaling_mode_property,
1596                                                    DRM_MODE_SCALE_NONE);
1597                         break;
1598                 case DRM_MODE_CONNECTOR_DVII:
1599                 case DRM_MODE_CONNECTOR_DVID:
1600                 case DRM_MODE_CONNECTOR_HDMIA:
1601                 case DRM_MODE_CONNECTOR_HDMIB:
1602                 case DRM_MODE_CONNECTOR_DisplayPort:
1603                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1604                                                     &amdgpu_connector_dp_funcs,
1605                                                     connector_type,
1606                                                     ddc);
1607                         drm_connector_helper_add(&amdgpu_connector->base,
1608                                                  &amdgpu_connector_dp_helper_funcs);
1609                         drm_object_attach_property(&amdgpu_connector->base.base,
1610                                                       adev->mode_info.underscan_property,
1611                                                       UNDERSCAN_OFF);
1612                         drm_object_attach_property(&amdgpu_connector->base.base,
1613                                                       adev->mode_info.underscan_hborder_property,
1614                                                       0);
1615                         drm_object_attach_property(&amdgpu_connector->base.base,
1616                                                       adev->mode_info.underscan_vborder_property,
1617                                                       0);
1618
1619                         drm_object_attach_property(&amdgpu_connector->base.base,
1620                                                    dev->mode_config.scaling_mode_property,
1621                                                    DRM_MODE_SCALE_NONE);
1622
1623                         drm_object_attach_property(&amdgpu_connector->base.base,
1624                                                    adev->mode_info.dither_property,
1625                                                    AMDGPU_FMT_DITHER_DISABLE);
1626
1627                         if (amdgpu_audio != 0)
1628                                 drm_object_attach_property(&amdgpu_connector->base.base,
1629                                                            adev->mode_info.audio_property,
1630                                                            AMDGPU_AUDIO_AUTO);
1631
1632                         subpixel_order = SubPixelHorizontalRGB;
1633                         connector->interlace_allowed = true;
1634                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1635                                 connector->doublescan_allowed = true;
1636                         else
1637                                 connector->doublescan_allowed = false;
1638                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1639                                 amdgpu_connector->dac_load_detect = true;
1640                                 drm_object_attach_property(&amdgpu_connector->base.base,
1641                                                               adev->mode_info.load_detect_property,
1642                                                               1);
1643                         }
1644                         break;
1645                 case DRM_MODE_CONNECTOR_LVDS:
1646                 case DRM_MODE_CONNECTOR_eDP:
1647                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1648                                                     &amdgpu_connector_edp_funcs,
1649                                                     connector_type,
1650                                                     ddc);
1651                         drm_connector_helper_add(&amdgpu_connector->base,
1652                                                  &amdgpu_connector_dp_helper_funcs);
1653                         drm_object_attach_property(&amdgpu_connector->base.base,
1654                                                       dev->mode_config.scaling_mode_property,
1655                                                       DRM_MODE_SCALE_FULLSCREEN);
1656                         subpixel_order = SubPixelHorizontalRGB;
1657                         connector->interlace_allowed = false;
1658                         connector->doublescan_allowed = false;
1659                         break;
1660                 }
1661         } else {
1662                 switch (connector_type) {
1663                 case DRM_MODE_CONNECTOR_VGA:
1664                         if (i2c_bus->valid) {
1665                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1666                                 if (!amdgpu_connector->ddc_bus)
1667                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1668                                 else
1669                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1670                         }
1671                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1672                                                     &amdgpu_connector_vga_funcs,
1673                                                     connector_type,
1674                                                     ddc);
1675                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1676                         amdgpu_connector->dac_load_detect = true;
1677                         drm_object_attach_property(&amdgpu_connector->base.base,
1678                                                       adev->mode_info.load_detect_property,
1679                                                       1);
1680                         drm_object_attach_property(&amdgpu_connector->base.base,
1681                                                    dev->mode_config.scaling_mode_property,
1682                                                    DRM_MODE_SCALE_NONE);
1683                         /* no HPD on analog connectors */
1684                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1685                         connector->interlace_allowed = true;
1686                         connector->doublescan_allowed = true;
1687                         break;
1688                 case DRM_MODE_CONNECTOR_DVIA:
1689                         if (i2c_bus->valid) {
1690                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1691                                 if (!amdgpu_connector->ddc_bus)
1692                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1693                                 else
1694                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1695                         }
1696                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1697                                                     &amdgpu_connector_vga_funcs,
1698                                                     connector_type,
1699                                                     ddc);
1700                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1701                         amdgpu_connector->dac_load_detect = true;
1702                         drm_object_attach_property(&amdgpu_connector->base.base,
1703                                                       adev->mode_info.load_detect_property,
1704                                                       1);
1705                         drm_object_attach_property(&amdgpu_connector->base.base,
1706                                                    dev->mode_config.scaling_mode_property,
1707                                                    DRM_MODE_SCALE_NONE);
1708                         /* no HPD on analog connectors */
1709                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1710                         connector->interlace_allowed = true;
1711                         connector->doublescan_allowed = true;
1712                         break;
1713                 case DRM_MODE_CONNECTOR_DVII:
1714                 case DRM_MODE_CONNECTOR_DVID:
1715                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1716                         if (!amdgpu_dig_connector)
1717                                 goto failed;
1718                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1719                         if (i2c_bus->valid) {
1720                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1721                                 if (!amdgpu_connector->ddc_bus)
1722                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1723                                 else
1724                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1725                         }
1726                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1727                                                     &amdgpu_connector_dvi_funcs,
1728                                                     connector_type,
1729                                                     ddc);
1730                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1731                         subpixel_order = SubPixelHorizontalRGB;
1732                         drm_object_attach_property(&amdgpu_connector->base.base,
1733                                                       adev->mode_info.coherent_mode_property,
1734                                                       1);
1735                         drm_object_attach_property(&amdgpu_connector->base.base,
1736                                                    adev->mode_info.underscan_property,
1737                                                    UNDERSCAN_OFF);
1738                         drm_object_attach_property(&amdgpu_connector->base.base,
1739                                                    adev->mode_info.underscan_hborder_property,
1740                                                    0);
1741                         drm_object_attach_property(&amdgpu_connector->base.base,
1742                                                    adev->mode_info.underscan_vborder_property,
1743                                                    0);
1744                         drm_object_attach_property(&amdgpu_connector->base.base,
1745                                                    dev->mode_config.scaling_mode_property,
1746                                                    DRM_MODE_SCALE_NONE);
1747
1748                         if (amdgpu_audio != 0) {
1749                                 drm_object_attach_property(&amdgpu_connector->base.base,
1750                                                            adev->mode_info.audio_property,
1751                                                            AMDGPU_AUDIO_AUTO);
1752                         }
1753                         drm_object_attach_property(&amdgpu_connector->base.base,
1754                                                    adev->mode_info.dither_property,
1755                                                    AMDGPU_FMT_DITHER_DISABLE);
1756                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1757                                 amdgpu_connector->dac_load_detect = true;
1758                                 drm_object_attach_property(&amdgpu_connector->base.base,
1759                                                            adev->mode_info.load_detect_property,
1760                                                            1);
1761                         }
1762                         connector->interlace_allowed = true;
1763                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1764                                 connector->doublescan_allowed = true;
1765                         else
1766                                 connector->doublescan_allowed = false;
1767                         break;
1768                 case DRM_MODE_CONNECTOR_HDMIA:
1769                 case DRM_MODE_CONNECTOR_HDMIB:
1770                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1771                         if (!amdgpu_dig_connector)
1772                                 goto failed;
1773                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1774                         if (i2c_bus->valid) {
1775                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1776                                 if (!amdgpu_connector->ddc_bus)
1777                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1778                                 else
1779                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1780                         }
1781                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1782                                                     &amdgpu_connector_dvi_funcs,
1783                                                     connector_type,
1784                                                     ddc);
1785                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1786                         drm_object_attach_property(&amdgpu_connector->base.base,
1787                                                       adev->mode_info.coherent_mode_property,
1788                                                       1);
1789                         drm_object_attach_property(&amdgpu_connector->base.base,
1790                                                    adev->mode_info.underscan_property,
1791                                                    UNDERSCAN_OFF);
1792                         drm_object_attach_property(&amdgpu_connector->base.base,
1793                                                    adev->mode_info.underscan_hborder_property,
1794                                                    0);
1795                         drm_object_attach_property(&amdgpu_connector->base.base,
1796                                                    adev->mode_info.underscan_vborder_property,
1797                                                    0);
1798                         drm_object_attach_property(&amdgpu_connector->base.base,
1799                                                    dev->mode_config.scaling_mode_property,
1800                                                    DRM_MODE_SCALE_NONE);
1801                         if (amdgpu_audio != 0) {
1802                                 drm_object_attach_property(&amdgpu_connector->base.base,
1803                                                            adev->mode_info.audio_property,
1804                                                            AMDGPU_AUDIO_AUTO);
1805                         }
1806                         drm_object_attach_property(&amdgpu_connector->base.base,
1807                                                    adev->mode_info.dither_property,
1808                                                    AMDGPU_FMT_DITHER_DISABLE);
1809                         subpixel_order = SubPixelHorizontalRGB;
1810                         connector->interlace_allowed = true;
1811                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1812                                 connector->doublescan_allowed = true;
1813                         else
1814                                 connector->doublescan_allowed = false;
1815                         break;
1816                 case DRM_MODE_CONNECTOR_DisplayPort:
1817                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1818                         if (!amdgpu_dig_connector)
1819                                 goto failed;
1820                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1821                         if (i2c_bus->valid) {
1822                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1823                                 if (amdgpu_connector->ddc_bus) {
1824                                         has_aux = true;
1825                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1826                                 } else {
1827                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1828                                 }
1829                         }
1830                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1831                                                     &amdgpu_connector_dp_funcs,
1832                                                     connector_type,
1833                                                     ddc);
1834                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1835                         subpixel_order = SubPixelHorizontalRGB;
1836                         drm_object_attach_property(&amdgpu_connector->base.base,
1837                                                       adev->mode_info.coherent_mode_property,
1838                                                       1);
1839                         drm_object_attach_property(&amdgpu_connector->base.base,
1840                                                    adev->mode_info.underscan_property,
1841                                                    UNDERSCAN_OFF);
1842                         drm_object_attach_property(&amdgpu_connector->base.base,
1843                                                    adev->mode_info.underscan_hborder_property,
1844                                                    0);
1845                         drm_object_attach_property(&amdgpu_connector->base.base,
1846                                                    adev->mode_info.underscan_vborder_property,
1847                                                    0);
1848                         drm_object_attach_property(&amdgpu_connector->base.base,
1849                                                    dev->mode_config.scaling_mode_property,
1850                                                    DRM_MODE_SCALE_NONE);
1851                         if (amdgpu_audio != 0) {
1852                                 drm_object_attach_property(&amdgpu_connector->base.base,
1853                                                            adev->mode_info.audio_property,
1854                                                            AMDGPU_AUDIO_AUTO);
1855                         }
1856                         drm_object_attach_property(&amdgpu_connector->base.base,
1857                                                    adev->mode_info.dither_property,
1858                                                    AMDGPU_FMT_DITHER_DISABLE);
1859                         connector->interlace_allowed = true;
1860                         /* in theory with a DP to VGA converter... */
1861                         connector->doublescan_allowed = false;
1862                         break;
1863                 case DRM_MODE_CONNECTOR_eDP:
1864                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1865                         if (!amdgpu_dig_connector)
1866                                 goto failed;
1867                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1868                         if (i2c_bus->valid) {
1869                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1870                                 if (amdgpu_connector->ddc_bus) {
1871                                         has_aux = true;
1872                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1873                                 } else {
1874                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1875                                 }
1876                         }
1877                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1878                                                     &amdgpu_connector_edp_funcs,
1879                                                     connector_type,
1880                                                     ddc);
1881                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1882                         drm_object_attach_property(&amdgpu_connector->base.base,
1883                                                       dev->mode_config.scaling_mode_property,
1884                                                       DRM_MODE_SCALE_FULLSCREEN);
1885                         subpixel_order = SubPixelHorizontalRGB;
1886                         connector->interlace_allowed = false;
1887                         connector->doublescan_allowed = false;
1888                         break;
1889                 case DRM_MODE_CONNECTOR_LVDS:
1890                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1891                         if (!amdgpu_dig_connector)
1892                                 goto failed;
1893                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1894                         if (i2c_bus->valid) {
1895                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1896                                 if (!amdgpu_connector->ddc_bus)
1897                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1898                                 else
1899                                         ddc = &amdgpu_connector->ddc_bus->adapter;
1900                         }
1901                         drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
1902                                                     &amdgpu_connector_lvds_funcs,
1903                                                     connector_type,
1904                                                     ddc);
1905                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1906                         drm_object_attach_property(&amdgpu_connector->base.base,
1907                                                       dev->mode_config.scaling_mode_property,
1908                                                       DRM_MODE_SCALE_FULLSCREEN);
1909                         subpixel_order = SubPixelHorizontalRGB;
1910                         connector->interlace_allowed = false;
1911                         connector->doublescan_allowed = false;
1912                         break;
1913                 }
1914         }
1915
1916         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1917                 if (i2c_bus->valid) {
1918                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1919                                             DRM_CONNECTOR_POLL_DISCONNECT;
1920                 }
1921         } else
1922                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1923
1924         connector->display_info.subpixel_order = subpixel_order;
1925         drm_connector_register(connector);
1926
1927         if (has_aux)
1928                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1929
1930         return;
1931
1932 failed:
1933         drm_connector_cleanup(connector);
1934         kfree(connector);
1935 }