8ca3783f2debefbc32f1ad3d6bc475cfbc16b986
[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_connectors.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_fb_helper.h>
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu.h"
32 #include "atom.h"
33 #include "atombios_encoders.h"
34 #include "atombios_dp.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_i2c.h"
37
38 #include <linux/pm_runtime.h>
39
40 void amdgpu_connector_hotplug(struct drm_connector *connector)
41 {
42         struct drm_device *dev = connector->dev;
43         struct amdgpu_device *adev = dev->dev_private;
44         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
45
46         /* bail if the connector does not have hpd pin, e.g.,
47          * VGA, TV, etc.
48          */
49         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
50                 return;
51
52         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
53
54         /* if the connector is already off, don't turn it back on */
55         if (connector->dpms != DRM_MODE_DPMS_ON)
56                 return;
57
58         /* just deal with DP (not eDP) here. */
59         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
60                 struct amdgpu_connector_atom_dig *dig_connector =
61                         amdgpu_connector->con_priv;
62
63                 /* if existing sink type was not DP no need to retrain */
64                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
65                         return;
66
67                 /* first get sink type as it may be reset after (un)plug */
68                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
69                 /* don't do anything if sink is not display port, i.e.,
70                  * passive dp->(dvi|hdmi) adaptor
71                  */
72                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
73                         int saved_dpms = connector->dpms;
74                         /* Only turn off the display if it's physically disconnected */
75                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
76                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
77                         } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
78                                 /* Don't try to start link training before we
79                                  * have the dpcd */
80                                 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
81                                         return;
82
83                                 /* set it to OFF so that drm_helper_connector_dpms()
84                                  * won't return immediately since the current state
85                                  * is ON at this point.
86                                  */
87                                 connector->dpms = DRM_MODE_DPMS_OFF;
88                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
89                         }
90                         connector->dpms = saved_dpms;
91                 }
92         }
93 }
94
95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
96 {
97         struct drm_crtc *crtc = encoder->crtc;
98
99         if (crtc && crtc->enabled) {
100                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
101                                          crtc->x, crtc->y, crtc->primary->fb);
102         }
103 }
104
105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
106 {
107         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
108         struct amdgpu_connector_atom_dig *dig_connector;
109         int bpc = 8;
110         unsigned mode_clock, max_tmds_clock;
111
112         switch (connector->connector_type) {
113         case DRM_MODE_CONNECTOR_DVII:
114         case DRM_MODE_CONNECTOR_HDMIB:
115                 if (amdgpu_connector->use_digital) {
116                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
117                                 if (connector->display_info.bpc)
118                                         bpc = connector->display_info.bpc;
119                         }
120                 }
121                 break;
122         case DRM_MODE_CONNECTOR_DVID:
123         case DRM_MODE_CONNECTOR_HDMIA:
124                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
125                         if (connector->display_info.bpc)
126                                 bpc = connector->display_info.bpc;
127                 }
128                 break;
129         case DRM_MODE_CONNECTOR_DisplayPort:
130                 dig_connector = amdgpu_connector->con_priv;
131                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
132                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
133                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
134                         if (connector->display_info.bpc)
135                                 bpc = connector->display_info.bpc;
136                 }
137                 break;
138         case DRM_MODE_CONNECTOR_eDP:
139         case DRM_MODE_CONNECTOR_LVDS:
140                 if (connector->display_info.bpc)
141                         bpc = connector->display_info.bpc;
142                 else {
143                         const struct drm_connector_helper_funcs *connector_funcs =
144                                 connector->helper_private;
145                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
146                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
147                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
148
149                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
150                                 bpc = 6;
151                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
152                                 bpc = 8;
153                 }
154                 break;
155         }
156
157         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
158                 /*
159                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
160                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
161                  * 12 bpc is always supported on hdmi deep color sinks, as this is
162                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
163                  */
164                 if (bpc > 12) {
165                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
166                                   connector->name, bpc);
167                         bpc = 12;
168                 }
169
170                 /* Any defined maximum tmds clock limit we must not exceed? */
171                 if (connector->display_info.max_tmds_clock > 0) {
172                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
173                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
174
175                         /* Maximum allowable input clock in kHz */
176                         max_tmds_clock = connector->display_info.max_tmds_clock;
177
178                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
179                                   connector->name, mode_clock, max_tmds_clock);
180
181                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
182                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
183                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
184                                     (mode_clock * 5/4 <= max_tmds_clock))
185                                         bpc = 10;
186                                 else
187                                         bpc = 8;
188
189                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
190                                           connector->name, bpc);
191                         }
192
193                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
194                                 bpc = 8;
195                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
196                                           connector->name, bpc);
197                         }
198                 } else if (bpc > 8) {
199                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
200                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
201                                   connector->name);
202                         bpc = 8;
203                 }
204         }
205
206         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
207                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
208                           connector->name);
209                 bpc = 8;
210         }
211
212         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
213                   connector->name, connector->display_info.bpc, bpc);
214
215         return bpc;
216 }
217
218 static void
219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
220                                       enum drm_connector_status status)
221 {
222         struct drm_encoder *best_encoder = NULL;
223         struct drm_encoder *encoder = NULL;
224         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
225         bool connected;
226         int i;
227
228         best_encoder = connector_funcs->best_encoder(connector);
229
230         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
231                 if (connector->encoder_ids[i] == 0)
232                         break;
233
234                 encoder = drm_encoder_find(connector->dev, NULL,
235                                         connector->encoder_ids[i]);
236                 if (!encoder)
237                         continue;
238
239                 if ((encoder == best_encoder) && (status == connector_status_connected))
240                         connected = true;
241                 else
242                         connected = false;
243
244                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
245
246         }
247 }
248
249 static struct drm_encoder *
250 amdgpu_connector_find_encoder(struct drm_connector *connector,
251                                int encoder_type)
252 {
253         struct drm_encoder *encoder;
254         int i;
255
256         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
257                 if (connector->encoder_ids[i] == 0)
258                         break;
259                 encoder = drm_encoder_find(connector->dev, NULL,
260                                         connector->encoder_ids[i]);
261                 if (!encoder)
262                         continue;
263
264                 if (encoder->encoder_type == encoder_type)
265                         return encoder;
266         }
267         return NULL;
268 }
269
270 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
271 {
272         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
273         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
274
275         if (amdgpu_connector->edid) {
276                 return amdgpu_connector->edid;
277         } else if (edid_blob) {
278                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
279                 if (edid)
280                         amdgpu_connector->edid = edid;
281         }
282         return amdgpu_connector->edid;
283 }
284
285 static struct edid *
286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
287 {
288         struct edid *edid;
289
290         if (adev->mode_info.bios_hardcoded_edid) {
291                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
292                 if (edid) {
293                         memcpy((unsigned char *)edid,
294                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
295                                adev->mode_info.bios_hardcoded_edid_size);
296                         return edid;
297                 }
298         }
299         return NULL;
300 }
301
302 static void amdgpu_connector_get_edid(struct drm_connector *connector)
303 {
304         struct drm_device *dev = connector->dev;
305         struct amdgpu_device *adev = dev->dev_private;
306         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
307
308         if (amdgpu_connector->edid)
309                 return;
310
311         /* on hw with routers, select right port */
312         if (amdgpu_connector->router.ddc_valid)
313                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
314
315         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
316              ENCODER_OBJECT_ID_NONE) &&
317             amdgpu_connector->ddc_bus->has_aux) {
318                 amdgpu_connector->edid = drm_get_edid(connector,
319                                                       &amdgpu_connector->ddc_bus->aux.ddc);
320         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
321                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
322                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
323
324                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
325                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
326                     amdgpu_connector->ddc_bus->has_aux)
327                         amdgpu_connector->edid = drm_get_edid(connector,
328                                                               &amdgpu_connector->ddc_bus->aux.ddc);
329                 else if (amdgpu_connector->ddc_bus)
330                         amdgpu_connector->edid = drm_get_edid(connector,
331                                                               &amdgpu_connector->ddc_bus->adapter);
332         } else if (amdgpu_connector->ddc_bus) {
333                 amdgpu_connector->edid = drm_get_edid(connector,
334                                                       &amdgpu_connector->ddc_bus->adapter);
335         }
336
337         if (!amdgpu_connector->edid) {
338                 /* some laptops provide a hardcoded edid in rom for LCDs */
339                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
340                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
341                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
342         }
343 }
344
345 static void amdgpu_connector_free_edid(struct drm_connector *connector)
346 {
347         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
348
349         kfree(amdgpu_connector->edid);
350         amdgpu_connector->edid = NULL;
351 }
352
353 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
354 {
355         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
356         int ret;
357
358         if (amdgpu_connector->edid) {
359                 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
360                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
361                 return ret;
362         }
363         drm_mode_connector_update_edid_property(connector, NULL);
364         return 0;
365 }
366
367 static struct drm_encoder *
368 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
369 {
370         int enc_id = connector->encoder_ids[0];
371
372         /* pick the encoder ids */
373         if (enc_id)
374                 return drm_encoder_find(connector->dev, NULL, enc_id);
375         return NULL;
376 }
377
378 static void amdgpu_get_native_mode(struct drm_connector *connector)
379 {
380         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
381         struct amdgpu_encoder *amdgpu_encoder;
382
383         if (encoder == NULL)
384                 return;
385
386         amdgpu_encoder = to_amdgpu_encoder(encoder);
387
388         if (!list_empty(&connector->probed_modes)) {
389                 struct drm_display_mode *preferred_mode =
390                         list_first_entry(&connector->probed_modes,
391                                          struct drm_display_mode, head);
392
393                 amdgpu_encoder->native_mode = *preferred_mode;
394         } else {
395                 amdgpu_encoder->native_mode.clock = 0;
396         }
397 }
398
399 static struct drm_display_mode *
400 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
401 {
402         struct drm_device *dev = encoder->dev;
403         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
404         struct drm_display_mode *mode = NULL;
405         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
406
407         if (native_mode->hdisplay != 0 &&
408             native_mode->vdisplay != 0 &&
409             native_mode->clock != 0) {
410                 mode = drm_mode_duplicate(dev, native_mode);
411                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
412                 drm_mode_set_name(mode);
413
414                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
415         } else if (native_mode->hdisplay != 0 &&
416                    native_mode->vdisplay != 0) {
417                 /* mac laptops without an edid */
418                 /* Note that this is not necessarily the exact panel mode,
419                  * but an approximation based on the cvt formula.  For these
420                  * systems we should ideally read the mode info out of the
421                  * registers or add a mode table, but this works and is much
422                  * simpler.
423                  */
424                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
425                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
426                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
427         }
428         return mode;
429 }
430
431 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
432                                                struct drm_connector *connector)
433 {
434         struct drm_device *dev = encoder->dev;
435         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
436         struct drm_display_mode *mode = NULL;
437         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
438         int i;
439         static const struct mode_size {
440                 int w;
441                 int h;
442         } common_modes[17] = {
443                 { 640,  480},
444                 { 720,  480},
445                 { 800,  600},
446                 { 848,  480},
447                 {1024,  768},
448                 {1152,  768},
449                 {1280,  720},
450                 {1280,  800},
451                 {1280,  854},
452                 {1280,  960},
453                 {1280, 1024},
454                 {1440,  900},
455                 {1400, 1050},
456                 {1680, 1050},
457                 {1600, 1200},
458                 {1920, 1080},
459                 {1920, 1200}
460         };
461
462         for (i = 0; i < 17; i++) {
463                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
464                         if (common_modes[i].w > 1024 ||
465                             common_modes[i].h > 768)
466                                 continue;
467                 }
468                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
469                         if (common_modes[i].w > native_mode->hdisplay ||
470                             common_modes[i].h > native_mode->vdisplay ||
471                             (common_modes[i].w == native_mode->hdisplay &&
472                              common_modes[i].h == native_mode->vdisplay))
473                                 continue;
474                 }
475                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
476                         continue;
477
478                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
479                 drm_mode_probed_add(connector, mode);
480         }
481 }
482
483 static int amdgpu_connector_set_property(struct drm_connector *connector,
484                                           struct drm_property *property,
485                                           uint64_t val)
486 {
487         struct drm_device *dev = connector->dev;
488         struct amdgpu_device *adev = dev->dev_private;
489         struct drm_encoder *encoder;
490         struct amdgpu_encoder *amdgpu_encoder;
491
492         if (property == adev->mode_info.coherent_mode_property) {
493                 struct amdgpu_encoder_atom_dig *dig;
494                 bool new_coherent_mode;
495
496                 /* need to find digital encoder on connector */
497                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
498                 if (!encoder)
499                         return 0;
500
501                 amdgpu_encoder = to_amdgpu_encoder(encoder);
502
503                 if (!amdgpu_encoder->enc_priv)
504                         return 0;
505
506                 dig = amdgpu_encoder->enc_priv;
507                 new_coherent_mode = val ? true : false;
508                 if (dig->coherent_mode != new_coherent_mode) {
509                         dig->coherent_mode = new_coherent_mode;
510                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
511                 }
512         }
513
514         if (property == adev->mode_info.audio_property) {
515                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
516                 /* need to find digital encoder on connector */
517                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
518                 if (!encoder)
519                         return 0;
520
521                 amdgpu_encoder = to_amdgpu_encoder(encoder);
522
523                 if (amdgpu_connector->audio != val) {
524                         amdgpu_connector->audio = val;
525                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
526                 }
527         }
528
529         if (property == adev->mode_info.dither_property) {
530                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
531                 /* need to find digital encoder on connector */
532                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
533                 if (!encoder)
534                         return 0;
535
536                 amdgpu_encoder = to_amdgpu_encoder(encoder);
537
538                 if (amdgpu_connector->dither != val) {
539                         amdgpu_connector->dither = val;
540                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
541                 }
542         }
543
544         if (property == adev->mode_info.underscan_property) {
545                 /* need to find digital encoder on connector */
546                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
547                 if (!encoder)
548                         return 0;
549
550                 amdgpu_encoder = to_amdgpu_encoder(encoder);
551
552                 if (amdgpu_encoder->underscan_type != val) {
553                         amdgpu_encoder->underscan_type = val;
554                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
555                 }
556         }
557
558         if (property == adev->mode_info.underscan_hborder_property) {
559                 /* need to find digital encoder on connector */
560                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
561                 if (!encoder)
562                         return 0;
563
564                 amdgpu_encoder = to_amdgpu_encoder(encoder);
565
566                 if (amdgpu_encoder->underscan_hborder != val) {
567                         amdgpu_encoder->underscan_hborder = val;
568                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
569                 }
570         }
571
572         if (property == adev->mode_info.underscan_vborder_property) {
573                 /* need to find digital encoder on connector */
574                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
575                 if (!encoder)
576                         return 0;
577
578                 amdgpu_encoder = to_amdgpu_encoder(encoder);
579
580                 if (amdgpu_encoder->underscan_vborder != val) {
581                         amdgpu_encoder->underscan_vborder = val;
582                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
583                 }
584         }
585
586         if (property == adev->mode_info.load_detect_property) {
587                 struct amdgpu_connector *amdgpu_connector =
588                         to_amdgpu_connector(connector);
589
590                 if (val == 0)
591                         amdgpu_connector->dac_load_detect = false;
592                 else
593                         amdgpu_connector->dac_load_detect = true;
594         }
595
596         if (property == dev->mode_config.scaling_mode_property) {
597                 enum amdgpu_rmx_type rmx_type;
598
599                 if (connector->encoder) {
600                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
601                 } else {
602                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
603                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
604                 }
605
606                 switch (val) {
607                 default:
608                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
609                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
610                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
611                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
612                 }
613                 if (amdgpu_encoder->rmx_type == rmx_type)
614                         return 0;
615
616                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
617                     (amdgpu_encoder->native_mode.clock == 0))
618                         return 0;
619
620                 amdgpu_encoder->rmx_type = rmx_type;
621
622                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
623         }
624
625         return 0;
626 }
627
628 static void
629 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
630                                         struct drm_connector *connector)
631 {
632         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
633         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
634         struct drm_display_mode *t, *mode;
635
636         /* If the EDID preferred mode doesn't match the native mode, use it */
637         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
638                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
639                         if (mode->hdisplay != native_mode->hdisplay ||
640                             mode->vdisplay != native_mode->vdisplay)
641                                 memcpy(native_mode, mode, sizeof(*mode));
642                 }
643         }
644
645         /* Try to get native mode details from EDID if necessary */
646         if (!native_mode->clock) {
647                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
648                         if (mode->hdisplay == native_mode->hdisplay &&
649                             mode->vdisplay == native_mode->vdisplay) {
650                                 *native_mode = *mode;
651                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
652                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
653                                 break;
654                         }
655                 }
656         }
657
658         if (!native_mode->clock) {
659                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
660                 amdgpu_encoder->rmx_type = RMX_OFF;
661         }
662 }
663
664 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
665 {
666         struct drm_encoder *encoder;
667         int ret = 0;
668         struct drm_display_mode *mode;
669
670         amdgpu_connector_get_edid(connector);
671         ret = amdgpu_connector_ddc_get_modes(connector);
672         if (ret > 0) {
673                 encoder = amdgpu_connector_best_single_encoder(connector);
674                 if (encoder) {
675                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
676                         /* add scaled modes */
677                         amdgpu_connector_add_common_modes(encoder, connector);
678                 }
679                 return ret;
680         }
681
682         encoder = amdgpu_connector_best_single_encoder(connector);
683         if (!encoder)
684                 return 0;
685
686         /* we have no EDID modes */
687         mode = amdgpu_connector_lcd_native_mode(encoder);
688         if (mode) {
689                 ret = 1;
690                 drm_mode_probed_add(connector, mode);
691                 /* add the width/height from vbios tables if available */
692                 connector->display_info.width_mm = mode->width_mm;
693                 connector->display_info.height_mm = mode->height_mm;
694                 /* add scaled modes */
695                 amdgpu_connector_add_common_modes(encoder, connector);
696         }
697
698         return ret;
699 }
700
701 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
702                                              struct drm_display_mode *mode)
703 {
704         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
705
706         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
707                 return MODE_PANEL;
708
709         if (encoder) {
710                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
711                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
712
713                 /* AVIVO hardware supports downscaling modes larger than the panel
714                  * to the panel size, but I'm not sure this is desirable.
715                  */
716                 if ((mode->hdisplay > native_mode->hdisplay) ||
717                     (mode->vdisplay > native_mode->vdisplay))
718                         return MODE_PANEL;
719
720                 /* if scaling is disabled, block non-native modes */
721                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
722                         if ((mode->hdisplay != native_mode->hdisplay) ||
723                             (mode->vdisplay != native_mode->vdisplay))
724                                 return MODE_PANEL;
725                 }
726         }
727
728         return MODE_OK;
729 }
730
731 static enum drm_connector_status
732 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
733 {
734         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
735         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
736         enum drm_connector_status ret = connector_status_disconnected;
737         int r;
738
739         r = pm_runtime_get_sync(connector->dev->dev);
740         if (r < 0)
741                 return connector_status_disconnected;
742
743         if (encoder) {
744                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
745                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
746
747                 /* check if panel is valid */
748                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
749                         ret = connector_status_connected;
750
751         }
752
753         /* check for edid as well */
754         amdgpu_connector_get_edid(connector);
755         if (amdgpu_connector->edid)
756                 ret = connector_status_connected;
757         /* check acpi lid status ??? */
758
759         amdgpu_connector_update_scratch_regs(connector, ret);
760         pm_runtime_mark_last_busy(connector->dev->dev);
761         pm_runtime_put_autosuspend(connector->dev->dev);
762         return ret;
763 }
764
765 static void amdgpu_connector_unregister(struct drm_connector *connector)
766 {
767         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
768
769         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
770                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
771                 amdgpu_connector->ddc_bus->has_aux = false;
772         }
773 }
774
775 static void amdgpu_connector_destroy(struct drm_connector *connector)
776 {
777         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
778
779         amdgpu_connector_free_edid(connector);
780         kfree(amdgpu_connector->con_priv);
781         drm_connector_unregister(connector);
782         drm_connector_cleanup(connector);
783         kfree(connector);
784 }
785
786 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
787                                               struct drm_property *property,
788                                               uint64_t value)
789 {
790         struct drm_device *dev = connector->dev;
791         struct amdgpu_encoder *amdgpu_encoder;
792         enum amdgpu_rmx_type rmx_type;
793
794         DRM_DEBUG_KMS("\n");
795         if (property != dev->mode_config.scaling_mode_property)
796                 return 0;
797
798         if (connector->encoder)
799                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
800         else {
801                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
802                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
803         }
804
805         switch (value) {
806         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
807         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
808         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
809         default:
810         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
811         }
812         if (amdgpu_encoder->rmx_type == rmx_type)
813                 return 0;
814
815         amdgpu_encoder->rmx_type = rmx_type;
816
817         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
818         return 0;
819 }
820
821
822 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
823         .get_modes = amdgpu_connector_lvds_get_modes,
824         .mode_valid = amdgpu_connector_lvds_mode_valid,
825         .best_encoder = amdgpu_connector_best_single_encoder,
826 };
827
828 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
829         .dpms = drm_helper_connector_dpms,
830         .detect = amdgpu_connector_lvds_detect,
831         .fill_modes = drm_helper_probe_single_connector_modes,
832         .early_unregister = amdgpu_connector_unregister,
833         .destroy = amdgpu_connector_destroy,
834         .set_property = amdgpu_connector_set_lcd_property,
835 };
836
837 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
838 {
839         int ret;
840
841         amdgpu_connector_get_edid(connector);
842         ret = amdgpu_connector_ddc_get_modes(connector);
843
844         return ret;
845 }
846
847 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
848                                             struct drm_display_mode *mode)
849 {
850         struct drm_device *dev = connector->dev;
851         struct amdgpu_device *adev = dev->dev_private;
852
853         /* XXX check mode bandwidth */
854
855         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
856                 return MODE_CLOCK_HIGH;
857
858         return MODE_OK;
859 }
860
861 static enum drm_connector_status
862 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
863 {
864         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
865         struct drm_encoder *encoder;
866         const struct drm_encoder_helper_funcs *encoder_funcs;
867         bool dret = false;
868         enum drm_connector_status ret = connector_status_disconnected;
869         int r;
870
871         r = pm_runtime_get_sync(connector->dev->dev);
872         if (r < 0)
873                 return connector_status_disconnected;
874
875         encoder = amdgpu_connector_best_single_encoder(connector);
876         if (!encoder)
877                 ret = connector_status_disconnected;
878
879         if (amdgpu_connector->ddc_bus)
880                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
881         if (dret) {
882                 amdgpu_connector->detected_by_load = false;
883                 amdgpu_connector_free_edid(connector);
884                 amdgpu_connector_get_edid(connector);
885
886                 if (!amdgpu_connector->edid) {
887                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
888                                         connector->name);
889                         ret = connector_status_connected;
890                 } else {
891                         amdgpu_connector->use_digital =
892                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
893
894                         /* some oems have boards with separate digital and analog connectors
895                          * with a shared ddc line (often vga + hdmi)
896                          */
897                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
898                                 amdgpu_connector_free_edid(connector);
899                                 ret = connector_status_disconnected;
900                         } else {
901                                 ret = connector_status_connected;
902                         }
903                 }
904         } else {
905
906                 /* if we aren't forcing don't do destructive polling */
907                 if (!force) {
908                         /* only return the previous status if we last
909                          * detected a monitor via load.
910                          */
911                         if (amdgpu_connector->detected_by_load)
912                                 ret = connector->status;
913                         goto out;
914                 }
915
916                 if (amdgpu_connector->dac_load_detect && encoder) {
917                         encoder_funcs = encoder->helper_private;
918                         ret = encoder_funcs->detect(encoder, connector);
919                         if (ret != connector_status_disconnected)
920                                 amdgpu_connector->detected_by_load = true;
921                 }
922         }
923
924         amdgpu_connector_update_scratch_regs(connector, ret);
925
926 out:
927         pm_runtime_mark_last_busy(connector->dev->dev);
928         pm_runtime_put_autosuspend(connector->dev->dev);
929
930         return ret;
931 }
932
933 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
934         .get_modes = amdgpu_connector_vga_get_modes,
935         .mode_valid = amdgpu_connector_vga_mode_valid,
936         .best_encoder = amdgpu_connector_best_single_encoder,
937 };
938
939 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
940         .dpms = drm_helper_connector_dpms,
941         .detect = amdgpu_connector_vga_detect,
942         .fill_modes = drm_helper_probe_single_connector_modes,
943         .early_unregister = amdgpu_connector_unregister,
944         .destroy = amdgpu_connector_destroy,
945         .set_property = amdgpu_connector_set_property,
946 };
947
948 static bool
949 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
950 {
951         struct drm_device *dev = connector->dev;
952         struct amdgpu_device *adev = dev->dev_private;
953         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
954         enum drm_connector_status status;
955
956         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
957                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
958                         status = connector_status_connected;
959                 else
960                         status = connector_status_disconnected;
961                 if (connector->status == status)
962                         return true;
963         }
964
965         return false;
966 }
967
968 /*
969  * DVI is complicated
970  * Do a DDC probe, if DDC probe passes, get the full EDID so
971  * we can do analog/digital monitor detection at this point.
972  * If the monitor is an analog monitor or we got no DDC,
973  * we need to find the DAC encoder object for this connector.
974  * If we got no DDC, we do load detection on the DAC encoder object.
975  * If we got analog DDC or load detection passes on the DAC encoder
976  * we have to check if this analog encoder is shared with anyone else (TV)
977  * if its shared we have to set the other connector to disconnected.
978  */
979 static enum drm_connector_status
980 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
981 {
982         struct drm_device *dev = connector->dev;
983         struct amdgpu_device *adev = dev->dev_private;
984         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
985         struct drm_encoder *encoder = NULL;
986         const struct drm_encoder_helper_funcs *encoder_funcs;
987         int i, r;
988         enum drm_connector_status ret = connector_status_disconnected;
989         bool dret = false, broken_edid = false;
990
991         r = pm_runtime_get_sync(connector->dev->dev);
992         if (r < 0)
993                 return connector_status_disconnected;
994
995         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
996                 ret = connector->status;
997                 goto exit;
998         }
999
1000         if (amdgpu_connector->ddc_bus)
1001                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1002         if (dret) {
1003                 amdgpu_connector->detected_by_load = false;
1004                 amdgpu_connector_free_edid(connector);
1005                 amdgpu_connector_get_edid(connector);
1006
1007                 if (!amdgpu_connector->edid) {
1008                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1009                                         connector->name);
1010                         ret = connector_status_connected;
1011                         broken_edid = true; /* defer use_digital to later */
1012                 } else {
1013                         amdgpu_connector->use_digital =
1014                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1015
1016                         /* some oems have boards with separate digital and analog connectors
1017                          * with a shared ddc line (often vga + hdmi)
1018                          */
1019                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1020                                 amdgpu_connector_free_edid(connector);
1021                                 ret = connector_status_disconnected;
1022                         } else {
1023                                 ret = connector_status_connected;
1024                         }
1025
1026                         /* This gets complicated.  We have boards with VGA + HDMI with a
1027                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1028                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1029                          * you don't really know what's connected to which port as both are digital.
1030                          */
1031                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1032                                 struct drm_connector *list_connector;
1033                                 struct amdgpu_connector *list_amdgpu_connector;
1034                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1035                                         if (connector == list_connector)
1036                                                 continue;
1037                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1038                                         if (list_amdgpu_connector->shared_ddc &&
1039                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1040                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1041                                                 /* cases where both connectors are digital */
1042                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1043                                                         /* hpd is our only option in this case */
1044                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1045                                                                 amdgpu_connector_free_edid(connector);
1046                                                                 ret = connector_status_disconnected;
1047                                                         }
1048                                                 }
1049                                         }
1050                                 }
1051                         }
1052                 }
1053         }
1054
1055         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1056                 goto out;
1057
1058         /* DVI-D and HDMI-A are digital only */
1059         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1060             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1061                 goto out;
1062
1063         /* if we aren't forcing don't do destructive polling */
1064         if (!force) {
1065                 /* only return the previous status if we last
1066                  * detected a monitor via load.
1067                  */
1068                 if (amdgpu_connector->detected_by_load)
1069                         ret = connector->status;
1070                 goto out;
1071         }
1072
1073         /* find analog encoder */
1074         if (amdgpu_connector->dac_load_detect) {
1075                 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1076                         if (connector->encoder_ids[i] == 0)
1077                                 break;
1078
1079                         encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
1080                         if (!encoder)
1081                                 continue;
1082
1083                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1084                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1085                                 continue;
1086
1087                         encoder_funcs = encoder->helper_private;
1088                         if (encoder_funcs->detect) {
1089                                 if (!broken_edid) {
1090                                         if (ret != connector_status_connected) {
1091                                                 /* deal with analog monitors without DDC */
1092                                                 ret = encoder_funcs->detect(encoder, connector);
1093                                                 if (ret == connector_status_connected) {
1094                                                         amdgpu_connector->use_digital = false;
1095                                                 }
1096                                                 if (ret != connector_status_disconnected)
1097                                                         amdgpu_connector->detected_by_load = true;
1098                                         }
1099                                 } else {
1100                                         enum drm_connector_status lret;
1101                                         /* assume digital unless load detected otherwise */
1102                                         amdgpu_connector->use_digital = true;
1103                                         lret = encoder_funcs->detect(encoder, connector);
1104                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1105                                         if (lret == connector_status_connected)
1106                                                 amdgpu_connector->use_digital = false;
1107                                 }
1108                                 break;
1109                         }
1110                 }
1111         }
1112
1113 out:
1114         /* updated in get modes as well since we need to know if it's analog or digital */
1115         amdgpu_connector_update_scratch_regs(connector, ret);
1116
1117 exit:
1118         pm_runtime_mark_last_busy(connector->dev->dev);
1119         pm_runtime_put_autosuspend(connector->dev->dev);
1120
1121         return ret;
1122 }
1123
1124 /* okay need to be smart in here about which encoder to pick */
1125 static struct drm_encoder *
1126 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1127 {
1128         int enc_id = connector->encoder_ids[0];
1129         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1130         struct drm_encoder *encoder;
1131         int i;
1132         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1133                 if (connector->encoder_ids[i] == 0)
1134                         break;
1135
1136                 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
1137                 if (!encoder)
1138                         continue;
1139
1140                 if (amdgpu_connector->use_digital == true) {
1141                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1142                                 return encoder;
1143                 } else {
1144                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1145                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1146                                 return encoder;
1147                 }
1148         }
1149
1150         /* see if we have a default encoder  TODO */
1151
1152         /* then check use digitial */
1153         /* pick the first one */
1154         if (enc_id)
1155                 return drm_encoder_find(connector->dev, NULL, enc_id);
1156         return NULL;
1157 }
1158
1159 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1160 {
1161         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1162         if (connector->force == DRM_FORCE_ON)
1163                 amdgpu_connector->use_digital = false;
1164         if (connector->force == DRM_FORCE_ON_DIGITAL)
1165                 amdgpu_connector->use_digital = true;
1166 }
1167
1168 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1169                                             struct drm_display_mode *mode)
1170 {
1171         struct drm_device *dev = connector->dev;
1172         struct amdgpu_device *adev = dev->dev_private;
1173         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1174
1175         /* XXX check mode bandwidth */
1176
1177         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1178                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1179                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1180                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1181                         return MODE_OK;
1182                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1183                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1184                         if (mode->clock > 340000)
1185                                 return MODE_CLOCK_HIGH;
1186                         else
1187                                 return MODE_OK;
1188                 } else {
1189                         return MODE_CLOCK_HIGH;
1190                 }
1191         }
1192
1193         /* check against the max pixel clock */
1194         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1195                 return MODE_CLOCK_HIGH;
1196
1197         return MODE_OK;
1198 }
1199
1200 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1201         .get_modes = amdgpu_connector_vga_get_modes,
1202         .mode_valid = amdgpu_connector_dvi_mode_valid,
1203         .best_encoder = amdgpu_connector_dvi_encoder,
1204 };
1205
1206 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1207         .dpms = drm_helper_connector_dpms,
1208         .detect = amdgpu_connector_dvi_detect,
1209         .fill_modes = drm_helper_probe_single_connector_modes,
1210         .set_property = amdgpu_connector_set_property,
1211         .early_unregister = amdgpu_connector_unregister,
1212         .destroy = amdgpu_connector_destroy,
1213         .force = amdgpu_connector_dvi_force,
1214 };
1215
1216 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1217 {
1218         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1219         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1220         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1221         int ret;
1222
1223         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1224             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1225                 struct drm_display_mode *mode;
1226
1227                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1228                         if (!amdgpu_dig_connector->edp_on)
1229                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1230                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1231                         amdgpu_connector_get_edid(connector);
1232                         ret = amdgpu_connector_ddc_get_modes(connector);
1233                         if (!amdgpu_dig_connector->edp_on)
1234                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1235                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1236                 } else {
1237                         /* need to setup ddc on the bridge */
1238                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1239                             ENCODER_OBJECT_ID_NONE) {
1240                                 if (encoder)
1241                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1242                         }
1243                         amdgpu_connector_get_edid(connector);
1244                         ret = amdgpu_connector_ddc_get_modes(connector);
1245                 }
1246
1247                 if (ret > 0) {
1248                         if (encoder) {
1249                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1250                                 /* add scaled modes */
1251                                 amdgpu_connector_add_common_modes(encoder, connector);
1252                         }
1253                         return ret;
1254                 }
1255
1256                 if (!encoder)
1257                         return 0;
1258
1259                 /* we have no EDID modes */
1260                 mode = amdgpu_connector_lcd_native_mode(encoder);
1261                 if (mode) {
1262                         ret = 1;
1263                         drm_mode_probed_add(connector, mode);
1264                         /* add the width/height from vbios tables if available */
1265                         connector->display_info.width_mm = mode->width_mm;
1266                         connector->display_info.height_mm = mode->height_mm;
1267                         /* add scaled modes */
1268                         amdgpu_connector_add_common_modes(encoder, connector);
1269                 }
1270         } else {
1271                 /* need to setup ddc on the bridge */
1272                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1273                         ENCODER_OBJECT_ID_NONE) {
1274                         if (encoder)
1275                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1276                 }
1277                 amdgpu_connector_get_edid(connector);
1278                 ret = amdgpu_connector_ddc_get_modes(connector);
1279
1280                 amdgpu_get_native_mode(connector);
1281         }
1282
1283         return ret;
1284 }
1285
1286 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1287 {
1288         struct drm_encoder *encoder;
1289         struct amdgpu_encoder *amdgpu_encoder;
1290         int i;
1291
1292         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1293                 if (connector->encoder_ids[i] == 0)
1294                         break;
1295
1296                 encoder = drm_encoder_find(connector->dev, NULL,
1297                                         connector->encoder_ids[i]);
1298                 if (!encoder)
1299                         continue;
1300
1301                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1302
1303                 switch (amdgpu_encoder->encoder_id) {
1304                 case ENCODER_OBJECT_ID_TRAVIS:
1305                 case ENCODER_OBJECT_ID_NUTMEG:
1306                         return amdgpu_encoder->encoder_id;
1307                 default:
1308                         break;
1309                 }
1310         }
1311
1312         return ENCODER_OBJECT_ID_NONE;
1313 }
1314
1315 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1316 {
1317         struct drm_encoder *encoder;
1318         struct amdgpu_encoder *amdgpu_encoder;
1319         int i;
1320         bool found = false;
1321
1322         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1323                 if (connector->encoder_ids[i] == 0)
1324                         break;
1325                 encoder = drm_encoder_find(connector->dev, NULL,
1326                                         connector->encoder_ids[i]);
1327                 if (!encoder)
1328                         continue;
1329
1330                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1331                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1332                         found = true;
1333         }
1334
1335         return found;
1336 }
1337
1338 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1339 {
1340         struct drm_device *dev = connector->dev;
1341         struct amdgpu_device *adev = dev->dev_private;
1342
1343         if ((adev->clock.default_dispclk >= 53900) &&
1344             amdgpu_connector_encoder_is_hbr2(connector)) {
1345                 return true;
1346         }
1347
1348         return false;
1349 }
1350
1351 static enum drm_connector_status
1352 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1353 {
1354         struct drm_device *dev = connector->dev;
1355         struct amdgpu_device *adev = dev->dev_private;
1356         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1357         enum drm_connector_status ret = connector_status_disconnected;
1358         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1359         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1360         int r;
1361
1362         r = pm_runtime_get_sync(connector->dev->dev);
1363         if (r < 0)
1364                 return connector_status_disconnected;
1365
1366         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1367                 ret = connector->status;
1368                 goto out;
1369         }
1370
1371         amdgpu_connector_free_edid(connector);
1372
1373         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1374             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1375                 if (encoder) {
1376                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1377                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1378
1379                         /* check if panel is valid */
1380                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1381                                 ret = connector_status_connected;
1382                 }
1383                 /* eDP is always DP */
1384                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1385                 if (!amdgpu_dig_connector->edp_on)
1386                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1387                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1388                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1389                         ret = connector_status_connected;
1390                 if (!amdgpu_dig_connector->edp_on)
1391                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1392                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1393         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1394                    ENCODER_OBJECT_ID_NONE) {
1395                 /* DP bridges are always DP */
1396                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1397                 /* get the DPCD from the bridge */
1398                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1399
1400                 if (encoder) {
1401                         /* setup ddc on the bridge */
1402                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1403                         /* bridge chips are always aux */
1404                         if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1405                                 ret = connector_status_connected;
1406                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1407                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1408                                 ret = encoder_funcs->detect(encoder, connector);
1409                         }
1410                 }
1411         } else {
1412                 amdgpu_dig_connector->dp_sink_type =
1413                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1414                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1415                         ret = connector_status_connected;
1416                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1417                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1418                 } else {
1419                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1420                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1421                                         ret = connector_status_connected;
1422                         } else {
1423                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1424                                 if (amdgpu_ddc_probe(amdgpu_connector, false))
1425                                         ret = connector_status_connected;
1426                         }
1427                 }
1428         }
1429
1430         amdgpu_connector_update_scratch_regs(connector, ret);
1431 out:
1432         pm_runtime_mark_last_busy(connector->dev->dev);
1433         pm_runtime_put_autosuspend(connector->dev->dev);
1434
1435         return ret;
1436 }
1437
1438 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1439                                            struct drm_display_mode *mode)
1440 {
1441         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1442         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1443
1444         /* XXX check mode bandwidth */
1445
1446         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1447             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1448                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1449
1450                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1451                         return MODE_PANEL;
1452
1453                 if (encoder) {
1454                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1455                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1456
1457                         /* AVIVO hardware supports downscaling modes larger than the panel
1458                          * to the panel size, but I'm not sure this is desirable.
1459                          */
1460                         if ((mode->hdisplay > native_mode->hdisplay) ||
1461                             (mode->vdisplay > native_mode->vdisplay))
1462                                 return MODE_PANEL;
1463
1464                         /* if scaling is disabled, block non-native modes */
1465                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1466                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1467                                     (mode->vdisplay != native_mode->vdisplay))
1468                                         return MODE_PANEL;
1469                         }
1470                 }
1471                 return MODE_OK;
1472         } else {
1473                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1474                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1475                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1476                 } else {
1477                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1478                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1479                                 if (mode->clock > 340000)
1480                                         return MODE_CLOCK_HIGH;
1481                         } else {
1482                                 if (mode->clock > 165000)
1483                                         return MODE_CLOCK_HIGH;
1484                         }
1485                 }
1486         }
1487
1488         return MODE_OK;
1489 }
1490
1491 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1492         .get_modes = amdgpu_connector_dp_get_modes,
1493         .mode_valid = amdgpu_connector_dp_mode_valid,
1494         .best_encoder = amdgpu_connector_dvi_encoder,
1495 };
1496
1497 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1498         .dpms = drm_helper_connector_dpms,
1499         .detect = amdgpu_connector_dp_detect,
1500         .fill_modes = drm_helper_probe_single_connector_modes,
1501         .set_property = amdgpu_connector_set_property,
1502         .early_unregister = amdgpu_connector_unregister,
1503         .destroy = amdgpu_connector_destroy,
1504         .force = amdgpu_connector_dvi_force,
1505 };
1506
1507 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1508         .dpms = drm_helper_connector_dpms,
1509         .detect = amdgpu_connector_dp_detect,
1510         .fill_modes = drm_helper_probe_single_connector_modes,
1511         .set_property = amdgpu_connector_set_lcd_property,
1512         .early_unregister = amdgpu_connector_unregister,
1513         .destroy = amdgpu_connector_destroy,
1514         .force = amdgpu_connector_dvi_force,
1515 };
1516
1517 void
1518 amdgpu_connector_add(struct amdgpu_device *adev,
1519                       uint32_t connector_id,
1520                       uint32_t supported_device,
1521                       int connector_type,
1522                       struct amdgpu_i2c_bus_rec *i2c_bus,
1523                       uint16_t connector_object_id,
1524                       struct amdgpu_hpd *hpd,
1525                       struct amdgpu_router *router)
1526 {
1527         struct drm_device *dev = adev->ddev;
1528         struct drm_connector *connector;
1529         struct amdgpu_connector *amdgpu_connector;
1530         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1531         struct drm_encoder *encoder;
1532         struct amdgpu_encoder *amdgpu_encoder;
1533         uint32_t subpixel_order = SubPixelNone;
1534         bool shared_ddc = false;
1535         bool is_dp_bridge = false;
1536         bool has_aux = false;
1537
1538         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1539                 return;
1540
1541         /* see if we already added it */
1542         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1543                 amdgpu_connector = to_amdgpu_connector(connector);
1544                 if (amdgpu_connector->connector_id == connector_id) {
1545                         amdgpu_connector->devices |= supported_device;
1546                         return;
1547                 }
1548                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1549                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1550                                 amdgpu_connector->shared_ddc = true;
1551                                 shared_ddc = true;
1552                         }
1553                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1554                             (amdgpu_connector->router.router_id == router->router_id)) {
1555                                 amdgpu_connector->shared_ddc = false;
1556                                 shared_ddc = false;
1557                         }
1558                 }
1559         }
1560
1561         /* check if it's a dp bridge */
1562         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1563                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1564                 if (amdgpu_encoder->devices & supported_device) {
1565                         switch (amdgpu_encoder->encoder_id) {
1566                         case ENCODER_OBJECT_ID_TRAVIS:
1567                         case ENCODER_OBJECT_ID_NUTMEG:
1568                                 is_dp_bridge = true;
1569                                 break;
1570                         default:
1571                                 break;
1572                         }
1573                 }
1574         }
1575
1576         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1577         if (!amdgpu_connector)
1578                 return;
1579
1580         connector = &amdgpu_connector->base;
1581
1582         amdgpu_connector->connector_id = connector_id;
1583         amdgpu_connector->devices = supported_device;
1584         amdgpu_connector->shared_ddc = shared_ddc;
1585         amdgpu_connector->connector_object_id = connector_object_id;
1586         amdgpu_connector->hpd = *hpd;
1587
1588         amdgpu_connector->router = *router;
1589         if (router->ddc_valid || router->cd_valid) {
1590                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1591                 if (!amdgpu_connector->router_bus)
1592                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1593         }
1594
1595         if (is_dp_bridge) {
1596                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1597                 if (!amdgpu_dig_connector)
1598                         goto failed;
1599                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1600                 if (i2c_bus->valid) {
1601                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1602                         if (amdgpu_connector->ddc_bus)
1603                                 has_aux = true;
1604                         else
1605                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1606                 }
1607                 switch (connector_type) {
1608                 case DRM_MODE_CONNECTOR_VGA:
1609                 case DRM_MODE_CONNECTOR_DVIA:
1610                 default:
1611                         drm_connector_init(dev, &amdgpu_connector->base,
1612                                            &amdgpu_connector_dp_funcs, connector_type);
1613                         drm_connector_helper_add(&amdgpu_connector->base,
1614                                                  &amdgpu_connector_dp_helper_funcs);
1615                         connector->interlace_allowed = true;
1616                         connector->doublescan_allowed = true;
1617                         amdgpu_connector->dac_load_detect = true;
1618                         drm_object_attach_property(&amdgpu_connector->base.base,
1619                                                       adev->mode_info.load_detect_property,
1620                                                       1);
1621                         drm_object_attach_property(&amdgpu_connector->base.base,
1622                                                    dev->mode_config.scaling_mode_property,
1623                                                    DRM_MODE_SCALE_NONE);
1624                         break;
1625                 case DRM_MODE_CONNECTOR_DVII:
1626                 case DRM_MODE_CONNECTOR_DVID:
1627                 case DRM_MODE_CONNECTOR_HDMIA:
1628                 case DRM_MODE_CONNECTOR_HDMIB:
1629                 case DRM_MODE_CONNECTOR_DisplayPort:
1630                         drm_connector_init(dev, &amdgpu_connector->base,
1631                                            &amdgpu_connector_dp_funcs, connector_type);
1632                         drm_connector_helper_add(&amdgpu_connector->base,
1633                                                  &amdgpu_connector_dp_helper_funcs);
1634                         drm_object_attach_property(&amdgpu_connector->base.base,
1635                                                       adev->mode_info.underscan_property,
1636                                                       UNDERSCAN_OFF);
1637                         drm_object_attach_property(&amdgpu_connector->base.base,
1638                                                       adev->mode_info.underscan_hborder_property,
1639                                                       0);
1640                         drm_object_attach_property(&amdgpu_connector->base.base,
1641                                                       adev->mode_info.underscan_vborder_property,
1642                                                       0);
1643
1644                         drm_object_attach_property(&amdgpu_connector->base.base,
1645                                                    dev->mode_config.scaling_mode_property,
1646                                                    DRM_MODE_SCALE_NONE);
1647
1648                         drm_object_attach_property(&amdgpu_connector->base.base,
1649                                                    adev->mode_info.dither_property,
1650                                                    AMDGPU_FMT_DITHER_DISABLE);
1651
1652                         if (amdgpu_audio != 0)
1653                                 drm_object_attach_property(&amdgpu_connector->base.base,
1654                                                            adev->mode_info.audio_property,
1655                                                            AMDGPU_AUDIO_AUTO);
1656
1657                         subpixel_order = SubPixelHorizontalRGB;
1658                         connector->interlace_allowed = true;
1659                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1660                                 connector->doublescan_allowed = true;
1661                         else
1662                                 connector->doublescan_allowed = false;
1663                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1664                                 amdgpu_connector->dac_load_detect = true;
1665                                 drm_object_attach_property(&amdgpu_connector->base.base,
1666                                                               adev->mode_info.load_detect_property,
1667                                                               1);
1668                         }
1669                         break;
1670                 case DRM_MODE_CONNECTOR_LVDS:
1671                 case DRM_MODE_CONNECTOR_eDP:
1672                         drm_connector_init(dev, &amdgpu_connector->base,
1673                                            &amdgpu_connector_edp_funcs, connector_type);
1674                         drm_connector_helper_add(&amdgpu_connector->base,
1675                                                  &amdgpu_connector_dp_helper_funcs);
1676                         drm_object_attach_property(&amdgpu_connector->base.base,
1677                                                       dev->mode_config.scaling_mode_property,
1678                                                       DRM_MODE_SCALE_FULLSCREEN);
1679                         subpixel_order = SubPixelHorizontalRGB;
1680                         connector->interlace_allowed = false;
1681                         connector->doublescan_allowed = false;
1682                         break;
1683                 }
1684         } else {
1685                 switch (connector_type) {
1686                 case DRM_MODE_CONNECTOR_VGA:
1687                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1688                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1689                         if (i2c_bus->valid) {
1690                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1691                                 if (!amdgpu_connector->ddc_bus)
1692                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1693                         }
1694                         amdgpu_connector->dac_load_detect = true;
1695                         drm_object_attach_property(&amdgpu_connector->base.base,
1696                                                       adev->mode_info.load_detect_property,
1697                                                       1);
1698                         drm_object_attach_property(&amdgpu_connector->base.base,
1699                                                    dev->mode_config.scaling_mode_property,
1700                                                    DRM_MODE_SCALE_NONE);
1701                         /* no HPD on analog connectors */
1702                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1703                         connector->interlace_allowed = true;
1704                         connector->doublescan_allowed = true;
1705                         break;
1706                 case DRM_MODE_CONNECTOR_DVIA:
1707                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1708                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1709                         if (i2c_bus->valid) {
1710                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1711                                 if (!amdgpu_connector->ddc_bus)
1712                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1713                         }
1714                         amdgpu_connector->dac_load_detect = true;
1715                         drm_object_attach_property(&amdgpu_connector->base.base,
1716                                                       adev->mode_info.load_detect_property,
1717                                                       1);
1718                         drm_object_attach_property(&amdgpu_connector->base.base,
1719                                                    dev->mode_config.scaling_mode_property,
1720                                                    DRM_MODE_SCALE_NONE);
1721                         /* no HPD on analog connectors */
1722                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1723                         connector->interlace_allowed = true;
1724                         connector->doublescan_allowed = true;
1725                         break;
1726                 case DRM_MODE_CONNECTOR_DVII:
1727                 case DRM_MODE_CONNECTOR_DVID:
1728                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1729                         if (!amdgpu_dig_connector)
1730                                 goto failed;
1731                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1732                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1733                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1734                         if (i2c_bus->valid) {
1735                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1736                                 if (!amdgpu_connector->ddc_bus)
1737                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1738                         }
1739                         subpixel_order = SubPixelHorizontalRGB;
1740                         drm_object_attach_property(&amdgpu_connector->base.base,
1741                                                       adev->mode_info.coherent_mode_property,
1742                                                       1);
1743                         drm_object_attach_property(&amdgpu_connector->base.base,
1744                                                    adev->mode_info.underscan_property,
1745                                                    UNDERSCAN_OFF);
1746                         drm_object_attach_property(&amdgpu_connector->base.base,
1747                                                    adev->mode_info.underscan_hborder_property,
1748                                                    0);
1749                         drm_object_attach_property(&amdgpu_connector->base.base,
1750                                                    adev->mode_info.underscan_vborder_property,
1751                                                    0);
1752                         drm_object_attach_property(&amdgpu_connector->base.base,
1753                                                    dev->mode_config.scaling_mode_property,
1754                                                    DRM_MODE_SCALE_NONE);
1755
1756                         if (amdgpu_audio != 0) {
1757                                 drm_object_attach_property(&amdgpu_connector->base.base,
1758                                                            adev->mode_info.audio_property,
1759                                                            AMDGPU_AUDIO_AUTO);
1760                         }
1761                         drm_object_attach_property(&amdgpu_connector->base.base,
1762                                                    adev->mode_info.dither_property,
1763                                                    AMDGPU_FMT_DITHER_DISABLE);
1764                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1765                                 amdgpu_connector->dac_load_detect = true;
1766                                 drm_object_attach_property(&amdgpu_connector->base.base,
1767                                                            adev->mode_info.load_detect_property,
1768                                                            1);
1769                         }
1770                         connector->interlace_allowed = true;
1771                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1772                                 connector->doublescan_allowed = true;
1773                         else
1774                                 connector->doublescan_allowed = false;
1775                         break;
1776                 case DRM_MODE_CONNECTOR_HDMIA:
1777                 case DRM_MODE_CONNECTOR_HDMIB:
1778                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1779                         if (!amdgpu_dig_connector)
1780                                 goto failed;
1781                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1782                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1783                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1784                         if (i2c_bus->valid) {
1785                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1786                                 if (!amdgpu_connector->ddc_bus)
1787                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1788                         }
1789                         drm_object_attach_property(&amdgpu_connector->base.base,
1790                                                       adev->mode_info.coherent_mode_property,
1791                                                       1);
1792                         drm_object_attach_property(&amdgpu_connector->base.base,
1793                                                    adev->mode_info.underscan_property,
1794                                                    UNDERSCAN_OFF);
1795                         drm_object_attach_property(&amdgpu_connector->base.base,
1796                                                    adev->mode_info.underscan_hborder_property,
1797                                                    0);
1798                         drm_object_attach_property(&amdgpu_connector->base.base,
1799                                                    adev->mode_info.underscan_vborder_property,
1800                                                    0);
1801                         drm_object_attach_property(&amdgpu_connector->base.base,
1802                                                    dev->mode_config.scaling_mode_property,
1803                                                    DRM_MODE_SCALE_NONE);
1804                         if (amdgpu_audio != 0) {
1805                                 drm_object_attach_property(&amdgpu_connector->base.base,
1806                                                            adev->mode_info.audio_property,
1807                                                            AMDGPU_AUDIO_AUTO);
1808                         }
1809                         drm_object_attach_property(&amdgpu_connector->base.base,
1810                                                    adev->mode_info.dither_property,
1811                                                    AMDGPU_FMT_DITHER_DISABLE);
1812                         subpixel_order = SubPixelHorizontalRGB;
1813                         connector->interlace_allowed = true;
1814                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1815                                 connector->doublescan_allowed = true;
1816                         else
1817                                 connector->doublescan_allowed = false;
1818                         break;
1819                 case DRM_MODE_CONNECTOR_DisplayPort:
1820                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1821                         if (!amdgpu_dig_connector)
1822                                 goto failed;
1823                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1824                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1825                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1826                         if (i2c_bus->valid) {
1827                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1828                                 if (amdgpu_connector->ddc_bus)
1829                                         has_aux = true;
1830                                 else
1831                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1832                         }
1833                         subpixel_order = SubPixelHorizontalRGB;
1834                         drm_object_attach_property(&amdgpu_connector->base.base,
1835                                                       adev->mode_info.coherent_mode_property,
1836                                                       1);
1837                         drm_object_attach_property(&amdgpu_connector->base.base,
1838                                                    adev->mode_info.underscan_property,
1839                                                    UNDERSCAN_OFF);
1840                         drm_object_attach_property(&amdgpu_connector->base.base,
1841                                                    adev->mode_info.underscan_hborder_property,
1842                                                    0);
1843                         drm_object_attach_property(&amdgpu_connector->base.base,
1844                                                    adev->mode_info.underscan_vborder_property,
1845                                                    0);
1846                         drm_object_attach_property(&amdgpu_connector->base.base,
1847                                                    dev->mode_config.scaling_mode_property,
1848                                                    DRM_MODE_SCALE_NONE);
1849                         if (amdgpu_audio != 0) {
1850                                 drm_object_attach_property(&amdgpu_connector->base.base,
1851                                                            adev->mode_info.audio_property,
1852                                                            AMDGPU_AUDIO_AUTO);
1853                         }
1854                         drm_object_attach_property(&amdgpu_connector->base.base,
1855                                                    adev->mode_info.dither_property,
1856                                                    AMDGPU_FMT_DITHER_DISABLE);
1857                         connector->interlace_allowed = true;
1858                         /* in theory with a DP to VGA converter... */
1859                         connector->doublescan_allowed = false;
1860                         break;
1861                 case DRM_MODE_CONNECTOR_eDP:
1862                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1863                         if (!amdgpu_dig_connector)
1864                                 goto failed;
1865                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1866                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1867                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1868                         if (i2c_bus->valid) {
1869                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1870                                 if (amdgpu_connector->ddc_bus)
1871                                         has_aux = true;
1872                                 else
1873                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1874                         }
1875                         drm_object_attach_property(&amdgpu_connector->base.base,
1876                                                       dev->mode_config.scaling_mode_property,
1877                                                       DRM_MODE_SCALE_FULLSCREEN);
1878                         subpixel_order = SubPixelHorizontalRGB;
1879                         connector->interlace_allowed = false;
1880                         connector->doublescan_allowed = false;
1881                         break;
1882                 case DRM_MODE_CONNECTOR_LVDS:
1883                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1884                         if (!amdgpu_dig_connector)
1885                                 goto failed;
1886                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1887                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1888                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1889                         if (i2c_bus->valid) {
1890                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1891                                 if (!amdgpu_connector->ddc_bus)
1892                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1893                         }
1894                         drm_object_attach_property(&amdgpu_connector->base.base,
1895                                                       dev->mode_config.scaling_mode_property,
1896                                                       DRM_MODE_SCALE_FULLSCREEN);
1897                         subpixel_order = SubPixelHorizontalRGB;
1898                         connector->interlace_allowed = false;
1899                         connector->doublescan_allowed = false;
1900                         break;
1901                 }
1902         }
1903
1904         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1905                 if (i2c_bus->valid) {
1906                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1907                                             DRM_CONNECTOR_POLL_DISCONNECT;
1908                 }
1909         } else
1910                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1911
1912         connector->display_info.subpixel_order = subpixel_order;
1913         drm_connector_register(connector);
1914
1915         if (has_aux)
1916                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1917
1918         return;
1919
1920 failed:
1921         drm_connector_cleanup(connector);
1922         kfree(connector);
1923 }