drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_fb_helper.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "atom.h"
  33 #include "atombios_encoders.h"
  34 #include "atombios_dp.h"
  35 #include "amdgpu_connectors.h"
  36 #include "amdgpu_i2c.h"
  37
  38 #include <linux/pm_runtime.h>
  39
  40 void amdgpu_connector_hotplug(struct drm_connector *connector)
  41 {
  42         struct drm_device *dev = connector->dev;
  43         struct amdgpu_device *adev = dev->dev_private;
  44         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  45
  46         /* bail if the connector does not have hpd pin, e.g.,
  47          * VGA, TV, etc.
  48          */
  49         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  50                 return;
  51
  52         amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  53
  54         /* if the connector is already off, don't turn it back on */
  55         if (connector->dpms != DRM_MODE_DPMS_ON)
  56                 return;
  57
  58         /* just deal with DP (not eDP) here. */
  59         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  60                 struct amdgpu_connector_atom_dig *dig_connector =
  61                         amdgpu_connector->con_priv;
  62
  63                 /* if existing sink type was not DP no need to retrain */
  64                 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  65                         return;
  66
  67                 /* first get sink type as it may be reset after (un)plug */
  68                 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  69                 /* don't do anything if sink is not display port, i.e.,
  70                  * passive dp->(dvi|hdmi) adaptor
  71                  */
  72                 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
  73                         int saved_dpms = connector->dpms;
  74                         /* Only turn off the display if it's physically disconnected */
  75                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
  76                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  77                         } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  78                                 /* Don't try to start link training before we
  79                                  * have the dpcd */
  80                                 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  81                                         return;
  82
  83                                 /* set it to OFF so that drm_helper_connector_dpms()
  84                                  * won't return immediately since the current state
  85                                  * is ON at this point.
  86                                  */
  87                                 connector->dpms = DRM_MODE_DPMS_OFF;
  88                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  89                         }
  90                         connector->dpms = saved_dpms;
  91                 }
  92         }
  93 }
  94
  95 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  96 {
  97         struct drm_crtc *crtc = encoder->crtc;
  98
  99         if (crtc && crtc->enabled) {
 100                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
 101                                          crtc->x, crtc->y, crtc->primary->fb);
 102         }
 103 }
 104
 105 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
 106 {
 107         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 108         struct amdgpu_connector_atom_dig *dig_connector;
 109         int bpc = 8;
 110         unsigned mode_clock, max_tmds_clock;
 111
 112         switch (connector->connector_type) {
 113         case DRM_MODE_CONNECTOR_DVII:
 114         case DRM_MODE_CONNECTOR_HDMIB:
 115                 if (amdgpu_connector->use_digital) {
 116                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 117                                 if (connector->display_info.bpc)
 118                                         bpc = connector->display_info.bpc;
 119                         }
 120                 }
 121                 break;
 122         case DRM_MODE_CONNECTOR_DVID:
 123         case DRM_MODE_CONNECTOR_HDMIA:
 124                 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 125                         if (connector->display_info.bpc)
 126                                 bpc = connector->display_info.bpc;
 127                 }
 128                 break;
 129         case DRM_MODE_CONNECTOR_DisplayPort:
 130                 dig_connector = amdgpu_connector->con_priv;
 131                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 132                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 133                     drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 134                         if (connector->display_info.bpc)
 135                                 bpc = connector->display_info.bpc;
 136                 }
 137                 break;
 138         case DRM_MODE_CONNECTOR_eDP:
 139         case DRM_MODE_CONNECTOR_LVDS:
 140                 if (connector->display_info.bpc)
 141                         bpc = connector->display_info.bpc;
 142                 else {
 143                         const struct drm_connector_helper_funcs *connector_funcs =
 144                                 connector->helper_private;
 145                         struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 146                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 147                         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 148
 149                         if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 150                                 bpc = 6;
 151                         else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 152                                 bpc = 8;
 153                 }
 154                 break;
 155         }
 156
 157         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 158                 /*
 159                  * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 160                  * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 161                  * 12 bpc is always supported on hdmi deep color sinks, as this is
 162                  * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 163                  */
 164                 if (bpc > 12) {
 165                         DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 166                                   connector->name, bpc);
 167                         bpc = 12;
 168                 }
 169
 170                 /* Any defined maximum tmds clock limit we must not exceed? */
 171                 if (connector->display_info.max_tmds_clock > 0) {
 172                         /* mode_clock is clock in kHz for mode to be modeset on this connector */
 173                         mode_clock = amdgpu_connector->pixelclock_for_modeset;
 174
 175                         /* Maximum allowable input clock in kHz */
 176                         max_tmds_clock = connector->display_info.max_tmds_clock;
 177
 178                         DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 179                                   connector->name, mode_clock, max_tmds_clock);
 180
 181                         /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 182                         if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 183                                 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 184                                     (mode_clock * 5/4 <= max_tmds_clock))
 185                                         bpc = 10;
 186                                 else
 187                                         bpc = 8;
 188
 189                                 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 190                                           connector->name, bpc);
 191                         }
 192
 193                         if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 194                                 bpc = 8;
 195                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 196                                           connector->name, bpc);
 197                         }
 198                 } else if (bpc > 8) {
 199                         /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 200                         DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 201                                   connector->name);
 202                         bpc = 8;
 203                 }
 204         }
 205
 206         if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 207                 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 208                           connector->name);
 209                 bpc = 8;
 210         }
 211
 212         DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 213                   connector->name, connector->display_info.bpc, bpc);
 214
 215         return bpc;
 216 }
 217
 218 static void
 219 amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 220                                       enum drm_connector_status status)
 221 {
 222         struct drm_encoder *best_encoder = NULL;
 223         struct drm_encoder *encoder = NULL;
 224         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 225         bool connected;
 226         int i;
 227
 228         best_encoder = connector_funcs->best_encoder(connector);
 229
 230         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 231                 if (connector->encoder_ids[i] == 0)
 232                         break;
 233
 234                 encoder = drm_encoder_find(connector->dev, NULL,
 235                                         connector->encoder_ids[i]);
 236                 if (!encoder)
 237                         continue;
 238
 239                 if ((encoder == best_encoder) && (status == connector_status_connected))
 240                         connected = true;
 241                 else
 242                         connected = false;
 243
 244                 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 245
 246         }
 247 }
 248
 249 static struct drm_encoder *
 250 amdgpu_connector_find_encoder(struct drm_connector *connector,
 251                                int encoder_type)
 252 {
 253         struct drm_encoder *encoder;
 254         int i;
 255
 256         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 257                 if (connector->encoder_ids[i] == 0)
 258                         break;
 259                 encoder = drm_encoder_find(connector->dev, NULL,
 260                                         connector->encoder_ids[i]);
 261                 if (!encoder)
 262                         continue;
 263
 264                 if (encoder->encoder_type == encoder_type)
 265                         return encoder;
 266         }
 267         return NULL;
 268 }
 269
 270 struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 271 {
 272         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 273         struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 274
 275         if (amdgpu_connector->edid) {
 276                 return amdgpu_connector->edid;
 277         } else if (edid_blob) {
 278                 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 279                 if (edid)
 280                         amdgpu_connector->edid = edid;
 281         }
 282         return amdgpu_connector->edid;
 283 }
 284
 285 static struct edid *
 286 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 287 {
 288         struct edid *edid;
 289
 290         if (adev->mode_info.bios_hardcoded_edid) {
 291                 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 292                 if (edid) {
 293                         memcpy((unsigned char *)edid,
 294                                (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 295                                adev->mode_info.bios_hardcoded_edid_size);
 296                         return edid;
 297                 }
 298         }
 299         return NULL;
 300 }
 301
 302 static void amdgpu_connector_get_edid(struct drm_connector *connector)
 303 {
 304         struct drm_device *dev = connector->dev;
 305         struct amdgpu_device *adev = dev->dev_private;
 306         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 307
 308         if (amdgpu_connector->edid)
 309                 return;
 310
 311         /* on hw with routers, select right port */
 312         if (amdgpu_connector->router.ddc_valid)
 313                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 314
 315         if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 316              ENCODER_OBJECT_ID_NONE) &&
 317             amdgpu_connector->ddc_bus->has_aux) {
 318                 amdgpu_connector->edid = drm_get_edid(connector,
 319                                                       &amdgpu_connector->ddc_bus->aux.ddc);
 320         } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 321                    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 322                 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 323
 324                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 325                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 326                     amdgpu_connector->ddc_bus->has_aux)
 327                         amdgpu_connector->edid = drm_get_edid(connector,
 328                                                               &amdgpu_connector->ddc_bus->aux.ddc);
 329                 else if (amdgpu_connector->ddc_bus)
 330                         amdgpu_connector->edid = drm_get_edid(connector,
 331                                                               &amdgpu_connector->ddc_bus->adapter);
 332         } else if (amdgpu_connector->ddc_bus) {
 333                 amdgpu_connector->edid = drm_get_edid(connector,
 334                                                       &amdgpu_connector->ddc_bus->adapter);
 335         }
 336
 337         if (!amdgpu_connector->edid) {
 338                 /* some laptops provide a hardcoded edid in rom for LCDs */
 339                 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 340                      (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 341                         amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 342         }
 343 }
 344
 345 static void amdgpu_connector_free_edid(struct drm_connector *connector)
 346 {
 347         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 348
 349         kfree(amdgpu_connector->edid);
 350         amdgpu_connector->edid = NULL;
 351 }
 352
 353 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 354 {
 355         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 356         int ret;
 357
 358         if (amdgpu_connector->edid) {
 359                 drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
 360                 ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 361                 drm_edid_to_eld(connector, amdgpu_connector->edid);
 362                 return ret;
 363         }
 364         drm_mode_connector_update_edid_property(connector, NULL);
 365         return 0;
 366 }
 367
 368 static struct drm_encoder *
 369 amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 370 {
 371         int enc_id = connector->encoder_ids[0];
 372
 373         /* pick the encoder ids */
 374         if (enc_id)
 375                 return drm_encoder_find(connector->dev, NULL, enc_id);
 376         return NULL;
 377 }
 378
 379 static void amdgpu_get_native_mode(struct drm_connector *connector)
 380 {
 381         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 382         struct amdgpu_encoder *amdgpu_encoder;
 383
 384         if (encoder == NULL)
 385                 return;
 386
 387         amdgpu_encoder = to_amdgpu_encoder(encoder);
 388
 389         if (!list_empty(&connector->probed_modes)) {
 390                 struct drm_display_mode *preferred_mode =
 391                         list_first_entry(&connector->probed_modes,
 392                                          struct drm_display_mode, head);
 393
 394                 amdgpu_encoder->native_mode = *preferred_mode;
 395         } else {
 396                 amdgpu_encoder->native_mode.clock = 0;
 397         }
 398 }
 399
 400 static struct drm_display_mode *
 401 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 402 {
 403         struct drm_device *dev = encoder->dev;
 404         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 405         struct drm_display_mode *mode = NULL;
 406         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 407
 408         if (native_mode->hdisplay != 0 &&
 409             native_mode->vdisplay != 0 &&
 410             native_mode->clock != 0) {
 411                 mode = drm_mode_duplicate(dev, native_mode);
 412                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 413                 drm_mode_set_name(mode);
 414
 415                 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 416         } else if (native_mode->hdisplay != 0 &&
 417                    native_mode->vdisplay != 0) {
 418                 /* mac laptops without an edid */
 419                 /* Note that this is not necessarily the exact panel mode,
 420                  * but an approximation based on the cvt formula.  For these
 421                  * systems we should ideally read the mode info out of the
 422                  * registers or add a mode table, but this works and is much
 423                  * simpler.
 424                  */
 425                 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 426                 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 427                 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 428         }
 429         return mode;
 430 }
 431
 432 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 433                                                struct drm_connector *connector)
 434 {
 435         struct drm_device *dev = encoder->dev;
 436         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 437         struct drm_display_mode *mode = NULL;
 438         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 439         int i;
 440         static const struct mode_size {
 441                 int w;
 442                 int h;
 443         } common_modes[17] = {
 444                 { 640,  480},
 445                 { 720,  480},
 446                 { 800,  600},
 447                 { 848,  480},
 448                 {1024,  768},
 449                 {1152,  768},
 450                 {1280,  720},
 451                 {1280,  800},
 452                 {1280,  854},
 453                 {1280,  960},
 454                 {1280, 1024},
 455                 {1440,  900},
 456                 {1400, 1050},
 457                 {1680, 1050},
 458                 {1600, 1200},
 459                 {1920, 1080},
 460                 {1920, 1200}
 461         };
 462
 463         for (i = 0; i < 17; i++) {
 464                 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 465                         if (common_modes[i].w > 1024 ||
 466                             common_modes[i].h > 768)
 467                                 continue;
 468                 }
 469                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 470                         if (common_modes[i].w > native_mode->hdisplay ||
 471                             common_modes[i].h > native_mode->vdisplay ||
 472                             (common_modes[i].w == native_mode->hdisplay &&
 473                              common_modes[i].h == native_mode->vdisplay))
 474                                 continue;
 475                 }
 476                 if (common_modes[i].w < 320 || common_modes[i].h < 200)
 477                         continue;
 478
 479                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 480                 drm_mode_probed_add(connector, mode);
 481         }
 482 }
 483
 484 static int amdgpu_connector_set_property(struct drm_connector *connector,
 485                                           struct drm_property *property,
 486                                           uint64_t val)
 487 {
 488         struct drm_device *dev = connector->dev;
 489         struct amdgpu_device *adev = dev->dev_private;
 490         struct drm_encoder *encoder;
 491         struct amdgpu_encoder *amdgpu_encoder;
 492
 493         if (property == adev->mode_info.coherent_mode_property) {
 494                 struct amdgpu_encoder_atom_dig *dig;
 495                 bool new_coherent_mode;
 496
 497                 /* need to find digital encoder on connector */
 498                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 499                 if (!encoder)
 500                         return 0;
 501
 502                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 503
 504                 if (!amdgpu_encoder->enc_priv)
 505                         return 0;
 506
 507                 dig = amdgpu_encoder->enc_priv;
 508                 new_coherent_mode = val ? true : false;
 509                 if (dig->coherent_mode != new_coherent_mode) {
 510                         dig->coherent_mode = new_coherent_mode;
 511                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 512                 }
 513         }
 514
 515         if (property == adev->mode_info.audio_property) {
 516                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 517                 /* need to find digital encoder on connector */
 518                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 519                 if (!encoder)
 520                         return 0;
 521
 522                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 523
 524                 if (amdgpu_connector->audio != val) {
 525                         amdgpu_connector->audio = val;
 526                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 527                 }
 528         }
 529
 530         if (property == adev->mode_info.dither_property) {
 531                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 532                 /* need to find digital encoder on connector */
 533                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 534                 if (!encoder)
 535                         return 0;
 536
 537                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 538
 539                 if (amdgpu_connector->dither != val) {
 540                         amdgpu_connector->dither = val;
 541                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 542                 }
 543         }
 544
 545         if (property == adev->mode_info.underscan_property) {
 546                 /* need to find digital encoder on connector */
 547                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 548                 if (!encoder)
 549                         return 0;
 550
 551                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 552
 553                 if (amdgpu_encoder->underscan_type != val) {
 554                         amdgpu_encoder->underscan_type = val;
 555                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 556                 }
 557         }
 558
 559         if (property == adev->mode_info.underscan_hborder_property) {
 560                 /* need to find digital encoder on connector */
 561                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 562                 if (!encoder)
 563                         return 0;
 564
 565                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 566
 567                 if (amdgpu_encoder->underscan_hborder != val) {
 568                         amdgpu_encoder->underscan_hborder = val;
 569                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 570                 }
 571         }
 572
 573         if (property == adev->mode_info.underscan_vborder_property) {
 574                 /* need to find digital encoder on connector */
 575                 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 576                 if (!encoder)
 577                         return 0;
 578
 579                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 580
 581                 if (amdgpu_encoder->underscan_vborder != val) {
 582                         amdgpu_encoder->underscan_vborder = val;
 583                         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 584                 }
 585         }
 586
 587         if (property == adev->mode_info.load_detect_property) {
 588                 struct amdgpu_connector *amdgpu_connector =
 589                         to_amdgpu_connector(connector);
 590
 591                 if (val == 0)
 592                         amdgpu_connector->dac_load_detect = false;
 593                 else
 594                         amdgpu_connector->dac_load_detect = true;
 595         }
 596
 597         if (property == dev->mode_config.scaling_mode_property) {
 598                 enum amdgpu_rmx_type rmx_type;
 599
 600                 if (connector->encoder) {
 601                         amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 602                 } else {
 603                         const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 604                         amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 605                 }
 606
 607                 switch (val) {
 608                 default:
 609                 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 610                 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 611                 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 612                 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 613                 }
 614                 if (amdgpu_encoder->rmx_type == rmx_type)
 615                         return 0;
 616
 617                 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 618                     (amdgpu_encoder->native_mode.clock == 0))
 619                         return 0;
 620
 621                 amdgpu_encoder->rmx_type = rmx_type;
 622
 623                 amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 624         }
 625
 626         return 0;
 627 }
 628
 629 static void
 630 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 631                                         struct drm_connector *connector)
 632 {
 633         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 634         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 635         struct drm_display_mode *t, *mode;
 636
 637         /* If the EDID preferred mode doesn't match the native mode, use it */
 638         list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 639                 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 640                         if (mode->hdisplay != native_mode->hdisplay ||
 641                             mode->vdisplay != native_mode->vdisplay)
 642                                 memcpy(native_mode, mode, sizeof(*mode));
 643                 }
 644         }
 645
 646         /* Try to get native mode details from EDID if necessary */
 647         if (!native_mode->clock) {
 648                 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 649                         if (mode->hdisplay == native_mode->hdisplay &&
 650                             mode->vdisplay == native_mode->vdisplay) {
 651                                 *native_mode = *mode;
 652                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 653                                 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 654                                 break;
 655                         }
 656                 }
 657         }
 658
 659         if (!native_mode->clock) {
 660                 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 661                 amdgpu_encoder->rmx_type = RMX_OFF;
 662         }
 663 }
 664
 665 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 666 {
 667         struct drm_encoder *encoder;
 668         int ret = 0;
 669         struct drm_display_mode *mode;
 670
 671         amdgpu_connector_get_edid(connector);
 672         ret = amdgpu_connector_ddc_get_modes(connector);
 673         if (ret > 0) {
 674                 encoder = amdgpu_connector_best_single_encoder(connector);
 675                 if (encoder) {
 676                         amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 677                         /* add scaled modes */
 678                         amdgpu_connector_add_common_modes(encoder, connector);
 679                 }
 680                 return ret;
 681         }
 682
 683         encoder = amdgpu_connector_best_single_encoder(connector);
 684         if (!encoder)
 685                 return 0;
 686
 687         /* we have no EDID modes */
 688         mode = amdgpu_connector_lcd_native_mode(encoder);
 689         if (mode) {
 690                 ret = 1;
 691                 drm_mode_probed_add(connector, mode);
 692                 /* add the width/height from vbios tables if available */
 693                 connector->display_info.width_mm = mode->width_mm;
 694                 connector->display_info.height_mm = mode->height_mm;
 695                 /* add scaled modes */
 696                 amdgpu_connector_add_common_modes(encoder, connector);
 697         }
 698
 699         return ret;
 700 }
 701
 702 static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 703                                              struct drm_display_mode *mode)
 704 {
 705         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 706
 707         if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 708                 return MODE_PANEL;
 709
 710         if (encoder) {
 711                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 712                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 713
 714                 /* AVIVO hardware supports downscaling modes larger than the panel
 715                  * to the panel size, but I'm not sure this is desirable.
 716                  */
 717                 if ((mode->hdisplay > native_mode->hdisplay) ||
 718                     (mode->vdisplay > native_mode->vdisplay))
 719                         return MODE_PANEL;
 720
 721                 /* if scaling is disabled, block non-native modes */
 722                 if (amdgpu_encoder->rmx_type == RMX_OFF) {
 723                         if ((mode->hdisplay != native_mode->hdisplay) ||
 724                             (mode->vdisplay != native_mode->vdisplay))
 725                                 return MODE_PANEL;
 726                 }
 727         }
 728
 729         return MODE_OK;
 730 }
 731
 732 static enum drm_connector_status
 733 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 734 {
 735         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 736         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 737         enum drm_connector_status ret = connector_status_disconnected;
 738         int r;
 739
 740         if (!drm_kms_helper_is_poll_worker()) {
 741                 r = pm_runtime_get_sync(connector->dev->dev);
 742                 if (r < 0)
 743                         return connector_status_disconnected;
 744         }
 745
 746         if (encoder) {
 747                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 748                 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 749
 750                 /* check if panel is valid */
 751                 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 752                         ret = connector_status_connected;
 753
 754         }
 755
 756         /* check for edid as well */
 757         amdgpu_connector_get_edid(connector);
 758         if (amdgpu_connector->edid)
 759                 ret = connector_status_connected;
 760         /* check acpi lid status ??? */
 761
 762         amdgpu_connector_update_scratch_regs(connector, ret);
 763
 764         if (!drm_kms_helper_is_poll_worker()) {
 765                 pm_runtime_mark_last_busy(connector->dev->dev);
 766                 pm_runtime_put_autosuspend(connector->dev->dev);
 767         }
 768
 769         return ret;
 770 }
 771
 772 static void amdgpu_connector_unregister(struct drm_connector *connector)
 773 {
 774         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 775
 776         if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 777                 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 778                 amdgpu_connector->ddc_bus->has_aux = false;
 779         }
 780 }
 781
 782 static void amdgpu_connector_destroy(struct drm_connector *connector)
 783 {
 784         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 785
 786         amdgpu_connector_free_edid(connector);
 787         kfree(amdgpu_connector->con_priv);
 788         drm_connector_unregister(connector);
 789         drm_connector_cleanup(connector);
 790         kfree(connector);
 791 }
 792
 793 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 794                                               struct drm_property *property,
 795                                               uint64_t value)
 796 {
 797         struct drm_device *dev = connector->dev;
 798         struct amdgpu_encoder *amdgpu_encoder;
 799         enum amdgpu_rmx_type rmx_type;
 800
 801         DRM_DEBUG_KMS("\n");
 802         if (property != dev->mode_config.scaling_mode_property)
 803                 return 0;
 804
 805         if (connector->encoder)
 806                 amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 807         else {
 808                 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 809                 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 810         }
 811
 812         switch (value) {
 813         case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 814         case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 815         case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 816         default:
 817         case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 818         }
 819         if (amdgpu_encoder->rmx_type == rmx_type)
 820                 return 0;
 821
 822         amdgpu_encoder->rmx_type = rmx_type;
 823
 824         amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 825         return 0;
 826 }
 827
 828
 829 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 830         .get_modes = amdgpu_connector_lvds_get_modes,
 831         .mode_valid = amdgpu_connector_lvds_mode_valid,
 832         .best_encoder = amdgpu_connector_best_single_encoder,
 833 };
 834
 835 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 836         .dpms = drm_helper_connector_dpms,
 837         .detect = amdgpu_connector_lvds_detect,
 838         .fill_modes = drm_helper_probe_single_connector_modes,
 839         .early_unregister = amdgpu_connector_unregister,
 840         .destroy = amdgpu_connector_destroy,
 841         .set_property = amdgpu_connector_set_lcd_property,
 842 };
 843
 844 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 845 {
 846         int ret;
 847
 848         amdgpu_connector_get_edid(connector);
 849         ret = amdgpu_connector_ddc_get_modes(connector);
 850
 851         return ret;
 852 }
 853
 854 static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 855                                             struct drm_display_mode *mode)
 856 {
 857         struct drm_device *dev = connector->dev;
 858         struct amdgpu_device *adev = dev->dev_private;
 859
 860         /* XXX check mode bandwidth */
 861
 862         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 863                 return MODE_CLOCK_HIGH;
 864
 865         return MODE_OK;
 866 }
 867
 868 static enum drm_connector_status
 869 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 870 {
 871         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 872         struct drm_encoder *encoder;
 873         const struct drm_encoder_helper_funcs *encoder_funcs;
 874         bool dret = false;
 875         enum drm_connector_status ret = connector_status_disconnected;
 876         int r;
 877
 878         if (!drm_kms_helper_is_poll_worker()) {
 879                 r = pm_runtime_get_sync(connector->dev->dev);
 880                 if (r < 0)
 881                         return connector_status_disconnected;
 882         }
 883
 884         encoder = amdgpu_connector_best_single_encoder(connector);
 885         if (!encoder)
 886                 ret = connector_status_disconnected;
 887
 888         if (amdgpu_connector->ddc_bus)
 889                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
 890         if (dret) {
 891                 amdgpu_connector->detected_by_load = false;
 892                 amdgpu_connector_free_edid(connector);
 893                 amdgpu_connector_get_edid(connector);
 894
 895                 if (!amdgpu_connector->edid) {
 896                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 897                                         connector->name);
 898                         ret = connector_status_connected;
 899                 } else {
 900                         amdgpu_connector->use_digital =
 901                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 902
 903                         /* some oems have boards with separate digital and analog connectors
 904                          * with a shared ddc line (often vga + hdmi)
 905                          */
 906                         if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 907                                 amdgpu_connector_free_edid(connector);
 908                                 ret = connector_status_disconnected;
 909                         } else {
 910                                 ret = connector_status_connected;
 911                         }
 912                 }
 913         } else {
 914
 915                 /* if we aren't forcing don't do destructive polling */
 916                 if (!force) {
 917                         /* only return the previous status if we last
 918                          * detected a monitor via load.
 919                          */
 920                         if (amdgpu_connector->detected_by_load)
 921                                 ret = connector->status;
 922                         goto out;
 923                 }
 924
 925                 if (amdgpu_connector->dac_load_detect && encoder) {
 926                         encoder_funcs = encoder->helper_private;
 927                         ret = encoder_funcs->detect(encoder, connector);
 928                         if (ret != connector_status_disconnected)
 929                                 amdgpu_connector->detected_by_load = true;
 930                 }
 931         }
 932
 933         amdgpu_connector_update_scratch_regs(connector, ret);
 934
 935 out:
 936         if (!drm_kms_helper_is_poll_worker()) {
 937                 pm_runtime_mark_last_busy(connector->dev->dev);
 938                 pm_runtime_put_autosuspend(connector->dev->dev);
 939         }
 940
 941         return ret;
 942 }
 943
 944 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 945         .get_modes = amdgpu_connector_vga_get_modes,
 946         .mode_valid = amdgpu_connector_vga_mode_valid,
 947         .best_encoder = amdgpu_connector_best_single_encoder,
 948 };
 949
 950 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 951         .dpms = drm_helper_connector_dpms,
 952         .detect = amdgpu_connector_vga_detect,
 953         .fill_modes = drm_helper_probe_single_connector_modes,
 954         .early_unregister = amdgpu_connector_unregister,
 955         .destroy = amdgpu_connector_destroy,
 956         .set_property = amdgpu_connector_set_property,
 957 };
 958
 959 static bool
 960 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 961 {
 962         struct drm_device *dev = connector->dev;
 963         struct amdgpu_device *adev = dev->dev_private;
 964         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 965         enum drm_connector_status status;
 966
 967         if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 968                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 969                         status = connector_status_connected;
 970                 else
 971                         status = connector_status_disconnected;
 972                 if (connector->status == status)
 973                         return true;
 974         }
 975
 976         return false;
 977 }
 978
 979 /*
 980  * DVI is complicated
 981  * Do a DDC probe, if DDC probe passes, get the full EDID so
 982  * we can do analog/digital monitor detection at this point.
 983  * If the monitor is an analog monitor or we got no DDC,
 984  * we need to find the DAC encoder object for this connector.
 985  * If we got no DDC, we do load detection on the DAC encoder object.
 986  * If we got analog DDC or load detection passes on the DAC encoder
 987  * we have to check if this analog encoder is shared with anyone else (TV)
 988  * if its shared we have to set the other connector to disconnected.
 989  */
 990 static enum drm_connector_status
 991 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 992 {
 993         struct drm_device *dev = connector->dev;
 994         struct amdgpu_device *adev = dev->dev_private;
 995         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 996         struct drm_encoder *encoder = NULL;
 997         const struct drm_encoder_helper_funcs *encoder_funcs;
 998         int i, r;
 999         enum drm_connector_status ret = connector_status_disconnected;
1000         bool dret = false, broken_edid = false;
1001
1002         if (!drm_kms_helper_is_poll_worker()) {
1003                 r = pm_runtime_get_sync(connector->dev->dev);
1004                 if (r < 0)
1005                         return connector_status_disconnected;
1006         }
1007
1008         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1009                 ret = connector->status;
1010                 goto exit;
1011         }
1012
1013         if (amdgpu_connector->ddc_bus)
1014                 dret = amdgpu_ddc_probe(amdgpu_connector, false);
1015         if (dret) {
1016                 amdgpu_connector->detected_by_load = false;
1017                 amdgpu_connector_free_edid(connector);
1018                 amdgpu_connector_get_edid(connector);
1019
1020                 if (!amdgpu_connector->edid) {
1021                         DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1022                                         connector->name);
1023                         ret = connector_status_connected;
1024                         broken_edid = true; /* defer use_digital to later */
1025                 } else {
1026                         amdgpu_connector->use_digital =
1027                                 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1028
1029                         /* some oems have boards with separate digital and analog connectors
1030                          * with a shared ddc line (often vga + hdmi)
1031                          */
1032                         if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1033                                 amdgpu_connector_free_edid(connector);
1034                                 ret = connector_status_disconnected;
1035                         } else {
1036                                 ret = connector_status_connected;
1037                         }
1038
1039                         /* This gets complicated.  We have boards with VGA + HDMI with a
1040                          * shared DDC line and we have boards with DVI-D + HDMI with a shared
1041                          * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1042                          * you don't really know what's connected to which port as both are digital.
1043                          */
1044                         if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1045                                 struct drm_connector *list_connector;
1046                                 struct amdgpu_connector *list_amdgpu_connector;
1047                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1048                                         if (connector == list_connector)
1049                                                 continue;
1050                                         list_amdgpu_connector = to_amdgpu_connector(list_connector);
1051                                         if (list_amdgpu_connector->shared_ddc &&
1052                                             (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1053                                              amdgpu_connector->ddc_bus->rec.i2c_id)) {
1054                                                 /* cases where both connectors are digital */
1055                                                 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1056                                                         /* hpd is our only option in this case */
1057                                                         if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1058                                                                 amdgpu_connector_free_edid(connector);
1059                                                                 ret = connector_status_disconnected;
1060                                                         }
1061                                                 }
1062                                         }
1063                                 }
1064                         }
1065                 }
1066         }
1067
1068         if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1069                 goto out;
1070
1071         /* DVI-D and HDMI-A are digital only */
1072         if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1073             (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1074                 goto out;
1075
1076         /* if we aren't forcing don't do destructive polling */
1077         if (!force) {
1078                 /* only return the previous status if we last
1079                  * detected a monitor via load.
1080                  */
1081                 if (amdgpu_connector->detected_by_load)
1082                         ret = connector->status;
1083                 goto out;
1084         }
1085
1086         /* find analog encoder */
1087         if (amdgpu_connector->dac_load_detect) {
1088                 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1089                         if (connector->encoder_ids[i] == 0)
1090                                 break;
1091
1092                         encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
1093                         if (!encoder)
1094                                 continue;
1095
1096                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1097                             encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1098                                 continue;
1099
1100                         encoder_funcs = encoder->helper_private;
1101                         if (encoder_funcs->detect) {
1102                                 if (!broken_edid) {
1103                                         if (ret != connector_status_connected) {
1104                                                 /* deal with analog monitors without DDC */
1105                                                 ret = encoder_funcs->detect(encoder, connector);
1106                                                 if (ret == connector_status_connected) {
1107                                                         amdgpu_connector->use_digital = false;
1108                                                 }
1109                                                 if (ret != connector_status_disconnected)
1110                                                         amdgpu_connector->detected_by_load = true;
1111                                         }
1112                                 } else {
1113                                         enum drm_connector_status lret;
1114                                         /* assume digital unless load detected otherwise */
1115                                         amdgpu_connector->use_digital = true;
1116                                         lret = encoder_funcs->detect(encoder, connector);
1117                                         DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1118                                         if (lret == connector_status_connected)
1119                                                 amdgpu_connector->use_digital = false;
1120                                 }
1121                                 break;
1122                         }
1123                 }
1124         }
1125
1126 out:
1127         /* updated in get modes as well since we need to know if it's analog or digital */
1128         amdgpu_connector_update_scratch_regs(connector, ret);
1129
1130 exit:
1131         if (!drm_kms_helper_is_poll_worker()) {
1132                 pm_runtime_mark_last_busy(connector->dev->dev);
1133                 pm_runtime_put_autosuspend(connector->dev->dev);
1134         }
1135
1136         return ret;
1137 }
1138
1139 /* okay need to be smart in here about which encoder to pick */
1140 static struct drm_encoder *
1141 amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1142 {
1143         int enc_id = connector->encoder_ids[0];
1144         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1145         struct drm_encoder *encoder;
1146         int i;
1147         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1148                 if (connector->encoder_ids[i] == 0)
1149                         break;
1150
1151                 encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
1152                 if (!encoder)
1153                         continue;
1154
1155                 if (amdgpu_connector->use_digital == true) {
1156                         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1157                                 return encoder;
1158                 } else {
1159                         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1160                             encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1161                                 return encoder;
1162                 }
1163         }
1164
1165         /* see if we have a default encoder  TODO */
1166
1167         /* then check use digitial */
1168         /* pick the first one */
1169         if (enc_id)
1170                 return drm_encoder_find(connector->dev, NULL, enc_id);
1171         return NULL;
1172 }
1173
1174 static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1175 {
1176         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1177         if (connector->force == DRM_FORCE_ON)
1178                 amdgpu_connector->use_digital = false;
1179         if (connector->force == DRM_FORCE_ON_DIGITAL)
1180                 amdgpu_connector->use_digital = true;
1181 }
1182
1183 static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1184                                             struct drm_display_mode *mode)
1185 {
1186         struct drm_device *dev = connector->dev;
1187         struct amdgpu_device *adev = dev->dev_private;
1188         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1189
1190         /* XXX check mode bandwidth */
1191
1192         if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1193                 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1194                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1195                     (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1196                         return MODE_OK;
1197                 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1198                         /* HDMI 1.3+ supports max clock of 340 Mhz */
1199                         if (mode->clock > 340000)
1200                                 return MODE_CLOCK_HIGH;
1201                         else
1202                                 return MODE_OK;
1203                 } else {
1204                         return MODE_CLOCK_HIGH;
1205                 }
1206         }
1207
1208         /* check against the max pixel clock */
1209         if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1210                 return MODE_CLOCK_HIGH;
1211
1212         return MODE_OK;
1213 }
1214
1215 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1216         .get_modes = amdgpu_connector_vga_get_modes,
1217         .mode_valid = amdgpu_connector_dvi_mode_valid,
1218         .best_encoder = amdgpu_connector_dvi_encoder,
1219 };
1220
1221 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1222         .dpms = drm_helper_connector_dpms,
1223         .detect = amdgpu_connector_dvi_detect,
1224         .fill_modes = drm_helper_probe_single_connector_modes,
1225         .set_property = amdgpu_connector_set_property,
1226         .early_unregister = amdgpu_connector_unregister,
1227         .destroy = amdgpu_connector_destroy,
1228         .force = amdgpu_connector_dvi_force,
1229 };
1230
1231 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1232 {
1233         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1234         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1235         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1236         int ret;
1237
1238         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1239             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1240                 struct drm_display_mode *mode;
1241
1242                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1243                         if (!amdgpu_dig_connector->edp_on)
1244                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1245                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1246                         amdgpu_connector_get_edid(connector);
1247                         ret = amdgpu_connector_ddc_get_modes(connector);
1248                         if (!amdgpu_dig_connector->edp_on)
1249                                 amdgpu_atombios_encoder_set_edp_panel_power(connector,
1250                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1251                 } else {
1252                         /* need to setup ddc on the bridge */
1253                         if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1254                             ENCODER_OBJECT_ID_NONE) {
1255                                 if (encoder)
1256                                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1257                         }
1258                         amdgpu_connector_get_edid(connector);
1259                         ret = amdgpu_connector_ddc_get_modes(connector);
1260                 }
1261
1262                 if (ret > 0) {
1263                         if (encoder) {
1264                                 amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1265                                 /* add scaled modes */
1266                                 amdgpu_connector_add_common_modes(encoder, connector);
1267                         }
1268                         return ret;
1269                 }
1270
1271                 if (!encoder)
1272                         return 0;
1273
1274                 /* we have no EDID modes */
1275                 mode = amdgpu_connector_lcd_native_mode(encoder);
1276                 if (mode) {
1277                         ret = 1;
1278                         drm_mode_probed_add(connector, mode);
1279                         /* add the width/height from vbios tables if available */
1280                         connector->display_info.width_mm = mode->width_mm;
1281                         connector->display_info.height_mm = mode->height_mm;
1282                         /* add scaled modes */
1283                         amdgpu_connector_add_common_modes(encoder, connector);
1284                 }
1285         } else {
1286                 /* need to setup ddc on the bridge */
1287                 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1288                         ENCODER_OBJECT_ID_NONE) {
1289                         if (encoder)
1290                                 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1291                 }
1292                 amdgpu_connector_get_edid(connector);
1293                 ret = amdgpu_connector_ddc_get_modes(connector);
1294
1295                 amdgpu_get_native_mode(connector);
1296         }
1297
1298         return ret;
1299 }
1300
1301 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1302 {
1303         struct drm_encoder *encoder;
1304         struct amdgpu_encoder *amdgpu_encoder;
1305         int i;
1306
1307         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1308                 if (connector->encoder_ids[i] == 0)
1309                         break;
1310
1311                 encoder = drm_encoder_find(connector->dev, NULL,
1312                                         connector->encoder_ids[i]);
1313                 if (!encoder)
1314                         continue;
1315
1316                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1317
1318                 switch (amdgpu_encoder->encoder_id) {
1319                 case ENCODER_OBJECT_ID_TRAVIS:
1320                 case ENCODER_OBJECT_ID_NUTMEG:
1321                         return amdgpu_encoder->encoder_id;
1322                 default:
1323                         break;
1324                 }
1325         }
1326
1327         return ENCODER_OBJECT_ID_NONE;
1328 }
1329
1330 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1331 {
1332         struct drm_encoder *encoder;
1333         struct amdgpu_encoder *amdgpu_encoder;
1334         int i;
1335         bool found = false;
1336
1337         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1338                 if (connector->encoder_ids[i] == 0)
1339                         break;
1340                 encoder = drm_encoder_find(connector->dev, NULL,
1341                                         connector->encoder_ids[i]);
1342                 if (!encoder)
1343                         continue;
1344
1345                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1346                 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1347                         found = true;
1348         }
1349
1350         return found;
1351 }
1352
1353 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1354 {
1355         struct drm_device *dev = connector->dev;
1356         struct amdgpu_device *adev = dev->dev_private;
1357
1358         if ((adev->clock.default_dispclk >= 53900) &&
1359             amdgpu_connector_encoder_is_hbr2(connector)) {
1360                 return true;
1361         }
1362
1363         return false;
1364 }
1365
1366 static enum drm_connector_status
1367 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1368 {
1369         struct drm_device *dev = connector->dev;
1370         struct amdgpu_device *adev = dev->dev_private;
1371         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1372         enum drm_connector_status ret = connector_status_disconnected;
1373         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1374         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1375         int r;
1376
1377         if (!drm_kms_helper_is_poll_worker()) {
1378                 r = pm_runtime_get_sync(connector->dev->dev);
1379                 if (r < 0)
1380                         return connector_status_disconnected;
1381         }
1382
1383         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1384                 ret = connector->status;
1385                 goto out;
1386         }
1387
1388         amdgpu_connector_free_edid(connector);
1389
1390         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1391             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1392                 if (encoder) {
1393                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1394                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1395
1396                         /* check if panel is valid */
1397                         if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1398                                 ret = connector_status_connected;
1399                 }
1400                 /* eDP is always DP */
1401                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1402                 if (!amdgpu_dig_connector->edp_on)
1403                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1404                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1405                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1406                         ret = connector_status_connected;
1407                 if (!amdgpu_dig_connector->edp_on)
1408                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
1409                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1410         } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1411                    ENCODER_OBJECT_ID_NONE) {
1412                 /* DP bridges are always DP */
1413                 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1414                 /* get the DPCD from the bridge */
1415                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1416
1417                 if (encoder) {
1418                         /* setup ddc on the bridge */
1419                         amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1420                         /* bridge chips are always aux */
1421                         if (amdgpu_ddc_probe(amdgpu_connector, true)) /* try DDC */
1422                                 ret = connector_status_connected;
1423                         else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1424                                 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1425                                 ret = encoder_funcs->detect(encoder, connector);
1426                         }
1427                 }
1428         } else {
1429                 amdgpu_dig_connector->dp_sink_type =
1430                         amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1431                 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1432                         ret = connector_status_connected;
1433                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1434                                 amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1435                 } else {
1436                         if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1437                                 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1438                                         ret = connector_status_connected;
1439                         } else {
1440                                 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1441                                 if (amdgpu_ddc_probe(amdgpu_connector, false))
1442                                         ret = connector_status_connected;
1443                         }
1444                 }
1445         }
1446
1447         amdgpu_connector_update_scratch_regs(connector, ret);
1448 out:
1449         if (!drm_kms_helper_is_poll_worker()) {
1450                 pm_runtime_mark_last_busy(connector->dev->dev);
1451                 pm_runtime_put_autosuspend(connector->dev->dev);
1452         }
1453
1454         return ret;
1455 }
1456
1457 static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1458                                            struct drm_display_mode *mode)
1459 {
1460         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1461         struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1462
1463         /* XXX check mode bandwidth */
1464
1465         if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1466             (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1467                 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1468
1469                 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1470                         return MODE_PANEL;
1471
1472                 if (encoder) {
1473                         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1474                         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1475
1476                         /* AVIVO hardware supports downscaling modes larger than the panel
1477                          * to the panel size, but I'm not sure this is desirable.
1478                          */
1479                         if ((mode->hdisplay > native_mode->hdisplay) ||
1480                             (mode->vdisplay > native_mode->vdisplay))
1481                                 return MODE_PANEL;
1482
1483                         /* if scaling is disabled, block non-native modes */
1484                         if (amdgpu_encoder->rmx_type == RMX_OFF) {
1485                                 if ((mode->hdisplay != native_mode->hdisplay) ||
1486                                     (mode->vdisplay != native_mode->vdisplay))
1487                                         return MODE_PANEL;
1488                         }
1489                 }
1490                 return MODE_OK;
1491         } else {
1492                 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1493                     (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1494                         return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1495                 } else {
1496                         if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1497                                 /* HDMI 1.3+ supports max clock of 340 Mhz */
1498                                 if (mode->clock > 340000)
1499                                         return MODE_CLOCK_HIGH;
1500                         } else {
1501                                 if (mode->clock > 165000)
1502                                         return MODE_CLOCK_HIGH;
1503                         }
1504                 }
1505         }
1506
1507         return MODE_OK;
1508 }
1509
1510 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1511         .get_modes = amdgpu_connector_dp_get_modes,
1512         .mode_valid = amdgpu_connector_dp_mode_valid,
1513         .best_encoder = amdgpu_connector_dvi_encoder,
1514 };
1515
1516 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1517         .dpms = drm_helper_connector_dpms,
1518         .detect = amdgpu_connector_dp_detect,
1519         .fill_modes = drm_helper_probe_single_connector_modes,
1520         .set_property = amdgpu_connector_set_property,
1521         .early_unregister = amdgpu_connector_unregister,
1522         .destroy = amdgpu_connector_destroy,
1523         .force = amdgpu_connector_dvi_force,
1524 };
1525
1526 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1527         .dpms = drm_helper_connector_dpms,
1528         .detect = amdgpu_connector_dp_detect,
1529         .fill_modes = drm_helper_probe_single_connector_modes,
1530         .set_property = amdgpu_connector_set_lcd_property,
1531         .early_unregister = amdgpu_connector_unregister,
1532         .destroy = amdgpu_connector_destroy,
1533         .force = amdgpu_connector_dvi_force,
1534 };
1535
1536 void
1537 amdgpu_connector_add(struct amdgpu_device *adev,
1538                       uint32_t connector_id,
1539                       uint32_t supported_device,
1540                       int connector_type,
1541                       struct amdgpu_i2c_bus_rec *i2c_bus,
1542                       uint16_t connector_object_id,
1543                       struct amdgpu_hpd *hpd,
1544                       struct amdgpu_router *router)
1545 {
1546         struct drm_device *dev = adev->ddev;
1547         struct drm_connector *connector;
1548         struct amdgpu_connector *amdgpu_connector;
1549         struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1550         struct drm_encoder *encoder;
1551         struct amdgpu_encoder *amdgpu_encoder;
1552         uint32_t subpixel_order = SubPixelNone;
1553         bool shared_ddc = false;
1554         bool is_dp_bridge = false;
1555         bool has_aux = false;
1556
1557         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1558                 return;
1559
1560         /* see if we already added it */
1561         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1562                 amdgpu_connector = to_amdgpu_connector(connector);
1563                 if (amdgpu_connector->connector_id == connector_id) {
1564                         amdgpu_connector->devices |= supported_device;
1565                         return;
1566                 }
1567                 if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1568                         if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1569                                 amdgpu_connector->shared_ddc = true;
1570                                 shared_ddc = true;
1571                         }
1572                         if (amdgpu_connector->router_bus && router->ddc_valid &&
1573                             (amdgpu_connector->router.router_id == router->router_id)) {
1574                                 amdgpu_connector->shared_ddc = false;
1575                                 shared_ddc = false;
1576                         }
1577                 }
1578         }
1579
1580         /* check if it's a dp bridge */
1581         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1582                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1583                 if (amdgpu_encoder->devices & supported_device) {
1584                         switch (amdgpu_encoder->encoder_id) {
1585                         case ENCODER_OBJECT_ID_TRAVIS:
1586                         case ENCODER_OBJECT_ID_NUTMEG:
1587                                 is_dp_bridge = true;
1588                                 break;
1589                         default:
1590                                 break;
1591                         }
1592                 }
1593         }
1594
1595         amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1596         if (!amdgpu_connector)
1597                 return;
1598
1599         connector = &amdgpu_connector->base;
1600
1601         amdgpu_connector->connector_id = connector_id;
1602         amdgpu_connector->devices = supported_device;
1603         amdgpu_connector->shared_ddc = shared_ddc;
1604         amdgpu_connector->connector_object_id = connector_object_id;
1605         amdgpu_connector->hpd = *hpd;
1606
1607         amdgpu_connector->router = *router;
1608         if (router->ddc_valid || router->cd_valid) {
1609                 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1610                 if (!amdgpu_connector->router_bus)
1611                         DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1612         }
1613
1614         if (is_dp_bridge) {
1615                 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1616                 if (!amdgpu_dig_connector)
1617                         goto failed;
1618                 amdgpu_connector->con_priv = amdgpu_dig_connector;
1619                 if (i2c_bus->valid) {
1620                         amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1621                         if (amdgpu_connector->ddc_bus)
1622                                 has_aux = true;
1623                         else
1624                                 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1625                 }
1626                 switch (connector_type) {
1627                 case DRM_MODE_CONNECTOR_VGA:
1628                 case DRM_MODE_CONNECTOR_DVIA:
1629                 default:
1630                         drm_connector_init(dev, &amdgpu_connector->base,
1631                                            &amdgpu_connector_dp_funcs, connector_type);
1632                         drm_connector_helper_add(&amdgpu_connector->base,
1633                                                  &amdgpu_connector_dp_helper_funcs);
1634                         connector->interlace_allowed = true;
1635                         connector->doublescan_allowed = true;
1636                         amdgpu_connector->dac_load_detect = true;
1637                         drm_object_attach_property(&amdgpu_connector->base.base,
1638                                                       adev->mode_info.load_detect_property,
1639                                                       1);
1640                         drm_object_attach_property(&amdgpu_connector->base.base,
1641                                                    dev->mode_config.scaling_mode_property,
1642                                                    DRM_MODE_SCALE_NONE);
1643                         break;
1644                 case DRM_MODE_CONNECTOR_DVII:
1645                 case DRM_MODE_CONNECTOR_DVID:
1646                 case DRM_MODE_CONNECTOR_HDMIA:
1647                 case DRM_MODE_CONNECTOR_HDMIB:
1648                 case DRM_MODE_CONNECTOR_DisplayPort:
1649                         drm_connector_init(dev, &amdgpu_connector->base,
1650                                            &amdgpu_connector_dp_funcs, connector_type);
1651                         drm_connector_helper_add(&amdgpu_connector->base,
1652                                                  &amdgpu_connector_dp_helper_funcs);
1653                         drm_object_attach_property(&amdgpu_connector->base.base,
1654                                                       adev->mode_info.underscan_property,
1655                                                       UNDERSCAN_OFF);
1656                         drm_object_attach_property(&amdgpu_connector->base.base,
1657                                                       adev->mode_info.underscan_hborder_property,
1658                                                       0);
1659                         drm_object_attach_property(&amdgpu_connector->base.base,
1660                                                       adev->mode_info.underscan_vborder_property,
1661                                                       0);
1662
1663                         drm_object_attach_property(&amdgpu_connector->base.base,
1664                                                    dev->mode_config.scaling_mode_property,
1665                                                    DRM_MODE_SCALE_NONE);
1666
1667                         drm_object_attach_property(&amdgpu_connector->base.base,
1668                                                    adev->mode_info.dither_property,
1669                                                    AMDGPU_FMT_DITHER_DISABLE);
1670
1671                         if (amdgpu_audio != 0)
1672                                 drm_object_attach_property(&amdgpu_connector->base.base,
1673                                                            adev->mode_info.audio_property,
1674                                                            AMDGPU_AUDIO_AUTO);
1675
1676                         subpixel_order = SubPixelHorizontalRGB;
1677                         connector->interlace_allowed = true;
1678                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1679                                 connector->doublescan_allowed = true;
1680                         else
1681                                 connector->doublescan_allowed = false;
1682                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1683                                 amdgpu_connector->dac_load_detect = true;
1684                                 drm_object_attach_property(&amdgpu_connector->base.base,
1685                                                               adev->mode_info.load_detect_property,
1686                                                               1);
1687                         }
1688                         break;
1689                 case DRM_MODE_CONNECTOR_LVDS:
1690                 case DRM_MODE_CONNECTOR_eDP:
1691                         drm_connector_init(dev, &amdgpu_connector->base,
1692                                            &amdgpu_connector_edp_funcs, connector_type);
1693                         drm_connector_helper_add(&amdgpu_connector->base,
1694                                                  &amdgpu_connector_dp_helper_funcs);
1695                         drm_object_attach_property(&amdgpu_connector->base.base,
1696                                                       dev->mode_config.scaling_mode_property,
1697                                                       DRM_MODE_SCALE_FULLSCREEN);
1698                         subpixel_order = SubPixelHorizontalRGB;
1699                         connector->interlace_allowed = false;
1700                         connector->doublescan_allowed = false;
1701                         break;
1702                 }
1703         } else {
1704                 switch (connector_type) {
1705                 case DRM_MODE_CONNECTOR_VGA:
1706                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1707                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1708                         if (i2c_bus->valid) {
1709                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1710                                 if (!amdgpu_connector->ddc_bus)
1711                                         DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1712                         }
1713                         amdgpu_connector->dac_load_detect = true;
1714                         drm_object_attach_property(&amdgpu_connector->base.base,
1715                                                       adev->mode_info.load_detect_property,
1716                                                       1);
1717                         drm_object_attach_property(&amdgpu_connector->base.base,
1718                                                    dev->mode_config.scaling_mode_property,
1719                                                    DRM_MODE_SCALE_NONE);
1720                         /* no HPD on analog connectors */
1721                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1722                         connector->interlace_allowed = true;
1723                         connector->doublescan_allowed = true;
1724                         break;
1725                 case DRM_MODE_CONNECTOR_DVIA:
1726                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1727                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1728                         if (i2c_bus->valid) {
1729                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1730                                 if (!amdgpu_connector->ddc_bus)
1731                                         DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1732                         }
1733                         amdgpu_connector->dac_load_detect = true;
1734                         drm_object_attach_property(&amdgpu_connector->base.base,
1735                                                       adev->mode_info.load_detect_property,
1736                                                       1);
1737                         drm_object_attach_property(&amdgpu_connector->base.base,
1738                                                    dev->mode_config.scaling_mode_property,
1739                                                    DRM_MODE_SCALE_NONE);
1740                         /* no HPD on analog connectors */
1741                         amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1742                         connector->interlace_allowed = true;
1743                         connector->doublescan_allowed = true;
1744                         break;
1745                 case DRM_MODE_CONNECTOR_DVII:
1746                 case DRM_MODE_CONNECTOR_DVID:
1747                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1748                         if (!amdgpu_dig_connector)
1749                                 goto failed;
1750                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1751                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1752                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1753                         if (i2c_bus->valid) {
1754                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1755                                 if (!amdgpu_connector->ddc_bus)
1756                                         DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1757                         }
1758                         subpixel_order = SubPixelHorizontalRGB;
1759                         drm_object_attach_property(&amdgpu_connector->base.base,
1760                                                       adev->mode_info.coherent_mode_property,
1761                                                       1);
1762                         drm_object_attach_property(&amdgpu_connector->base.base,
1763                                                    adev->mode_info.underscan_property,
1764                                                    UNDERSCAN_OFF);
1765                         drm_object_attach_property(&amdgpu_connector->base.base,
1766                                                    adev->mode_info.underscan_hborder_property,
1767                                                    0);
1768                         drm_object_attach_property(&amdgpu_connector->base.base,
1769                                                    adev->mode_info.underscan_vborder_property,
1770                                                    0);
1771                         drm_object_attach_property(&amdgpu_connector->base.base,
1772                                                    dev->mode_config.scaling_mode_property,
1773                                                    DRM_MODE_SCALE_NONE);
1774
1775                         if (amdgpu_audio != 0) {
1776                                 drm_object_attach_property(&amdgpu_connector->base.base,
1777                                                            adev->mode_info.audio_property,
1778                                                            AMDGPU_AUDIO_AUTO);
1779                         }
1780                         drm_object_attach_property(&amdgpu_connector->base.base,
1781                                                    adev->mode_info.dither_property,
1782                                                    AMDGPU_FMT_DITHER_DISABLE);
1783                         if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1784                                 amdgpu_connector->dac_load_detect = true;
1785                                 drm_object_attach_property(&amdgpu_connector->base.base,
1786                                                            adev->mode_info.load_detect_property,
1787                                                            1);
1788                         }
1789                         connector->interlace_allowed = true;
1790                         if (connector_type == DRM_MODE_CONNECTOR_DVII)
1791                                 connector->doublescan_allowed = true;
1792                         else
1793                                 connector->doublescan_allowed = false;
1794                         break;
1795                 case DRM_MODE_CONNECTOR_HDMIA:
1796                 case DRM_MODE_CONNECTOR_HDMIB:
1797                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1798                         if (!amdgpu_dig_connector)
1799                                 goto failed;
1800                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1801                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1802                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1803                         if (i2c_bus->valid) {
1804                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1805                                 if (!amdgpu_connector->ddc_bus)
1806                                         DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1807                         }
1808                         drm_object_attach_property(&amdgpu_connector->base.base,
1809                                                       adev->mode_info.coherent_mode_property,
1810                                                       1);
1811                         drm_object_attach_property(&amdgpu_connector->base.base,
1812                                                    adev->mode_info.underscan_property,
1813                                                    UNDERSCAN_OFF);
1814                         drm_object_attach_property(&amdgpu_connector->base.base,
1815                                                    adev->mode_info.underscan_hborder_property,
1816                                                    0);
1817                         drm_object_attach_property(&amdgpu_connector->base.base,
1818                                                    adev->mode_info.underscan_vborder_property,
1819                                                    0);
1820                         drm_object_attach_property(&amdgpu_connector->base.base,
1821                                                    dev->mode_config.scaling_mode_property,
1822                                                    DRM_MODE_SCALE_NONE);
1823                         if (amdgpu_audio != 0) {
1824                                 drm_object_attach_property(&amdgpu_connector->base.base,
1825                                                            adev->mode_info.audio_property,
1826                                                            AMDGPU_AUDIO_AUTO);
1827                         }
1828                         drm_object_attach_property(&amdgpu_connector->base.base,
1829                                                    adev->mode_info.dither_property,
1830                                                    AMDGPU_FMT_DITHER_DISABLE);
1831                         subpixel_order = SubPixelHorizontalRGB;
1832                         connector->interlace_allowed = true;
1833                         if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1834                                 connector->doublescan_allowed = true;
1835                         else
1836                                 connector->doublescan_allowed = false;
1837                         break;
1838                 case DRM_MODE_CONNECTOR_DisplayPort:
1839                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1840                         if (!amdgpu_dig_connector)
1841                                 goto failed;
1842                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1843                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1844                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1845                         if (i2c_bus->valid) {
1846                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1847                                 if (amdgpu_connector->ddc_bus)
1848                                         has_aux = true;
1849                                 else
1850                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1851                         }
1852                         subpixel_order = SubPixelHorizontalRGB;
1853                         drm_object_attach_property(&amdgpu_connector->base.base,
1854                                                       adev->mode_info.coherent_mode_property,
1855                                                       1);
1856                         drm_object_attach_property(&amdgpu_connector->base.base,
1857                                                    adev->mode_info.underscan_property,
1858                                                    UNDERSCAN_OFF);
1859                         drm_object_attach_property(&amdgpu_connector->base.base,
1860                                                    adev->mode_info.underscan_hborder_property,
1861                                                    0);
1862                         drm_object_attach_property(&amdgpu_connector->base.base,
1863                                                    adev->mode_info.underscan_vborder_property,
1864                                                    0);
1865                         drm_object_attach_property(&amdgpu_connector->base.base,
1866                                                    dev->mode_config.scaling_mode_property,
1867                                                    DRM_MODE_SCALE_NONE);
1868                         if (amdgpu_audio != 0) {
1869                                 drm_object_attach_property(&amdgpu_connector->base.base,
1870                                                            adev->mode_info.audio_property,
1871                                                            AMDGPU_AUDIO_AUTO);
1872                         }
1873                         drm_object_attach_property(&amdgpu_connector->base.base,
1874                                                    adev->mode_info.dither_property,
1875                                                    AMDGPU_FMT_DITHER_DISABLE);
1876                         connector->interlace_allowed = true;
1877                         /* in theory with a DP to VGA converter... */
1878                         connector->doublescan_allowed = false;
1879                         break;
1880                 case DRM_MODE_CONNECTOR_eDP:
1881                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1882                         if (!amdgpu_dig_connector)
1883                                 goto failed;
1884                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1885                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1886                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1887                         if (i2c_bus->valid) {
1888                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1889                                 if (amdgpu_connector->ddc_bus)
1890                                         has_aux = true;
1891                                 else
1892                                         DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1893                         }
1894                         drm_object_attach_property(&amdgpu_connector->base.base,
1895                                                       dev->mode_config.scaling_mode_property,
1896                                                       DRM_MODE_SCALE_FULLSCREEN);
1897                         subpixel_order = SubPixelHorizontalRGB;
1898                         connector->interlace_allowed = false;
1899                         connector->doublescan_allowed = false;
1900                         break;
1901                 case DRM_MODE_CONNECTOR_LVDS:
1902                         amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1903                         if (!amdgpu_dig_connector)
1904                                 goto failed;
1905                         amdgpu_connector->con_priv = amdgpu_dig_connector;
1906                         drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1907                         drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1908                         if (i2c_bus->valid) {
1909                                 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1910                                 if (!amdgpu_connector->ddc_bus)
1911                                         DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1912                         }
1913                         drm_object_attach_property(&amdgpu_connector->base.base,
1914                                                       dev->mode_config.scaling_mode_property,
1915                                                       DRM_MODE_SCALE_FULLSCREEN);
1916                         subpixel_order = SubPixelHorizontalRGB;
1917                         connector->interlace_allowed = false;
1918                         connector->doublescan_allowed = false;
1919                         break;
1920                 }
1921         }
1922
1923         if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1924                 if (i2c_bus->valid) {
1925                         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1926                                             DRM_CONNECTOR_POLL_DISCONNECT;
1927                 }
1928         } else
1929                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1930
1931         connector->display_info.subpixel_order = subpixel_order;
1932         drm_connector_register(connector);
1933
1934         if (has_aux)
1935                 amdgpu_atombios_dp_aux_init(amdgpu_connector);
1936
1937         return;
1938
1939 failed:
1940         drm_connector_cleanup(connector);
1941         kfree(connector);
1942 }