drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include <linux/slab.h>
  26 #include <linux/pci.h>
  27 #include <linux/acpi.h>
  28 #include <drm/drmP.h>
  29 #include <linux/firmware.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu.h"
  32 #include "cgs_linux.h"
  33 #include "atom.h"
  34 #include "amdgpu_ucode.h"
  35
  36 struct amdgpu_cgs_device {
  37         struct cgs_device base;
  38         struct amdgpu_device *adev;
  39 };
  40
  41 #define CGS_FUNC_ADEV                                                   \
  42         struct amdgpu_device *adev =                                    \
  43                 ((struct amdgpu_cgs_device *)cgs_device)->adev
  44
  45 static int amdgpu_cgs_gpu_mem_info(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
  46                                    uint64_t *mc_start, uint64_t *mc_size,
  47                                    uint64_t *mem_size)
  48 {
  49         CGS_FUNC_ADEV;
  50         switch(type) {
  51         case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
  52         case CGS_GPU_MEM_TYPE__VISIBLE_FB:
  53                 *mc_start = 0;
  54                 *mc_size = adev->mc.visible_vram_size;
  55                 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
  56                 break;
  57         case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
  58         case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
  59                 *mc_start = adev->mc.visible_vram_size;
  60                 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
  61                 *mem_size = *mc_size;
  62                 break;
  63         case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
  64         case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
  65                 *mc_start = adev->mc.gtt_start;
  66                 *mc_size = adev->mc.gtt_size;
  67                 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
  68                 break;
  69         default:
  70                 return -EINVAL;
  71         }
  72
  73         return 0;
  74 }
  75
  76 static int amdgpu_cgs_gmap_kmem(struct cgs_device *cgs_device, void *kmem,
  77                                 uint64_t size,
  78                                 uint64_t min_offset, uint64_t max_offset,
  79                                 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
  80 {
  81         CGS_FUNC_ADEV;
  82         int ret;
  83         struct amdgpu_bo *bo;
  84         struct page *kmem_page = vmalloc_to_page(kmem);
  85         int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
  86
  87         struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
  88         ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
  89                                AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
  90         if (ret)
  91                 return ret;
  92         ret = amdgpu_bo_reserve(bo, false);
  93         if (unlikely(ret != 0))
  94                 return ret;
  95
  96         /* pin buffer into GTT */
  97         ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
  98                                        min_offset, max_offset, mcaddr);
  99         amdgpu_bo_unreserve(bo);
 100
 101         *kmem_handle = (cgs_handle_t)bo;
 102         return ret;
 103 }
 104
 105 static int amdgpu_cgs_gunmap_kmem(struct cgs_device *cgs_device, cgs_handle_t kmem_handle)
 106 {
 107         struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
 108
 109         if (obj) {
 110                 int r = amdgpu_bo_reserve(obj, false);
 111                 if (likely(r == 0)) {
 112                         amdgpu_bo_unpin(obj);
 113                         amdgpu_bo_unreserve(obj);
 114                 }
 115                 amdgpu_bo_unref(&obj);
 116
 117         }
 118         return 0;
 119 }
 120
 121 static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
 122                                     enum cgs_gpu_mem_type type,
 123                                     uint64_t size, uint64_t align,
 124                                     uint64_t min_offset, uint64_t max_offset,
 125                                     cgs_handle_t *handle)
 126 {
 127         CGS_FUNC_ADEV;
 128         uint16_t flags = 0;
 129         int ret = 0;
 130         uint32_t domain = 0;
 131         struct amdgpu_bo *obj;
 132         struct ttm_placement placement;
 133         struct ttm_place place;
 134
 135         if (min_offset > max_offset) {
 136                 BUG_ON(1);
 137                 return -EINVAL;
 138         }
 139
 140         /* fail if the alignment is not a power of 2 */
 141         if (((align != 1) && (align & (align - 1)))
 142             || size == 0 || align == 0)
 143                 return -EINVAL;
 144
 145
 146         switch(type) {
 147         case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
 148         case CGS_GPU_MEM_TYPE__VISIBLE_FB:
 149                 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 150                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 151                 domain = AMDGPU_GEM_DOMAIN_VRAM;
 152                 if (max_offset > adev->mc.real_vram_size)
 153                         return -EINVAL;
 154                 place.fpfn = min_offset >> PAGE_SHIFT;
 155                 place.lpfn = max_offset >> PAGE_SHIFT;
 156                 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 157                         TTM_PL_FLAG_VRAM;
 158                 break;
 159         case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
 160         case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
 161                 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 162                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 163                 domain = AMDGPU_GEM_DOMAIN_VRAM;
 164                 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 165                         place.fpfn =
 166                                 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
 167                         place.lpfn =
 168                                 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
 169                         place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 170                                 TTM_PL_FLAG_VRAM;
 171                 }
 172
 173                 break;
 174         case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
 175                 domain = AMDGPU_GEM_DOMAIN_GTT;
 176                 place.fpfn = min_offset >> PAGE_SHIFT;
 177                 place.lpfn = max_offset >> PAGE_SHIFT;
 178                 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
 179                 break;
 180         case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
 181                 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 182                 domain = AMDGPU_GEM_DOMAIN_GTT;
 183                 place.fpfn = min_offset >> PAGE_SHIFT;
 184                 place.lpfn = max_offset >> PAGE_SHIFT;
 185                 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
 186                         TTM_PL_FLAG_UNCACHED;
 187                 break;
 188         default:
 189                 return -EINVAL;
 190         }
 191
 192
 193         *handle = 0;
 194
 195         placement.placement = &place;
 196         placement.num_placement = 1;
 197         placement.busy_placement = &place;
 198         placement.num_busy_placement = 1;
 199
 200         ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
 201                                           true, domain, flags,
 202                                           NULL, &placement, NULL,
 203                                           &obj);
 204         if (ret) {
 205                 DRM_ERROR("(%d) bo create failed\n", ret);
 206                 return ret;
 207         }
 208         *handle = (cgs_handle_t)obj;
 209
 210         return ret;
 211 }
 212
 213 static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 214 {
 215         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 216
 217         if (obj) {
 218                 int r = amdgpu_bo_reserve(obj, false);
 219                 if (likely(r == 0)) {
 220                         amdgpu_bo_kunmap(obj);
 221                         amdgpu_bo_unpin(obj);
 222                         amdgpu_bo_unreserve(obj);
 223                 }
 224                 amdgpu_bo_unref(&obj);
 225
 226         }
 227         return 0;
 228 }
 229
 230 static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
 231                                    uint64_t *mcaddr)
 232 {
 233         int r;
 234         u64 min_offset, max_offset;
 235         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 236
 237         WARN_ON_ONCE(obj->placement.num_placement > 1);
 238
 239         min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
 240         max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
 241
 242         r = amdgpu_bo_reserve(obj, false);
 243         if (unlikely(r != 0))
 244                 return r;
 245         r = amdgpu_bo_pin_restricted(obj, obj->prefered_domains,
 246                                      min_offset, max_offset, mcaddr);
 247         amdgpu_bo_unreserve(obj);
 248         return r;
 249 }
 250
 251 static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 252 {
 253         int r;
 254         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 255         r = amdgpu_bo_reserve(obj, false);
 256         if (unlikely(r != 0))
 257                 return r;
 258         r = amdgpu_bo_unpin(obj);
 259         amdgpu_bo_unreserve(obj);
 260         return r;
 261 }
 262
 263 static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
 264                                    void **map)
 265 {
 266         int r;
 267         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 268         r = amdgpu_bo_reserve(obj, false);
 269         if (unlikely(r != 0))
 270                 return r;
 271         r = amdgpu_bo_kmap(obj, map);
 272         amdgpu_bo_unreserve(obj);
 273         return r;
 274 }
 275
 276 static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
 277 {
 278         int r;
 279         struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
 280         r = amdgpu_bo_reserve(obj, false);
 281         if (unlikely(r != 0))
 282                 return r;
 283         amdgpu_bo_kunmap(obj);
 284         amdgpu_bo_unreserve(obj);
 285         return r;
 286 }
 287
 288 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
 289 {
 290         CGS_FUNC_ADEV;
 291         return RREG32(offset);
 292 }
 293
 294 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
 295                                       uint32_t value)
 296 {
 297         CGS_FUNC_ADEV;
 298         WREG32(offset, value);
 299 }
 300
 301 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
 302                                              enum cgs_ind_reg space,
 303                                              unsigned index)
 304 {
 305         CGS_FUNC_ADEV;
 306         switch (space) {
 307         case CGS_IND_REG__MMIO:
 308                 return RREG32_IDX(index);
 309         case CGS_IND_REG__PCIE:
 310                 return RREG32_PCIE(index);
 311         case CGS_IND_REG__SMC:
 312                 return RREG32_SMC(index);
 313         case CGS_IND_REG__UVD_CTX:
 314                 return RREG32_UVD_CTX(index);
 315         case CGS_IND_REG__DIDT:
 316                 return RREG32_DIDT(index);
 317         case CGS_IND_REG_GC_CAC:
 318                 return RREG32_GC_CAC(index);
 319         case CGS_IND_REG__AUDIO_ENDPT:
 320                 DRM_ERROR("audio endpt register access not implemented.\n");
 321                 return 0;
 322         }
 323         WARN(1, "Invalid indirect register space");
 324         return 0;
 325 }
 326
 327 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
 328                                           enum cgs_ind_reg space,
 329                                           unsigned index, uint32_t value)
 330 {
 331         CGS_FUNC_ADEV;
 332         switch (space) {
 333         case CGS_IND_REG__MMIO:
 334                 return WREG32_IDX(index, value);
 335         case CGS_IND_REG__PCIE:
 336                 return WREG32_PCIE(index, value);
 337         case CGS_IND_REG__SMC:
 338                 return WREG32_SMC(index, value);
 339         case CGS_IND_REG__UVD_CTX:
 340                 return WREG32_UVD_CTX(index, value);
 341         case CGS_IND_REG__DIDT:
 342                 return WREG32_DIDT(index, value);
 343         case CGS_IND_REG_GC_CAC:
 344                 return WREG32_GC_CAC(index, value);
 345         case CGS_IND_REG__AUDIO_ENDPT:
 346                 DRM_ERROR("audio endpt register access not implemented.\n");
 347                 return;
 348         }
 349         WARN(1, "Invalid indirect register space");
 350 }
 351
 352 static uint8_t amdgpu_cgs_read_pci_config_byte(struct cgs_device *cgs_device, unsigned addr)
 353 {
 354         CGS_FUNC_ADEV;
 355         uint8_t val;
 356         int ret = pci_read_config_byte(adev->pdev, addr, &val);
 357         if (WARN(ret, "pci_read_config_byte error"))
 358                 return 0;
 359         return val;
 360 }
 361
 362 static uint16_t amdgpu_cgs_read_pci_config_word(struct cgs_device *cgs_device, unsigned addr)
 363 {
 364         CGS_FUNC_ADEV;
 365         uint16_t val;
 366         int ret = pci_read_config_word(adev->pdev, addr, &val);
 367         if (WARN(ret, "pci_read_config_word error"))
 368                 return 0;
 369         return val;
 370 }
 371
 372 static uint32_t amdgpu_cgs_read_pci_config_dword(struct cgs_device *cgs_device,
 373                                                  unsigned addr)
 374 {
 375         CGS_FUNC_ADEV;
 376         uint32_t val;
 377         int ret = pci_read_config_dword(adev->pdev, addr, &val);
 378         if (WARN(ret, "pci_read_config_dword error"))
 379                 return 0;
 380         return val;
 381 }
 382
 383 static void amdgpu_cgs_write_pci_config_byte(struct cgs_device *cgs_device, unsigned addr,
 384                                              uint8_t value)
 385 {
 386         CGS_FUNC_ADEV;
 387         int ret = pci_write_config_byte(adev->pdev, addr, value);
 388         WARN(ret, "pci_write_config_byte error");
 389 }
 390
 391 static void amdgpu_cgs_write_pci_config_word(struct cgs_device *cgs_device, unsigned addr,
 392                                              uint16_t value)
 393 {
 394         CGS_FUNC_ADEV;
 395         int ret = pci_write_config_word(adev->pdev, addr, value);
 396         WARN(ret, "pci_write_config_word error");
 397 }
 398
 399 static void amdgpu_cgs_write_pci_config_dword(struct cgs_device *cgs_device, unsigned addr,
 400                                               uint32_t value)
 401 {
 402         CGS_FUNC_ADEV;
 403         int ret = pci_write_config_dword(adev->pdev, addr, value);
 404         WARN(ret, "pci_write_config_dword error");
 405 }
 406
 407
 408 static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
 409                                        enum cgs_resource_type resource_type,
 410                                        uint64_t size,
 411                                        uint64_t offset,
 412                                        uint64_t *resource_base)
 413 {
 414         CGS_FUNC_ADEV;
 415
 416         if (resource_base == NULL)
 417                 return -EINVAL;
 418
 419         switch (resource_type) {
 420         case CGS_RESOURCE_TYPE_MMIO:
 421                 if (adev->rmmio_size == 0)
 422                         return -ENOENT;
 423                 if ((offset + size) > adev->rmmio_size)
 424                         return -EINVAL;
 425                 *resource_base = adev->rmmio_base;
 426                 return 0;
 427         case CGS_RESOURCE_TYPE_DOORBELL:
 428                 if (adev->doorbell.size == 0)
 429                         return -ENOENT;
 430                 if ((offset + size) > adev->doorbell.size)
 431                         return -EINVAL;
 432                 *resource_base = adev->doorbell.base;
 433                 return 0;
 434         case CGS_RESOURCE_TYPE_FB:
 435         case CGS_RESOURCE_TYPE_IO:
 436         case CGS_RESOURCE_TYPE_ROM:
 437         default:
 438                 return -EINVAL;
 439         }
 440 }
 441
 442 static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
 443                                                   unsigned table, uint16_t *size,
 444                                                   uint8_t *frev, uint8_t *crev)
 445 {
 446         CGS_FUNC_ADEV;
 447         uint16_t data_start;
 448
 449         if (amdgpu_atom_parse_data_header(
 450                     adev->mode_info.atom_context, table, size,
 451                     frev, crev, &data_start))
 452                 return (uint8_t*)adev->mode_info.atom_context->bios +
 453                         data_start;
 454
 455         return NULL;
 456 }
 457
 458 static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
 459                                               uint8_t *frev, uint8_t *crev)
 460 {
 461         CGS_FUNC_ADEV;
 462
 463         if (amdgpu_atom_parse_cmd_header(
 464                     adev->mode_info.atom_context, table,
 465                     frev, crev))
 466                 return 0;
 467
 468         return -EINVAL;
 469 }
 470
 471 static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
 472                                           void *args)
 473 {
 474         CGS_FUNC_ADEV;
 475
 476         return amdgpu_atom_execute_table(
 477                 adev->mode_info.atom_context, table, args);
 478 }
 479
 480 static int amdgpu_cgs_create_pm_request(struct cgs_device *cgs_device, cgs_handle_t *request)
 481 {
 482         /* TODO */
 483         return 0;
 484 }
 485
 486 static int amdgpu_cgs_destroy_pm_request(struct cgs_device *cgs_device, cgs_handle_t request)
 487 {
 488         /* TODO */
 489         return 0;
 490 }
 491
 492 static int amdgpu_cgs_set_pm_request(struct cgs_device *cgs_device, cgs_handle_t request,
 493                                      int active)
 494 {
 495         /* TODO */
 496         return 0;
 497 }
 498
 499 static int amdgpu_cgs_pm_request_clock(struct cgs_device *cgs_device, cgs_handle_t request,
 500                                        enum cgs_clock clock, unsigned freq)
 501 {
 502         /* TODO */
 503         return 0;
 504 }
 505
 506 static int amdgpu_cgs_pm_request_engine(struct cgs_device *cgs_device, cgs_handle_t request,
 507                                         enum cgs_engine engine, int powered)
 508 {
 509         /* TODO */
 510         return 0;
 511 }
 512
 513
 514
 515 static int amdgpu_cgs_pm_query_clock_limits(struct cgs_device *cgs_device,
 516                                             enum cgs_clock clock,
 517                                             struct cgs_clock_limits *limits)
 518 {
 519         /* TODO */
 520         return 0;
 521 }
 522
 523 static int amdgpu_cgs_set_camera_voltages(struct cgs_device *cgs_device, uint32_t mask,
 524                                           const uint32_t *voltages)
 525 {
 526         DRM_ERROR("not implemented");
 527         return -EPERM;
 528 }
 529
 530 struct cgs_irq_params {
 531         unsigned src_id;
 532         cgs_irq_source_set_func_t set;
 533         cgs_irq_handler_func_t handler;
 534         void *private_data;
 535 };
 536
 537 static int cgs_set_irq_state(struct amdgpu_device *adev,
 538                              struct amdgpu_irq_src *src,
 539                              unsigned type,
 540                              enum amdgpu_interrupt_state state)
 541 {
 542         struct cgs_irq_params *irq_params =
 543                 (struct cgs_irq_params *)src->data;
 544         if (!irq_params)
 545                 return -EINVAL;
 546         if (!irq_params->set)
 547                 return -EINVAL;
 548         return irq_params->set(irq_params->private_data,
 549                                irq_params->src_id,
 550                                type,
 551                                (int)state);
 552 }
 553
 554 static int cgs_process_irq(struct amdgpu_device *adev,
 555                            struct amdgpu_irq_src *source,
 556                            struct amdgpu_iv_entry *entry)
 557 {
 558         struct cgs_irq_params *irq_params =
 559                 (struct cgs_irq_params *)source->data;
 560         if (!irq_params)
 561                 return -EINVAL;
 562         if (!irq_params->handler)
 563                 return -EINVAL;
 564         return irq_params->handler(irq_params->private_data,
 565                                    irq_params->src_id,
 566                                    entry->iv_entry);
 567 }
 568
 569 static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
 570         .set = cgs_set_irq_state,
 571         .process = cgs_process_irq,
 572 };
 573
 574 static int amdgpu_cgs_add_irq_source(void *cgs_device,
 575                                      unsigned client_id,
 576                                      unsigned src_id,
 577                                      unsigned num_types,
 578                                      cgs_irq_source_set_func_t set,
 579                                      cgs_irq_handler_func_t handler,
 580                                      void *private_data)
 581 {
 582         CGS_FUNC_ADEV;
 583         int ret = 0;
 584         struct cgs_irq_params *irq_params;
 585         struct amdgpu_irq_src *source =
 586                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
 587         if (!source)
 588                 return -ENOMEM;
 589         irq_params =
 590                 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
 591         if (!irq_params) {
 592                 kfree(source);
 593                 return -ENOMEM;
 594         }
 595         source->num_types = num_types;
 596         source->funcs = &cgs_irq_funcs;
 597         irq_params->src_id = src_id;
 598         irq_params->set = set;
 599         irq_params->handler = handler;
 600         irq_params->private_data = private_data;
 601         source->data = (void *)irq_params;
 602         ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
 603         if (ret) {
 604                 kfree(irq_params);
 605                 kfree(source);
 606         }
 607
 608         return ret;
 609 }
 610
 611 static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
 612                               unsigned src_id, unsigned type)
 613 {
 614         CGS_FUNC_ADEV;
 615
 616         if (!adev->irq.client[client_id].sources)
 617                 return -EINVAL;
 618
 619         return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
 620 }
 621
 622 static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
 623                               unsigned src_id, unsigned type)
 624 {
 625         CGS_FUNC_ADEV;
 626
 627         if (!adev->irq.client[client_id].sources)
 628                 return -EINVAL;
 629
 630         return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
 631 }
 632
 633 static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
 634                                   enum amd_ip_block_type block_type,
 635                                   enum amd_clockgating_state state)
 636 {
 637         CGS_FUNC_ADEV;
 638         int i, r = -1;
 639
 640         for (i = 0; i < adev->num_ip_blocks; i++) {
 641                 if (!adev->ip_blocks[i].status.valid)
 642                         continue;
 643
 644                 if (adev->ip_blocks[i].version->type == block_type) {
 645                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
 646                                                                 (void *)adev,
 647                                                                         state);
 648                         break;
 649                 }
 650         }
 651         return r;
 652 }
 653
 654 static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
 655                                   enum amd_ip_block_type block_type,
 656                                   enum amd_powergating_state state)
 657 {
 658         CGS_FUNC_ADEV;
 659         int i, r = -1;
 660
 661         for (i = 0; i < adev->num_ip_blocks; i++) {
 662                 if (!adev->ip_blocks[i].status.valid)
 663                         continue;
 664
 665                 if (adev->ip_blocks[i].version->type == block_type) {
 666                         r = adev->ip_blocks[i].version->funcs->set_powergating_state(
 667                                                                 (void *)adev,
 668                                                                         state);
 669                         break;
 670                 }
 671         }
 672         return r;
 673 }
 674
 675
 676 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
 677 {
 678         CGS_FUNC_ADEV;
 679         enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
 680
 681         switch (fw_type) {
 682         case CGS_UCODE_ID_SDMA0:
 683                 result = AMDGPU_UCODE_ID_SDMA0;
 684                 break;
 685         case CGS_UCODE_ID_SDMA1:
 686                 result = AMDGPU_UCODE_ID_SDMA1;
 687                 break;
 688         case CGS_UCODE_ID_CP_CE:
 689                 result = AMDGPU_UCODE_ID_CP_CE;
 690                 break;
 691         case CGS_UCODE_ID_CP_PFP:
 692                 result = AMDGPU_UCODE_ID_CP_PFP;
 693                 break;
 694         case CGS_UCODE_ID_CP_ME:
 695                 result = AMDGPU_UCODE_ID_CP_ME;
 696                 break;
 697         case CGS_UCODE_ID_CP_MEC:
 698         case CGS_UCODE_ID_CP_MEC_JT1:
 699                 result = AMDGPU_UCODE_ID_CP_MEC1;
 700                 break;
 701         case CGS_UCODE_ID_CP_MEC_JT2:
 702                 /* for VI. JT2 should be the same as JT1, because:
 703                         1, MEC2 and MEC1 use exactly same FW.
 704                         2, JT2 is not pached but JT1 is.
 705                 */
 706                 if (adev->asic_type >= CHIP_TOPAZ)
 707                         result = AMDGPU_UCODE_ID_CP_MEC1;
 708                 else
 709                         result = AMDGPU_UCODE_ID_CP_MEC2;
 710                 break;
 711         case CGS_UCODE_ID_RLC_G:
 712                 result = AMDGPU_UCODE_ID_RLC_G;
 713                 break;
 714         case CGS_UCODE_ID_STORAGE:
 715                 result = AMDGPU_UCODE_ID_STORAGE;
 716                 break;
 717         default:
 718                 DRM_ERROR("Firmware type not supported\n");
 719         }
 720         return result;
 721 }
 722
 723 static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
 724 {
 725         CGS_FUNC_ADEV;
 726         if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
 727                 release_firmware(adev->pm.fw);
 728                 adev->pm.fw = NULL;
 729                 return 0;
 730         }
 731         /* cannot release other firmware because they are not created by cgs */
 732         return -EINVAL;
 733 }
 734
 735 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
 736                                         enum cgs_ucode_id type)
 737 {
 738         CGS_FUNC_ADEV;
 739         uint16_t fw_version = 0;
 740
 741         switch (type) {
 742                 case CGS_UCODE_ID_SDMA0:
 743                         fw_version = adev->sdma.instance[0].fw_version;
 744                         break;
 745                 case CGS_UCODE_ID_SDMA1:
 746                         fw_version = adev->sdma.instance[1].fw_version;
 747                         break;
 748                 case CGS_UCODE_ID_CP_CE:
 749                         fw_version = adev->gfx.ce_fw_version;
 750                         break;
 751                 case CGS_UCODE_ID_CP_PFP:
 752                         fw_version = adev->gfx.pfp_fw_version;
 753                         break;
 754                 case CGS_UCODE_ID_CP_ME:
 755                         fw_version = adev->gfx.me_fw_version;
 756                         break;
 757                 case CGS_UCODE_ID_CP_MEC:
 758                         fw_version = adev->gfx.mec_fw_version;
 759                         break;
 760                 case CGS_UCODE_ID_CP_MEC_JT1:
 761                         fw_version = adev->gfx.mec_fw_version;
 762                         break;
 763                 case CGS_UCODE_ID_CP_MEC_JT2:
 764                         fw_version = adev->gfx.mec_fw_version;
 765                         break;
 766                 case CGS_UCODE_ID_RLC_G:
 767                         fw_version = adev->gfx.rlc_fw_version;
 768                         break;
 769                 case CGS_UCODE_ID_STORAGE:
 770                         break;
 771                 default:
 772                         DRM_ERROR("firmware type %d do not have version\n", type);
 773                         break;
 774         }
 775         return fw_version;
 776 }
 777
 778 static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
 779                                         bool en)
 780 {
 781         CGS_FUNC_ADEV;
 782
 783         if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||
 784                 adev->gfx.rlc.funcs->exit_safe_mode == NULL)
 785                 return 0;
 786
 787         if (en)
 788                 adev->gfx.rlc.funcs->enter_safe_mode(adev);
 789         else
 790                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
 791
 792         return 0;
 793 }
 794
 795 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 796                                         enum cgs_ucode_id type,
 797                                         struct cgs_firmware_info *info)
 798 {
 799         CGS_FUNC_ADEV;
 800
 801         if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
 802                 uint64_t gpu_addr;
 803                 uint32_t data_size;
 804                 const struct gfx_firmware_header_v1_0 *header;
 805                 enum AMDGPU_UCODE_ID id;
 806                 struct amdgpu_firmware_info *ucode;
 807
 808                 id = fw_type_convert(cgs_device, type);
 809                 ucode = &adev->firmware.ucode[id];
 810                 if (ucode->fw == NULL)
 811                         return -EINVAL;
 812
 813                 gpu_addr  = ucode->mc_addr;
 814                 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 815                 data_size = le32_to_cpu(header->header.ucode_size_bytes);
 816
 817                 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
 818                     (type == CGS_UCODE_ID_CP_MEC_JT2)) {
 819                         gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
 820                         data_size = le32_to_cpu(header->jt_size) << 2;
 821                 }
 822
 823                 info->kptr = ucode->kaddr;
 824                 info->image_size = data_size;
 825                 info->mc_addr = gpu_addr;
 826                 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
 827
 828                 if (CGS_UCODE_ID_CP_MEC == type)
 829                         info->image_size = (header->jt_offset) << 2;
 830
 831                 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
 832                 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
 833         } else {
 834                 char fw_name[30] = {0};
 835                 int err = 0;
 836                 uint32_t ucode_size;
 837                 uint32_t ucode_start_address;
 838                 const uint8_t *src;
 839                 const struct smc_firmware_header_v1_0 *hdr;
 840                 const struct common_firmware_header *header;
 841                 struct amdgpu_firmware_info *ucode = NULL;
 842
 843                 if (!adev->pm.fw) {
 844                         switch (adev->asic_type) {
 845                         case CHIP_TOPAZ:
 846                                 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
 847                                     ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
 848                                     ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
 849                                         info->is_kicker = true;
 850                                         strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
 851                                 } else
 852                                         strcpy(fw_name, "amdgpu/topaz_smc.bin");
 853                                 break;
 854                         case CHIP_TONGA:
 855                                 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
 856                                     ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
 857                                         info->is_kicker = true;
 858                                         strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
 859                                 } else
 860                                         strcpy(fw_name, "amdgpu/tonga_smc.bin");
 861                                 break;
 862                         case CHIP_FIJI:
 863                                 strcpy(fw_name, "amdgpu/fiji_smc.bin");
 864                                 break;
 865                         case CHIP_POLARIS11:
 866                                 if (type == CGS_UCODE_ID_SMU) {
 867                                         if (((adev->pdev->device == 0x67ef) &&
 868                                              ((adev->pdev->revision == 0xe0) ||
 869                                               (adev->pdev->revision == 0xe2) ||
 870                                               (adev->pdev->revision == 0xe5))) ||
 871                                             ((adev->pdev->device == 0x67ff) &&
 872                                              ((adev->pdev->revision == 0xcf) ||
 873                                               (adev->pdev->revision == 0xef) ||
 874                                               (adev->pdev->revision == 0xff)))) {
 875                                                 info->is_kicker = true;
 876                                                 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
 877                                         } else
 878                                                 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
 879                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 880                                         strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
 881                                 }
 882                                 break;
 883                         case CHIP_POLARIS10:
 884                                 if (type == CGS_UCODE_ID_SMU) {
 885                                         if ((adev->pdev->device == 0x67df) &&
 886                                             ((adev->pdev->revision == 0xe0) ||
 887                                              (adev->pdev->revision == 0xe3) ||
 888                                              (adev->pdev->revision == 0xe4) ||
 889                                              (adev->pdev->revision == 0xe5) ||
 890                                              (adev->pdev->revision == 0xe7) ||
 891                                              (adev->pdev->revision == 0xef))) {
 892                                                 info->is_kicker = true;
 893                                                 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
 894                                         } else
 895                                                 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
 896                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 897                                         strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
 898                                 }
 899                                 break;
 900                         case CHIP_POLARIS12:
 901                                 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
 902                                 break;
 903                         case CHIP_VEGA10:
 904                                 strcpy(fw_name, "amdgpu/vega10_smc.bin");
 905                                 break;
 906                         default:
 907                                 DRM_ERROR("SMC firmware not supported\n");
 908                                 return -EINVAL;
 909                         }
 910
 911                         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 912                         if (err) {
 913                                 DRM_ERROR("Failed to request firmware\n");
 914                                 return err;
 915                         }
 916
 917                         err = amdgpu_ucode_validate(adev->pm.fw);
 918                         if (err) {
 919                                 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
 920                                 release_firmware(adev->pm.fw);
 921                                 adev->pm.fw = NULL;
 922                                 return err;
 923                         }
 924
 925                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 926                                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 927                                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 928                                 ucode->fw = adev->pm.fw;
 929                                 header = (const struct common_firmware_header *)ucode->fw->data;
 930                                 adev->firmware.fw_size +=
 931                                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 932                         }
 933                 }
 934
 935                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 936                 amdgpu_ucode_print_smc_hdr(&hdr->header);
 937                 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 938                 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 939                 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 940                 src = (const uint8_t *)(adev->pm.fw->data +
 941                        le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 942
 943                 info->version = adev->pm.fw_version;
 944                 info->image_size = ucode_size;
 945                 info->ucode_start_address = ucode_start_address;
 946                 info->kptr = (void *)src;
 947         }
 948         return 0;
 949 }
 950
 951 static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
 952 {
 953         CGS_FUNC_ADEV;
 954         return amdgpu_sriov_vf(adev);
 955 }
 956
 957 static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
 958                                         struct cgs_system_info *sys_info)
 959 {
 960         CGS_FUNC_ADEV;
 961
 962         if (NULL == sys_info)
 963                 return -ENODEV;
 964
 965         if (sizeof(struct cgs_system_info) != sys_info->size)
 966                 return -ENODEV;
 967
 968         switch (sys_info->info_id) {
 969         case CGS_SYSTEM_INFO_ADAPTER_BDF_ID:
 970                 sys_info->value = adev->pdev->devfn | (adev->pdev->bus->number << 8);
 971                 break;
 972         case CGS_SYSTEM_INFO_PCIE_GEN_INFO:
 973                 sys_info->value = adev->pm.pcie_gen_mask;
 974                 break;
 975         case CGS_SYSTEM_INFO_PCIE_MLW:
 976                 sys_info->value = adev->pm.pcie_mlw_mask;
 977                 break;
 978         case CGS_SYSTEM_INFO_PCIE_DEV:
 979                 sys_info->value = adev->pdev->device;
 980                 break;
 981         case CGS_SYSTEM_INFO_PCIE_REV:
 982                 sys_info->value = adev->pdev->revision;
 983                 break;
 984         case CGS_SYSTEM_INFO_CG_FLAGS:
 985                 sys_info->value = adev->cg_flags;
 986                 break;
 987         case CGS_SYSTEM_INFO_PG_FLAGS:
 988                 sys_info->value = adev->pg_flags;
 989                 break;
 990         case CGS_SYSTEM_INFO_GFX_CU_INFO:
 991                 sys_info->value = adev->gfx.cu_info.number;
 992                 break;
 993         case CGS_SYSTEM_INFO_GFX_SE_INFO:
 994                 sys_info->value = adev->gfx.config.max_shader_engines;
 995                 break;
 996         case CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID:
 997                 sys_info->value = adev->pdev->subsystem_device;
 998                 break;
 999         case CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID:
1000                 sys_info->value = adev->pdev->subsystem_vendor;
1001                 break;
1002         default:
1003                 return -ENODEV;
1004         }
1005
1006         return 0;
1007 }
1008
1009 static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
1010                                           struct cgs_display_info *info)
1011 {
1012         CGS_FUNC_ADEV;
1013         struct amdgpu_crtc *amdgpu_crtc;
1014         struct drm_device *ddev = adev->ddev;
1015         struct drm_crtc *crtc;
1016         uint32_t line_time_us, vblank_lines;
1017         struct cgs_mode_info *mode_info;
1018
1019         if (info == NULL)
1020                 return -EINVAL;
1021
1022         mode_info = info->mode_info;
1023
1024         if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1025                 list_for_each_entry(crtc,
1026                                 &ddev->mode_config.crtc_list, head) {
1027                         amdgpu_crtc = to_amdgpu_crtc(crtc);
1028                         if (crtc->enabled) {
1029                                 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
1030                                 info->display_count++;
1031                         }
1032                         if (mode_info != NULL &&
1033                                 crtc->enabled && amdgpu_crtc->enabled &&
1034                                 amdgpu_crtc->hw_mode.clock) {
1035                                 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
1036                                                         amdgpu_crtc->hw_mode.clock;
1037                                 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
1038                                                         amdgpu_crtc->hw_mode.crtc_vdisplay +
1039                                                         (amdgpu_crtc->v_border * 2);
1040                                 mode_info->vblank_time_us = vblank_lines * line_time_us;
1041                                 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
1042                                 mode_info->ref_clock = adev->clock.spll.reference_freq;
1043                                 mode_info = NULL;
1044                         }
1045                 }
1046         }
1047
1048         return 0;
1049 }
1050
1051
1052 static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
1053 {
1054         CGS_FUNC_ADEV;
1055
1056         adev->pm.dpm_enabled = enabled;
1057
1058         return 0;
1059 }
1060
1061 /** \brief evaluate acpi namespace object, handle or pathname must be valid
1062  *  \param cgs_device
1063  *  \param info input/output arguments for the control method
1064  *  \return status
1065  */
1066
1067 #if defined(CONFIG_ACPI)
1068 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
1069                                     struct cgs_acpi_method_info *info)
1070 {
1071         CGS_FUNC_ADEV;
1072         acpi_handle handle;
1073         struct acpi_object_list input;
1074         struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
1075         union acpi_object *params, *obj;
1076         uint8_t name[5] = {'\0'};
1077         struct cgs_acpi_method_argument *argument;
1078         uint32_t i, count;
1079         acpi_status status;
1080         int result;
1081
1082         handle = ACPI_HANDLE(&adev->pdev->dev);
1083         if (!handle)
1084                 return -ENODEV;
1085
1086         memset(&input, 0, sizeof(struct acpi_object_list));
1087
1088         /* validate input info */
1089         if (info->size != sizeof(struct cgs_acpi_method_info))
1090                 return -EINVAL;
1091
1092         input.count = info->input_count;
1093         if (info->input_count > 0) {
1094                 if (info->pinput_argument == NULL)
1095                         return -EINVAL;
1096                 argument = info->pinput_argument;
1097                 for (i = 0; i < info->input_count; i++) {
1098                         if (((argument->type == ACPI_TYPE_STRING) ||
1099                              (argument->type == ACPI_TYPE_BUFFER)) &&
1100                             (argument->pointer == NULL))
1101                                 return -EINVAL;
1102                         argument++;
1103                 }
1104         }
1105
1106         if (info->output_count > 0) {
1107                 if (info->poutput_argument == NULL)
1108                         return -EINVAL;
1109                 argument = info->poutput_argument;
1110                 for (i = 0; i < info->output_count; i++) {
1111                         if (((argument->type == ACPI_TYPE_STRING) ||
1112                                 (argument->type == ACPI_TYPE_BUFFER))
1113                                 && (argument->pointer == NULL))
1114                                 return -EINVAL;
1115                         argument++;
1116                 }
1117         }
1118
1119         /* The path name passed to acpi_evaluate_object should be null terminated */
1120         if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
1121                 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
1122                 name[4] = '\0';
1123         }
1124
1125         /* parse input parameters */
1126         if (input.count > 0) {
1127                 input.pointer = params =
1128                                 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
1129                 if (params == NULL)
1130                         return -EINVAL;
1131
1132                 argument = info->pinput_argument;
1133
1134                 for (i = 0; i < input.count; i++) {
1135                         params->type = argument->type;
1136                         switch (params->type) {
1137                         case ACPI_TYPE_INTEGER:
1138                                 params->integer.value = argument->value;
1139                                 break;
1140                         case ACPI_TYPE_STRING:
1141                                 params->string.length = argument->data_length;
1142                                 params->string.pointer = argument->pointer;
1143                                 break;
1144                         case ACPI_TYPE_BUFFER:
1145                                 params->buffer.length = argument->data_length;
1146                                 params->buffer.pointer = argument->pointer;
1147                                 break;
1148                         default:
1149                                 break;
1150                         }
1151                         params++;
1152                         argument++;
1153                 }
1154         }
1155
1156         /* parse output info */
1157         count = info->output_count;
1158         argument = info->poutput_argument;
1159
1160         /* evaluate the acpi method */
1161         status = acpi_evaluate_object(handle, name, &input, &output);
1162
1163         if (ACPI_FAILURE(status)) {
1164                 result = -EIO;
1165                 goto free_input;
1166         }
1167
1168         /* return the output info */
1169         obj = output.pointer;
1170
1171         if (count > 1) {
1172                 if ((obj->type != ACPI_TYPE_PACKAGE) ||
1173                         (obj->package.count != count)) {
1174                         result = -EIO;
1175                         goto free_obj;
1176                 }
1177                 params = obj->package.elements;
1178         } else
1179                 params = obj;
1180
1181         if (params == NULL) {
1182                 result = -EIO;
1183                 goto free_obj;
1184         }
1185
1186         for (i = 0; i < count; i++) {
1187                 if (argument->type != params->type) {
1188                         result = -EIO;
1189                         goto free_obj;
1190                 }
1191                 switch (params->type) {
1192                 case ACPI_TYPE_INTEGER:
1193                         argument->value = params->integer.value;
1194                         break;
1195                 case ACPI_TYPE_STRING:
1196                         if ((params->string.length != argument->data_length) ||
1197                                 (params->string.pointer == NULL)) {
1198                                 result = -EIO;
1199                                 goto free_obj;
1200                         }
1201                         strncpy(argument->pointer,
1202                                 params->string.pointer,
1203                                 params->string.length);
1204                         break;
1205                 case ACPI_TYPE_BUFFER:
1206                         if (params->buffer.pointer == NULL) {
1207                                 result = -EIO;
1208                                 goto free_obj;
1209                         }
1210                         memcpy(argument->pointer,
1211                                 params->buffer.pointer,
1212                                 argument->data_length);
1213                         break;
1214                 default:
1215                         break;
1216                 }
1217                 argument++;
1218                 params++;
1219         }
1220
1221         result = 0;
1222 free_obj:
1223         kfree(obj);
1224 free_input:
1225         kfree((void *)input.pointer);
1226         return result;
1227 }
1228 #else
1229 static int amdgpu_cgs_acpi_eval_object(struct cgs_device *cgs_device,
1230                                 struct cgs_acpi_method_info *info)
1231 {
1232         return -EIO;
1233 }
1234 #endif
1235
1236 static int amdgpu_cgs_call_acpi_method(struct cgs_device *cgs_device,
1237                                         uint32_t acpi_method,
1238                                         uint32_t acpi_function,
1239                                         void *pinput, void *poutput,
1240                                         uint32_t output_count,
1241                                         uint32_t input_size,
1242                                         uint32_t output_size)
1243 {
1244         struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
1245         struct cgs_acpi_method_argument acpi_output = {0};
1246         struct cgs_acpi_method_info info = {0};
1247
1248         acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
1249         acpi_input[0].data_length = sizeof(uint32_t);
1250         acpi_input[0].value = acpi_function;
1251
1252         acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
1253         acpi_input[1].data_length = input_size;
1254         acpi_input[1].pointer = pinput;
1255
1256         acpi_output.type = CGS_ACPI_TYPE_BUFFER;
1257         acpi_output.data_length = output_size;
1258         acpi_output.pointer = poutput;
1259
1260         info.size = sizeof(struct cgs_acpi_method_info);
1261         info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
1262         info.input_count = 2;
1263         info.name = acpi_method;
1264         info.pinput_argument = acpi_input;
1265         info.output_count = output_count;
1266         info.poutput_argument = &acpi_output;
1267
1268         return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
1269 }
1270
1271 static const struct cgs_ops amdgpu_cgs_ops = {
1272         .gpu_mem_info = amdgpu_cgs_gpu_mem_info,
1273         .gmap_kmem = amdgpu_cgs_gmap_kmem,
1274         .gunmap_kmem = amdgpu_cgs_gunmap_kmem,
1275         .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
1276         .free_gpu_mem = amdgpu_cgs_free_gpu_mem,
1277         .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
1278         .gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,
1279         .kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,
1280         .kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,
1281         .read_register = amdgpu_cgs_read_register,
1282         .write_register = amdgpu_cgs_write_register,
1283         .read_ind_register = amdgpu_cgs_read_ind_register,
1284         .write_ind_register = amdgpu_cgs_write_ind_register,
1285         .read_pci_config_byte = amdgpu_cgs_read_pci_config_byte,
1286         .read_pci_config_word = amdgpu_cgs_read_pci_config_word,
1287         .read_pci_config_dword = amdgpu_cgs_read_pci_config_dword,
1288         .write_pci_config_byte = amdgpu_cgs_write_pci_config_byte,
1289         .write_pci_config_word = amdgpu_cgs_write_pci_config_word,
1290         .write_pci_config_dword = amdgpu_cgs_write_pci_config_dword,
1291         .get_pci_resource = amdgpu_cgs_get_pci_resource,
1292         .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
1293         .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
1294         .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
1295         .create_pm_request = amdgpu_cgs_create_pm_request,
1296         .destroy_pm_request = amdgpu_cgs_destroy_pm_request,
1297         .set_pm_request = amdgpu_cgs_set_pm_request,
1298         .pm_request_clock = amdgpu_cgs_pm_request_clock,
1299         .pm_request_engine = amdgpu_cgs_pm_request_engine,
1300         .pm_query_clock_limits = amdgpu_cgs_pm_query_clock_limits,
1301         .set_camera_voltages = amdgpu_cgs_set_camera_voltages,
1302         .get_firmware_info = amdgpu_cgs_get_firmware_info,
1303         .rel_firmware = amdgpu_cgs_rel_firmware,
1304         .set_powergating_state = amdgpu_cgs_set_powergating_state,
1305         .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
1306         .get_active_displays_info = amdgpu_cgs_get_active_displays_info,
1307         .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
1308         .call_acpi_method = amdgpu_cgs_call_acpi_method,
1309         .query_system_info = amdgpu_cgs_query_system_info,
1310         .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
1311         .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
1312 };
1313
1314 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
1315         .add_irq_source = amdgpu_cgs_add_irq_source,
1316         .irq_get = amdgpu_cgs_irq_get,
1317         .irq_put = amdgpu_cgs_irq_put
1318 };
1319
1320 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
1321 {
1322         struct amdgpu_cgs_device *cgs_device =
1323                 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1324
1325         if (!cgs_device) {
1326                 DRM_ERROR("Couldn't allocate CGS device structure\n");
1327                 return NULL;
1328         }
1329
1330         cgs_device->base.ops = &amdgpu_cgs_ops;
1331         cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1332         cgs_device->adev = adev;
1333
1334         return (struct cgs_device *)cgs_device;
1335 }
1336
1337 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
1338 {
1339         kfree(cgs_device);
1340 }