drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define ohci_info(ohci, f, args...)     dev_info(ohci->card.device, f, ##args)
  58 #define ohci_notice(ohci, f, args...)   dev_notice(ohci->card.device, f, ##args)
  59 #define ohci_err(ohci, f, args...)      dev_err(ohci->card.device, f, ##args)
  60
  61 #define DESCRIPTOR_OUTPUT_MORE          0
  62 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  63 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  64 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  65 #define DESCRIPTOR_STATUS               (1 << 11)
  66 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  67 #define DESCRIPTOR_PING                 (1 << 7)
  68 #define DESCRIPTOR_YY                   (1 << 6)
  69 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  70 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  71 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  72 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  73 #define DESCRIPTOR_WAIT                 (3 << 0)
  74
  75 #define DESCRIPTOR_CMD                  (0xf << 12)
  76
  77 struct descriptor {
  78         __le16 req_count;
  79         __le16 control;
  80         __le32 data_address;
  81         __le32 branch_address;
  82         __le16 res_count;
  83         __le16 transfer_status;
  84 } __attribute__((aligned(16)));
  85
  86 #define CONTROL_SET(regs)       (regs)
  87 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  88 #define COMMAND_PTR(regs)       ((regs) + 12)
  89 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  90
  91 #define AR_BUFFER_SIZE  (32*1024)
  92 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  93 /* we need at least two pages for proper list management */
  94 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  95
  96 #define MAX_ASYNC_PAYLOAD       4096
  97 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  98 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  99
 100 struct ar_context {
 101         struct fw_ohci *ohci;
 102         struct page *pages[AR_BUFFERS];
 103         void *buffer;
 104         struct descriptor *descriptors;
 105         dma_addr_t descriptors_bus;
 106         void *pointer;
 107         unsigned int last_buffer_index;
 108         u32 regs;
 109         struct tasklet_struct tasklet;
 110 };
 111
 112 struct context;
 113
 114 typedef int (*descriptor_callback_t)(struct context *ctx,
 115                                      struct descriptor *d,
 116                                      struct descriptor *last);
 117
 118 /*
 119  * A buffer that contains a block of DMA-able coherent memory used for
 120  * storing a portion of a DMA descriptor program.
 121  */
 122 struct descriptor_buffer {
 123         struct list_head list;
 124         dma_addr_t buffer_bus;
 125         size_t buffer_size;
 126         size_t used;
 127         struct descriptor buffer[0];
 128 };
 129
 130 struct context {
 131         struct fw_ohci *ohci;
 132         u32 regs;
 133         int total_allocation;
 134         u32 current_bus;
 135         bool running;
 136         bool flushing;
 137
 138         /*
 139          * List of page-sized buffers for storing DMA descriptors.
 140          * Head of list contains buffers in use and tail of list contains
 141          * free buffers.
 142          */
 143         struct list_head buffer_list;
 144
 145         /*
 146          * Pointer to a buffer inside buffer_list that contains the tail
 147          * end of the current DMA program.
 148          */
 149         struct descriptor_buffer *buffer_tail;
 150
 151         /*
 152          * The descriptor containing the branch address of the first
 153          * descriptor that has not yet been filled by the device.
 154          */
 155         struct descriptor *last;
 156
 157         /*
 158          * The last descriptor block in the DMA program. It contains the branch
 159          * address that must be updated upon appending a new descriptor.
 160          */
 161         struct descriptor *prev;
 162         int prev_z;
 163
 164         descriptor_callback_t callback;
 165
 166         struct tasklet_struct tasklet;
 167 };
 168
 169 #define IT_HEADER_SY(v)          ((v) <<  0)
 170 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 171 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 172 #define IT_HEADER_TAG(v)         ((v) << 14)
 173 #define IT_HEADER_SPEED(v)       ((v) << 16)
 174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 175
 176 struct iso_context {
 177         struct fw_iso_context base;
 178         struct context context;
 179         void *header;
 180         size_t header_length;
 181         unsigned long flushing_completions;
 182         u32 mc_buffer_bus;
 183         u16 mc_completed;
 184         u16 last_timestamp;
 185         u8 sync;
 186         u8 tags;
 187 };
 188
 189 #define CONFIG_ROM_SIZE 1024
 190
 191 struct fw_ohci {
 192         struct fw_card card;
 193
 194         __iomem char *registers;
 195         int node_id;
 196         int generation;
 197         int request_generation; /* for timestamping incoming requests */
 198         unsigned quirks;
 199         unsigned int pri_req_max;
 200         u32 bus_time;
 201         bool bus_time_running;
 202         bool is_root;
 203         bool csr_state_setclear_abdicate;
 204         int n_ir;
 205         int n_it;
 206         /*
 207          * Spinlock for accessing fw_ohci data.  Never call out of
 208          * this driver with this lock held.
 209          */
 210         spinlock_t lock;
 211
 212         struct mutex phy_reg_mutex;
 213
 214         void *misc_buffer;
 215         dma_addr_t misc_buffer_bus;
 216
 217         struct ar_context ar_request_ctx;
 218         struct ar_context ar_response_ctx;
 219         struct context at_request_ctx;
 220         struct context at_response_ctx;
 221
 222         u32 it_context_support;
 223         u32 it_context_mask;     /* unoccupied IT contexts */
 224         struct iso_context *it_context_list;
 225         u64 ir_context_channels; /* unoccupied channels */
 226         u32 ir_context_support;
 227         u32 ir_context_mask;     /* unoccupied IR contexts */
 228         struct iso_context *ir_context_list;
 229         u64 mc_channels; /* channels in use by the multichannel IR context */
 230         bool mc_allocated;
 231
 232         __be32    *config_rom;
 233         dma_addr_t config_rom_bus;
 234         __be32    *next_config_rom;
 235         dma_addr_t next_config_rom_bus;
 236         __be32     next_header;
 237
 238         __le32    *self_id;
 239         dma_addr_t self_id_bus;
 240         struct work_struct bus_reset_work;
 241
 242         u32 self_id_buffer[512];
 243 };
 244
 245 static struct workqueue_struct *selfid_workqueue;
 246
 247 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 248 {
 249         return container_of(card, struct fw_ohci, card);
 250 }
 251
 252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 253 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 254 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 256 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 257 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 258
 259 #define CONTEXT_RUN     0x8000
 260 #define CONTEXT_WAKE    0x1000
 261 #define CONTEXT_DEAD    0x0800
 262 #define CONTEXT_ACTIVE  0x0400
 263
 264 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 265 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 266 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 267
 268 #define OHCI1394_REGISTER_SIZE          0x800
 269 #define OHCI1394_PCI_HCI_Control        0x40
 270 #define SELF_ID_BUF_SIZE                0x800
 271 #define OHCI_TCODE_PHY_PACKET           0x0e
 272 #define OHCI_VERSION_1_1                0x010010
 273
 274 static char ohci_driver_name[] = KBUILD_MODNAME;
 275
 276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 277 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 278 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 280 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 281 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 282 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 283 #define PCI_DEVICE_ID_VIA_VT630X        0x3044
 284 #define PCI_REV_ID_VIA_VT6306           0x46
 285 #define PCI_DEVICE_ID_VIA_VT6315        0x3403
 286
 287 #define QUIRK_CYCLE_TIMER               0x1
 288 #define QUIRK_RESET_PACKET              0x2
 289 #define QUIRK_BE_HEADERS                0x4
 290 #define QUIRK_NO_1394A                  0x8
 291 #define QUIRK_NO_MSI                    0x10
 292 #define QUIRK_TI_SLLZ059                0x20
 293 #define QUIRK_IR_WAKE                   0x40
 294
 295 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 296 static const struct {
 297         unsigned short vendor, device, revision, flags;
 298 } ohci_quirks[] = {
 299         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 300                 QUIRK_CYCLE_TIMER},
 301
 302         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 303                 QUIRK_BE_HEADERS},
 304
 305         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 306                 QUIRK_NO_MSI},
 307
 308         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 309                 QUIRK_RESET_PACKET},
 310
 311         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 312                 QUIRK_NO_MSI},
 313
 314         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 315                 QUIRK_CYCLE_TIMER},
 316
 317         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 318                 QUIRK_NO_MSI},
 319
 320         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 321                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 322
 323         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 324                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 325
 326         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 327                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 328
 329         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 330                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 331
 332         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 333                 QUIRK_RESET_PACKET},
 334
 335         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
 336                 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
 337
 338         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
 339                 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
 340
 341         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
 342                 QUIRK_NO_MSI},
 343
 344         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 345                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 346 };
 347
 348 /* This overrides anything that was found in ohci_quirks[]. */
 349 static int param_quirks;
 350 module_param_named(quirks, param_quirks, int, 0644);
 351 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 352         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 353         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 354         ", AR/selfID endianness = "     __stringify(QUIRK_BE_HEADERS)
 355         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 356         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 357         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 358         ", IR wake unreliable = "       __stringify(QUIRK_IR_WAKE)
 359         ")");
 360
 361 #define OHCI_PARAM_DEBUG_AT_AR          1
 362 #define OHCI_PARAM_DEBUG_SELFIDS        2
 363 #define OHCI_PARAM_DEBUG_IRQS           4
 364 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 365
 366 static int param_debug;
 367 module_param_named(debug, param_debug, int, 0644);
 368 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 369         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 370         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 371         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 372         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 373         ", or a combination, or all = -1)");
 374
 375 static bool param_remote_dma;
 376 module_param_named(remote_dma, param_remote_dma, bool, 0444);
 377 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
 378
 379 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 380 {
 381         if (likely(!(param_debug &
 382                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 383                 return;
 384
 385         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 386             !(evt & OHCI1394_busReset))
 387                 return;
 388
 389         ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 390             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 391             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 392             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 393             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 394             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 395             evt & OHCI1394_isochRx              ? " IR"                 : "",
 396             evt & OHCI1394_isochTx              ? " IT"                 : "",
 397             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 398             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 399             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 400             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 401             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 402             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 403             evt & OHCI1394_busReset             ? " busReset"           : "",
 404             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 405                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 406                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 407                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 408                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 409                     OHCI1394_cycleInconsistent |
 410                     OHCI1394_regAccessFail | OHCI1394_busReset)
 411                                                 ? " ?"                  : "");
 412 }
 413
 414 static const char *speed[] = {
 415         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 416 };
 417 static const char *power[] = {
 418         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 419         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 420 };
 421 static const char port[] = { '.', '-', 'p', 'c', };
 422
 423 static char _p(u32 *s, int shift)
 424 {
 425         return port[*s >> shift & 3];
 426 }
 427
 428 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 429 {
 430         u32 *s;
 431
 432         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 433                 return;
 434
 435         ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
 436                     self_id_count, generation, ohci->node_id);
 437
 438         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 439                 if ((*s & 1 << 23) == 0)
 440                         ohci_notice(ohci,
 441                             "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
 442                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 443                             speed[*s >> 14 & 3], *s >> 16 & 63,
 444                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 445                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 446                 else
 447                         ohci_notice(ohci,
 448                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 449                             *s, *s >> 24 & 63,
 450                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 451                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 452 }
 453
 454 static const char *evts[] = {
 455         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 456         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 457         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 458         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 459         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 460         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 461         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 462         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 463         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 464         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 465         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 466         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 467         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 468         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 469         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 470         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 471         [0x20] = "pending/cancelled",
 472 };
 473 static const char *tcodes[] = {
 474         [0x0] = "QW req",               [0x1] = "BW req",
 475         [0x2] = "W resp",               [0x3] = "-reserved-",
 476         [0x4] = "QR req",               [0x5] = "BR req",
 477         [0x6] = "QR resp",              [0x7] = "BR resp",
 478         [0x8] = "cycle start",          [0x9] = "Lk req",
 479         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 480         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 481         [0xe] = "link internal",        [0xf] = "-reserved-",
 482 };
 483
 484 static void log_ar_at_event(struct fw_ohci *ohci,
 485                             char dir, int speed, u32 *header, int evt)
 486 {
 487         int tcode = header[0] >> 4 & 0xf;
 488         char specific[12];
 489
 490         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 491                 return;
 492
 493         if (unlikely(evt >= ARRAY_SIZE(evts)))
 494                         evt = 0x1f;
 495
 496         if (evt == OHCI1394_evt_bus_reset) {
 497                 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
 498                             dir, (header[2] >> 16) & 0xff);
 499                 return;
 500         }
 501
 502         switch (tcode) {
 503         case 0x0: case 0x6: case 0x8:
 504                 snprintf(specific, sizeof(specific), " = %08x",
 505                          be32_to_cpu((__force __be32)header[3]));
 506                 break;
 507         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 508                 snprintf(specific, sizeof(specific), " %x,%x",
 509                          header[3] >> 16, header[3] & 0xffff);
 510                 break;
 511         default:
 512                 specific[0] = '\0';
 513         }
 514
 515         switch (tcode) {
 516         case 0xa:
 517                 ohci_notice(ohci, "A%c %s, %s\n",
 518                             dir, evts[evt], tcodes[tcode]);
 519                 break;
 520         case 0xe:
 521                 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
 522                             dir, evts[evt], header[1], header[2]);
 523                 break;
 524         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 525                 ohci_notice(ohci,
 526                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
 527                             dir, speed, header[0] >> 10 & 0x3f,
 528                             header[1] >> 16, header[0] >> 16, evts[evt],
 529                             tcodes[tcode], header[1] & 0xffff, header[2], specific);
 530                 break;
 531         default:
 532                 ohci_notice(ohci,
 533                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
 534                             dir, speed, header[0] >> 10 & 0x3f,
 535                             header[1] >> 16, header[0] >> 16, evts[evt],
 536                             tcodes[tcode], specific);
 537         }
 538 }
 539
 540 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 541 {
 542         writel(data, ohci->registers + offset);
 543 }
 544
 545 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 546 {
 547         return readl(ohci->registers + offset);
 548 }
 549
 550 static inline void flush_writes(const struct fw_ohci *ohci)
 551 {
 552         /* Do a dummy read to flush writes. */
 553         reg_read(ohci, OHCI1394_Version);
 554 }
 555
 556 /*
 557  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 558  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 559  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 560  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 561  */
 562 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 563 {
 564         u32 val;
 565         int i;
 566
 567         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 568         for (i = 0; i < 3 + 100; i++) {
 569                 val = reg_read(ohci, OHCI1394_PhyControl);
 570                 if (!~val)
 571                         return -ENODEV; /* Card was ejected. */
 572
 573                 if (val & OHCI1394_PhyControl_ReadDone)
 574                         return OHCI1394_PhyControl_ReadData(val);
 575
 576                 /*
 577                  * Try a few times without waiting.  Sleeping is necessary
 578                  * only when the link/PHY interface is busy.
 579                  */
 580                 if (i >= 3)
 581                         msleep(1);
 582         }
 583         ohci_err(ohci, "failed to read phy reg %d\n", addr);
 584         dump_stack();
 585
 586         return -EBUSY;
 587 }
 588
 589 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 590 {
 591         int i;
 592
 593         reg_write(ohci, OHCI1394_PhyControl,
 594                   OHCI1394_PhyControl_Write(addr, val));
 595         for (i = 0; i < 3 + 100; i++) {
 596                 val = reg_read(ohci, OHCI1394_PhyControl);
 597                 if (!~val)
 598                         return -ENODEV; /* Card was ejected. */
 599
 600                 if (!(val & OHCI1394_PhyControl_WritePending))
 601                         return 0;
 602
 603                 if (i >= 3)
 604                         msleep(1);
 605         }
 606         ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
 607         dump_stack();
 608
 609         return -EBUSY;
 610 }
 611
 612 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 613                           int clear_bits, int set_bits)
 614 {
 615         int ret = read_phy_reg(ohci, addr);
 616         if (ret < 0)
 617                 return ret;
 618
 619         /*
 620          * The interrupt status bits are cleared by writing a one bit.
 621          * Avoid clearing them unless explicitly requested in set_bits.
 622          */
 623         if (addr == 5)
 624                 clear_bits |= PHY_INT_STATUS_BITS;
 625
 626         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 627 }
 628
 629 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 630 {
 631         int ret;
 632
 633         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 634         if (ret < 0)
 635                 return ret;
 636
 637         return read_phy_reg(ohci, addr);
 638 }
 639
 640 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 641 {
 642         struct fw_ohci *ohci = fw_ohci(card);
 643         int ret;
 644
 645         mutex_lock(&ohci->phy_reg_mutex);
 646         ret = read_phy_reg(ohci, addr);
 647         mutex_unlock(&ohci->phy_reg_mutex);
 648
 649         return ret;
 650 }
 651
 652 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 653                                int clear_bits, int set_bits)
 654 {
 655         struct fw_ohci *ohci = fw_ohci(card);
 656         int ret;
 657
 658         mutex_lock(&ohci->phy_reg_mutex);
 659         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 660         mutex_unlock(&ohci->phy_reg_mutex);
 661
 662         return ret;
 663 }
 664
 665 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 666 {
 667         return page_private(ctx->pages[i]);
 668 }
 669
 670 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 671 {
 672         struct descriptor *d;
 673
 674         d = &ctx->descriptors[index];
 675         d->branch_address  &= cpu_to_le32(~0xf);
 676         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 677         d->transfer_status =  0;
 678
 679         wmb(); /* finish init of new descriptors before branch_address update */
 680         d = &ctx->descriptors[ctx->last_buffer_index];
 681         d->branch_address  |= cpu_to_le32(1);
 682
 683         ctx->last_buffer_index = index;
 684
 685         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 686 }
 687
 688 static void ar_context_release(struct ar_context *ctx)
 689 {
 690         unsigned int i;
 691
 692         vunmap(ctx->buffer);
 693
 694         for (i = 0; i < AR_BUFFERS; i++)
 695                 if (ctx->pages[i]) {
 696                         dma_unmap_page(ctx->ohci->card.device,
 697                                        ar_buffer_bus(ctx, i),
 698                                        PAGE_SIZE, DMA_FROM_DEVICE);
 699                         __free_page(ctx->pages[i]);
 700                 }
 701 }
 702
 703 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 704 {
 705         struct fw_ohci *ohci = ctx->ohci;
 706
 707         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 708                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 709                 flush_writes(ohci);
 710
 711                 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
 712         }
 713         /* FIXME: restart? */
 714 }
 715
 716 static inline unsigned int ar_next_buffer_index(unsigned int index)
 717 {
 718         return (index + 1) % AR_BUFFERS;
 719 }
 720
 721 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 722 {
 723         return ar_next_buffer_index(ctx->last_buffer_index);
 724 }
 725
 726 /*
 727  * We search for the buffer that contains the last AR packet DMA data written
 728  * by the controller.
 729  */
 730 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 731                                                  unsigned int *buffer_offset)
 732 {
 733         unsigned int i, next_i, last = ctx->last_buffer_index;
 734         __le16 res_count, next_res_count;
 735
 736         i = ar_first_buffer_index(ctx);
 737         res_count = READ_ONCE(ctx->descriptors[i].res_count);
 738
 739         /* A buffer that is not yet completely filled must be the last one. */
 740         while (i != last && res_count == 0) {
 741
 742                 /* Peek at the next descriptor. */
 743                 next_i = ar_next_buffer_index(i);
 744                 rmb(); /* read descriptors in order */
 745                 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
 746                 /*
 747                  * If the next descriptor is still empty, we must stop at this
 748                  * descriptor.
 749                  */
 750                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 751                         /*
 752                          * The exception is when the DMA data for one packet is
 753                          * split over three buffers; in this case, the middle
 754                          * buffer's descriptor might be never updated by the
 755                          * controller and look still empty, and we have to peek
 756                          * at the third one.
 757                          */
 758                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 759                                 next_i = ar_next_buffer_index(next_i);
 760                                 rmb();
 761                                 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
 762                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 763                                         goto next_buffer_is_active;
 764                         }
 765
 766                         break;
 767                 }
 768
 769 next_buffer_is_active:
 770                 i = next_i;
 771                 res_count = next_res_count;
 772         }
 773
 774         rmb(); /* read res_count before the DMA data */
 775
 776         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 777         if (*buffer_offset > PAGE_SIZE) {
 778                 *buffer_offset = 0;
 779                 ar_context_abort(ctx, "corrupted descriptor");
 780         }
 781
 782         return i;
 783 }
 784
 785 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 786                                     unsigned int end_buffer_index,
 787                                     unsigned int end_buffer_offset)
 788 {
 789         unsigned int i;
 790
 791         i = ar_first_buffer_index(ctx);
 792         while (i != end_buffer_index) {
 793                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 794                                         ar_buffer_bus(ctx, i),
 795                                         PAGE_SIZE, DMA_FROM_DEVICE);
 796                 i = ar_next_buffer_index(i);
 797         }
 798         if (end_buffer_offset > 0)
 799                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 800                                         ar_buffer_bus(ctx, i),
 801                                         end_buffer_offset, DMA_FROM_DEVICE);
 802 }
 803
 804 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 805 #define cond_le32_to_cpu(v) \
 806         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 807 #else
 808 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 809 #endif
 810
 811 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 812 {
 813         struct fw_ohci *ohci = ctx->ohci;
 814         struct fw_packet p;
 815         u32 status, length, tcode;
 816         int evt;
 817
 818         p.header[0] = cond_le32_to_cpu(buffer[0]);
 819         p.header[1] = cond_le32_to_cpu(buffer[1]);
 820         p.header[2] = cond_le32_to_cpu(buffer[2]);
 821
 822         tcode = (p.header[0] >> 4) & 0x0f;
 823         switch (tcode) {
 824         case TCODE_WRITE_QUADLET_REQUEST:
 825         case TCODE_READ_QUADLET_RESPONSE:
 826                 p.header[3] = (__force __u32) buffer[3];
 827                 p.header_length = 16;
 828                 p.payload_length = 0;
 829                 break;
 830
 831         case TCODE_READ_BLOCK_REQUEST :
 832                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 833                 p.header_length = 16;
 834                 p.payload_length = 0;
 835                 break;
 836
 837         case TCODE_WRITE_BLOCK_REQUEST:
 838         case TCODE_READ_BLOCK_RESPONSE:
 839         case TCODE_LOCK_REQUEST:
 840         case TCODE_LOCK_RESPONSE:
 841                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 842                 p.header_length = 16;
 843                 p.payload_length = p.header[3] >> 16;
 844                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 845                         ar_context_abort(ctx, "invalid packet length");
 846                         return NULL;
 847                 }
 848                 break;
 849
 850         case TCODE_WRITE_RESPONSE:
 851         case TCODE_READ_QUADLET_REQUEST:
 852         case OHCI_TCODE_PHY_PACKET:
 853                 p.header_length = 12;
 854                 p.payload_length = 0;
 855                 break;
 856
 857         default:
 858                 ar_context_abort(ctx, "invalid tcode");
 859                 return NULL;
 860         }
 861
 862         p.payload = (void *) buffer + p.header_length;
 863
 864         /* FIXME: What to do about evt_* errors? */
 865         length = (p.header_length + p.payload_length + 3) / 4;
 866         status = cond_le32_to_cpu(buffer[length]);
 867         evt    = (status >> 16) & 0x1f;
 868
 869         p.ack        = evt - 16;
 870         p.speed      = (status >> 21) & 0x7;
 871         p.timestamp  = status & 0xffff;
 872         p.generation = ohci->request_generation;
 873
 874         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 875
 876         /*
 877          * Several controllers, notably from NEC and VIA, forget to
 878          * write ack_complete status at PHY packet reception.
 879          */
 880         if (evt == OHCI1394_evt_no_status &&
 881             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 882                 p.ack = ACK_COMPLETE;
 883
 884         /*
 885          * The OHCI bus reset handler synthesizes a PHY packet with
 886          * the new generation number when a bus reset happens (see
 887          * section 8.4.2.3).  This helps us determine when a request
 888          * was received and make sure we send the response in the same
 889          * generation.  We only need this for requests; for responses
 890          * we use the unique tlabel for finding the matching
 891          * request.
 892          *
 893          * Alas some chips sometimes emit bus reset packets with a
 894          * wrong generation.  We set the correct generation for these
 895          * at a slightly incorrect time (in bus_reset_work).
 896          */
 897         if (evt == OHCI1394_evt_bus_reset) {
 898                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 899                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 900         } else if (ctx == &ohci->ar_request_ctx) {
 901                 fw_core_handle_request(&ohci->card, &p);
 902         } else {
 903                 fw_core_handle_response(&ohci->card, &p);
 904         }
 905
 906         return buffer + length + 1;
 907 }
 908
 909 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 910 {
 911         void *next;
 912
 913         while (p < end) {
 914                 next = handle_ar_packet(ctx, p);
 915                 if (!next)
 916                         return p;
 917                 p = next;
 918         }
 919
 920         return p;
 921 }
 922
 923 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 924 {
 925         unsigned int i;
 926
 927         i = ar_first_buffer_index(ctx);
 928         while (i != end_buffer) {
 929                 dma_sync_single_for_device(ctx->ohci->card.device,
 930                                            ar_buffer_bus(ctx, i),
 931                                            PAGE_SIZE, DMA_FROM_DEVICE);
 932                 ar_context_link_page(ctx, i);
 933                 i = ar_next_buffer_index(i);
 934         }
 935 }
 936
 937 static void ar_context_tasklet(unsigned long data)
 938 {
 939         struct ar_context *ctx = (struct ar_context *)data;
 940         unsigned int end_buffer_index, end_buffer_offset;
 941         void *p, *end;
 942
 943         p = ctx->pointer;
 944         if (!p)
 945                 return;
 946
 947         end_buffer_index = ar_search_last_active_buffer(ctx,
 948                                                         &end_buffer_offset);
 949         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 950         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 951
 952         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 953                 /*
 954                  * The filled part of the overall buffer wraps around; handle
 955                  * all packets up to the buffer end here.  If the last packet
 956                  * wraps around, its tail will be visible after the buffer end
 957                  * because the buffer start pages are mapped there again.
 958                  */
 959                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 960                 p = handle_ar_packets(ctx, p, buffer_end);
 961                 if (p < buffer_end)
 962                         goto error;
 963                 /* adjust p to point back into the actual buffer */
 964                 p -= AR_BUFFERS * PAGE_SIZE;
 965         }
 966
 967         p = handle_ar_packets(ctx, p, end);
 968         if (p != end) {
 969                 if (p > end)
 970                         ar_context_abort(ctx, "inconsistent descriptor");
 971                 goto error;
 972         }
 973
 974         ctx->pointer = p;
 975         ar_recycle_buffers(ctx, end_buffer_index);
 976
 977         return;
 978
 979 error:
 980         ctx->pointer = NULL;
 981 }
 982
 983 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 984                            unsigned int descriptors_offset, u32 regs)
 985 {
 986         unsigned int i;
 987         dma_addr_t dma_addr;
 988         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 989         struct descriptor *d;
 990
 991         ctx->regs        = regs;
 992         ctx->ohci        = ohci;
 993         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 994
 995         for (i = 0; i < AR_BUFFERS; i++) {
 996                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 997                 if (!ctx->pages[i])
 998                         goto out_of_memory;
 999                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1000                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
1001                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1002                         __free_page(ctx->pages[i]);
1003                         ctx->pages[i] = NULL;
1004                         goto out_of_memory;
1005                 }
1006                 set_page_private(ctx->pages[i], dma_addr);
1007         }
1008
1009         for (i = 0; i < AR_BUFFERS; i++)
1010                 pages[i]              = ctx->pages[i];
1011         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1012                 pages[AR_BUFFERS + i] = ctx->pages[i];
1013         ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1014         if (!ctx->buffer)
1015                 goto out_of_memory;
1016
1017         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1018         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1019
1020         for (i = 0; i < AR_BUFFERS; i++) {
1021                 d = &ctx->descriptors[i];
1022                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1023                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1024                                                 DESCRIPTOR_STATUS |
1025                                                 DESCRIPTOR_BRANCH_ALWAYS);
1026                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1027                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1028                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1029         }
1030
1031         return 0;
1032
1033 out_of_memory:
1034         ar_context_release(ctx);
1035
1036         return -ENOMEM;
1037 }
1038
1039 static void ar_context_run(struct ar_context *ctx)
1040 {
1041         unsigned int i;
1042
1043         for (i = 0; i < AR_BUFFERS; i++)
1044                 ar_context_link_page(ctx, i);
1045
1046         ctx->pointer = ctx->buffer;
1047
1048         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1049         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1050 }
1051
1052 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1053 {
1054         __le16 branch;
1055
1056         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1057
1058         /* figure out which descriptor the branch address goes in */
1059         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1060                 return d;
1061         else
1062                 return d + z - 1;
1063 }
1064
1065 static void context_tasklet(unsigned long data)
1066 {
1067         struct context *ctx = (struct context *) data;
1068         struct descriptor *d, *last;
1069         u32 address;
1070         int z;
1071         struct descriptor_buffer *desc;
1072
1073         desc = list_entry(ctx->buffer_list.next,
1074                         struct descriptor_buffer, list);
1075         last = ctx->last;
1076         while (last->branch_address != 0) {
1077                 struct descriptor_buffer *old_desc = desc;
1078                 address = le32_to_cpu(last->branch_address);
1079                 z = address & 0xf;
1080                 address &= ~0xf;
1081                 ctx->current_bus = address;
1082
1083                 /* If the branch address points to a buffer outside of the
1084                  * current buffer, advance to the next buffer. */
1085                 if (address < desc->buffer_bus ||
1086                                 address >= desc->buffer_bus + desc->used)
1087                         desc = list_entry(desc->list.next,
1088                                         struct descriptor_buffer, list);
1089                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1090                 last = find_branch_descriptor(d, z);
1091
1092                 if (!ctx->callback(ctx, d, last))
1093                         break;
1094
1095                 if (old_desc != desc) {
1096                         /* If we've advanced to the next buffer, move the
1097                          * previous buffer to the free list. */
1098                         unsigned long flags;
1099                         old_desc->used = 0;
1100                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1101                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1102                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1103                 }
1104                 ctx->last = last;
1105         }
1106 }
1107
1108 /*
1109  * Allocate a new buffer and add it to the list of free buffers for this
1110  * context.  Must be called with ohci->lock held.
1111  */
1112 static int context_add_buffer(struct context *ctx)
1113 {
1114         struct descriptor_buffer *desc;
1115         dma_addr_t uninitialized_var(bus_addr);
1116         int offset;
1117
1118         /*
1119          * 16MB of descriptors should be far more than enough for any DMA
1120          * program.  This will catch run-away userspace or DoS attacks.
1121          */
1122         if (ctx->total_allocation >= 16*1024*1024)
1123                 return -ENOMEM;
1124
1125         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1126                         &bus_addr, GFP_ATOMIC);
1127         if (!desc)
1128                 return -ENOMEM;
1129
1130         offset = (void *)&desc->buffer - (void *)desc;
1131         desc->buffer_size = PAGE_SIZE - offset;
1132         desc->buffer_bus = bus_addr + offset;
1133         desc->used = 0;
1134
1135         list_add_tail(&desc->list, &ctx->buffer_list);
1136         ctx->total_allocation += PAGE_SIZE;
1137
1138         return 0;
1139 }
1140
1141 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1142                         u32 regs, descriptor_callback_t callback)
1143 {
1144         ctx->ohci = ohci;
1145         ctx->regs = regs;
1146         ctx->total_allocation = 0;
1147
1148         INIT_LIST_HEAD(&ctx->buffer_list);
1149         if (context_add_buffer(ctx) < 0)
1150                 return -ENOMEM;
1151
1152         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1153                         struct descriptor_buffer, list);
1154
1155         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1156         ctx->callback = callback;
1157
1158         /*
1159          * We put a dummy descriptor in the buffer that has a NULL
1160          * branch address and looks like it's been sent.  That way we
1161          * have a descriptor to append DMA programs to.
1162          */
1163         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1164         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1165         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1166         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1167         ctx->last = ctx->buffer_tail->buffer;
1168         ctx->prev = ctx->buffer_tail->buffer;
1169         ctx->prev_z = 1;
1170
1171         return 0;
1172 }
1173
1174 static void context_release(struct context *ctx)
1175 {
1176         struct fw_card *card = &ctx->ohci->card;
1177         struct descriptor_buffer *desc, *tmp;
1178
1179         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1180                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1181                         desc->buffer_bus -
1182                         ((void *)&desc->buffer - (void *)desc));
1183 }
1184
1185 /* Must be called with ohci->lock held */
1186 static struct descriptor *context_get_descriptors(struct context *ctx,
1187                                                   int z, dma_addr_t *d_bus)
1188 {
1189         struct descriptor *d = NULL;
1190         struct descriptor_buffer *desc = ctx->buffer_tail;
1191
1192         if (z * sizeof(*d) > desc->buffer_size)
1193                 return NULL;
1194
1195         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1196                 /* No room for the descriptor in this buffer, so advance to the
1197                  * next one. */
1198
1199                 if (desc->list.next == &ctx->buffer_list) {
1200                         /* If there is no free buffer next in the list,
1201                          * allocate one. */
1202                         if (context_add_buffer(ctx) < 0)
1203                                 return NULL;
1204                 }
1205                 desc = list_entry(desc->list.next,
1206                                 struct descriptor_buffer, list);
1207                 ctx->buffer_tail = desc;
1208         }
1209
1210         d = desc->buffer + desc->used / sizeof(*d);
1211         memset(d, 0, z * sizeof(*d));
1212         *d_bus = desc->buffer_bus + desc->used;
1213
1214         return d;
1215 }
1216
1217 static void context_run(struct context *ctx, u32 extra)
1218 {
1219         struct fw_ohci *ohci = ctx->ohci;
1220
1221         reg_write(ohci, COMMAND_PTR(ctx->regs),
1222                   le32_to_cpu(ctx->last->branch_address));
1223         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1224         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1225         ctx->running = true;
1226         flush_writes(ohci);
1227 }
1228
1229 static void context_append(struct context *ctx,
1230                            struct descriptor *d, int z, int extra)
1231 {
1232         dma_addr_t d_bus;
1233         struct descriptor_buffer *desc = ctx->buffer_tail;
1234         struct descriptor *d_branch;
1235
1236         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1237
1238         desc->used += (z + extra) * sizeof(*d);
1239
1240         wmb(); /* finish init of new descriptors before branch_address update */
1241
1242         d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1243         d_branch->branch_address = cpu_to_le32(d_bus | z);
1244
1245         /*
1246          * VT6306 incorrectly checks only the single descriptor at the
1247          * CommandPtr when the wake bit is written, so if it's a
1248          * multi-descriptor block starting with an INPUT_MORE, put a copy of
1249          * the branch address in the first descriptor.
1250          *
1251          * Not doing this for transmit contexts since not sure how it interacts
1252          * with skip addresses.
1253          */
1254         if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1255             d_branch != ctx->prev &&
1256             (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1257              cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1258                 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1259         }
1260
1261         ctx->prev = d;
1262         ctx->prev_z = z;
1263 }
1264
1265 static void context_stop(struct context *ctx)
1266 {
1267         struct fw_ohci *ohci = ctx->ohci;
1268         u32 reg;
1269         int i;
1270
1271         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1272         ctx->running = false;
1273
1274         for (i = 0; i < 1000; i++) {
1275                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1276                 if ((reg & CONTEXT_ACTIVE) == 0)
1277                         return;
1278
1279                 if (i)
1280                         udelay(10);
1281         }
1282         ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1283 }
1284
1285 struct driver_data {
1286         u8 inline_data[8];
1287         struct fw_packet *packet;
1288 };
1289
1290 /*
1291  * This function apppends a packet to the DMA queue for transmission.
1292  * Must always be called with the ochi->lock held to ensure proper
1293  * generation handling and locking around packet queue manipulation.
1294  */
1295 static int at_context_queue_packet(struct context *ctx,
1296                                    struct fw_packet *packet)
1297 {
1298         struct fw_ohci *ohci = ctx->ohci;
1299         dma_addr_t d_bus, uninitialized_var(payload_bus);
1300         struct driver_data *driver_data;
1301         struct descriptor *d, *last;
1302         __le32 *header;
1303         int z, tcode;
1304
1305         d = context_get_descriptors(ctx, 4, &d_bus);
1306         if (d == NULL) {
1307                 packet->ack = RCODE_SEND_ERROR;
1308                 return -1;
1309         }
1310
1311         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1312         d[0].res_count = cpu_to_le16(packet->timestamp);
1313
1314         /*
1315          * The DMA format for asynchronous link packets is different
1316          * from the IEEE1394 layout, so shift the fields around
1317          * accordingly.
1318          */
1319
1320         tcode = (packet->header[0] >> 4) & 0x0f;
1321         header = (__le32 *) &d[1];
1322         switch (tcode) {
1323         case TCODE_WRITE_QUADLET_REQUEST:
1324         case TCODE_WRITE_BLOCK_REQUEST:
1325         case TCODE_WRITE_RESPONSE:
1326         case TCODE_READ_QUADLET_REQUEST:
1327         case TCODE_READ_BLOCK_REQUEST:
1328         case TCODE_READ_QUADLET_RESPONSE:
1329         case TCODE_READ_BLOCK_RESPONSE:
1330         case TCODE_LOCK_REQUEST:
1331         case TCODE_LOCK_RESPONSE:
1332                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1333                                         (packet->speed << 16));
1334                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1335                                         (packet->header[0] & 0xffff0000));
1336                 header[2] = cpu_to_le32(packet->header[2]);
1337
1338                 if (TCODE_IS_BLOCK_PACKET(tcode))
1339                         header[3] = cpu_to_le32(packet->header[3]);
1340                 else
1341                         header[3] = (__force __le32) packet->header[3];
1342
1343                 d[0].req_count = cpu_to_le16(packet->header_length);
1344                 break;
1345
1346         case TCODE_LINK_INTERNAL:
1347                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1348                                         (packet->speed << 16));
1349                 header[1] = cpu_to_le32(packet->header[1]);
1350                 header[2] = cpu_to_le32(packet->header[2]);
1351                 d[0].req_count = cpu_to_le16(12);
1352
1353                 if (is_ping_packet(&packet->header[1]))
1354                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1355                 break;
1356
1357         case TCODE_STREAM_DATA:
1358                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1359                                         (packet->speed << 16));
1360                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1361                 d[0].req_count = cpu_to_le16(8);
1362                 break;
1363
1364         default:
1365                 /* BUG(); */
1366                 packet->ack = RCODE_SEND_ERROR;
1367                 return -1;
1368         }
1369
1370         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1371         driver_data = (struct driver_data *) &d[3];
1372         driver_data->packet = packet;
1373         packet->driver_data = driver_data;
1374
1375         if (packet->payload_length > 0) {
1376                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1377                         payload_bus = dma_map_single(ohci->card.device,
1378                                                      packet->payload,
1379                                                      packet->payload_length,
1380                                                      DMA_TO_DEVICE);
1381                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1382                                 packet->ack = RCODE_SEND_ERROR;
1383                                 return -1;
1384                         }
1385                         packet->payload_bus     = payload_bus;
1386                         packet->payload_mapped  = true;
1387                 } else {
1388                         memcpy(driver_data->inline_data, packet->payload,
1389                                packet->payload_length);
1390                         payload_bus = d_bus + 3 * sizeof(*d);
1391                 }
1392
1393                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1394                 d[2].data_address = cpu_to_le32(payload_bus);
1395                 last = &d[2];
1396                 z = 3;
1397         } else {
1398                 last = &d[0];
1399                 z = 2;
1400         }
1401
1402         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1403                                      DESCRIPTOR_IRQ_ALWAYS |
1404                                      DESCRIPTOR_BRANCH_ALWAYS);
1405
1406         /* FIXME: Document how the locking works. */
1407         if (ohci->generation != packet->generation) {
1408                 if (packet->payload_mapped)
1409                         dma_unmap_single(ohci->card.device, payload_bus,
1410                                          packet->payload_length, DMA_TO_DEVICE);
1411                 packet->ack = RCODE_GENERATION;
1412                 return -1;
1413         }
1414
1415         context_append(ctx, d, z, 4 - z);
1416
1417         if (ctx->running)
1418                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1419         else
1420                 context_run(ctx, 0);
1421
1422         return 0;
1423 }
1424
1425 static void at_context_flush(struct context *ctx)
1426 {
1427         tasklet_disable(&ctx->tasklet);
1428
1429         ctx->flushing = true;
1430         context_tasklet((unsigned long)ctx);
1431         ctx->flushing = false;
1432
1433         tasklet_enable(&ctx->tasklet);
1434 }
1435
1436 static int handle_at_packet(struct context *context,
1437                             struct descriptor *d,
1438                             struct descriptor *last)
1439 {
1440         struct driver_data *driver_data;
1441         struct fw_packet *packet;
1442         struct fw_ohci *ohci = context->ohci;
1443         int evt;
1444
1445         if (last->transfer_status == 0 && !context->flushing)
1446                 /* This descriptor isn't done yet, stop iteration. */
1447                 return 0;
1448
1449         driver_data = (struct driver_data *) &d[3];
1450         packet = driver_data->packet;
1451         if (packet == NULL)
1452                 /* This packet was cancelled, just continue. */
1453                 return 1;
1454
1455         if (packet->payload_mapped)
1456                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1457                                  packet->payload_length, DMA_TO_DEVICE);
1458
1459         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1460         packet->timestamp = le16_to_cpu(last->res_count);
1461
1462         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1463
1464         switch (evt) {
1465         case OHCI1394_evt_timeout:
1466                 /* Async response transmit timed out. */
1467                 packet->ack = RCODE_CANCELLED;
1468                 break;
1469
1470         case OHCI1394_evt_flushed:
1471                 /*
1472                  * The packet was flushed should give same error as
1473                  * when we try to use a stale generation count.
1474                  */
1475                 packet->ack = RCODE_GENERATION;
1476                 break;
1477
1478         case OHCI1394_evt_missing_ack:
1479                 if (context->flushing)
1480                         packet->ack = RCODE_GENERATION;
1481                 else {
1482                         /*
1483                          * Using a valid (current) generation count, but the
1484                          * node is not on the bus or not sending acks.
1485                          */
1486                         packet->ack = RCODE_NO_ACK;
1487                 }
1488                 break;
1489
1490         case ACK_COMPLETE + 0x10:
1491         case ACK_PENDING + 0x10:
1492         case ACK_BUSY_X + 0x10:
1493         case ACK_BUSY_A + 0x10:
1494         case ACK_BUSY_B + 0x10:
1495         case ACK_DATA_ERROR + 0x10:
1496         case ACK_TYPE_ERROR + 0x10:
1497                 packet->ack = evt - 0x10;
1498                 break;
1499
1500         case OHCI1394_evt_no_status:
1501                 if (context->flushing) {
1502                         packet->ack = RCODE_GENERATION;
1503                         break;
1504                 }
1505                 /* fall through */
1506
1507         default:
1508                 packet->ack = RCODE_SEND_ERROR;
1509                 break;
1510         }
1511
1512         packet->callback(packet, &ohci->card, packet->ack);
1513
1514         return 1;
1515 }
1516
1517 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1518 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1519 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1520 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1521 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1522
1523 static void handle_local_rom(struct fw_ohci *ohci,
1524                              struct fw_packet *packet, u32 csr)
1525 {
1526         struct fw_packet response;
1527         int tcode, length, i;
1528
1529         tcode = HEADER_GET_TCODE(packet->header[0]);
1530         if (TCODE_IS_BLOCK_PACKET(tcode))
1531                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1532         else
1533                 length = 4;
1534
1535         i = csr - CSR_CONFIG_ROM;
1536         if (i + length > CONFIG_ROM_SIZE) {
1537                 fw_fill_response(&response, packet->header,
1538                                  RCODE_ADDRESS_ERROR, NULL, 0);
1539         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1540                 fw_fill_response(&response, packet->header,
1541                                  RCODE_TYPE_ERROR, NULL, 0);
1542         } else {
1543                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1544                                  (void *) ohci->config_rom + i, length);
1545         }
1546
1547         fw_core_handle_response(&ohci->card, &response);
1548 }
1549
1550 static void handle_local_lock(struct fw_ohci *ohci,
1551                               struct fw_packet *packet, u32 csr)
1552 {
1553         struct fw_packet response;
1554         int tcode, length, ext_tcode, sel, try;
1555         __be32 *payload, lock_old;
1556         u32 lock_arg, lock_data;
1557
1558         tcode = HEADER_GET_TCODE(packet->header[0]);
1559         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1560         payload = packet->payload;
1561         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1562
1563         if (tcode == TCODE_LOCK_REQUEST &&
1564             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1565                 lock_arg = be32_to_cpu(payload[0]);
1566                 lock_data = be32_to_cpu(payload[1]);
1567         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1568                 lock_arg = 0;
1569                 lock_data = 0;
1570         } else {
1571                 fw_fill_response(&response, packet->header,
1572                                  RCODE_TYPE_ERROR, NULL, 0);
1573                 goto out;
1574         }
1575
1576         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1577         reg_write(ohci, OHCI1394_CSRData, lock_data);
1578         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1579         reg_write(ohci, OHCI1394_CSRControl, sel);
1580
1581         for (try = 0; try < 20; try++)
1582                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1583                         lock_old = cpu_to_be32(reg_read(ohci,
1584                                                         OHCI1394_CSRData));
1585                         fw_fill_response(&response, packet->header,
1586                                          RCODE_COMPLETE,
1587                                          &lock_old, sizeof(lock_old));
1588                         goto out;
1589                 }
1590
1591         ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1592         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1593
1594  out:
1595         fw_core_handle_response(&ohci->card, &response);
1596 }
1597
1598 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1599 {
1600         u64 offset, csr;
1601
1602         if (ctx == &ctx->ohci->at_request_ctx) {
1603                 packet->ack = ACK_PENDING;
1604                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1605         }
1606
1607         offset =
1608                 ((unsigned long long)
1609                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1610                 packet->header[2];
1611         csr = offset - CSR_REGISTER_BASE;
1612
1613         /* Handle config rom reads. */
1614         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1615                 handle_local_rom(ctx->ohci, packet, csr);
1616         else switch (csr) {
1617         case CSR_BUS_MANAGER_ID:
1618         case CSR_BANDWIDTH_AVAILABLE:
1619         case CSR_CHANNELS_AVAILABLE_HI:
1620         case CSR_CHANNELS_AVAILABLE_LO:
1621                 handle_local_lock(ctx->ohci, packet, csr);
1622                 break;
1623         default:
1624                 if (ctx == &ctx->ohci->at_request_ctx)
1625                         fw_core_handle_request(&ctx->ohci->card, packet);
1626                 else
1627                         fw_core_handle_response(&ctx->ohci->card, packet);
1628                 break;
1629         }
1630
1631         if (ctx == &ctx->ohci->at_response_ctx) {
1632                 packet->ack = ACK_COMPLETE;
1633                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1634         }
1635 }
1636
1637 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1638 {
1639         unsigned long flags;
1640         int ret;
1641
1642         spin_lock_irqsave(&ctx->ohci->lock, flags);
1643
1644         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1645             ctx->ohci->generation == packet->generation) {
1646                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1647                 handle_local_request(ctx, packet);
1648                 return;
1649         }
1650
1651         ret = at_context_queue_packet(ctx, packet);
1652         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1653
1654         if (ret < 0)
1655                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1656
1657 }
1658
1659 static void detect_dead_context(struct fw_ohci *ohci,
1660                                 const char *name, unsigned int regs)
1661 {
1662         u32 ctl;
1663
1664         ctl = reg_read(ohci, CONTROL_SET(regs));
1665         if (ctl & CONTEXT_DEAD)
1666                 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1667                         name, evts[ctl & 0x1f]);
1668 }
1669
1670 static void handle_dead_contexts(struct fw_ohci *ohci)
1671 {
1672         unsigned int i;
1673         char name[8];
1674
1675         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1676         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1677         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1678         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1679         for (i = 0; i < 32; ++i) {
1680                 if (!(ohci->it_context_support & (1 << i)))
1681                         continue;
1682                 sprintf(name, "IT%u", i);
1683                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1684         }
1685         for (i = 0; i < 32; ++i) {
1686                 if (!(ohci->ir_context_support & (1 << i)))
1687                         continue;
1688                 sprintf(name, "IR%u", i);
1689                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1690         }
1691         /* TODO: maybe try to flush and restart the dead contexts */
1692 }
1693
1694 static u32 cycle_timer_ticks(u32 cycle_timer)
1695 {
1696         u32 ticks;
1697
1698         ticks = cycle_timer & 0xfff;
1699         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1700         ticks += (3072 * 8000) * (cycle_timer >> 25);
1701
1702         return ticks;
1703 }
1704
1705 /*
1706  * Some controllers exhibit one or more of the following bugs when updating the
1707  * iso cycle timer register:
1708  *  - When the lowest six bits are wrapping around to zero, a read that happens
1709  *    at the same time will return garbage in the lowest ten bits.
1710  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1711  *    not incremented for about 60 ns.
1712  *  - Occasionally, the entire register reads zero.
1713  *
1714  * To catch these, we read the register three times and ensure that the
1715  * difference between each two consecutive reads is approximately the same, i.e.
1716  * less than twice the other.  Furthermore, any negative difference indicates an
1717  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1718  * execute, so we have enough precision to compute the ratio of the differences.)
1719  */
1720 static u32 get_cycle_time(struct fw_ohci *ohci)
1721 {
1722         u32 c0, c1, c2;
1723         u32 t0, t1, t2;
1724         s32 diff01, diff12;
1725         int i;
1726
1727         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1728
1729         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1730                 i = 0;
1731                 c1 = c2;
1732                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1733                 do {
1734                         c0 = c1;
1735                         c1 = c2;
1736                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1737                         t0 = cycle_timer_ticks(c0);
1738                         t1 = cycle_timer_ticks(c1);
1739                         t2 = cycle_timer_ticks(c2);
1740                         diff01 = t1 - t0;
1741                         diff12 = t2 - t1;
1742                 } while ((diff01 <= 0 || diff12 <= 0 ||
1743                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1744                          && i++ < 20);
1745         }
1746
1747         return c2;
1748 }
1749
1750 /*
1751  * This function has to be called at least every 64 seconds.  The bus_time
1752  * field stores not only the upper 25 bits of the BUS_TIME register but also
1753  * the most significant bit of the cycle timer in bit 6 so that we can detect
1754  * changes in this bit.
1755  */
1756 static u32 update_bus_time(struct fw_ohci *ohci)
1757 {
1758         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1759
1760         if (unlikely(!ohci->bus_time_running)) {
1761                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1762                 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1763                                  (cycle_time_seconds & 0x40);
1764                 ohci->bus_time_running = true;
1765         }
1766
1767         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1768                 ohci->bus_time += 0x40;
1769
1770         return ohci->bus_time | cycle_time_seconds;
1771 }
1772
1773 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1774 {
1775         int reg;
1776
1777         mutex_lock(&ohci->phy_reg_mutex);
1778         reg = write_phy_reg(ohci, 7, port_index);
1779         if (reg >= 0)
1780                 reg = read_phy_reg(ohci, 8);
1781         mutex_unlock(&ohci->phy_reg_mutex);
1782         if (reg < 0)
1783                 return reg;
1784
1785         switch (reg & 0x0f) {
1786         case 0x06:
1787                 return 2;       /* is child node (connected to parent node) */
1788         case 0x0e:
1789                 return 3;       /* is parent node (connected to child node) */
1790         }
1791         return 1;               /* not connected */
1792 }
1793
1794 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1795         int self_id_count)
1796 {
1797         int i;
1798         u32 entry;
1799
1800         for (i = 0; i < self_id_count; i++) {
1801                 entry = ohci->self_id_buffer[i];
1802                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1803                         return -1;
1804                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1805                         return i;
1806         }
1807         return i;
1808 }
1809
1810 static int initiated_reset(struct fw_ohci *ohci)
1811 {
1812         int reg;
1813         int ret = 0;
1814
1815         mutex_lock(&ohci->phy_reg_mutex);
1816         reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1817         if (reg >= 0) {
1818                 reg = read_phy_reg(ohci, 8);
1819                 reg |= 0x40;
1820                 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1821                 if (reg >= 0) {
1822                         reg = read_phy_reg(ohci, 12); /* read register 12 */
1823                         if (reg >= 0) {
1824                                 if ((reg & 0x08) == 0x08) {
1825                                         /* bit 3 indicates "initiated reset" */
1826                                         ret = 0x2;
1827                                 }
1828                         }
1829                 }
1830         }
1831         mutex_unlock(&ohci->phy_reg_mutex);
1832         return ret;
1833 }
1834
1835 /*
1836  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1837  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1838  * Construct the selfID from phy register contents.
1839  */
1840 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1841 {
1842         int reg, i, pos, status;
1843         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1844         u32 self_id = 0x8040c800;
1845
1846         reg = reg_read(ohci, OHCI1394_NodeID);
1847         if (!(reg & OHCI1394_NodeID_idValid)) {
1848                 ohci_notice(ohci,
1849                             "node ID not valid, new bus reset in progress\n");
1850                 return -EBUSY;
1851         }
1852         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1853
1854         reg = ohci_read_phy_reg(&ohci->card, 4);
1855         if (reg < 0)
1856                 return reg;
1857         self_id |= ((reg & 0x07) << 8); /* power class */
1858
1859         reg = ohci_read_phy_reg(&ohci->card, 1);
1860         if (reg < 0)
1861                 return reg;
1862         self_id |= ((reg & 0x3f) << 16); /* gap count */
1863
1864         for (i = 0; i < 3; i++) {
1865                 status = get_status_for_port(ohci, i);
1866                 if (status < 0)
1867                         return status;
1868                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1869         }
1870
1871         self_id |= initiated_reset(ohci);
1872
1873         pos = get_self_id_pos(ohci, self_id, self_id_count);
1874         if (pos >= 0) {
1875                 memmove(&(ohci->self_id_buffer[pos+1]),
1876                         &(ohci->self_id_buffer[pos]),
1877                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1878                 ohci->self_id_buffer[pos] = self_id;
1879                 self_id_count++;
1880         }
1881         return self_id_count;
1882 }
1883
1884 static void bus_reset_work(struct work_struct *work)
1885 {
1886         struct fw_ohci *ohci =
1887                 container_of(work, struct fw_ohci, bus_reset_work);
1888         int self_id_count, generation, new_generation, i, j;
1889         u32 reg;
1890         void *free_rom = NULL;
1891         dma_addr_t free_rom_bus = 0;
1892         bool is_new_root;
1893
1894         reg = reg_read(ohci, OHCI1394_NodeID);
1895         if (!(reg & OHCI1394_NodeID_idValid)) {
1896                 ohci_notice(ohci,
1897                             "node ID not valid, new bus reset in progress\n");
1898                 return;
1899         }
1900         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1901                 ohci_notice(ohci, "malconfigured bus\n");
1902                 return;
1903         }
1904         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1905                                OHCI1394_NodeID_nodeNumber);
1906
1907         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1908         if (!(ohci->is_root && is_new_root))
1909                 reg_write(ohci, OHCI1394_LinkControlSet,
1910                           OHCI1394_LinkControl_cycleMaster);
1911         ohci->is_root = is_new_root;
1912
1913         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1914         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1915                 ohci_notice(ohci, "self ID receive error\n");
1916                 return;
1917         }
1918         /*
1919          * The count in the SelfIDCount register is the number of
1920          * bytes in the self ID receive buffer.  Since we also receive
1921          * the inverted quadlets and a header quadlet, we shift one
1922          * bit extra to get the actual number of self IDs.
1923          */
1924         self_id_count = (reg >> 3) & 0xff;
1925
1926         if (self_id_count > 252) {
1927                 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1928                 return;
1929         }
1930
1931         generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1932         rmb();
1933
1934         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1935                 u32 id  = cond_le32_to_cpu(ohci->self_id[i]);
1936                 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1937
1938                 if (id != ~id2) {
1939                         /*
1940                          * If the invalid data looks like a cycle start packet,
1941                          * it's likely to be the result of the cycle master
1942                          * having a wrong gap count.  In this case, the self IDs
1943                          * so far are valid and should be processed so that the
1944                          * bus manager can then correct the gap count.
1945                          */
1946                         if (id == 0xffff008f) {
1947                                 ohci_notice(ohci, "ignoring spurious self IDs\n");
1948                                 self_id_count = j;
1949                                 break;
1950                         }
1951
1952                         ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1953                                     j, self_id_count, id, id2);
1954                         return;
1955                 }
1956                 ohci->self_id_buffer[j] = id;
1957         }
1958
1959         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1960                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1961                 if (self_id_count < 0) {
1962                         ohci_notice(ohci,
1963                                     "could not construct local self ID\n");
1964                         return;
1965                 }
1966         }
1967
1968         if (self_id_count == 0) {
1969                 ohci_notice(ohci, "no self IDs\n");
1970                 return;
1971         }
1972         rmb();
1973
1974         /*
1975          * Check the consistency of the self IDs we just read.  The
1976          * problem we face is that a new bus reset can start while we
1977          * read out the self IDs from the DMA buffer. If this happens,
1978          * the DMA buffer will be overwritten with new self IDs and we
1979          * will read out inconsistent data.  The OHCI specification
1980          * (section 11.2) recommends a technique similar to
1981          * linux/seqlock.h, where we remember the generation of the
1982          * self IDs in the buffer before reading them out and compare
1983          * it to the current generation after reading them out.  If
1984          * the two generations match we know we have a consistent set
1985          * of self IDs.
1986          */
1987
1988         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1989         if (new_generation != generation) {
1990                 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1991                 return;
1992         }
1993
1994         /* FIXME: Document how the locking works. */
1995         spin_lock_irq(&ohci->lock);
1996
1997         ohci->generation = -1; /* prevent AT packet queueing */
1998         context_stop(&ohci->at_request_ctx);
1999         context_stop(&ohci->at_response_ctx);
2000
2001         spin_unlock_irq(&ohci->lock);
2002
2003         /*
2004          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2005          * packets in the AT queues and software needs to drain them.
2006          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2007          */
2008         at_context_flush(&ohci->at_request_ctx);
2009         at_context_flush(&ohci->at_response_ctx);
2010
2011         spin_lock_irq(&ohci->lock);
2012
2013         ohci->generation = generation;
2014         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2015
2016         if (ohci->quirks & QUIRK_RESET_PACKET)
2017                 ohci->request_generation = generation;
2018
2019         /*
2020          * This next bit is unrelated to the AT context stuff but we
2021          * have to do it under the spinlock also.  If a new config rom
2022          * was set up before this reset, the old one is now no longer
2023          * in use and we can free it. Update the config rom pointers
2024          * to point to the current config rom and clear the
2025          * next_config_rom pointer so a new update can take place.
2026          */
2027
2028         if (ohci->next_config_rom != NULL) {
2029                 if (ohci->next_config_rom != ohci->config_rom) {
2030                         free_rom      = ohci->config_rom;
2031                         free_rom_bus  = ohci->config_rom_bus;
2032                 }
2033                 ohci->config_rom      = ohci->next_config_rom;
2034                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
2035                 ohci->next_config_rom = NULL;
2036
2037                 /*
2038                  * Restore config_rom image and manually update
2039                  * config_rom registers.  Writing the header quadlet
2040                  * will indicate that the config rom is ready, so we
2041                  * do that last.
2042                  */
2043                 reg_write(ohci, OHCI1394_BusOptions,
2044                           be32_to_cpu(ohci->config_rom[2]));
2045                 ohci->config_rom[0] = ohci->next_header;
2046                 reg_write(ohci, OHCI1394_ConfigROMhdr,
2047                           be32_to_cpu(ohci->next_header));
2048         }
2049
2050         if (param_remote_dma) {
2051                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2052                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2053         }
2054
2055         spin_unlock_irq(&ohci->lock);
2056
2057         if (free_rom)
2058                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2059                                   free_rom, free_rom_bus);
2060
2061         log_selfids(ohci, generation, self_id_count);
2062
2063         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2064                                  self_id_count, ohci->self_id_buffer,
2065                                  ohci->csr_state_setclear_abdicate);
2066         ohci->csr_state_setclear_abdicate = false;
2067 }
2068
2069 static irqreturn_t irq_handler(int irq, void *data)
2070 {
2071         struct fw_ohci *ohci = data;
2072         u32 event, iso_event;
2073         int i;
2074
2075         event = reg_read(ohci, OHCI1394_IntEventClear);
2076
2077         if (!event || !~event)
2078                 return IRQ_NONE;
2079
2080         /*
2081          * busReset and postedWriteErr must not be cleared yet
2082          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2083          */
2084         reg_write(ohci, OHCI1394_IntEventClear,
2085                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2086         log_irqs(ohci, event);
2087
2088         if (event & OHCI1394_selfIDComplete)
2089                 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2090
2091         if (event & OHCI1394_RQPkt)
2092                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2093
2094         if (event & OHCI1394_RSPkt)
2095                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2096
2097         if (event & OHCI1394_reqTxComplete)
2098                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2099
2100         if (event & OHCI1394_respTxComplete)
2101                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2102
2103         if (event & OHCI1394_isochRx) {
2104                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2105                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2106
2107                 while (iso_event) {
2108                         i = ffs(iso_event) - 1;
2109                         tasklet_schedule(
2110                                 &ohci->ir_context_list[i].context.tasklet);
2111                         iso_event &= ~(1 << i);
2112                 }
2113         }
2114
2115         if (event & OHCI1394_isochTx) {
2116                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2117                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2118
2119                 while (iso_event) {
2120                         i = ffs(iso_event) - 1;
2121                         tasklet_schedule(
2122                                 &ohci->it_context_list[i].context.tasklet);
2123                         iso_event &= ~(1 << i);
2124                 }
2125         }
2126
2127         if (unlikely(event & OHCI1394_regAccessFail))
2128                 ohci_err(ohci, "register access failure\n");
2129
2130         if (unlikely(event & OHCI1394_postedWriteErr)) {
2131                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2132                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2133                 reg_write(ohci, OHCI1394_IntEventClear,
2134                           OHCI1394_postedWriteErr);
2135                 if (printk_ratelimit())
2136                         ohci_err(ohci, "PCI posted write error\n");
2137         }
2138
2139         if (unlikely(event & OHCI1394_cycleTooLong)) {
2140                 if (printk_ratelimit())
2141                         ohci_notice(ohci, "isochronous cycle too long\n");
2142                 reg_write(ohci, OHCI1394_LinkControlSet,
2143                           OHCI1394_LinkControl_cycleMaster);
2144         }
2145
2146         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2147                 /*
2148                  * We need to clear this event bit in order to make
2149                  * cycleMatch isochronous I/O work.  In theory we should
2150                  * stop active cycleMatch iso contexts now and restart
2151                  * them at least two cycles later.  (FIXME?)
2152                  */
2153                 if (printk_ratelimit())
2154                         ohci_notice(ohci, "isochronous cycle inconsistent\n");
2155         }
2156
2157         if (unlikely(event & OHCI1394_unrecoverableError))
2158                 handle_dead_contexts(ohci);
2159
2160         if (event & OHCI1394_cycle64Seconds) {
2161                 spin_lock(&ohci->lock);
2162                 update_bus_time(ohci);
2163                 spin_unlock(&ohci->lock);
2164         } else
2165                 flush_writes(ohci);
2166
2167         return IRQ_HANDLED;
2168 }
2169
2170 static int software_reset(struct fw_ohci *ohci)
2171 {
2172         u32 val;
2173         int i;
2174
2175         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2176         for (i = 0; i < 500; i++) {
2177                 val = reg_read(ohci, OHCI1394_HCControlSet);
2178                 if (!~val)
2179                         return -ENODEV; /* Card was ejected. */
2180
2181                 if (!(val & OHCI1394_HCControl_softReset))
2182                         return 0;
2183
2184                 msleep(1);
2185         }
2186
2187         return -EBUSY;
2188 }
2189
2190 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2191 {
2192         size_t size = length * 4;
2193
2194         memcpy(dest, src, size);
2195         if (size < CONFIG_ROM_SIZE)
2196                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2197 }
2198
2199 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2200 {
2201         bool enable_1394a;
2202         int ret, clear, set, offset;
2203
2204         /* Check if the driver should configure link and PHY. */
2205         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2206               OHCI1394_HCControl_programPhyEnable))
2207                 return 0;
2208
2209         /* Paranoia: check whether the PHY supports 1394a, too. */
2210         enable_1394a = false;
2211         ret = read_phy_reg(ohci, 2);
2212         if (ret < 0)
2213                 return ret;
2214         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2215                 ret = read_paged_phy_reg(ohci, 1, 8);
2216                 if (ret < 0)
2217                         return ret;
2218                 if (ret >= 1)
2219                         enable_1394a = true;
2220         }
2221
2222         if (ohci->quirks & QUIRK_NO_1394A)
2223                 enable_1394a = false;
2224
2225         /* Configure PHY and link consistently. */
2226         if (enable_1394a) {
2227                 clear = 0;
2228                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2229         } else {
2230                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2231                 set = 0;
2232         }
2233         ret = update_phy_reg(ohci, 5, clear, set);
2234         if (ret < 0)
2235                 return ret;
2236
2237         if (enable_1394a)
2238                 offset = OHCI1394_HCControlSet;
2239         else
2240                 offset = OHCI1394_HCControlClear;
2241         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2242
2243         /* Clean up: configuration has been taken care of. */
2244         reg_write(ohci, OHCI1394_HCControlClear,
2245                   OHCI1394_HCControl_programPhyEnable);
2246
2247         return 0;
2248 }
2249
2250 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2251 {
2252         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2253         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2254         int reg, i;
2255
2256         reg = read_phy_reg(ohci, 2);
2257         if (reg < 0)
2258                 return reg;
2259         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2260                 return 0;
2261
2262         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2263                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2264                 if (reg < 0)
2265                         return reg;
2266                 if (reg != id[i])
2267                         return 0;
2268         }
2269         return 1;
2270 }
2271
2272 static int ohci_enable(struct fw_card *card,
2273                        const __be32 *config_rom, size_t length)
2274 {
2275         struct fw_ohci *ohci = fw_ohci(card);
2276         u32 lps, version, irqs;
2277         int i, ret;
2278
2279         ret = software_reset(ohci);
2280         if (ret < 0) {
2281                 ohci_err(ohci, "failed to reset ohci card\n");
2282                 return ret;
2283         }
2284
2285         /*
2286          * Now enable LPS, which we need in order to start accessing
2287          * most of the registers.  In fact, on some cards (ALI M5251),
2288          * accessing registers in the SClk domain without LPS enabled
2289          * will lock up the machine.  Wait 50msec to make sure we have
2290          * full link enabled.  However, with some cards (well, at least
2291          * a JMicron PCIe card), we have to try again sometimes.
2292          *
2293          * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2294          * cannot actually use the phy at that time.  These need tens of
2295          * millisecods pause between LPS write and first phy access too.
2296          */
2297
2298         reg_write(ohci, OHCI1394_HCControlSet,
2299                   OHCI1394_HCControl_LPS |
2300                   OHCI1394_HCControl_postedWriteEnable);
2301         flush_writes(ohci);
2302
2303         for (lps = 0, i = 0; !lps && i < 3; i++) {
2304                 msleep(50);
2305                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2306                       OHCI1394_HCControl_LPS;
2307         }
2308
2309         if (!lps) {
2310                 ohci_err(ohci, "failed to set Link Power Status\n");
2311                 return -EIO;
2312         }
2313
2314         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2315                 ret = probe_tsb41ba3d(ohci);
2316                 if (ret < 0)
2317                         return ret;
2318                 if (ret)
2319                         ohci_notice(ohci, "local TSB41BA3D phy\n");
2320                 else
2321                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2322         }
2323
2324         reg_write(ohci, OHCI1394_HCControlClear,
2325                   OHCI1394_HCControl_noByteSwapData);
2326
2327         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2328         reg_write(ohci, OHCI1394_LinkControlSet,
2329                   OHCI1394_LinkControl_cycleTimerEnable |
2330                   OHCI1394_LinkControl_cycleMaster);
2331
2332         reg_write(ohci, OHCI1394_ATRetries,
2333                   OHCI1394_MAX_AT_REQ_RETRIES |
2334                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2335                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2336                   (200 << 16));
2337
2338         ohci->bus_time_running = false;
2339
2340         for (i = 0; i < 32; i++)
2341                 if (ohci->ir_context_support & (1 << i))
2342                         reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2343                                   IR_CONTEXT_MULTI_CHANNEL_MODE);
2344
2345         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2346         if (version >= OHCI_VERSION_1_1) {
2347                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2348                           0xfffffffe);
2349                 card->broadcast_channel_auto_allocated = true;
2350         }
2351
2352         /* Get implemented bits of the priority arbitration request counter. */
2353         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2354         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2355         reg_write(ohci, OHCI1394_FairnessControl, 0);
2356         card->priority_budget_implemented = ohci->pri_req_max != 0;
2357
2358         reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2359         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2360         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2361
2362         ret = configure_1394a_enhancements(ohci);
2363         if (ret < 0)
2364                 return ret;
2365
2366         /* Activate link_on bit and contender bit in our self ID packets.*/
2367         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2368         if (ret < 0)
2369                 return ret;
2370
2371         /*
2372          * When the link is not yet enabled, the atomic config rom
2373          * update mechanism described below in ohci_set_config_rom()
2374          * is not active.  We have to update ConfigRomHeader and
2375          * BusOptions manually, and the write to ConfigROMmap takes
2376          * effect immediately.  We tie this to the enabling of the
2377          * link, so we have a valid config rom before enabling - the
2378          * OHCI requires that ConfigROMhdr and BusOptions have valid
2379          * values before enabling.
2380          *
2381          * However, when the ConfigROMmap is written, some controllers
2382          * always read back quadlets 0 and 2 from the config rom to
2383          * the ConfigRomHeader and BusOptions registers on bus reset.
2384          * They shouldn't do that in this initial case where the link
2385          * isn't enabled.  This means we have to use the same
2386          * workaround here, setting the bus header to 0 and then write
2387          * the right values in the bus reset tasklet.
2388          */
2389
2390         if (config_rom) {
2391                 ohci->next_config_rom =
2392                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2393                                            &ohci->next_config_rom_bus,
2394                                            GFP_KERNEL);
2395                 if (ohci->next_config_rom == NULL)
2396                         return -ENOMEM;
2397
2398                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2399         } else {
2400                 /*
2401                  * In the suspend case, config_rom is NULL, which
2402                  * means that we just reuse the old config rom.
2403                  */
2404                 ohci->next_config_rom = ohci->config_rom;
2405                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2406         }
2407
2408         ohci->next_header = ohci->next_config_rom[0];
2409         ohci->next_config_rom[0] = 0;
2410         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2411         reg_write(ohci, OHCI1394_BusOptions,
2412                   be32_to_cpu(ohci->next_config_rom[2]));
2413         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2414
2415         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2416
2417         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2418                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2419                 OHCI1394_isochTx | OHCI1394_isochRx |
2420                 OHCI1394_postedWriteErr |
2421                 OHCI1394_selfIDComplete |
2422                 OHCI1394_regAccessFail |
2423                 OHCI1394_cycleInconsistent |
2424                 OHCI1394_unrecoverableError |
2425                 OHCI1394_cycleTooLong |
2426                 OHCI1394_masterIntEnable;
2427         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2428                 irqs |= OHCI1394_busReset;
2429         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2430
2431         reg_write(ohci, OHCI1394_HCControlSet,
2432                   OHCI1394_HCControl_linkEnable |
2433                   OHCI1394_HCControl_BIBimageValid);
2434
2435         reg_write(ohci, OHCI1394_LinkControlSet,
2436                   OHCI1394_LinkControl_rcvSelfID |
2437                   OHCI1394_LinkControl_rcvPhyPkt);
2438
2439         ar_context_run(&ohci->ar_request_ctx);
2440         ar_context_run(&ohci->ar_response_ctx);
2441
2442         flush_writes(ohci);
2443
2444         /* We are ready to go, reset bus to finish initialization. */
2445         fw_schedule_bus_reset(&ohci->card, false, true);
2446
2447         return 0;
2448 }
2449
2450 static int ohci_set_config_rom(struct fw_card *card,
2451                                const __be32 *config_rom, size_t length)
2452 {
2453         struct fw_ohci *ohci;
2454         __be32 *next_config_rom;
2455         dma_addr_t uninitialized_var(next_config_rom_bus);
2456
2457         ohci = fw_ohci(card);
2458
2459         /*
2460          * When the OHCI controller is enabled, the config rom update
2461          * mechanism is a bit tricky, but easy enough to use.  See
2462          * section 5.5.6 in the OHCI specification.
2463          *
2464          * The OHCI controller caches the new config rom address in a
2465          * shadow register (ConfigROMmapNext) and needs a bus reset
2466          * for the changes to take place.  When the bus reset is
2467          * detected, the controller loads the new values for the
2468          * ConfigRomHeader and BusOptions registers from the specified
2469          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2470          * shadow register. All automatically and atomically.
2471          *
2472          * Now, there's a twist to this story.  The automatic load of
2473          * ConfigRomHeader and BusOptions doesn't honor the
2474          * noByteSwapData bit, so with a be32 config rom, the
2475          * controller will load be32 values in to these registers
2476          * during the atomic update, even on litte endian
2477          * architectures.  The workaround we use is to put a 0 in the
2478          * header quadlet; 0 is endian agnostic and means that the
2479          * config rom isn't ready yet.  In the bus reset tasklet we
2480          * then set up the real values for the two registers.
2481          *
2482          * We use ohci->lock to avoid racing with the code that sets
2483          * ohci->next_config_rom to NULL (see bus_reset_work).
2484          */
2485
2486         next_config_rom =
2487                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2488                                    &next_config_rom_bus, GFP_KERNEL);
2489         if (next_config_rom == NULL)
2490                 return -ENOMEM;
2491
2492         spin_lock_irq(&ohci->lock);
2493
2494         /*
2495          * If there is not an already pending config_rom update,
2496          * push our new allocation into the ohci->next_config_rom
2497          * and then mark the local variable as null so that we
2498          * won't deallocate the new buffer.
2499          *
2500          * OTOH, if there is a pending config_rom update, just
2501          * use that buffer with the new config_rom data, and
2502          * let this routine free the unused DMA allocation.
2503          */
2504
2505         if (ohci->next_config_rom == NULL) {
2506                 ohci->next_config_rom = next_config_rom;
2507                 ohci->next_config_rom_bus = next_config_rom_bus;
2508                 next_config_rom = NULL;
2509         }
2510
2511         copy_config_rom(ohci->next_config_rom, config_rom, length);
2512
2513         ohci->next_header = config_rom[0];
2514         ohci->next_config_rom[0] = 0;
2515
2516         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2517
2518         spin_unlock_irq(&ohci->lock);
2519
2520         /* If we didn't use the DMA allocation, delete it. */
2521         if (next_config_rom != NULL)
2522                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2523                                   next_config_rom, next_config_rom_bus);
2524
2525         /*
2526          * Now initiate a bus reset to have the changes take
2527          * effect. We clean up the old config rom memory and DMA
2528          * mappings in the bus reset tasklet, since the OHCI
2529          * controller could need to access it before the bus reset
2530          * takes effect.
2531          */
2532
2533         fw_schedule_bus_reset(&ohci->card, true, true);
2534
2535         return 0;
2536 }
2537
2538 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2539 {
2540         struct fw_ohci *ohci = fw_ohci(card);
2541
2542         at_context_transmit(&ohci->at_request_ctx, packet);
2543 }
2544
2545 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2546 {
2547         struct fw_ohci *ohci = fw_ohci(card);
2548
2549         at_context_transmit(&ohci->at_response_ctx, packet);
2550 }
2551
2552 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2553 {
2554         struct fw_ohci *ohci = fw_ohci(card);
2555         struct context *ctx = &ohci->at_request_ctx;
2556         struct driver_data *driver_data = packet->driver_data;
2557         int ret = -ENOENT;
2558
2559         tasklet_disable(&ctx->tasklet);
2560
2561         if (packet->ack != 0)
2562                 goto out;
2563
2564         if (packet->payload_mapped)
2565                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2566                                  packet->payload_length, DMA_TO_DEVICE);
2567
2568         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2569         driver_data->packet = NULL;
2570         packet->ack = RCODE_CANCELLED;
2571         packet->callback(packet, &ohci->card, packet->ack);
2572         ret = 0;
2573  out:
2574         tasklet_enable(&ctx->tasklet);
2575
2576         return ret;
2577 }
2578
2579 static int ohci_enable_phys_dma(struct fw_card *card,
2580                                 int node_id, int generation)
2581 {
2582         struct fw_ohci *ohci = fw_ohci(card);
2583         unsigned long flags;
2584         int n, ret = 0;
2585
2586         if (param_remote_dma)
2587                 return 0;
2588
2589         /*
2590          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2591          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2592          */
2593
2594         spin_lock_irqsave(&ohci->lock, flags);
2595
2596         if (ohci->generation != generation) {
2597                 ret = -ESTALE;
2598                 goto out;
2599         }
2600
2601         /*
2602          * Note, if the node ID contains a non-local bus ID, physical DMA is
2603          * enabled for _all_ nodes on remote buses.
2604          */
2605
2606         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2607         if (n < 32)
2608                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2609         else
2610                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2611
2612         flush_writes(ohci);
2613  out:
2614         spin_unlock_irqrestore(&ohci->lock, flags);
2615
2616         return ret;
2617 }
2618
2619 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2620 {
2621         struct fw_ohci *ohci = fw_ohci(card);
2622         unsigned long flags;
2623         u32 value;
2624
2625         switch (csr_offset) {
2626         case CSR_STATE_CLEAR:
2627         case CSR_STATE_SET:
2628                 if (ohci->is_root &&
2629                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2630                      OHCI1394_LinkControl_cycleMaster))
2631                         value = CSR_STATE_BIT_CMSTR;
2632                 else
2633                         value = 0;
2634                 if (ohci->csr_state_setclear_abdicate)
2635                         value |= CSR_STATE_BIT_ABDICATE;
2636
2637                 return value;
2638
2639         case CSR_NODE_IDS:
2640                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2641
2642         case CSR_CYCLE_TIME:
2643                 return get_cycle_time(ohci);
2644
2645         case CSR_BUS_TIME:
2646                 /*
2647                  * We might be called just after the cycle timer has wrapped
2648                  * around but just before the cycle64Seconds handler, so we
2649                  * better check here, too, if the bus time needs to be updated.
2650                  */
2651                 spin_lock_irqsave(&ohci->lock, flags);
2652                 value = update_bus_time(ohci);
2653                 spin_unlock_irqrestore(&ohci->lock, flags);
2654                 return value;
2655
2656         case CSR_BUSY_TIMEOUT:
2657                 value = reg_read(ohci, OHCI1394_ATRetries);
2658                 return (value >> 4) & 0x0ffff00f;
2659
2660         case CSR_PRIORITY_BUDGET:
2661                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2662                         (ohci->pri_req_max << 8);
2663
2664         default:
2665                 WARN_ON(1);
2666                 return 0;
2667         }
2668 }
2669
2670 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2671 {
2672         struct fw_ohci *ohci = fw_ohci(card);
2673         unsigned long flags;
2674
2675         switch (csr_offset) {
2676         case CSR_STATE_CLEAR:
2677                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2678                         reg_write(ohci, OHCI1394_LinkControlClear,
2679                                   OHCI1394_LinkControl_cycleMaster);
2680                         flush_writes(ohci);
2681                 }
2682                 if (value & CSR_STATE_BIT_ABDICATE)
2683                         ohci->csr_state_setclear_abdicate = false;
2684                 break;
2685
2686         case CSR_STATE_SET:
2687                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2688                         reg_write(ohci, OHCI1394_LinkControlSet,
2689                                   OHCI1394_LinkControl_cycleMaster);
2690                         flush_writes(ohci);
2691                 }
2692                 if (value & CSR_STATE_BIT_ABDICATE)
2693                         ohci->csr_state_setclear_abdicate = true;
2694                 break;
2695
2696         case CSR_NODE_IDS:
2697                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2698                 flush_writes(ohci);
2699                 break;
2700
2701         case CSR_CYCLE_TIME:
2702                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2703                 reg_write(ohci, OHCI1394_IntEventSet,
2704                           OHCI1394_cycleInconsistent);
2705                 flush_writes(ohci);
2706                 break;
2707
2708         case CSR_BUS_TIME:
2709                 spin_lock_irqsave(&ohci->lock, flags);
2710                 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2711                                  (value & ~0x7f);
2712                 spin_unlock_irqrestore(&ohci->lock, flags);
2713                 break;
2714
2715         case CSR_BUSY_TIMEOUT:
2716                 value = (value & 0xf) | ((value & 0xf) << 4) |
2717                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2718                 reg_write(ohci, OHCI1394_ATRetries, value);
2719                 flush_writes(ohci);
2720                 break;
2721
2722         case CSR_PRIORITY_BUDGET:
2723                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2724                 flush_writes(ohci);
2725                 break;
2726
2727         default:
2728                 WARN_ON(1);
2729                 break;
2730         }
2731 }
2732
2733 static void flush_iso_completions(struct iso_context *ctx)
2734 {
2735         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2736                               ctx->header_length, ctx->header,
2737                               ctx->base.callback_data);
2738         ctx->header_length = 0;
2739 }
2740
2741 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2742 {
2743         u32 *ctx_hdr;
2744
2745         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2746                 if (ctx->base.drop_overflow_headers)
2747                         return;
2748                 flush_iso_completions(ctx);
2749         }
2750
2751         ctx_hdr = ctx->header + ctx->header_length;
2752         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2753
2754         /*
2755          * The two iso header quadlets are byteswapped to little
2756          * endian by the controller, but we want to present them
2757          * as big endian for consistency with the bus endianness.
2758          */
2759         if (ctx->base.header_size > 0)
2760                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2761         if (ctx->base.header_size > 4)
2762                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2763         if (ctx->base.header_size > 8)
2764                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2765         ctx->header_length += ctx->base.header_size;
2766 }
2767
2768 static int handle_ir_packet_per_buffer(struct context *context,
2769                                        struct descriptor *d,
2770                                        struct descriptor *last)
2771 {
2772         struct iso_context *ctx =
2773                 container_of(context, struct iso_context, context);
2774         struct descriptor *pd;
2775         u32 buffer_dma;
2776
2777         for (pd = d; pd <= last; pd++)
2778                 if (pd->transfer_status)
2779                         break;
2780         if (pd > last)
2781                 /* Descriptor(s) not done yet, stop iteration */
2782                 return 0;
2783
2784         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2785                 d++;
2786                 buffer_dma = le32_to_cpu(d->data_address);
2787                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2788                                               buffer_dma & PAGE_MASK,
2789                                               buffer_dma & ~PAGE_MASK,
2790                                               le16_to_cpu(d->req_count),
2791                                               DMA_FROM_DEVICE);
2792         }
2793
2794         copy_iso_headers(ctx, (u32 *) (last + 1));
2795
2796         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2797                 flush_iso_completions(ctx);
2798
2799         return 1;
2800 }
2801
2802 /* d == last because each descriptor block is only a single descriptor. */
2803 static int handle_ir_buffer_fill(struct context *context,
2804                                  struct descriptor *d,
2805                                  struct descriptor *last)
2806 {
2807         struct iso_context *ctx =
2808                 container_of(context, struct iso_context, context);
2809         unsigned int req_count, res_count, completed;
2810         u32 buffer_dma;
2811
2812         req_count = le16_to_cpu(last->req_count);
2813         res_count = le16_to_cpu(READ_ONCE(last->res_count));
2814         completed = req_count - res_count;
2815         buffer_dma = le32_to_cpu(last->data_address);
2816
2817         if (completed > 0) {
2818                 ctx->mc_buffer_bus = buffer_dma;
2819                 ctx->mc_completed = completed;
2820         }
2821
2822         if (res_count != 0)
2823                 /* Descriptor(s) not done yet, stop iteration */
2824                 return 0;
2825
2826         dma_sync_single_range_for_cpu(context->ohci->card.device,
2827                                       buffer_dma & PAGE_MASK,
2828                                       buffer_dma & ~PAGE_MASK,
2829                                       completed, DMA_FROM_DEVICE);
2830
2831         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2832                 ctx->base.callback.mc(&ctx->base,
2833                                       buffer_dma + completed,
2834                                       ctx->base.callback_data);
2835                 ctx->mc_completed = 0;
2836         }
2837
2838         return 1;
2839 }
2840
2841 static void flush_ir_buffer_fill(struct iso_context *ctx)
2842 {
2843         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2844                                       ctx->mc_buffer_bus & PAGE_MASK,
2845                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2846                                       ctx->mc_completed, DMA_FROM_DEVICE);
2847
2848         ctx->base.callback.mc(&ctx->base,
2849                               ctx->mc_buffer_bus + ctx->mc_completed,
2850                               ctx->base.callback_data);
2851         ctx->mc_completed = 0;
2852 }
2853
2854 static inline void sync_it_packet_for_cpu(struct context *context,
2855                                           struct descriptor *pd)
2856 {
2857         __le16 control;
2858         u32 buffer_dma;
2859
2860         /* only packets beginning with OUTPUT_MORE* have data buffers */
2861         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2862                 return;
2863
2864         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2865         pd += 2;
2866
2867         /*
2868          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2869          * data buffer is in the context program's coherent page and must not
2870          * be synced.
2871          */
2872         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2873             (context->current_bus          & PAGE_MASK)) {
2874                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2875                         return;
2876                 pd++;
2877         }
2878
2879         do {
2880                 buffer_dma = le32_to_cpu(pd->data_address);
2881                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2882                                               buffer_dma & PAGE_MASK,
2883                                               buffer_dma & ~PAGE_MASK,
2884                                               le16_to_cpu(pd->req_count),
2885                                               DMA_TO_DEVICE);
2886                 control = pd->control;
2887                 pd++;
2888         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2889 }
2890
2891 static int handle_it_packet(struct context *context,
2892                             struct descriptor *d,
2893                             struct descriptor *last)
2894 {
2895         struct iso_context *ctx =
2896                 container_of(context, struct iso_context, context);
2897         struct descriptor *pd;
2898         __be32 *ctx_hdr;
2899
2900         for (pd = d; pd <= last; pd++)
2901                 if (pd->transfer_status)
2902                         break;
2903         if (pd > last)
2904                 /* Descriptor(s) not done yet, stop iteration */
2905                 return 0;
2906
2907         sync_it_packet_for_cpu(context, d);
2908
2909         if (ctx->header_length + 4 > PAGE_SIZE) {
2910                 if (ctx->base.drop_overflow_headers)
2911                         return 1;
2912                 flush_iso_completions(ctx);
2913         }
2914
2915         ctx_hdr = ctx->header + ctx->header_length;
2916         ctx->last_timestamp = le16_to_cpu(last->res_count);
2917         /* Present this value as big-endian to match the receive code */
2918         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2919                                le16_to_cpu(pd->res_count));
2920         ctx->header_length += 4;
2921
2922         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2923                 flush_iso_completions(ctx);
2924
2925         return 1;
2926 }
2927
2928 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2929 {
2930         u32 hi = channels >> 32, lo = channels;
2931
2932         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2933         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2934         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2935         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2936         mmiowb();
2937         ohci->mc_channels = channels;
2938 }
2939
2940 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2941                                 int type, int channel, size_t header_size)
2942 {
2943         struct fw_ohci *ohci = fw_ohci(card);
2944         struct iso_context *uninitialized_var(ctx);
2945         descriptor_callback_t uninitialized_var(callback);
2946         u64 *uninitialized_var(channels);
2947         u32 *uninitialized_var(mask), uninitialized_var(regs);
2948         int index, ret = -EBUSY;
2949
2950         spin_lock_irq(&ohci->lock);
2951
2952         switch (type) {
2953         case FW_ISO_CONTEXT_TRANSMIT:
2954                 mask     = &ohci->it_context_mask;
2955                 callback = handle_it_packet;
2956                 index    = ffs(*mask) - 1;
2957                 if (index >= 0) {
2958                         *mask &= ~(1 << index);
2959                         regs = OHCI1394_IsoXmitContextBase(index);
2960                         ctx  = &ohci->it_context_list[index];
2961                 }
2962                 break;
2963
2964         case FW_ISO_CONTEXT_RECEIVE:
2965                 channels = &ohci->ir_context_channels;
2966                 mask     = &ohci->ir_context_mask;
2967                 callback = handle_ir_packet_per_buffer;
2968                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2969                 if (index >= 0) {
2970                         *channels &= ~(1ULL << channel);
2971                         *mask     &= ~(1 << index);
2972                         regs = OHCI1394_IsoRcvContextBase(index);
2973                         ctx  = &ohci->ir_context_list[index];
2974                 }
2975                 break;
2976
2977         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2978                 mask     = &ohci->ir_context_mask;
2979                 callback = handle_ir_buffer_fill;
2980                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2981                 if (index >= 0) {
2982                         ohci->mc_allocated = true;
2983                         *mask &= ~(1 << index);
2984                         regs = OHCI1394_IsoRcvContextBase(index);
2985                         ctx  = &ohci->ir_context_list[index];
2986                 }
2987                 break;
2988
2989         default:
2990                 index = -1;
2991                 ret = -ENOSYS;
2992         }
2993
2994         spin_unlock_irq(&ohci->lock);
2995
2996         if (index < 0)
2997                 return ERR_PTR(ret);
2998
2999         memset(ctx, 0, sizeof(*ctx));
3000         ctx->header_length = 0;
3001         ctx->header = (void *) __get_free_page(GFP_KERNEL);
3002         if (ctx->header == NULL) {
3003                 ret = -ENOMEM;
3004                 goto out;
3005         }
3006         ret = context_init(&ctx->context, ohci, regs, callback);
3007         if (ret < 0)
3008                 goto out_with_header;
3009
3010         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3011                 set_multichannel_mask(ohci, 0);
3012                 ctx->mc_completed = 0;
3013         }
3014
3015         return &ctx->base;
3016
3017  out_with_header:
3018         free_page((unsigned long)ctx->header);
3019  out:
3020         spin_lock_irq(&ohci->lock);
3021
3022         switch (type) {
3023         case FW_ISO_CONTEXT_RECEIVE:
3024                 *channels |= 1ULL << channel;
3025                 break;
3026
3027         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3028                 ohci->mc_allocated = false;
3029                 break;
3030         }
3031         *mask |= 1 << index;
3032
3033         spin_unlock_irq(&ohci->lock);
3034
3035         return ERR_PTR(ret);
3036 }
3037
3038 static int ohci_start_iso(struct fw_iso_context *base,
3039                           s32 cycle, u32 sync, u32 tags)
3040 {
3041         struct iso_context *ctx = container_of(base, struct iso_context, base);
3042         struct fw_ohci *ohci = ctx->context.ohci;
3043         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3044         int index;
3045
3046         /* the controller cannot start without any queued packets */
3047         if (ctx->context.last->branch_address == 0)
3048                 return -ENODATA;
3049
3050         switch (ctx->base.type) {
3051         case FW_ISO_CONTEXT_TRANSMIT:
3052                 index = ctx - ohci->it_context_list;
3053                 match = 0;
3054                 if (cycle >= 0)
3055                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3056                                 (cycle & 0x7fff) << 16;
3057
3058                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3059                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3060                 context_run(&ctx->context, match);
3061                 break;
3062
3063         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3064                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3065                 /* fall through */
3066         case FW_ISO_CONTEXT_RECEIVE:
3067                 index = ctx - ohci->ir_context_list;
3068                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3069                 if (cycle >= 0) {
3070                         match |= (cycle & 0x07fff) << 12;
3071                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3072                 }
3073
3074                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3075                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3076                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3077                 context_run(&ctx->context, control);
3078
3079                 ctx->sync = sync;
3080                 ctx->tags = tags;
3081
3082                 break;
3083         }
3084
3085         return 0;
3086 }
3087
3088 static int ohci_stop_iso(struct fw_iso_context *base)
3089 {
3090         struct fw_ohci *ohci = fw_ohci(base->card);
3091         struct iso_context *ctx = container_of(base, struct iso_context, base);
3092         int index;
3093
3094         switch (ctx->base.type) {
3095         case FW_ISO_CONTEXT_TRANSMIT:
3096                 index = ctx - ohci->it_context_list;
3097                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3098                 break;
3099
3100         case FW_ISO_CONTEXT_RECEIVE:
3101         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3102                 index = ctx - ohci->ir_context_list;
3103                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3104                 break;
3105         }
3106         flush_writes(ohci);
3107         context_stop(&ctx->context);
3108         tasklet_kill(&ctx->context.tasklet);
3109
3110         return 0;
3111 }
3112
3113 static void ohci_free_iso_context(struct fw_iso_context *base)
3114 {
3115         struct fw_ohci *ohci = fw_ohci(base->card);
3116         struct iso_context *ctx = container_of(base, struct iso_context, base);
3117         unsigned long flags;
3118         int index;
3119
3120         ohci_stop_iso(base);
3121         context_release(&ctx->context);
3122         free_page((unsigned long)ctx->header);
3123
3124         spin_lock_irqsave(&ohci->lock, flags);
3125
3126         switch (base->type) {
3127         case FW_ISO_CONTEXT_TRANSMIT:
3128                 index = ctx - ohci->it_context_list;
3129                 ohci->it_context_mask |= 1 << index;
3130                 break;
3131
3132         case FW_ISO_CONTEXT_RECEIVE:
3133                 index = ctx - ohci->ir_context_list;
3134                 ohci->ir_context_mask |= 1 << index;
3135                 ohci->ir_context_channels |= 1ULL << base->channel;
3136                 break;
3137
3138         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3139                 index = ctx - ohci->ir_context_list;
3140                 ohci->ir_context_mask |= 1 << index;
3141                 ohci->ir_context_channels |= ohci->mc_channels;
3142                 ohci->mc_channels = 0;
3143                 ohci->mc_allocated = false;
3144                 break;
3145         }
3146
3147         spin_unlock_irqrestore(&ohci->lock, flags);
3148 }
3149
3150 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3151 {
3152         struct fw_ohci *ohci = fw_ohci(base->card);
3153         unsigned long flags;
3154         int ret;
3155
3156         switch (base->type) {
3157         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3158
3159                 spin_lock_irqsave(&ohci->lock, flags);
3160
3161                 /* Don't allow multichannel to grab other contexts' channels. */
3162                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3163                         *channels = ohci->ir_context_channels;
3164                         ret = -EBUSY;
3165                 } else {
3166                         set_multichannel_mask(ohci, *channels);
3167                         ret = 0;
3168                 }
3169
3170                 spin_unlock_irqrestore(&ohci->lock, flags);
3171
3172                 break;
3173         default:
3174                 ret = -EINVAL;
3175         }
3176
3177         return ret;
3178 }
3179
3180 #ifdef CONFIG_PM
3181 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3182 {
3183         int i;
3184         struct iso_context *ctx;
3185
3186         for (i = 0 ; i < ohci->n_ir ; i++) {
3187                 ctx = &ohci->ir_context_list[i];
3188                 if (ctx->context.running)
3189                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3190         }
3191
3192         for (i = 0 ; i < ohci->n_it ; i++) {
3193                 ctx = &ohci->it_context_list[i];
3194                 if (ctx->context.running)
3195                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3196         }
3197 }
3198 #endif
3199
3200 static int queue_iso_transmit(struct iso_context *ctx,
3201                               struct fw_iso_packet *packet,
3202                               struct fw_iso_buffer *buffer,
3203                               unsigned long payload)
3204 {
3205         struct descriptor *d, *last, *pd;
3206         struct fw_iso_packet *p;
3207         __le32 *header;
3208         dma_addr_t d_bus, page_bus;
3209         u32 z, header_z, payload_z, irq;
3210         u32 payload_index, payload_end_index, next_page_index;
3211         int page, end_page, i, length, offset;
3212
3213         p = packet;
3214         payload_index = payload;
3215
3216         if (p->skip)
3217                 z = 1;
3218         else
3219                 z = 2;
3220         if (p->header_length > 0)
3221                 z++;
3222
3223         /* Determine the first page the payload isn't contained in. */
3224         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3225         if (p->payload_length > 0)
3226                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3227         else
3228                 payload_z = 0;
3229
3230         z += payload_z;
3231
3232         /* Get header size in number of descriptors. */
3233         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3234
3235         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3236         if (d == NULL)
3237                 return -ENOMEM;
3238
3239         if (!p->skip) {
3240                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3241                 d[0].req_count = cpu_to_le16(8);
3242                 /*
3243                  * Link the skip address to this descriptor itself.  This causes
3244                  * a context to skip a cycle whenever lost cycles or FIFO
3245                  * overruns occur, without dropping the data.  The application
3246                  * should then decide whether this is an error condition or not.
3247                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3248                  */
3249                 d[0].branch_address = cpu_to_le32(d_bus | z);
3250
3251                 header = (__le32 *) &d[1];
3252                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3253                                         IT_HEADER_TAG(p->tag) |
3254                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3255                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3256                                         IT_HEADER_SPEED(ctx->base.speed));
3257                 header[1] =
3258                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3259                                                           p->payload_length));
3260         }
3261
3262         if (p->header_length > 0) {
3263                 d[2].req_count    = cpu_to_le16(p->header_length);
3264                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3265                 memcpy(&d[z], p->header, p->header_length);
3266         }
3267
3268         pd = d + z - payload_z;
3269         payload_end_index = payload_index + p->payload_length;
3270         for (i = 0; i < payload_z; i++) {
3271                 page               = payload_index >> PAGE_SHIFT;
3272                 offset             = payload_index & ~PAGE_MASK;
3273                 next_page_index    = (page + 1) << PAGE_SHIFT;
3274                 length             =
3275                         min(next_page_index, payload_end_index) - payload_index;
3276                 pd[i].req_count    = cpu_to_le16(length);
3277
3278                 page_bus = page_private(buffer->pages[page]);
3279                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3280
3281                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3282                                                  page_bus, offset, length,
3283                                                  DMA_TO_DEVICE);
3284
3285                 payload_index += length;
3286         }
3287
3288         if (p->interrupt)
3289                 irq = DESCRIPTOR_IRQ_ALWAYS;
3290         else
3291                 irq = DESCRIPTOR_NO_IRQ;
3292
3293         last = z == 2 ? d : d + z - 1;
3294         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3295                                      DESCRIPTOR_STATUS |
3296                                      DESCRIPTOR_BRANCH_ALWAYS |
3297                                      irq);
3298
3299         context_append(&ctx->context, d, z, header_z);
3300
3301         return 0;
3302 }
3303
3304 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3305                                        struct fw_iso_packet *packet,
3306                                        struct fw_iso_buffer *buffer,
3307                                        unsigned long payload)
3308 {
3309         struct device *device = ctx->context.ohci->card.device;
3310         struct descriptor *d, *pd;
3311         dma_addr_t d_bus, page_bus;
3312         u32 z, header_z, rest;
3313         int i, j, length;
3314         int page, offset, packet_count, header_size, payload_per_buffer;
3315
3316         /*
3317          * The OHCI controller puts the isochronous header and trailer in the
3318          * buffer, so we need at least 8 bytes.
3319          */
3320         packet_count = packet->header_length / ctx->base.header_size;
3321         header_size  = max(ctx->base.header_size, (size_t)8);
3322
3323         /* Get header size in number of descriptors. */
3324         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3325         page     = payload >> PAGE_SHIFT;
3326         offset   = payload & ~PAGE_MASK;
3327         payload_per_buffer = packet->payload_length / packet_count;
3328
3329         for (i = 0; i < packet_count; i++) {
3330                 /* d points to the header descriptor */
3331                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3332                 d = context_get_descriptors(&ctx->context,
3333                                 z + header_z, &d_bus);
3334                 if (d == NULL)
3335                         return -ENOMEM;
3336
3337                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3338                                               DESCRIPTOR_INPUT_MORE);
3339                 if (packet->skip && i == 0)
3340                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3341                 d->req_count    = cpu_to_le16(header_size);
3342                 d->res_count    = d->req_count;
3343                 d->transfer_status = 0;
3344                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3345
3346                 rest = payload_per_buffer;
3347                 pd = d;
3348                 for (j = 1; j < z; j++) {
3349                         pd++;
3350                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3351                                                   DESCRIPTOR_INPUT_MORE);
3352
3353                         if (offset + rest < PAGE_SIZE)
3354                                 length = rest;
3355                         else
3356                                 length = PAGE_SIZE - offset;
3357                         pd->req_count = cpu_to_le16(length);
3358                         pd->res_count = pd->req_count;
3359                         pd->transfer_status = 0;
3360
3361                         page_bus = page_private(buffer->pages[page]);
3362                         pd->data_address = cpu_to_le32(page_bus + offset);
3363
3364                         dma_sync_single_range_for_device(device, page_bus,
3365                                                          offset, length,
3366                                                          DMA_FROM_DEVICE);
3367
3368                         offset = (offset + length) & ~PAGE_MASK;
3369                         rest -= length;
3370                         if (offset == 0)
3371                                 page++;
3372                 }
3373                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3374                                           DESCRIPTOR_INPUT_LAST |
3375                                           DESCRIPTOR_BRANCH_ALWAYS);
3376                 if (packet->interrupt && i == packet_count - 1)
3377                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3378
3379                 context_append(&ctx->context, d, z, header_z);
3380         }
3381
3382         return 0;
3383 }
3384
3385 static int queue_iso_buffer_fill(struct iso_context *ctx,
3386                                  struct fw_iso_packet *packet,
3387                                  struct fw_iso_buffer *buffer,
3388                                  unsigned long payload)
3389 {
3390         struct descriptor *d;
3391         dma_addr_t d_bus, page_bus;
3392         int page, offset, rest, z, i, length;
3393
3394         page   = payload >> PAGE_SHIFT;
3395         offset = payload & ~PAGE_MASK;
3396         rest   = packet->payload_length;
3397
3398         /* We need one descriptor for each page in the buffer. */
3399         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3400
3401         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3402                 return -EFAULT;
3403
3404         for (i = 0; i < z; i++) {
3405                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3406                 if (d == NULL)
3407                         return -ENOMEM;
3408
3409                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3410                                          DESCRIPTOR_BRANCH_ALWAYS);
3411                 if (packet->skip && i == 0)
3412                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3413                 if (packet->interrupt && i == z - 1)
3414                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3415
3416                 if (offset + rest < PAGE_SIZE)
3417                         length = rest;
3418                 else
3419                         length = PAGE_SIZE - offset;
3420                 d->req_count = cpu_to_le16(length);
3421                 d->res_count = d->req_count;
3422                 d->transfer_status = 0;
3423
3424                 page_bus = page_private(buffer->pages[page]);
3425                 d->data_address = cpu_to_le32(page_bus + offset);
3426
3427                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3428                                                  page_bus, offset, length,
3429                                                  DMA_FROM_DEVICE);
3430
3431                 rest -= length;
3432                 offset = 0;
3433                 page++;
3434
3435                 context_append(&ctx->context, d, 1, 0);
3436         }
3437
3438         return 0;
3439 }
3440
3441 static int ohci_queue_iso(struct fw_iso_context *base,
3442                           struct fw_iso_packet *packet,
3443                           struct fw_iso_buffer *buffer,
3444                           unsigned long payload)
3445 {
3446         struct iso_context *ctx = container_of(base, struct iso_context, base);
3447         unsigned long flags;
3448         int ret = -ENOSYS;
3449
3450         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3451         switch (base->type) {
3452         case FW_ISO_CONTEXT_TRANSMIT:
3453                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3454                 break;
3455         case FW_ISO_CONTEXT_RECEIVE:
3456                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3457                 break;
3458         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3459                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3460                 break;
3461         }
3462         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3463
3464         return ret;
3465 }
3466
3467 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3468 {
3469         struct context *ctx =
3470                         &container_of(base, struct iso_context, base)->context;
3471
3472         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3473 }
3474
3475 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3476 {
3477         struct iso_context *ctx = container_of(base, struct iso_context, base);
3478         int ret = 0;
3479
3480         tasklet_disable(&ctx->context.tasklet);
3481
3482         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3483                 context_tasklet((unsigned long)&ctx->context);
3484
3485                 switch (base->type) {
3486                 case FW_ISO_CONTEXT_TRANSMIT:
3487                 case FW_ISO_CONTEXT_RECEIVE:
3488                         if (ctx->header_length != 0)
3489                                 flush_iso_completions(ctx);
3490                         break;
3491                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3492                         if (ctx->mc_completed != 0)
3493                                 flush_ir_buffer_fill(ctx);
3494                         break;
3495                 default:
3496                         ret = -ENOSYS;
3497                 }
3498
3499                 clear_bit_unlock(0, &ctx->flushing_completions);
3500                 smp_mb__after_atomic();
3501         }
3502
3503         tasklet_enable(&ctx->context.tasklet);
3504
3505         return ret;
3506 }
3507
3508 static const struct fw_card_driver ohci_driver = {
3509         .enable                 = ohci_enable,
3510         .read_phy_reg           = ohci_read_phy_reg,
3511         .update_phy_reg         = ohci_update_phy_reg,
3512         .set_config_rom         = ohci_set_config_rom,
3513         .send_request           = ohci_send_request,
3514         .send_response          = ohci_send_response,
3515         .cancel_packet          = ohci_cancel_packet,
3516         .enable_phys_dma        = ohci_enable_phys_dma,
3517         .read_csr               = ohci_read_csr,
3518         .write_csr              = ohci_write_csr,
3519
3520         .allocate_iso_context   = ohci_allocate_iso_context,
3521         .free_iso_context       = ohci_free_iso_context,
3522         .set_iso_channels       = ohci_set_iso_channels,
3523         .queue_iso              = ohci_queue_iso,
3524         .flush_queue_iso        = ohci_flush_queue_iso,
3525         .flush_iso_completions  = ohci_flush_iso_completions,
3526         .start_iso              = ohci_start_iso,
3527         .stop_iso               = ohci_stop_iso,
3528 };
3529
3530 #ifdef CONFIG_PPC_PMAC
3531 static void pmac_ohci_on(struct pci_dev *dev)
3532 {
3533         if (machine_is(powermac)) {
3534                 struct device_node *ofn = pci_device_to_OF_node(dev);
3535
3536                 if (ofn) {
3537                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3538                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3539                 }
3540         }
3541 }
3542
3543 static void pmac_ohci_off(struct pci_dev *dev)
3544 {
3545         if (machine_is(powermac)) {
3546                 struct device_node *ofn = pci_device_to_OF_node(dev);
3547
3548                 if (ofn) {
3549                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3550                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3551                 }
3552         }
3553 }
3554 #else
3555 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3556 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3557 #endif /* CONFIG_PPC_PMAC */
3558
3559 static int pci_probe(struct pci_dev *dev,
3560                                const struct pci_device_id *ent)
3561 {
3562         struct fw_ohci *ohci;
3563         u32 bus_options, max_receive, link_speed, version;
3564         u64 guid;
3565         int i, err;
3566         size_t size;
3567
3568         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3569                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3570                 return -ENOSYS;
3571         }
3572
3573         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3574         if (ohci == NULL) {
3575                 err = -ENOMEM;
3576                 goto fail;
3577         }
3578
3579         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3580
3581         pmac_ohci_on(dev);
3582
3583         err = pci_enable_device(dev);
3584         if (err) {
3585                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3586                 goto fail_free;
3587         }
3588
3589         pci_set_master(dev);
3590         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3591         pci_set_drvdata(dev, ohci);
3592
3593         spin_lock_init(&ohci->lock);
3594         mutex_init(&ohci->phy_reg_mutex);
3595
3596         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3597
3598         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3599             pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3600                 ohci_err(ohci, "invalid MMIO resource\n");
3601                 err = -ENXIO;
3602                 goto fail_disable;
3603         }
3604
3605         err = pci_request_region(dev, 0, ohci_driver_name);
3606         if (err) {
3607                 ohci_err(ohci, "MMIO resource unavailable\n");
3608                 goto fail_disable;
3609         }
3610
3611         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3612         if (ohci->registers == NULL) {
3613                 ohci_err(ohci, "failed to remap registers\n");
3614                 err = -ENXIO;
3615                 goto fail_iomem;
3616         }
3617
3618         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3619                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3620                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3621                      ohci_quirks[i].device == dev->device) &&
3622                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3623                      ohci_quirks[i].revision >= dev->revision)) {
3624                         ohci->quirks = ohci_quirks[i].flags;
3625                         break;
3626                 }
3627         if (param_quirks)
3628                 ohci->quirks = param_quirks;
3629
3630         /*
3631          * Because dma_alloc_coherent() allocates at least one page,
3632          * we save space by using a common buffer for the AR request/
3633          * response descriptors and the self IDs buffer.
3634          */
3635         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3636         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3637         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3638                                                PAGE_SIZE,
3639                                                &ohci->misc_buffer_bus,
3640                                                GFP_KERNEL);
3641         if (!ohci->misc_buffer) {
3642                 err = -ENOMEM;
3643                 goto fail_iounmap;
3644         }
3645
3646         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3647                               OHCI1394_AsReqRcvContextControlSet);
3648         if (err < 0)
3649                 goto fail_misc_buf;
3650
3651         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3652                               OHCI1394_AsRspRcvContextControlSet);
3653         if (err < 0)
3654                 goto fail_arreq_ctx;
3655
3656         err = context_init(&ohci->at_request_ctx, ohci,
3657                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3658         if (err < 0)
3659                 goto fail_arrsp_ctx;
3660
3661         err = context_init(&ohci->at_response_ctx, ohci,
3662                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3663         if (err < 0)
3664                 goto fail_atreq_ctx;
3665
3666         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3667         ohci->ir_context_channels = ~0ULL;
3668         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3669         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3670         ohci->ir_context_mask = ohci->ir_context_support;
3671         ohci->n_ir = hweight32(ohci->ir_context_mask);
3672         size = sizeof(struct iso_context) * ohci->n_ir;
3673         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3674
3675         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3676         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3677         /* JMicron JMB38x often shows 0 at first read, just ignore it */
3678         if (!ohci->it_context_support) {
3679                 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3680                 ohci->it_context_support = 0xf;
3681         }
3682         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3683         ohci->it_context_mask = ohci->it_context_support;
3684         ohci->n_it = hweight32(ohci->it_context_mask);
3685         size = sizeof(struct iso_context) * ohci->n_it;
3686         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3687
3688         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3689                 err = -ENOMEM;
3690                 goto fail_contexts;
3691         }
3692
3693         ohci->self_id     = ohci->misc_buffer     + PAGE_SIZE/2;
3694         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3695
3696         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3697         max_receive = (bus_options >> 12) & 0xf;
3698         link_speed = bus_options & 0x7;
3699         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3700                 reg_read(ohci, OHCI1394_GUIDLo);
3701
3702         if (!(ohci->quirks & QUIRK_NO_MSI))
3703                 pci_enable_msi(dev);
3704         if (request_irq(dev->irq, irq_handler,
3705                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3706                         ohci_driver_name, ohci)) {
3707                 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3708                 err = -EIO;
3709                 goto fail_msi;
3710         }
3711
3712         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3713         if (err)
3714                 goto fail_irq;
3715
3716         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3717         ohci_notice(ohci,
3718                     "added OHCI v%x.%x device as card %d, "
3719                     "%d IR + %d IT contexts, quirks 0x%x%s\n",
3720                     version >> 16, version & 0xff, ohci->card.index,
3721                     ohci->n_ir, ohci->n_it, ohci->quirks,
3722                     reg_read(ohci, OHCI1394_PhyUpperBound) ?
3723                         ", physUB" : "");
3724
3725         return 0;
3726
3727  fail_irq:
3728         free_irq(dev->irq, ohci);
3729  fail_msi:
3730         pci_disable_msi(dev);
3731  fail_contexts:
3732         kfree(ohci->ir_context_list);
3733         kfree(ohci->it_context_list);
3734         context_release(&ohci->at_response_ctx);
3735  fail_atreq_ctx:
3736         context_release(&ohci->at_request_ctx);
3737  fail_arrsp_ctx:
3738         ar_context_release(&ohci->ar_response_ctx);
3739  fail_arreq_ctx:
3740         ar_context_release(&ohci->ar_request_ctx);
3741  fail_misc_buf:
3742         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3743                           ohci->misc_buffer, ohci->misc_buffer_bus);
3744  fail_iounmap:
3745         pci_iounmap(dev, ohci->registers);
3746  fail_iomem:
3747         pci_release_region(dev, 0);
3748  fail_disable:
3749         pci_disable_device(dev);
3750  fail_free:
3751         kfree(ohci);
3752         pmac_ohci_off(dev);
3753  fail:
3754         return err;
3755 }
3756
3757 static void pci_remove(struct pci_dev *dev)
3758 {
3759         struct fw_ohci *ohci = pci_get_drvdata(dev);
3760
3761         /*
3762          * If the removal is happening from the suspend state, LPS won't be
3763          * enabled and host registers (eg., IntMaskClear) won't be accessible.
3764          */
3765         if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3766                 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3767                 flush_writes(ohci);
3768         }
3769         cancel_work_sync(&ohci->bus_reset_work);
3770         fw_core_remove_card(&ohci->card);
3771
3772         /*
3773          * FIXME: Fail all pending packets here, now that the upper
3774          * layers can't queue any more.
3775          */
3776
3777         software_reset(ohci);
3778         free_irq(dev->irq, ohci);
3779
3780         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3781                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3782                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3783         if (ohci->config_rom)
3784                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3785                                   ohci->config_rom, ohci->config_rom_bus);
3786         ar_context_release(&ohci->ar_request_ctx);
3787         ar_context_release(&ohci->ar_response_ctx);
3788         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3789                           ohci->misc_buffer, ohci->misc_buffer_bus);
3790         context_release(&ohci->at_request_ctx);
3791         context_release(&ohci->at_response_ctx);
3792         kfree(ohci->it_context_list);
3793         kfree(ohci->ir_context_list);
3794         pci_disable_msi(dev);
3795         pci_iounmap(dev, ohci->registers);
3796         pci_release_region(dev, 0);
3797         pci_disable_device(dev);
3798         kfree(ohci);
3799         pmac_ohci_off(dev);
3800
3801         dev_notice(&dev->dev, "removed fw-ohci device\n");
3802 }
3803
3804 #ifdef CONFIG_PM
3805 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3806 {
3807         struct fw_ohci *ohci = pci_get_drvdata(dev);
3808         int err;
3809
3810         software_reset(ohci);
3811         err = pci_save_state(dev);
3812         if (err) {
3813                 ohci_err(ohci, "pci_save_state failed\n");
3814                 return err;
3815         }
3816         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3817         if (err)
3818                 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3819         pmac_ohci_off(dev);
3820
3821         return 0;
3822 }
3823
3824 static int pci_resume(struct pci_dev *dev)
3825 {
3826         struct fw_ohci *ohci = pci_get_drvdata(dev);
3827         int err;
3828
3829         pmac_ohci_on(dev);
3830         pci_set_power_state(dev, PCI_D0);
3831         pci_restore_state(dev);
3832         err = pci_enable_device(dev);
3833         if (err) {
3834                 ohci_err(ohci, "pci_enable_device failed\n");
3835                 return err;
3836         }
3837
3838         /* Some systems don't setup GUID register on resume from ram  */
3839         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3840                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3841                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3842                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3843         }
3844
3845         err = ohci_enable(&ohci->card, NULL, 0);
3846         if (err)
3847                 return err;
3848
3849         ohci_resume_iso_dma(ohci);
3850
3851         return 0;
3852 }
3853 #endif
3854
3855 static const struct pci_device_id pci_table[] = {
3856         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3857         { }
3858 };
3859
3860 MODULE_DEVICE_TABLE(pci, pci_table);
3861
3862 static struct pci_driver fw_ohci_pci_driver = {
3863         .name           = ohci_driver_name,
3864         .id_table       = pci_table,
3865         .probe          = pci_probe,
3866         .remove         = pci_remove,
3867 #ifdef CONFIG_PM
3868         .resume         = pci_resume,
3869         .suspend        = pci_suspend,
3870 #endif
3871 };
3872
3873 static int __init fw_ohci_init(void)
3874 {
3875         selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3876         if (!selfid_workqueue)
3877                 return -ENOMEM;
3878
3879         return pci_register_driver(&fw_ohci_pci_driver);
3880 }
3881
3882 static void __exit fw_ohci_cleanup(void)
3883 {
3884         pci_unregister_driver(&fw_ohci_pci_driver);
3885         destroy_workqueue(selfid_workqueue);
3886 }
3887
3888 module_init(fw_ohci_init);
3889 module_exit(fw_ohci_cleanup);
3890
3891 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3892 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3893 MODULE_LICENSE("GPL");
3894
3895 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3896 MODULE_ALIAS("ohci1394");