Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[sfrench/cifs-2.6.git] / drivers / firewire / ohci.c
1 /*
2  * Driver for OHCI 1394 controllers
3  *
4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
43 #include <asm/page.h>
44 #include <asm/system.h>
45
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
48 #endif
49
50 #include "core.h"
51 #include "ohci.h"
52
53 #define DESCRIPTOR_OUTPUT_MORE          0
54 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
57 #define DESCRIPTOR_STATUS               (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
59 #define DESCRIPTOR_PING                 (1 << 7)
60 #define DESCRIPTOR_YY                   (1 << 6)
61 #define DESCRIPTOR_NO_IRQ               (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
65 #define DESCRIPTOR_WAIT                 (3 << 0)
66
67 struct descriptor {
68         __le16 req_count;
69         __le16 control;
70         __le32 data_address;
71         __le32 branch_address;
72         __le16 res_count;
73         __le16 transfer_status;
74 } __attribute__((aligned(16)));
75
76 struct db_descriptor {
77         __le16 first_size;
78         __le16 control;
79         __le16 second_req_count;
80         __le16 first_req_count;
81         __le32 branch_address;
82         __le16 second_res_count;
83         __le16 first_res_count;
84         __le32 reserved0;
85         __le32 first_buffer;
86         __le32 second_buffer;
87         __le32 reserved1;
88 } __attribute__((aligned(16)));
89
90 #define CONTROL_SET(regs)       (regs)
91 #define CONTROL_CLEAR(regs)     ((regs) + 4)
92 #define COMMAND_PTR(regs)       ((regs) + 12)
93 #define CONTEXT_MATCH(regs)     ((regs) + 16)
94
95 struct ar_buffer {
96         struct descriptor descriptor;
97         struct ar_buffer *next;
98         __le32 data[0];
99 };
100
101 struct ar_context {
102         struct fw_ohci *ohci;
103         struct ar_buffer *current_buffer;
104         struct ar_buffer *last_buffer;
105         void *pointer;
106         u32 regs;
107         struct tasklet_struct tasklet;
108 };
109
110 struct context;
111
112 typedef int (*descriptor_callback_t)(struct context *ctx,
113                                      struct descriptor *d,
114                                      struct descriptor *last);
115
116 /*
117  * A buffer that contains a block of DMA-able coherent memory used for
118  * storing a portion of a DMA descriptor program.
119  */
120 struct descriptor_buffer {
121         struct list_head list;
122         dma_addr_t buffer_bus;
123         size_t buffer_size;
124         size_t used;
125         struct descriptor buffer[0];
126 };
127
128 struct context {
129         struct fw_ohci *ohci;
130         u32 regs;
131         int total_allocation;
132
133         /*
134          * List of page-sized buffers for storing DMA descriptors.
135          * Head of list contains buffers in use and tail of list contains
136          * free buffers.
137          */
138         struct list_head buffer_list;
139
140         /*
141          * Pointer to a buffer inside buffer_list that contains the tail
142          * end of the current DMA program.
143          */
144         struct descriptor_buffer *buffer_tail;
145
146         /*
147          * The descriptor containing the branch address of the first
148          * descriptor that has not yet been filled by the device.
149          */
150         struct descriptor *last;
151
152         /*
153          * The last descriptor in the DMA program.  It contains the branch
154          * address that must be updated upon appending a new descriptor.
155          */
156         struct descriptor *prev;
157
158         descriptor_callback_t callback;
159
160         struct tasklet_struct tasklet;
161 };
162
163 #define IT_HEADER_SY(v)          ((v) <<  0)
164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
166 #define IT_HEADER_TAG(v)         ((v) << 14)
167 #define IT_HEADER_SPEED(v)       ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170 struct iso_context {
171         struct fw_iso_context base;
172         struct context context;
173         int excess_bytes;
174         void *header;
175         size_t header_length;
176 };
177
178 #define CONFIG_ROM_SIZE 1024
179
180 struct fw_ohci {
181         struct fw_card card;
182
183         __iomem char *registers;
184         dma_addr_t self_id_bus;
185         __le32 *self_id_cpu;
186         struct tasklet_struct bus_reset_tasklet;
187         int node_id;
188         int generation;
189         int request_generation; /* for timestamping incoming requests */
190         atomic_t bus_seconds;
191
192         bool use_dualbuffer;
193         bool old_uninorth;
194         bool bus_reset_packet_quirk;
195
196         /*
197          * Spinlock for accessing fw_ohci data.  Never call out of
198          * this driver with this lock held.
199          */
200         spinlock_t lock;
201         u32 self_id_buffer[512];
202
203         /* Config rom buffers */
204         __be32 *config_rom;
205         dma_addr_t config_rom_bus;
206         __be32 *next_config_rom;
207         dma_addr_t next_config_rom_bus;
208         __be32 next_header;
209
210         struct ar_context ar_request_ctx;
211         struct ar_context ar_response_ctx;
212         struct context at_request_ctx;
213         struct context at_response_ctx;
214
215         u32 it_context_mask;
216         struct iso_context *it_context_list;
217         u64 ir_context_channels;
218         u32 ir_context_mask;
219         struct iso_context *ir_context_list;
220 };
221
222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223 {
224         return container_of(card, struct fw_ohci, card);
225 }
226
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
228 #define IR_CONTEXT_BUFFER_FILL          0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
233
234 #define CONTEXT_RUN     0x8000
235 #define CONTEXT_WAKE    0x1000
236 #define CONTEXT_DEAD    0x0800
237 #define CONTEXT_ACTIVE  0x0400
238
239 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
242
243 #define OHCI1394_REGISTER_SIZE          0x800
244 #define OHCI_LOOP_COUNT                 500
245 #define OHCI1394_PCI_HCI_Control        0x40
246 #define SELF_ID_BUF_SIZE                0x800
247 #define OHCI_TCODE_PHY_PACKET           0x0e
248 #define OHCI_VERSION_1_1                0x010010
249
250 static char ohci_driver_name[] = KBUILD_MODNAME;
251
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
253
254 #define OHCI_PARAM_DEBUG_AT_AR          1
255 #define OHCI_PARAM_DEBUG_SELFIDS        2
256 #define OHCI_PARAM_DEBUG_IRQS           4
257 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
258
259 static int param_debug;
260 module_param_named(debug, param_debug, int, 0644);
261 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
262         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
263         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
264         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
265         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266         ", or a combination, or all = -1)");
267
268 static void log_irqs(u32 evt)
269 {
270         if (likely(!(param_debug &
271                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
272                 return;
273
274         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
275             !(evt & OHCI1394_busReset))
276                 return;
277
278         fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
280             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
281             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
282             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
283             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
284             evt & OHCI1394_isochRx              ? " IR"                 : "",
285             evt & OHCI1394_isochTx              ? " IT"                 : "",
286             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
287             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
288             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
289             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
290             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
291             evt & OHCI1394_busReset             ? " busReset"           : "",
292             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
293                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
294                     OHCI1394_respTxComplete | OHCI1394_isochRx |
295                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
296                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
297                     OHCI1394_cycleInconsistent |
298                     OHCI1394_regAccessFail | OHCI1394_busReset)
299                                                 ? " ?"                  : "");
300 }
301
302 static const char *speed[] = {
303         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
304 };
305 static const char *power[] = {
306         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
307         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
308 };
309 static const char port[] = { '.', '-', 'p', 'c', };
310
311 static char _p(u32 *s, int shift)
312 {
313         return port[*s >> shift & 3];
314 }
315
316 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
317 {
318         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
319                 return;
320
321         fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
322                   self_id_count, generation, node_id);
323
324         for (; self_id_count--; ++s)
325                 if ((*s & 1 << 23) == 0)
326                         fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
327                             "%s gc=%d %s %s%s%s\n",
328                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
329                             speed[*s >> 14 & 3], *s >> 16 & 63,
330                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
331                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
332                 else
333                         fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
334                             *s, *s >> 24 & 63,
335                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
336                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
337 }
338
339 static const char *evts[] = {
340         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
341         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
342         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
343         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
344         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
345         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
346         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
347         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
348         [0x10] = "-reserved-",          [0x11] = "ack_complete",
349         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
350         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
351         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
352         [0x18] = "-reserved-",          [0x19] = "-reserved-",
353         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
354         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
355         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
356         [0x20] = "pending/cancelled",
357 };
358 static const char *tcodes[] = {
359         [0x0] = "QW req",               [0x1] = "BW req",
360         [0x2] = "W resp",               [0x3] = "-reserved-",
361         [0x4] = "QR req",               [0x5] = "BR req",
362         [0x6] = "QR resp",              [0x7] = "BR resp",
363         [0x8] = "cycle start",          [0x9] = "Lk req",
364         [0xa] = "async stream packet",  [0xb] = "Lk resp",
365         [0xc] = "-reserved-",           [0xd] = "-reserved-",
366         [0xe] = "link internal",        [0xf] = "-reserved-",
367 };
368 static const char *phys[] = {
369         [0x0] = "phy config packet",    [0x1] = "link-on packet",
370         [0x2] = "self-id packet",       [0x3] = "-reserved-",
371 };
372
373 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
374 {
375         int tcode = header[0] >> 4 & 0xf;
376         char specific[12];
377
378         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
379                 return;
380
381         if (unlikely(evt >= ARRAY_SIZE(evts)))
382                         evt = 0x1f;
383
384         if (evt == OHCI1394_evt_bus_reset) {
385                 fw_notify("A%c evt_bus_reset, generation %d\n",
386                     dir, (header[2] >> 16) & 0xff);
387                 return;
388         }
389
390         if (header[0] == ~header[1]) {
391                 fw_notify("A%c %s, %s, %08x\n",
392                     dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
393                 return;
394         }
395
396         switch (tcode) {
397         case 0x0: case 0x6: case 0x8:
398                 snprintf(specific, sizeof(specific), " = %08x",
399                          be32_to_cpu((__force __be32)header[3]));
400                 break;
401         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
402                 snprintf(specific, sizeof(specific), " %x,%x",
403                          header[3] >> 16, header[3] & 0xffff);
404                 break;
405         default:
406                 specific[0] = '\0';
407         }
408
409         switch (tcode) {
410         case 0xe: case 0xa:
411                 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
412                 break;
413         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
414                 fw_notify("A%c spd %x tl %02x, "
415                     "%04x -> %04x, %s, "
416                     "%s, %04x%08x%s\n",
417                     dir, speed, header[0] >> 10 & 0x3f,
418                     header[1] >> 16, header[0] >> 16, evts[evt],
419                     tcodes[tcode], header[1] & 0xffff, header[2], specific);
420                 break;
421         default:
422                 fw_notify("A%c spd %x tl %02x, "
423                     "%04x -> %04x, %s, "
424                     "%s%s\n",
425                     dir, speed, header[0] >> 10 & 0x3f,
426                     header[1] >> 16, header[0] >> 16, evts[evt],
427                     tcodes[tcode], specific);
428         }
429 }
430
431 #else
432
433 #define log_irqs(evt)
434 #define log_selfids(node_id, generation, self_id_count, sid)
435 #define log_ar_at_event(dir, speed, header, evt)
436
437 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
438
439 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
440 {
441         writel(data, ohci->registers + offset);
442 }
443
444 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
445 {
446         return readl(ohci->registers + offset);
447 }
448
449 static inline void flush_writes(const struct fw_ohci *ohci)
450 {
451         /* Do a dummy read to flush writes. */
452         reg_read(ohci, OHCI1394_Version);
453 }
454
455 static int ohci_update_phy_reg(struct fw_card *card, int addr,
456                                int clear_bits, int set_bits)
457 {
458         struct fw_ohci *ohci = fw_ohci(card);
459         u32 val, old;
460
461         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
462         flush_writes(ohci);
463         msleep(2);
464         val = reg_read(ohci, OHCI1394_PhyControl);
465         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
466                 fw_error("failed to set phy reg bits.\n");
467                 return -EBUSY;
468         }
469
470         old = OHCI1394_PhyControl_ReadData(val);
471         old = (old & ~clear_bits) | set_bits;
472         reg_write(ohci, OHCI1394_PhyControl,
473                   OHCI1394_PhyControl_Write(addr, old));
474
475         return 0;
476 }
477
478 static int ar_context_add_page(struct ar_context *ctx)
479 {
480         struct device *dev = ctx->ohci->card.device;
481         struct ar_buffer *ab;
482         dma_addr_t uninitialized_var(ab_bus);
483         size_t offset;
484
485         ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
486         if (ab == NULL)
487                 return -ENOMEM;
488
489         ab->next = NULL;
490         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
491         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
492                                                     DESCRIPTOR_STATUS |
493                                                     DESCRIPTOR_BRANCH_ALWAYS);
494         offset = offsetof(struct ar_buffer, data);
495         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
496         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
497         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
498         ab->descriptor.branch_address = 0;
499
500         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
501         ctx->last_buffer->next = ab;
502         ctx->last_buffer = ab;
503
504         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
505         flush_writes(ctx->ohci);
506
507         return 0;
508 }
509
510 static void ar_context_release(struct ar_context *ctx)
511 {
512         struct ar_buffer *ab, *ab_next;
513         size_t offset;
514         dma_addr_t ab_bus;
515
516         for (ab = ctx->current_buffer; ab; ab = ab_next) {
517                 ab_next = ab->next;
518                 offset = offsetof(struct ar_buffer, data);
519                 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
520                 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
521                                   ab, ab_bus);
522         }
523 }
524
525 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
526 #define cond_le32_to_cpu(v) \
527         (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
528 #else
529 #define cond_le32_to_cpu(v) le32_to_cpu(v)
530 #endif
531
532 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
533 {
534         struct fw_ohci *ohci = ctx->ohci;
535         struct fw_packet p;
536         u32 status, length, tcode;
537         int evt;
538
539         p.header[0] = cond_le32_to_cpu(buffer[0]);
540         p.header[1] = cond_le32_to_cpu(buffer[1]);
541         p.header[2] = cond_le32_to_cpu(buffer[2]);
542
543         tcode = (p.header[0] >> 4) & 0x0f;
544         switch (tcode) {
545         case TCODE_WRITE_QUADLET_REQUEST:
546         case TCODE_READ_QUADLET_RESPONSE:
547                 p.header[3] = (__force __u32) buffer[3];
548                 p.header_length = 16;
549                 p.payload_length = 0;
550                 break;
551
552         case TCODE_READ_BLOCK_REQUEST :
553                 p.header[3] = cond_le32_to_cpu(buffer[3]);
554                 p.header_length = 16;
555                 p.payload_length = 0;
556                 break;
557
558         case TCODE_WRITE_BLOCK_REQUEST:
559         case TCODE_READ_BLOCK_RESPONSE:
560         case TCODE_LOCK_REQUEST:
561         case TCODE_LOCK_RESPONSE:
562                 p.header[3] = cond_le32_to_cpu(buffer[3]);
563                 p.header_length = 16;
564                 p.payload_length = p.header[3] >> 16;
565                 break;
566
567         case TCODE_WRITE_RESPONSE:
568         case TCODE_READ_QUADLET_REQUEST:
569         case OHCI_TCODE_PHY_PACKET:
570                 p.header_length = 12;
571                 p.payload_length = 0;
572                 break;
573
574         default:
575                 /* FIXME: Stop context, discard everything, and restart? */
576                 p.header_length = 0;
577                 p.payload_length = 0;
578         }
579
580         p.payload = (void *) buffer + p.header_length;
581
582         /* FIXME: What to do about evt_* errors? */
583         length = (p.header_length + p.payload_length + 3) / 4;
584         status = cond_le32_to_cpu(buffer[length]);
585         evt    = (status >> 16) & 0x1f;
586
587         p.ack        = evt - 16;
588         p.speed      = (status >> 21) & 0x7;
589         p.timestamp  = status & 0xffff;
590         p.generation = ohci->request_generation;
591
592         log_ar_at_event('R', p.speed, p.header, evt);
593
594         /*
595          * The OHCI bus reset handler synthesizes a phy packet with
596          * the new generation number when a bus reset happens (see
597          * section 8.4.2.3).  This helps us determine when a request
598          * was received and make sure we send the response in the same
599          * generation.  We only need this for requests; for responses
600          * we use the unique tlabel for finding the matching
601          * request.
602          *
603          * Alas some chips sometimes emit bus reset packets with a
604          * wrong generation.  We set the correct generation for these
605          * at a slightly incorrect time (in bus_reset_tasklet).
606          */
607         if (evt == OHCI1394_evt_bus_reset) {
608                 if (!ohci->bus_reset_packet_quirk)
609                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
610         } else if (ctx == &ohci->ar_request_ctx) {
611                 fw_core_handle_request(&ohci->card, &p);
612         } else {
613                 fw_core_handle_response(&ohci->card, &p);
614         }
615
616         return buffer + length + 1;
617 }
618
619 static void ar_context_tasklet(unsigned long data)
620 {
621         struct ar_context *ctx = (struct ar_context *)data;
622         struct fw_ohci *ohci = ctx->ohci;
623         struct ar_buffer *ab;
624         struct descriptor *d;
625         void *buffer, *end;
626
627         ab = ctx->current_buffer;
628         d = &ab->descriptor;
629
630         if (d->res_count == 0) {
631                 size_t size, rest, offset;
632                 dma_addr_t start_bus;
633                 void *start;
634
635                 /*
636                  * This descriptor is finished and we may have a
637                  * packet split across this and the next buffer. We
638                  * reuse the page for reassembling the split packet.
639                  */
640
641                 offset = offsetof(struct ar_buffer, data);
642                 start = buffer = ab;
643                 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
644
645                 ab = ab->next;
646                 d = &ab->descriptor;
647                 size = buffer + PAGE_SIZE - ctx->pointer;
648                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
649                 memmove(buffer, ctx->pointer, size);
650                 memcpy(buffer + size, ab->data, rest);
651                 ctx->current_buffer = ab;
652                 ctx->pointer = (void *) ab->data + rest;
653                 end = buffer + size + rest;
654
655                 while (buffer < end)
656                         buffer = handle_ar_packet(ctx, buffer);
657
658                 dma_free_coherent(ohci->card.device, PAGE_SIZE,
659                                   start, start_bus);
660                 ar_context_add_page(ctx);
661         } else {
662                 buffer = ctx->pointer;
663                 ctx->pointer = end =
664                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
665
666                 while (buffer < end)
667                         buffer = handle_ar_packet(ctx, buffer);
668         }
669 }
670
671 static int ar_context_init(struct ar_context *ctx,
672                            struct fw_ohci *ohci, u32 regs)
673 {
674         struct ar_buffer ab;
675
676         ctx->regs        = regs;
677         ctx->ohci        = ohci;
678         ctx->last_buffer = &ab;
679         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
680
681         ar_context_add_page(ctx);
682         ar_context_add_page(ctx);
683         ctx->current_buffer = ab.next;
684         ctx->pointer = ctx->current_buffer->data;
685
686         return 0;
687 }
688
689 static void ar_context_run(struct ar_context *ctx)
690 {
691         struct ar_buffer *ab = ctx->current_buffer;
692         dma_addr_t ab_bus;
693         size_t offset;
694
695         offset = offsetof(struct ar_buffer, data);
696         ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
697
698         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
699         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
700         flush_writes(ctx->ohci);
701 }
702
703 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
704 {
705         int b, key;
706
707         b   = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
708         key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
709
710         /* figure out which descriptor the branch address goes in */
711         if (z == 2 && (b == 3 || key == 2))
712                 return d;
713         else
714                 return d + z - 1;
715 }
716
717 static void context_tasklet(unsigned long data)
718 {
719         struct context *ctx = (struct context *) data;
720         struct descriptor *d, *last;
721         u32 address;
722         int z;
723         struct descriptor_buffer *desc;
724
725         desc = list_entry(ctx->buffer_list.next,
726                         struct descriptor_buffer, list);
727         last = ctx->last;
728         while (last->branch_address != 0) {
729                 struct descriptor_buffer *old_desc = desc;
730                 address = le32_to_cpu(last->branch_address);
731                 z = address & 0xf;
732                 address &= ~0xf;
733
734                 /* If the branch address points to a buffer outside of the
735                  * current buffer, advance to the next buffer. */
736                 if (address < desc->buffer_bus ||
737                                 address >= desc->buffer_bus + desc->used)
738                         desc = list_entry(desc->list.next,
739                                         struct descriptor_buffer, list);
740                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
741                 last = find_branch_descriptor(d, z);
742
743                 if (!ctx->callback(ctx, d, last))
744                         break;
745
746                 if (old_desc != desc) {
747                         /* If we've advanced to the next buffer, move the
748                          * previous buffer to the free list. */
749                         unsigned long flags;
750                         old_desc->used = 0;
751                         spin_lock_irqsave(&ctx->ohci->lock, flags);
752                         list_move_tail(&old_desc->list, &ctx->buffer_list);
753                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
754                 }
755                 ctx->last = last;
756         }
757 }
758
759 /*
760  * Allocate a new buffer and add it to the list of free buffers for this
761  * context.  Must be called with ohci->lock held.
762  */
763 static int context_add_buffer(struct context *ctx)
764 {
765         struct descriptor_buffer *desc;
766         dma_addr_t uninitialized_var(bus_addr);
767         int offset;
768
769         /*
770          * 16MB of descriptors should be far more than enough for any DMA
771          * program.  This will catch run-away userspace or DoS attacks.
772          */
773         if (ctx->total_allocation >= 16*1024*1024)
774                 return -ENOMEM;
775
776         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
777                         &bus_addr, GFP_ATOMIC);
778         if (!desc)
779                 return -ENOMEM;
780
781         offset = (void *)&desc->buffer - (void *)desc;
782         desc->buffer_size = PAGE_SIZE - offset;
783         desc->buffer_bus = bus_addr + offset;
784         desc->used = 0;
785
786         list_add_tail(&desc->list, &ctx->buffer_list);
787         ctx->total_allocation += PAGE_SIZE;
788
789         return 0;
790 }
791
792 static int context_init(struct context *ctx, struct fw_ohci *ohci,
793                         u32 regs, descriptor_callback_t callback)
794 {
795         ctx->ohci = ohci;
796         ctx->regs = regs;
797         ctx->total_allocation = 0;
798
799         INIT_LIST_HEAD(&ctx->buffer_list);
800         if (context_add_buffer(ctx) < 0)
801                 return -ENOMEM;
802
803         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
804                         struct descriptor_buffer, list);
805
806         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
807         ctx->callback = callback;
808
809         /*
810          * We put a dummy descriptor in the buffer that has a NULL
811          * branch address and looks like it's been sent.  That way we
812          * have a descriptor to append DMA programs to.
813          */
814         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
815         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
816         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
817         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
818         ctx->last = ctx->buffer_tail->buffer;
819         ctx->prev = ctx->buffer_tail->buffer;
820
821         return 0;
822 }
823
824 static void context_release(struct context *ctx)
825 {
826         struct fw_card *card = &ctx->ohci->card;
827         struct descriptor_buffer *desc, *tmp;
828
829         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
830                 dma_free_coherent(card->device, PAGE_SIZE, desc,
831                         desc->buffer_bus -
832                         ((void *)&desc->buffer - (void *)desc));
833 }
834
835 /* Must be called with ohci->lock held */
836 static struct descriptor *context_get_descriptors(struct context *ctx,
837                                                   int z, dma_addr_t *d_bus)
838 {
839         struct descriptor *d = NULL;
840         struct descriptor_buffer *desc = ctx->buffer_tail;
841
842         if (z * sizeof(*d) > desc->buffer_size)
843                 return NULL;
844
845         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
846                 /* No room for the descriptor in this buffer, so advance to the
847                  * next one. */
848
849                 if (desc->list.next == &ctx->buffer_list) {
850                         /* If there is no free buffer next in the list,
851                          * allocate one. */
852                         if (context_add_buffer(ctx) < 0)
853                                 return NULL;
854                 }
855                 desc = list_entry(desc->list.next,
856                                 struct descriptor_buffer, list);
857                 ctx->buffer_tail = desc;
858         }
859
860         d = desc->buffer + desc->used / sizeof(*d);
861         memset(d, 0, z * sizeof(*d));
862         *d_bus = desc->buffer_bus + desc->used;
863
864         return d;
865 }
866
867 static void context_run(struct context *ctx, u32 extra)
868 {
869         struct fw_ohci *ohci = ctx->ohci;
870
871         reg_write(ohci, COMMAND_PTR(ctx->regs),
872                   le32_to_cpu(ctx->last->branch_address));
873         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
874         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
875         flush_writes(ohci);
876 }
877
878 static void context_append(struct context *ctx,
879                            struct descriptor *d, int z, int extra)
880 {
881         dma_addr_t d_bus;
882         struct descriptor_buffer *desc = ctx->buffer_tail;
883
884         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
885
886         desc->used += (z + extra) * sizeof(*d);
887         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
888         ctx->prev = find_branch_descriptor(d, z);
889
890         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
891         flush_writes(ctx->ohci);
892 }
893
894 static void context_stop(struct context *ctx)
895 {
896         u32 reg;
897         int i;
898
899         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
900         flush_writes(ctx->ohci);
901
902         for (i = 0; i < 10; i++) {
903                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
904                 if ((reg & CONTEXT_ACTIVE) == 0)
905                         return;
906
907                 mdelay(1);
908         }
909         fw_error("Error: DMA context still active (0x%08x)\n", reg);
910 }
911
912 struct driver_data {
913         struct fw_packet *packet;
914 };
915
916 /*
917  * This function apppends a packet to the DMA queue for transmission.
918  * Must always be called with the ochi->lock held to ensure proper
919  * generation handling and locking around packet queue manipulation.
920  */
921 static int at_context_queue_packet(struct context *ctx,
922                                    struct fw_packet *packet)
923 {
924         struct fw_ohci *ohci = ctx->ohci;
925         dma_addr_t d_bus, uninitialized_var(payload_bus);
926         struct driver_data *driver_data;
927         struct descriptor *d, *last;
928         __le32 *header;
929         int z, tcode;
930         u32 reg;
931
932         d = context_get_descriptors(ctx, 4, &d_bus);
933         if (d == NULL) {
934                 packet->ack = RCODE_SEND_ERROR;
935                 return -1;
936         }
937
938         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
939         d[0].res_count = cpu_to_le16(packet->timestamp);
940
941         /*
942          * The DMA format for asyncronous link packets is different
943          * from the IEEE1394 layout, so shift the fields around
944          * accordingly.  If header_length is 8, it's a PHY packet, to
945          * which we need to prepend an extra quadlet.
946          */
947
948         header = (__le32 *) &d[1];
949         switch (packet->header_length) {
950         case 16:
951         case 12:
952                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
953                                         (packet->speed << 16));
954                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
955                                         (packet->header[0] & 0xffff0000));
956                 header[2] = cpu_to_le32(packet->header[2]);
957
958                 tcode = (packet->header[0] >> 4) & 0x0f;
959                 if (TCODE_IS_BLOCK_PACKET(tcode))
960                         header[3] = cpu_to_le32(packet->header[3]);
961                 else
962                         header[3] = (__force __le32) packet->header[3];
963
964                 d[0].req_count = cpu_to_le16(packet->header_length);
965                 break;
966
967         case 8:
968                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
969                                         (packet->speed << 16));
970                 header[1] = cpu_to_le32(packet->header[0]);
971                 header[2] = cpu_to_le32(packet->header[1]);
972                 d[0].req_count = cpu_to_le16(12);
973                 break;
974
975         case 4:
976                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
977                                         (packet->speed << 16));
978                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
979                 d[0].req_count = cpu_to_le16(8);
980                 break;
981
982         default:
983                 /* BUG(); */
984                 packet->ack = RCODE_SEND_ERROR;
985                 return -1;
986         }
987
988         driver_data = (struct driver_data *) &d[3];
989         driver_data->packet = packet;
990         packet->driver_data = driver_data;
991
992         if (packet->payload_length > 0) {
993                 payload_bus =
994                         dma_map_single(ohci->card.device, packet->payload,
995                                        packet->payload_length, DMA_TO_DEVICE);
996                 if (dma_mapping_error(ohci->card.device, payload_bus)) {
997                         packet->ack = RCODE_SEND_ERROR;
998                         return -1;
999                 }
1000                 packet->payload_bus     = payload_bus;
1001                 packet->payload_mapped  = true;
1002
1003                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1004                 d[2].data_address = cpu_to_le32(payload_bus);
1005                 last = &d[2];
1006                 z = 3;
1007         } else {
1008                 last = &d[0];
1009                 z = 2;
1010         }
1011
1012         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1013                                      DESCRIPTOR_IRQ_ALWAYS |
1014                                      DESCRIPTOR_BRANCH_ALWAYS);
1015
1016         /*
1017          * If the controller and packet generations don't match, we need to
1018          * bail out and try again.  If IntEvent.busReset is set, the AT context
1019          * is halted, so appending to the context and trying to run it is
1020          * futile.  Most controllers do the right thing and just flush the AT
1021          * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1022          * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1023          * up stalling out.  So we just bail out in software and try again
1024          * later, and everyone is happy.
1025          * FIXME: Document how the locking works.
1026          */
1027         if (ohci->generation != packet->generation ||
1028             reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1029                 if (packet->payload_mapped)
1030                         dma_unmap_single(ohci->card.device, payload_bus,
1031                                          packet->payload_length, DMA_TO_DEVICE);
1032                 packet->ack = RCODE_GENERATION;
1033                 return -1;
1034         }
1035
1036         context_append(ctx, d, z, 4 - z);
1037
1038         /* If the context isn't already running, start it up. */
1039         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1040         if ((reg & CONTEXT_RUN) == 0)
1041                 context_run(ctx, 0);
1042
1043         return 0;
1044 }
1045
1046 static int handle_at_packet(struct context *context,
1047                             struct descriptor *d,
1048                             struct descriptor *last)
1049 {
1050         struct driver_data *driver_data;
1051         struct fw_packet *packet;
1052         struct fw_ohci *ohci = context->ohci;
1053         int evt;
1054
1055         if (last->transfer_status == 0)
1056                 /* This descriptor isn't done yet, stop iteration. */
1057                 return 0;
1058
1059         driver_data = (struct driver_data *) &d[3];
1060         packet = driver_data->packet;
1061         if (packet == NULL)
1062                 /* This packet was cancelled, just continue. */
1063                 return 1;
1064
1065         if (packet->payload_mapped)
1066                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1067                                  packet->payload_length, DMA_TO_DEVICE);
1068
1069         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1070         packet->timestamp = le16_to_cpu(last->res_count);
1071
1072         log_ar_at_event('T', packet->speed, packet->header, evt);
1073
1074         switch (evt) {
1075         case OHCI1394_evt_timeout:
1076                 /* Async response transmit timed out. */
1077                 packet->ack = RCODE_CANCELLED;
1078                 break;
1079
1080         case OHCI1394_evt_flushed:
1081                 /*
1082                  * The packet was flushed should give same error as
1083                  * when we try to use a stale generation count.
1084                  */
1085                 packet->ack = RCODE_GENERATION;
1086                 break;
1087
1088         case OHCI1394_evt_missing_ack:
1089                 /*
1090                  * Using a valid (current) generation count, but the
1091                  * node is not on the bus or not sending acks.
1092                  */
1093                 packet->ack = RCODE_NO_ACK;
1094                 break;
1095
1096         case ACK_COMPLETE + 0x10:
1097         case ACK_PENDING + 0x10:
1098         case ACK_BUSY_X + 0x10:
1099         case ACK_BUSY_A + 0x10:
1100         case ACK_BUSY_B + 0x10:
1101         case ACK_DATA_ERROR + 0x10:
1102         case ACK_TYPE_ERROR + 0x10:
1103                 packet->ack = evt - 0x10;
1104                 break;
1105
1106         default:
1107                 packet->ack = RCODE_SEND_ERROR;
1108                 break;
1109         }
1110
1111         packet->callback(packet, &ohci->card, packet->ack);
1112
1113         return 1;
1114 }
1115
1116 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1117 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1118 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1119 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1120 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1121
1122 static void handle_local_rom(struct fw_ohci *ohci,
1123                              struct fw_packet *packet, u32 csr)
1124 {
1125         struct fw_packet response;
1126         int tcode, length, i;
1127
1128         tcode = HEADER_GET_TCODE(packet->header[0]);
1129         if (TCODE_IS_BLOCK_PACKET(tcode))
1130                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1131         else
1132                 length = 4;
1133
1134         i = csr - CSR_CONFIG_ROM;
1135         if (i + length > CONFIG_ROM_SIZE) {
1136                 fw_fill_response(&response, packet->header,
1137                                  RCODE_ADDRESS_ERROR, NULL, 0);
1138         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1139                 fw_fill_response(&response, packet->header,
1140                                  RCODE_TYPE_ERROR, NULL, 0);
1141         } else {
1142                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1143                                  (void *) ohci->config_rom + i, length);
1144         }
1145
1146         fw_core_handle_response(&ohci->card, &response);
1147 }
1148
1149 static void handle_local_lock(struct fw_ohci *ohci,
1150                               struct fw_packet *packet, u32 csr)
1151 {
1152         struct fw_packet response;
1153         int tcode, length, ext_tcode, sel;
1154         __be32 *payload, lock_old;
1155         u32 lock_arg, lock_data;
1156
1157         tcode = HEADER_GET_TCODE(packet->header[0]);
1158         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1159         payload = packet->payload;
1160         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1161
1162         if (tcode == TCODE_LOCK_REQUEST &&
1163             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1164                 lock_arg = be32_to_cpu(payload[0]);
1165                 lock_data = be32_to_cpu(payload[1]);
1166         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1167                 lock_arg = 0;
1168                 lock_data = 0;
1169         } else {
1170                 fw_fill_response(&response, packet->header,
1171                                  RCODE_TYPE_ERROR, NULL, 0);
1172                 goto out;
1173         }
1174
1175         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1176         reg_write(ohci, OHCI1394_CSRData, lock_data);
1177         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1178         reg_write(ohci, OHCI1394_CSRControl, sel);
1179
1180         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1181                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1182         else
1183                 fw_notify("swap not done yet\n");
1184
1185         fw_fill_response(&response, packet->header,
1186                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1187  out:
1188         fw_core_handle_response(&ohci->card, &response);
1189 }
1190
1191 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1192 {
1193         u64 offset;
1194         u32 csr;
1195
1196         if (ctx == &ctx->ohci->at_request_ctx) {
1197                 packet->ack = ACK_PENDING;
1198                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1199         }
1200
1201         offset =
1202                 ((unsigned long long)
1203                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1204                 packet->header[2];
1205         csr = offset - CSR_REGISTER_BASE;
1206
1207         /* Handle config rom reads. */
1208         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1209                 handle_local_rom(ctx->ohci, packet, csr);
1210         else switch (csr) {
1211         case CSR_BUS_MANAGER_ID:
1212         case CSR_BANDWIDTH_AVAILABLE:
1213         case CSR_CHANNELS_AVAILABLE_HI:
1214         case CSR_CHANNELS_AVAILABLE_LO:
1215                 handle_local_lock(ctx->ohci, packet, csr);
1216                 break;
1217         default:
1218                 if (ctx == &ctx->ohci->at_request_ctx)
1219                         fw_core_handle_request(&ctx->ohci->card, packet);
1220                 else
1221                         fw_core_handle_response(&ctx->ohci->card, packet);
1222                 break;
1223         }
1224
1225         if (ctx == &ctx->ohci->at_response_ctx) {
1226                 packet->ack = ACK_COMPLETE;
1227                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1228         }
1229 }
1230
1231 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1232 {
1233         unsigned long flags;
1234         int ret;
1235
1236         spin_lock_irqsave(&ctx->ohci->lock, flags);
1237
1238         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1239             ctx->ohci->generation == packet->generation) {
1240                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1241                 handle_local_request(ctx, packet);
1242                 return;
1243         }
1244
1245         ret = at_context_queue_packet(ctx, packet);
1246         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1247
1248         if (ret < 0)
1249                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1250
1251 }
1252
1253 static void bus_reset_tasklet(unsigned long data)
1254 {
1255         struct fw_ohci *ohci = (struct fw_ohci *)data;
1256         int self_id_count, i, j, reg;
1257         int generation, new_generation;
1258         unsigned long flags;
1259         void *free_rom = NULL;
1260         dma_addr_t free_rom_bus = 0;
1261
1262         reg = reg_read(ohci, OHCI1394_NodeID);
1263         if (!(reg & OHCI1394_NodeID_idValid)) {
1264                 fw_notify("node ID not valid, new bus reset in progress\n");
1265                 return;
1266         }
1267         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1268                 fw_notify("malconfigured bus\n");
1269                 return;
1270         }
1271         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1272                                OHCI1394_NodeID_nodeNumber);
1273
1274         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1275         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1276                 fw_notify("inconsistent self IDs\n");
1277                 return;
1278         }
1279         /*
1280          * The count in the SelfIDCount register is the number of
1281          * bytes in the self ID receive buffer.  Since we also receive
1282          * the inverted quadlets and a header quadlet, we shift one
1283          * bit extra to get the actual number of self IDs.
1284          */
1285         self_id_count = (reg >> 3) & 0xff;
1286         if (self_id_count == 0 || self_id_count > 252) {
1287                 fw_notify("inconsistent self IDs\n");
1288                 return;
1289         }
1290         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1291         rmb();
1292
1293         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1294                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1295                         fw_notify("inconsistent self IDs\n");
1296                         return;
1297                 }
1298                 ohci->self_id_buffer[j] =
1299                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1300         }
1301         rmb();
1302
1303         /*
1304          * Check the consistency of the self IDs we just read.  The
1305          * problem we face is that a new bus reset can start while we
1306          * read out the self IDs from the DMA buffer. If this happens,
1307          * the DMA buffer will be overwritten with new self IDs and we
1308          * will read out inconsistent data.  The OHCI specification
1309          * (section 11.2) recommends a technique similar to
1310          * linux/seqlock.h, where we remember the generation of the
1311          * self IDs in the buffer before reading them out and compare
1312          * it to the current generation after reading them out.  If
1313          * the two generations match we know we have a consistent set
1314          * of self IDs.
1315          */
1316
1317         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1318         if (new_generation != generation) {
1319                 fw_notify("recursive bus reset detected, "
1320                           "discarding self ids\n");
1321                 return;
1322         }
1323
1324         /* FIXME: Document how the locking works. */
1325         spin_lock_irqsave(&ohci->lock, flags);
1326
1327         ohci->generation = generation;
1328         context_stop(&ohci->at_request_ctx);
1329         context_stop(&ohci->at_response_ctx);
1330         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1331
1332         if (ohci->bus_reset_packet_quirk)
1333                 ohci->request_generation = generation;
1334
1335         /*
1336          * This next bit is unrelated to the AT context stuff but we
1337          * have to do it under the spinlock also.  If a new config rom
1338          * was set up before this reset, the old one is now no longer
1339          * in use and we can free it. Update the config rom pointers
1340          * to point to the current config rom and clear the
1341          * next_config_rom pointer so a new udpate can take place.
1342          */
1343
1344         if (ohci->next_config_rom != NULL) {
1345                 if (ohci->next_config_rom != ohci->config_rom) {
1346                         free_rom      = ohci->config_rom;
1347                         free_rom_bus  = ohci->config_rom_bus;
1348                 }
1349                 ohci->config_rom      = ohci->next_config_rom;
1350                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1351                 ohci->next_config_rom = NULL;
1352
1353                 /*
1354                  * Restore config_rom image and manually update
1355                  * config_rom registers.  Writing the header quadlet
1356                  * will indicate that the config rom is ready, so we
1357                  * do that last.
1358                  */
1359                 reg_write(ohci, OHCI1394_BusOptions,
1360                           be32_to_cpu(ohci->config_rom[2]));
1361                 ohci->config_rom[0] = ohci->next_header;
1362                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1363                           be32_to_cpu(ohci->next_header));
1364         }
1365
1366 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1367         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1368         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1369 #endif
1370
1371         spin_unlock_irqrestore(&ohci->lock, flags);
1372
1373         if (free_rom)
1374                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1375                                   free_rom, free_rom_bus);
1376
1377         log_selfids(ohci->node_id, generation,
1378                     self_id_count, ohci->self_id_buffer);
1379
1380         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1381                                  self_id_count, ohci->self_id_buffer);
1382 }
1383
1384 static irqreturn_t irq_handler(int irq, void *data)
1385 {
1386         struct fw_ohci *ohci = data;
1387         u32 event, iso_event, cycle_time;
1388         int i;
1389
1390         event = reg_read(ohci, OHCI1394_IntEventClear);
1391
1392         if (!event || !~event)
1393                 return IRQ_NONE;
1394
1395         /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1396         reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1397         log_irqs(event);
1398
1399         if (event & OHCI1394_selfIDComplete)
1400                 tasklet_schedule(&ohci->bus_reset_tasklet);
1401
1402         if (event & OHCI1394_RQPkt)
1403                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1404
1405         if (event & OHCI1394_RSPkt)
1406                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1407
1408         if (event & OHCI1394_reqTxComplete)
1409                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1410
1411         if (event & OHCI1394_respTxComplete)
1412                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1413
1414         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1415         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1416
1417         while (iso_event) {
1418                 i = ffs(iso_event) - 1;
1419                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1420                 iso_event &= ~(1 << i);
1421         }
1422
1423         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1424         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1425
1426         while (iso_event) {
1427                 i = ffs(iso_event) - 1;
1428                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1429                 iso_event &= ~(1 << i);
1430         }
1431
1432         if (unlikely(event & OHCI1394_regAccessFail))
1433                 fw_error("Register access failure - "
1434                          "please notify linux1394-devel@lists.sf.net\n");
1435
1436         if (unlikely(event & OHCI1394_postedWriteErr))
1437                 fw_error("PCI posted write error\n");
1438
1439         if (unlikely(event & OHCI1394_cycleTooLong)) {
1440                 if (printk_ratelimit())
1441                         fw_notify("isochronous cycle too long\n");
1442                 reg_write(ohci, OHCI1394_LinkControlSet,
1443                           OHCI1394_LinkControl_cycleMaster);
1444         }
1445
1446         if (unlikely(event & OHCI1394_cycleInconsistent)) {
1447                 /*
1448                  * We need to clear this event bit in order to make
1449                  * cycleMatch isochronous I/O work.  In theory we should
1450                  * stop active cycleMatch iso contexts now and restart
1451                  * them at least two cycles later.  (FIXME?)
1452                  */
1453                 if (printk_ratelimit())
1454                         fw_notify("isochronous cycle inconsistent\n");
1455         }
1456
1457         if (event & OHCI1394_cycle64Seconds) {
1458                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1459                 if ((cycle_time & 0x80000000) == 0)
1460                         atomic_inc(&ohci->bus_seconds);
1461         }
1462
1463         return IRQ_HANDLED;
1464 }
1465
1466 static int software_reset(struct fw_ohci *ohci)
1467 {
1468         int i;
1469
1470         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1471
1472         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1473                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1474                      OHCI1394_HCControl_softReset) == 0)
1475                         return 0;
1476                 msleep(1);
1477         }
1478
1479         return -EBUSY;
1480 }
1481
1482 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1483 {
1484         size_t size = length * 4;
1485
1486         memcpy(dest, src, size);
1487         if (size < CONFIG_ROM_SIZE)
1488                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1489 }
1490
1491 static int ohci_enable(struct fw_card *card,
1492                        const __be32 *config_rom, size_t length)
1493 {
1494         struct fw_ohci *ohci = fw_ohci(card);
1495         struct pci_dev *dev = to_pci_dev(card->device);
1496         u32 lps;
1497         int i;
1498
1499         if (software_reset(ohci)) {
1500                 fw_error("Failed to reset ohci card.\n");
1501                 return -EBUSY;
1502         }
1503
1504         /*
1505          * Now enable LPS, which we need in order to start accessing
1506          * most of the registers.  In fact, on some cards (ALI M5251),
1507          * accessing registers in the SClk domain without LPS enabled
1508          * will lock up the machine.  Wait 50msec to make sure we have
1509          * full link enabled.  However, with some cards (well, at least
1510          * a JMicron PCIe card), we have to try again sometimes.
1511          */
1512         reg_write(ohci, OHCI1394_HCControlSet,
1513                   OHCI1394_HCControl_LPS |
1514                   OHCI1394_HCControl_postedWriteEnable);
1515         flush_writes(ohci);
1516
1517         for (lps = 0, i = 0; !lps && i < 3; i++) {
1518                 msleep(50);
1519                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1520                       OHCI1394_HCControl_LPS;
1521         }
1522
1523         if (!lps) {
1524                 fw_error("Failed to set Link Power Status\n");
1525                 return -EIO;
1526         }
1527
1528         reg_write(ohci, OHCI1394_HCControlClear,
1529                   OHCI1394_HCControl_noByteSwapData);
1530
1531         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1532         reg_write(ohci, OHCI1394_LinkControlClear,
1533                   OHCI1394_LinkControl_rcvPhyPkt);
1534         reg_write(ohci, OHCI1394_LinkControlSet,
1535                   OHCI1394_LinkControl_rcvSelfID |
1536                   OHCI1394_LinkControl_cycleTimerEnable |
1537                   OHCI1394_LinkControl_cycleMaster);
1538
1539         reg_write(ohci, OHCI1394_ATRetries,
1540                   OHCI1394_MAX_AT_REQ_RETRIES |
1541                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1542                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1543
1544         ar_context_run(&ohci->ar_request_ctx);
1545         ar_context_run(&ohci->ar_response_ctx);
1546
1547         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1548         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1549         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1550         reg_write(ohci, OHCI1394_IntMaskSet,
1551                   OHCI1394_selfIDComplete |
1552                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1553                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1554                   OHCI1394_isochRx | OHCI1394_isochTx |
1555                   OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1556                   OHCI1394_cycleInconsistent |
1557                   OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1558                   OHCI1394_masterIntEnable);
1559         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1560                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1561
1562         /* Activate link_on bit and contender bit in our self ID packets.*/
1563         if (ohci_update_phy_reg(card, 4, 0,
1564                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1565                 return -EIO;
1566
1567         /*
1568          * When the link is not yet enabled, the atomic config rom
1569          * update mechanism described below in ohci_set_config_rom()
1570          * is not active.  We have to update ConfigRomHeader and
1571          * BusOptions manually, and the write to ConfigROMmap takes
1572          * effect immediately.  We tie this to the enabling of the
1573          * link, so we have a valid config rom before enabling - the
1574          * OHCI requires that ConfigROMhdr and BusOptions have valid
1575          * values before enabling.
1576          *
1577          * However, when the ConfigROMmap is written, some controllers
1578          * always read back quadlets 0 and 2 from the config rom to
1579          * the ConfigRomHeader and BusOptions registers on bus reset.
1580          * They shouldn't do that in this initial case where the link
1581          * isn't enabled.  This means we have to use the same
1582          * workaround here, setting the bus header to 0 and then write
1583          * the right values in the bus reset tasklet.
1584          */
1585
1586         if (config_rom) {
1587                 ohci->next_config_rom =
1588                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1589                                            &ohci->next_config_rom_bus,
1590                                            GFP_KERNEL);
1591                 if (ohci->next_config_rom == NULL)
1592                         return -ENOMEM;
1593
1594                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1595         } else {
1596                 /*
1597                  * In the suspend case, config_rom is NULL, which
1598                  * means that we just reuse the old config rom.
1599                  */
1600                 ohci->next_config_rom = ohci->config_rom;
1601                 ohci->next_config_rom_bus = ohci->config_rom_bus;
1602         }
1603
1604         ohci->next_header = ohci->next_config_rom[0];
1605         ohci->next_config_rom[0] = 0;
1606         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1607         reg_write(ohci, OHCI1394_BusOptions,
1608                   be32_to_cpu(ohci->next_config_rom[2]));
1609         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1610
1611         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1612
1613         if (request_irq(dev->irq, irq_handler,
1614                         IRQF_SHARED, ohci_driver_name, ohci)) {
1615                 fw_error("Failed to allocate shared interrupt %d.\n",
1616                          dev->irq);
1617                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1618                                   ohci->config_rom, ohci->config_rom_bus);
1619                 return -EIO;
1620         }
1621
1622         reg_write(ohci, OHCI1394_HCControlSet,
1623                   OHCI1394_HCControl_linkEnable |
1624                   OHCI1394_HCControl_BIBimageValid);
1625         flush_writes(ohci);
1626
1627         /*
1628          * We are ready to go, initiate bus reset to finish the
1629          * initialization.
1630          */
1631
1632         fw_core_initiate_bus_reset(&ohci->card, 1);
1633
1634         return 0;
1635 }
1636
1637 static int ohci_set_config_rom(struct fw_card *card,
1638                                const __be32 *config_rom, size_t length)
1639 {
1640         struct fw_ohci *ohci;
1641         unsigned long flags;
1642         int ret = -EBUSY;
1643         __be32 *next_config_rom;
1644         dma_addr_t uninitialized_var(next_config_rom_bus);
1645
1646         ohci = fw_ohci(card);
1647
1648         /*
1649          * When the OHCI controller is enabled, the config rom update
1650          * mechanism is a bit tricky, but easy enough to use.  See
1651          * section 5.5.6 in the OHCI specification.
1652          *
1653          * The OHCI controller caches the new config rom address in a
1654          * shadow register (ConfigROMmapNext) and needs a bus reset
1655          * for the changes to take place.  When the bus reset is
1656          * detected, the controller loads the new values for the
1657          * ConfigRomHeader and BusOptions registers from the specified
1658          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1659          * shadow register. All automatically and atomically.
1660          *
1661          * Now, there's a twist to this story.  The automatic load of
1662          * ConfigRomHeader and BusOptions doesn't honor the
1663          * noByteSwapData bit, so with a be32 config rom, the
1664          * controller will load be32 values in to these registers
1665          * during the atomic update, even on litte endian
1666          * architectures.  The workaround we use is to put a 0 in the
1667          * header quadlet; 0 is endian agnostic and means that the
1668          * config rom isn't ready yet.  In the bus reset tasklet we
1669          * then set up the real values for the two registers.
1670          *
1671          * We use ohci->lock to avoid racing with the code that sets
1672          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1673          */
1674
1675         next_config_rom =
1676                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1677                                    &next_config_rom_bus, GFP_KERNEL);
1678         if (next_config_rom == NULL)
1679                 return -ENOMEM;
1680
1681         spin_lock_irqsave(&ohci->lock, flags);
1682
1683         if (ohci->next_config_rom == NULL) {
1684                 ohci->next_config_rom = next_config_rom;
1685                 ohci->next_config_rom_bus = next_config_rom_bus;
1686
1687                 copy_config_rom(ohci->next_config_rom, config_rom, length);
1688
1689                 ohci->next_header = config_rom[0];
1690                 ohci->next_config_rom[0] = 0;
1691
1692                 reg_write(ohci, OHCI1394_ConfigROMmap,
1693                           ohci->next_config_rom_bus);
1694                 ret = 0;
1695         }
1696
1697         spin_unlock_irqrestore(&ohci->lock, flags);
1698
1699         /*
1700          * Now initiate a bus reset to have the changes take
1701          * effect. We clean up the old config rom memory and DMA
1702          * mappings in the bus reset tasklet, since the OHCI
1703          * controller could need to access it before the bus reset
1704          * takes effect.
1705          */
1706         if (ret == 0)
1707                 fw_core_initiate_bus_reset(&ohci->card, 1);
1708         else
1709                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1710                                   next_config_rom, next_config_rom_bus);
1711
1712         return ret;
1713 }
1714
1715 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1716 {
1717         struct fw_ohci *ohci = fw_ohci(card);
1718
1719         at_context_transmit(&ohci->at_request_ctx, packet);
1720 }
1721
1722 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1723 {
1724         struct fw_ohci *ohci = fw_ohci(card);
1725
1726         at_context_transmit(&ohci->at_response_ctx, packet);
1727 }
1728
1729 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1730 {
1731         struct fw_ohci *ohci = fw_ohci(card);
1732         struct context *ctx = &ohci->at_request_ctx;
1733         struct driver_data *driver_data = packet->driver_data;
1734         int ret = -ENOENT;
1735
1736         tasklet_disable(&ctx->tasklet);
1737
1738         if (packet->ack != 0)
1739                 goto out;
1740
1741         if (packet->payload_mapped)
1742                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1743                                  packet->payload_length, DMA_TO_DEVICE);
1744
1745         log_ar_at_event('T', packet->speed, packet->header, 0x20);
1746         driver_data->packet = NULL;
1747         packet->ack = RCODE_CANCELLED;
1748         packet->callback(packet, &ohci->card, packet->ack);
1749         ret = 0;
1750  out:
1751         tasklet_enable(&ctx->tasklet);
1752
1753         return ret;
1754 }
1755
1756 static int ohci_enable_phys_dma(struct fw_card *card,
1757                                 int node_id, int generation)
1758 {
1759 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1760         return 0;
1761 #else
1762         struct fw_ohci *ohci = fw_ohci(card);
1763         unsigned long flags;
1764         int n, ret = 0;
1765
1766         /*
1767          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1768          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1769          */
1770
1771         spin_lock_irqsave(&ohci->lock, flags);
1772
1773         if (ohci->generation != generation) {
1774                 ret = -ESTALE;
1775                 goto out;
1776         }
1777
1778         /*
1779          * Note, if the node ID contains a non-local bus ID, physical DMA is
1780          * enabled for _all_ nodes on remote buses.
1781          */
1782
1783         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1784         if (n < 32)
1785                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1786         else
1787                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1788
1789         flush_writes(ohci);
1790  out:
1791         spin_unlock_irqrestore(&ohci->lock, flags);
1792
1793         return ret;
1794 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1795 }
1796
1797 static u64 ohci_get_bus_time(struct fw_card *card)
1798 {
1799         struct fw_ohci *ohci = fw_ohci(card);
1800         u32 cycle_time;
1801         u64 bus_time;
1802
1803         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1804         bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1805
1806         return bus_time;
1807 }
1808
1809 static void copy_iso_headers(struct iso_context *ctx, void *p)
1810 {
1811         int i = ctx->header_length;
1812
1813         if (i + ctx->base.header_size > PAGE_SIZE)
1814                 return;
1815
1816         /*
1817          * The iso header is byteswapped to little endian by
1818          * the controller, but the remaining header quadlets
1819          * are big endian.  We want to present all the headers
1820          * as big endian, so we have to swap the first quadlet.
1821          */
1822         if (ctx->base.header_size > 0)
1823                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1824         if (ctx->base.header_size > 4)
1825                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1826         if (ctx->base.header_size > 8)
1827                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1828         ctx->header_length += ctx->base.header_size;
1829 }
1830
1831 static int handle_ir_dualbuffer_packet(struct context *context,
1832                                        struct descriptor *d,
1833                                        struct descriptor *last)
1834 {
1835         struct iso_context *ctx =
1836                 container_of(context, struct iso_context, context);
1837         struct db_descriptor *db = (struct db_descriptor *) d;
1838         __le32 *ir_header;
1839         size_t header_length;
1840         void *p, *end;
1841
1842         if (db->first_res_count != 0 && db->second_res_count != 0) {
1843                 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1844                         /* This descriptor isn't done yet, stop iteration. */
1845                         return 0;
1846                 }
1847                 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1848         }
1849
1850         header_length = le16_to_cpu(db->first_req_count) -
1851                 le16_to_cpu(db->first_res_count);
1852
1853         p = db + 1;
1854         end = p + header_length;
1855         while (p < end) {
1856                 copy_iso_headers(ctx, p);
1857                 ctx->excess_bytes +=
1858                         (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1859                 p += max(ctx->base.header_size, (size_t)8);
1860         }
1861
1862         ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1863                 le16_to_cpu(db->second_res_count);
1864
1865         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1866                 ir_header = (__le32 *) (db + 1);
1867                 ctx->base.callback(&ctx->base,
1868                                    le32_to_cpu(ir_header[0]) & 0xffff,
1869                                    ctx->header_length, ctx->header,
1870                                    ctx->base.callback_data);
1871                 ctx->header_length = 0;
1872         }
1873
1874         return 1;
1875 }
1876
1877 static int handle_ir_packet_per_buffer(struct context *context,
1878                                        struct descriptor *d,
1879                                        struct descriptor *last)
1880 {
1881         struct iso_context *ctx =
1882                 container_of(context, struct iso_context, context);
1883         struct descriptor *pd;
1884         __le32 *ir_header;
1885         void *p;
1886
1887         for (pd = d; pd <= last; pd++) {
1888                 if (pd->transfer_status)
1889                         break;
1890         }
1891         if (pd > last)
1892                 /* Descriptor(s) not done yet, stop iteration */
1893                 return 0;
1894
1895         p = last + 1;
1896         copy_iso_headers(ctx, p);
1897
1898         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1899                 ir_header = (__le32 *) p;
1900                 ctx->base.callback(&ctx->base,
1901                                    le32_to_cpu(ir_header[0]) & 0xffff,
1902                                    ctx->header_length, ctx->header,
1903                                    ctx->base.callback_data);
1904                 ctx->header_length = 0;
1905         }
1906
1907         return 1;
1908 }
1909
1910 static int handle_it_packet(struct context *context,
1911                             struct descriptor *d,
1912                             struct descriptor *last)
1913 {
1914         struct iso_context *ctx =
1915                 container_of(context, struct iso_context, context);
1916         int i;
1917         struct descriptor *pd;
1918
1919         for (pd = d; pd <= last; pd++)
1920                 if (pd->transfer_status)
1921                         break;
1922         if (pd > last)
1923                 /* Descriptor(s) not done yet, stop iteration */
1924                 return 0;
1925
1926         i = ctx->header_length;
1927         if (i + 4 < PAGE_SIZE) {
1928                 /* Present this value as big-endian to match the receive code */
1929                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1930                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1931                                 le16_to_cpu(pd->res_count));
1932                 ctx->header_length += 4;
1933         }
1934         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1935                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1936                                    ctx->header_length, ctx->header,
1937                                    ctx->base.callback_data);
1938                 ctx->header_length = 0;
1939         }
1940         return 1;
1941 }
1942
1943 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1944                                 int type, int channel, size_t header_size)
1945 {
1946         struct fw_ohci *ohci = fw_ohci(card);
1947         struct iso_context *ctx, *list;
1948         descriptor_callback_t callback;
1949         u64 *channels, dont_care = ~0ULL;
1950         u32 *mask, regs;
1951         unsigned long flags;
1952         int index, ret = -ENOMEM;
1953
1954         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1955                 channels = &dont_care;
1956                 mask = &ohci->it_context_mask;
1957                 list = ohci->it_context_list;
1958                 callback = handle_it_packet;
1959         } else {
1960                 channels = &ohci->ir_context_channels;
1961                 mask = &ohci->ir_context_mask;
1962                 list = ohci->ir_context_list;
1963                 if (ohci->use_dualbuffer)
1964                         callback = handle_ir_dualbuffer_packet;
1965                 else
1966                         callback = handle_ir_packet_per_buffer;
1967         }
1968
1969         spin_lock_irqsave(&ohci->lock, flags);
1970         index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1971         if (index >= 0) {
1972                 *channels &= ~(1ULL << channel);
1973                 *mask &= ~(1 << index);
1974         }
1975         spin_unlock_irqrestore(&ohci->lock, flags);
1976
1977         if (index < 0)
1978                 return ERR_PTR(-EBUSY);
1979
1980         if (type == FW_ISO_CONTEXT_TRANSMIT)
1981                 regs = OHCI1394_IsoXmitContextBase(index);
1982         else
1983                 regs = OHCI1394_IsoRcvContextBase(index);
1984
1985         ctx = &list[index];
1986         memset(ctx, 0, sizeof(*ctx));
1987         ctx->header_length = 0;
1988         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1989         if (ctx->header == NULL)
1990                 goto out;
1991
1992         ret = context_init(&ctx->context, ohci, regs, callback);
1993         if (ret < 0)
1994                 goto out_with_header;
1995
1996         return &ctx->base;
1997
1998  out_with_header:
1999         free_page((unsigned long)ctx->header);
2000  out:
2001         spin_lock_irqsave(&ohci->lock, flags);
2002         *mask |= 1 << index;
2003         spin_unlock_irqrestore(&ohci->lock, flags);
2004
2005         return ERR_PTR(ret);
2006 }
2007
2008 static int ohci_start_iso(struct fw_iso_context *base,
2009                           s32 cycle, u32 sync, u32 tags)
2010 {
2011         struct iso_context *ctx = container_of(base, struct iso_context, base);
2012         struct fw_ohci *ohci = ctx->context.ohci;
2013         u32 control, match;
2014         int index;
2015
2016         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2017                 index = ctx - ohci->it_context_list;
2018                 match = 0;
2019                 if (cycle >= 0)
2020                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2021                                 (cycle & 0x7fff) << 16;
2022
2023                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2024                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2025                 context_run(&ctx->context, match);
2026         } else {
2027                 index = ctx - ohci->ir_context_list;
2028                 control = IR_CONTEXT_ISOCH_HEADER;
2029                 if (ohci->use_dualbuffer)
2030                         control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2031                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2032                 if (cycle >= 0) {
2033                         match |= (cycle & 0x07fff) << 12;
2034                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2035                 }
2036
2037                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2038                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2039                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2040                 context_run(&ctx->context, control);
2041         }
2042
2043         return 0;
2044 }
2045
2046 static int ohci_stop_iso(struct fw_iso_context *base)
2047 {
2048         struct fw_ohci *ohci = fw_ohci(base->card);
2049         struct iso_context *ctx = container_of(base, struct iso_context, base);
2050         int index;
2051
2052         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2053                 index = ctx - ohci->it_context_list;
2054                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2055         } else {
2056                 index = ctx - ohci->ir_context_list;
2057                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2058         }
2059         flush_writes(ohci);
2060         context_stop(&ctx->context);
2061
2062         return 0;
2063 }
2064
2065 static void ohci_free_iso_context(struct fw_iso_context *base)
2066 {
2067         struct fw_ohci *ohci = fw_ohci(base->card);
2068         struct iso_context *ctx = container_of(base, struct iso_context, base);
2069         unsigned long flags;
2070         int index;
2071
2072         ohci_stop_iso(base);
2073         context_release(&ctx->context);
2074         free_page((unsigned long)ctx->header);
2075
2076         spin_lock_irqsave(&ohci->lock, flags);
2077
2078         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2079                 index = ctx - ohci->it_context_list;
2080                 ohci->it_context_mask |= 1 << index;
2081         } else {
2082                 index = ctx - ohci->ir_context_list;
2083                 ohci->ir_context_mask |= 1 << index;
2084                 ohci->ir_context_channels |= 1ULL << base->channel;
2085         }
2086
2087         spin_unlock_irqrestore(&ohci->lock, flags);
2088 }
2089
2090 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2091                                    struct fw_iso_packet *packet,
2092                                    struct fw_iso_buffer *buffer,
2093                                    unsigned long payload)
2094 {
2095         struct iso_context *ctx = container_of(base, struct iso_context, base);
2096         struct descriptor *d, *last, *pd;
2097         struct fw_iso_packet *p;
2098         __le32 *header;
2099         dma_addr_t d_bus, page_bus;
2100         u32 z, header_z, payload_z, irq;
2101         u32 payload_index, payload_end_index, next_page_index;
2102         int page, end_page, i, length, offset;
2103
2104         /*
2105          * FIXME: Cycle lost behavior should be configurable: lose
2106          * packet, retransmit or terminate..
2107          */
2108
2109         p = packet;
2110         payload_index = payload;
2111
2112         if (p->skip)
2113                 z = 1;
2114         else
2115                 z = 2;
2116         if (p->header_length > 0)
2117                 z++;
2118
2119         /* Determine the first page the payload isn't contained in. */
2120         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2121         if (p->payload_length > 0)
2122                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2123         else
2124                 payload_z = 0;
2125
2126         z += payload_z;
2127
2128         /* Get header size in number of descriptors. */
2129         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2130
2131         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2132         if (d == NULL)
2133                 return -ENOMEM;
2134
2135         if (!p->skip) {
2136                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2137                 d[0].req_count = cpu_to_le16(8);
2138
2139                 header = (__le32 *) &d[1];
2140                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2141                                         IT_HEADER_TAG(p->tag) |
2142                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2143                                         IT_HEADER_CHANNEL(ctx->base.channel) |
2144                                         IT_HEADER_SPEED(ctx->base.speed));
2145                 header[1] =
2146                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2147                                                           p->payload_length));
2148         }
2149
2150         if (p->header_length > 0) {
2151                 d[2].req_count    = cpu_to_le16(p->header_length);
2152                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2153                 memcpy(&d[z], p->header, p->header_length);
2154         }
2155
2156         pd = d + z - payload_z;
2157         payload_end_index = payload_index + p->payload_length;
2158         for (i = 0; i < payload_z; i++) {
2159                 page               = payload_index >> PAGE_SHIFT;
2160                 offset             = payload_index & ~PAGE_MASK;
2161                 next_page_index    = (page + 1) << PAGE_SHIFT;
2162                 length             =
2163                         min(next_page_index, payload_end_index) - payload_index;
2164                 pd[i].req_count    = cpu_to_le16(length);
2165
2166                 page_bus = page_private(buffer->pages[page]);
2167                 pd[i].data_address = cpu_to_le32(page_bus + offset);
2168
2169                 payload_index += length;
2170         }
2171
2172         if (p->interrupt)
2173                 irq = DESCRIPTOR_IRQ_ALWAYS;
2174         else
2175                 irq = DESCRIPTOR_NO_IRQ;
2176
2177         last = z == 2 ? d : d + z - 1;
2178         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2179                                      DESCRIPTOR_STATUS |
2180                                      DESCRIPTOR_BRANCH_ALWAYS |
2181                                      irq);
2182
2183         context_append(&ctx->context, d, z, header_z);
2184
2185         return 0;
2186 }
2187
2188 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2189                                              struct fw_iso_packet *packet,
2190                                              struct fw_iso_buffer *buffer,
2191                                              unsigned long payload)
2192 {
2193         struct iso_context *ctx = container_of(base, struct iso_context, base);
2194         struct db_descriptor *db = NULL;
2195         struct descriptor *d;
2196         struct fw_iso_packet *p;
2197         dma_addr_t d_bus, page_bus;
2198         u32 z, header_z, length, rest;
2199         int page, offset, packet_count, header_size;
2200
2201         /*
2202          * FIXME: Cycle lost behavior should be configurable: lose
2203          * packet, retransmit or terminate..
2204          */
2205
2206         p = packet;
2207         z = 2;
2208
2209         /*
2210          * The OHCI controller puts the isochronous header and trailer in the
2211          * buffer, so we need at least 8 bytes.
2212          */
2213         packet_count = p->header_length / ctx->base.header_size;
2214         header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2215
2216         /* Get header size in number of descriptors. */
2217         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2218         page     = payload >> PAGE_SHIFT;
2219         offset   = payload & ~PAGE_MASK;
2220         rest     = p->payload_length;
2221         /*
2222          * The controllers I've tested have not worked correctly when
2223          * second_req_count is zero.  Rather than do something we know won't
2224          * work, return an error
2225          */
2226         if (rest == 0)
2227                 return -EINVAL;
2228
2229         while (rest > 0) {
2230                 d = context_get_descriptors(&ctx->context,
2231                                             z + header_z, &d_bus);
2232                 if (d == NULL)
2233                         return -ENOMEM;
2234
2235                 db = (struct db_descriptor *) d;
2236                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2237                                           DESCRIPTOR_BRANCH_ALWAYS);
2238                 db->first_size =
2239                     cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2240                 if (p->skip && rest == p->payload_length) {
2241                         db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2242                         db->first_req_count = db->first_size;
2243                 } else {
2244                         db->first_req_count = cpu_to_le16(header_size);
2245                 }
2246                 db->first_res_count = db->first_req_count;
2247                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2248
2249                 if (p->skip && rest == p->payload_length)
2250                         length = 4;
2251                 else if (offset + rest < PAGE_SIZE)
2252                         length = rest;
2253                 else
2254                         length = PAGE_SIZE - offset;
2255
2256                 db->second_req_count = cpu_to_le16(length);
2257                 db->second_res_count = db->second_req_count;
2258                 page_bus = page_private(buffer->pages[page]);
2259                 db->second_buffer = cpu_to_le32(page_bus + offset);
2260
2261                 if (p->interrupt && length == rest)
2262                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2263
2264                 context_append(&ctx->context, d, z, header_z);
2265                 offset = (offset + length) & ~PAGE_MASK;
2266                 rest -= length;
2267                 if (offset == 0)
2268                         page++;
2269         }
2270
2271         return 0;
2272 }
2273
2274 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2275                                         struct fw_iso_packet *packet,
2276                                         struct fw_iso_buffer *buffer,
2277                                         unsigned long payload)
2278 {
2279         struct iso_context *ctx = container_of(base, struct iso_context, base);
2280         struct descriptor *d, *pd;
2281         struct fw_iso_packet *p = packet;
2282         dma_addr_t d_bus, page_bus;
2283         u32 z, header_z, rest;
2284         int i, j, length;
2285         int page, offset, packet_count, header_size, payload_per_buffer;
2286
2287         /*
2288          * The OHCI controller puts the isochronous header and trailer in the
2289          * buffer, so we need at least 8 bytes.
2290          */
2291         packet_count = p->header_length / ctx->base.header_size;
2292         header_size  = max(ctx->base.header_size, (size_t)8);
2293
2294         /* Get header size in number of descriptors. */
2295         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2296         page     = payload >> PAGE_SHIFT;
2297         offset   = payload & ~PAGE_MASK;
2298         payload_per_buffer = p->payload_length / packet_count;
2299
2300         for (i = 0; i < packet_count; i++) {
2301                 /* d points to the header descriptor */
2302                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2303                 d = context_get_descriptors(&ctx->context,
2304                                 z + header_z, &d_bus);
2305                 if (d == NULL)
2306                         return -ENOMEM;
2307
2308                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
2309                                               DESCRIPTOR_INPUT_MORE);
2310                 if (p->skip && i == 0)
2311                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2312                 d->req_count    = cpu_to_le16(header_size);
2313                 d->res_count    = d->req_count;
2314                 d->transfer_status = 0;
2315                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2316
2317                 rest = payload_per_buffer;
2318                 pd = d;
2319                 for (j = 1; j < z; j++) {
2320                         pd++;
2321                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2322                                                   DESCRIPTOR_INPUT_MORE);
2323
2324                         if (offset + rest < PAGE_SIZE)
2325                                 length = rest;
2326                         else
2327                                 length = PAGE_SIZE - offset;
2328                         pd->req_count = cpu_to_le16(length);
2329                         pd->res_count = pd->req_count;
2330                         pd->transfer_status = 0;
2331
2332                         page_bus = page_private(buffer->pages[page]);
2333                         pd->data_address = cpu_to_le32(page_bus + offset);
2334
2335                         offset = (offset + length) & ~PAGE_MASK;
2336                         rest -= length;
2337                         if (offset == 0)
2338                                 page++;
2339                 }
2340                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2341                                           DESCRIPTOR_INPUT_LAST |
2342                                           DESCRIPTOR_BRANCH_ALWAYS);
2343                 if (p->interrupt && i == packet_count - 1)
2344                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2345
2346                 context_append(&ctx->context, d, z, header_z);
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int ohci_queue_iso(struct fw_iso_context *base,
2353                           struct fw_iso_packet *packet,
2354                           struct fw_iso_buffer *buffer,
2355                           unsigned long payload)
2356 {
2357         struct iso_context *ctx = container_of(base, struct iso_context, base);
2358         unsigned long flags;
2359         int ret;
2360
2361         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2362         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2363                 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2364         else if (ctx->context.ohci->use_dualbuffer)
2365                 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2366                                                         buffer, payload);
2367         else
2368                 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2369                                                         buffer, payload);
2370         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2371
2372         return ret;
2373 }
2374
2375 static const struct fw_card_driver ohci_driver = {
2376         .enable                 = ohci_enable,
2377         .update_phy_reg         = ohci_update_phy_reg,
2378         .set_config_rom         = ohci_set_config_rom,
2379         .send_request           = ohci_send_request,
2380         .send_response          = ohci_send_response,
2381         .cancel_packet          = ohci_cancel_packet,
2382         .enable_phys_dma        = ohci_enable_phys_dma,
2383         .get_bus_time           = ohci_get_bus_time,
2384
2385         .allocate_iso_context   = ohci_allocate_iso_context,
2386         .free_iso_context       = ohci_free_iso_context,
2387         .queue_iso              = ohci_queue_iso,
2388         .start_iso              = ohci_start_iso,
2389         .stop_iso               = ohci_stop_iso,
2390 };
2391
2392 #ifdef CONFIG_PPC_PMAC
2393 static void ohci_pmac_on(struct pci_dev *dev)
2394 {
2395         if (machine_is(powermac)) {
2396                 struct device_node *ofn = pci_device_to_OF_node(dev);
2397
2398                 if (ofn) {
2399                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2400                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2401                 }
2402         }
2403 }
2404
2405 static void ohci_pmac_off(struct pci_dev *dev)
2406 {
2407         if (machine_is(powermac)) {
2408                 struct device_node *ofn = pci_device_to_OF_node(dev);
2409
2410                 if (ofn) {
2411                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2412                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2413                 }
2414         }
2415 }
2416 #else
2417 #define ohci_pmac_on(dev)
2418 #define ohci_pmac_off(dev)
2419 #endif /* CONFIG_PPC_PMAC */
2420
2421 #define PCI_VENDOR_ID_AGERE             PCI_VENDOR_ID_ATT
2422 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
2423
2424 static int __devinit pci_probe(struct pci_dev *dev,
2425                                const struct pci_device_id *ent)
2426 {
2427         struct fw_ohci *ohci;
2428         u32 bus_options, max_receive, link_speed, version;
2429         u64 guid;
2430         int err;
2431         size_t size;
2432
2433         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2434         if (ohci == NULL) {
2435                 err = -ENOMEM;
2436                 goto fail;
2437         }
2438
2439         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2440
2441         ohci_pmac_on(dev);
2442
2443         err = pci_enable_device(dev);
2444         if (err) {
2445                 fw_error("Failed to enable OHCI hardware\n");
2446                 goto fail_free;
2447         }
2448
2449         pci_set_master(dev);
2450         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2451         pci_set_drvdata(dev, ohci);
2452
2453         spin_lock_init(&ohci->lock);
2454
2455         tasklet_init(&ohci->bus_reset_tasklet,
2456                      bus_reset_tasklet, (unsigned long)ohci);
2457
2458         err = pci_request_region(dev, 0, ohci_driver_name);
2459         if (err) {
2460                 fw_error("MMIO resource unavailable\n");
2461                 goto fail_disable;
2462         }
2463
2464         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2465         if (ohci->registers == NULL) {
2466                 fw_error("Failed to remap registers\n");
2467                 err = -ENXIO;
2468                 goto fail_iomem;
2469         }
2470
2471         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2472 #if 0
2473         /* FIXME: make it a context option or remove dual-buffer mode */
2474         ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2475 #endif
2476
2477         /* dual-buffer mode is broken if more than one IR context is active */
2478         if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2479             dev->device == PCI_DEVICE_ID_AGERE_FW643)
2480                 ohci->use_dualbuffer = false;
2481
2482         /* dual-buffer mode is broken */
2483         if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2484             dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2485                 ohci->use_dualbuffer = false;
2486
2487 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2488 #if !defined(CONFIG_X86_32)
2489         /* dual-buffer mode is broken with descriptor addresses above 2G */
2490         if (dev->vendor == PCI_VENDOR_ID_TI &&
2491             dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2492                 ohci->use_dualbuffer = false;
2493 #endif
2494
2495 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2496         ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2497                              dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2498 #endif
2499         ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2500
2501         ar_context_init(&ohci->ar_request_ctx, ohci,
2502                         OHCI1394_AsReqRcvContextControlSet);
2503
2504         ar_context_init(&ohci->ar_response_ctx, ohci,
2505                         OHCI1394_AsRspRcvContextControlSet);
2506
2507         context_init(&ohci->at_request_ctx, ohci,
2508                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2509
2510         context_init(&ohci->at_response_ctx, ohci,
2511                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2512
2513         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2514         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2515         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2516         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2517         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2518
2519         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2520         ohci->ir_context_channels = ~0ULL;
2521         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2522         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2523         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2524         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2525
2526         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2527                 err = -ENOMEM;
2528                 goto fail_contexts;
2529         }
2530
2531         /* self-id dma buffer allocation */
2532         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2533                                                SELF_ID_BUF_SIZE,
2534                                                &ohci->self_id_bus,
2535                                                GFP_KERNEL);
2536         if (ohci->self_id_cpu == NULL) {
2537                 err = -ENOMEM;
2538                 goto fail_contexts;
2539         }
2540
2541         bus_options = reg_read(ohci, OHCI1394_BusOptions);
2542         max_receive = (bus_options >> 12) & 0xf;
2543         link_speed = bus_options & 0x7;
2544         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2545                 reg_read(ohci, OHCI1394_GUIDLo);
2546
2547         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2548         if (err)
2549                 goto fail_self_id;
2550
2551         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2552                   dev_name(&dev->dev), version >> 16, version & 0xff);
2553
2554         return 0;
2555
2556  fail_self_id:
2557         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2558                           ohci->self_id_cpu, ohci->self_id_bus);
2559  fail_contexts:
2560         kfree(ohci->ir_context_list);
2561         kfree(ohci->it_context_list);
2562         context_release(&ohci->at_response_ctx);
2563         context_release(&ohci->at_request_ctx);
2564         ar_context_release(&ohci->ar_response_ctx);
2565         ar_context_release(&ohci->ar_request_ctx);
2566         pci_iounmap(dev, ohci->registers);
2567  fail_iomem:
2568         pci_release_region(dev, 0);
2569  fail_disable:
2570         pci_disable_device(dev);
2571  fail_free:
2572         kfree(&ohci->card);
2573         ohci_pmac_off(dev);
2574  fail:
2575         if (err == -ENOMEM)
2576                 fw_error("Out of memory\n");
2577
2578         return err;
2579 }
2580
2581 static void pci_remove(struct pci_dev *dev)
2582 {
2583         struct fw_ohci *ohci;
2584
2585         ohci = pci_get_drvdata(dev);
2586         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2587         flush_writes(ohci);
2588         fw_core_remove_card(&ohci->card);
2589
2590         /*
2591          * FIXME: Fail all pending packets here, now that the upper
2592          * layers can't queue any more.
2593          */
2594
2595         software_reset(ohci);
2596         free_irq(dev->irq, ohci);
2597
2598         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2599                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2600                                   ohci->next_config_rom, ohci->next_config_rom_bus);
2601         if (ohci->config_rom)
2602                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2603                                   ohci->config_rom, ohci->config_rom_bus);
2604         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2605                           ohci->self_id_cpu, ohci->self_id_bus);
2606         ar_context_release(&ohci->ar_request_ctx);
2607         ar_context_release(&ohci->ar_response_ctx);
2608         context_release(&ohci->at_request_ctx);
2609         context_release(&ohci->at_response_ctx);
2610         kfree(ohci->it_context_list);
2611         kfree(ohci->ir_context_list);
2612         pci_iounmap(dev, ohci->registers);
2613         pci_release_region(dev, 0);
2614         pci_disable_device(dev);
2615         kfree(&ohci->card);
2616         ohci_pmac_off(dev);
2617
2618         fw_notify("Removed fw-ohci device.\n");
2619 }
2620
2621 #ifdef CONFIG_PM
2622 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2623 {
2624         struct fw_ohci *ohci = pci_get_drvdata(dev);
2625         int err;
2626
2627         software_reset(ohci);
2628         free_irq(dev->irq, ohci);
2629         err = pci_save_state(dev);
2630         if (err) {
2631                 fw_error("pci_save_state failed\n");
2632                 return err;
2633         }
2634         err = pci_set_power_state(dev, pci_choose_state(dev, state));
2635         if (err)
2636                 fw_error("pci_set_power_state failed with %d\n", err);
2637         ohci_pmac_off(dev);
2638
2639         return 0;
2640 }
2641
2642 static int pci_resume(struct pci_dev *dev)
2643 {
2644         struct fw_ohci *ohci = pci_get_drvdata(dev);
2645         int err;
2646
2647         ohci_pmac_on(dev);
2648         pci_set_power_state(dev, PCI_D0);
2649         pci_restore_state(dev);
2650         err = pci_enable_device(dev);
2651         if (err) {
2652                 fw_error("pci_enable_device failed\n");
2653                 return err;
2654         }
2655
2656         return ohci_enable(&ohci->card, NULL, 0);
2657 }
2658 #endif
2659
2660 static struct pci_device_id pci_table[] = {
2661         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2662         { }
2663 };
2664
2665 MODULE_DEVICE_TABLE(pci, pci_table);
2666
2667 static struct pci_driver fw_ohci_pci_driver = {
2668         .name           = ohci_driver_name,
2669         .id_table       = pci_table,
2670         .probe          = pci_probe,
2671         .remove         = pci_remove,
2672 #ifdef CONFIG_PM
2673         .resume         = pci_resume,
2674         .suspend        = pci_suspend,
2675 #endif
2676 };
2677
2678 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2679 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2680 MODULE_LICENSE("GPL");
2681
2682 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2683 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2684 MODULE_ALIAS("ohci1394");
2685 #endif
2686
2687 static int __init fw_ohci_init(void)
2688 {
2689         return pci_register_driver(&fw_ohci_pci_driver);
2690 }
2691
2692 static void __exit fw_ohci_cleanup(void)
2693 {
2694         pci_unregister_driver(&fw_ohci_pci_driver);
2695 }
2696
2697 module_init(fw_ohci_init);
2698 module_exit(fw_ohci_cleanup);