drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/pci.h>
  26 #include <linux/delay.h>
  27 #include <linux/poll.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/mm.h>
  30
  31 #include <asm/uaccess.h>
  32 #include <asm/semaphore.h>
  33
  34 #include "fw-transaction.h"
  35 #include "fw-ohci.h"
  36
  37 #define DESCRIPTOR_OUTPUT_MORE          0
  38 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  39 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  40 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  41 #define DESCRIPTOR_STATUS               (1 << 11)
  42 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  43 #define DESCRIPTOR_PING                 (1 << 7)
  44 #define DESCRIPTOR_YY                   (1 << 6)
  45 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  46 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  47 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  48 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  49 #define DESCRIPTOR_WAIT                 (3 << 0)
  50
  51 struct descriptor {
  52         __le16 req_count;
  53         __le16 control;
  54         __le32 data_address;
  55         __le32 branch_address;
  56         __le16 res_count;
  57         __le16 transfer_status;
  58 } __attribute__((aligned(16)));
  59
  60 struct db_descriptor {
  61         __le16 first_size;
  62         __le16 control;
  63         __le16 second_req_count;
  64         __le16 first_req_count;
  65         __le32 branch_address;
  66         __le16 second_res_count;
  67         __le16 first_res_count;
  68         __le32 reserved0;
  69         __le32 first_buffer;
  70         __le32 second_buffer;
  71         __le32 reserved1;
  72 } __attribute__((aligned(16)));
  73
  74 #define CONTROL_SET(regs)       (regs)
  75 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  76 #define COMMAND_PTR(regs)       ((regs) + 12)
  77 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  78
  79 struct ar_buffer {
  80         struct descriptor descriptor;
  81         struct ar_buffer *next;
  82         __le32 data[0];
  83 };
  84
  85 struct ar_context {
  86         struct fw_ohci *ohci;
  87         struct ar_buffer *current_buffer;
  88         struct ar_buffer *last_buffer;
  89         void *pointer;
  90         u32 regs;
  91         struct tasklet_struct tasklet;
  92 };
  93
  94 struct context;
  95
  96 typedef int (*descriptor_callback_t)(struct context *ctx,
  97                                      struct descriptor *d,
  98                                      struct descriptor *last);
  99 struct context {
 100         struct fw_ohci *ohci;
 101         u32 regs;
 102
 103         struct descriptor *buffer;
 104         dma_addr_t buffer_bus;
 105         size_t buffer_size;
 106         struct descriptor *head_descriptor;
 107         struct descriptor *tail_descriptor;
 108         struct descriptor *tail_descriptor_last;
 109         struct descriptor *prev_descriptor;
 110
 111         descriptor_callback_t callback;
 112
 113         struct tasklet_struct tasklet;
 114 };
 115
 116 #define IT_HEADER_SY(v)          ((v) <<  0)
 117 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 118 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 119 #define IT_HEADER_TAG(v)         ((v) << 14)
 120 #define IT_HEADER_SPEED(v)       ((v) << 16)
 121 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 122
 123 struct iso_context {
 124         struct fw_iso_context base;
 125         struct context context;
 126         void *header;
 127         size_t header_length;
 128 };
 129
 130 #define CONFIG_ROM_SIZE 1024
 131
 132 struct fw_ohci {
 133         struct fw_card card;
 134
 135         u32 version;
 136         __iomem char *registers;
 137         dma_addr_t self_id_bus;
 138         __le32 *self_id_cpu;
 139         struct tasklet_struct bus_reset_tasklet;
 140         int node_id;
 141         int generation;
 142         int request_generation;
 143         u32 bus_seconds;
 144
 145         /*
 146          * Spinlock for accessing fw_ohci data.  Never call out of
 147          * this driver with this lock held.
 148          */
 149         spinlock_t lock;
 150         u32 self_id_buffer[512];
 151
 152         /* Config rom buffers */
 153         __be32 *config_rom;
 154         dma_addr_t config_rom_bus;
 155         __be32 *next_config_rom;
 156         dma_addr_t next_config_rom_bus;
 157         u32 next_header;
 158
 159         struct ar_context ar_request_ctx;
 160         struct ar_context ar_response_ctx;
 161         struct context at_request_ctx;
 162         struct context at_response_ctx;
 163
 164         u32 it_context_mask;
 165         struct iso_context *it_context_list;
 166         u32 ir_context_mask;
 167         struct iso_context *ir_context_list;
 168 };
 169
 170 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 171 {
 172         return container_of(card, struct fw_ohci, card);
 173 }
 174
 175 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 176 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 177 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 178 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 179 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 180 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 181
 182 #define CONTEXT_RUN     0x8000
 183 #define CONTEXT_WAKE    0x1000
 184 #define CONTEXT_DEAD    0x0800
 185 #define CONTEXT_ACTIVE  0x0400
 186
 187 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 188 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 189 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 190
 191 #define FW_OHCI_MAJOR                   240
 192 #define OHCI1394_REGISTER_SIZE          0x800
 193 #define OHCI_LOOP_COUNT                 500
 194 #define OHCI1394_PCI_HCI_Control        0x40
 195 #define SELF_ID_BUF_SIZE                0x800
 196 #define OHCI_TCODE_PHY_PACKET           0x0e
 197 #define OHCI_VERSION_1_1                0x010010
 198 #define ISO_BUFFER_SIZE                 (64 * 1024)
 199 #define AT_BUFFER_SIZE                  4096
 200
 201 static char ohci_driver_name[] = KBUILD_MODNAME;
 202
 203 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 204 {
 205         writel(data, ohci->registers + offset);
 206 }
 207
 208 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 209 {
 210         return readl(ohci->registers + offset);
 211 }
 212
 213 static inline void flush_writes(const struct fw_ohci *ohci)
 214 {
 215         /* Do a dummy read to flush writes. */
 216         reg_read(ohci, OHCI1394_Version);
 217 }
 218
 219 static int
 220 ohci_update_phy_reg(struct fw_card *card, int addr,
 221                     int clear_bits, int set_bits)
 222 {
 223         struct fw_ohci *ohci = fw_ohci(card);
 224         u32 val, old;
 225
 226         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 227         msleep(2);
 228         val = reg_read(ohci, OHCI1394_PhyControl);
 229         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 230                 fw_error("failed to set phy reg bits.\n");
 231                 return -EBUSY;
 232         }
 233
 234         old = OHCI1394_PhyControl_ReadData(val);
 235         old = (old & ~clear_bits) | set_bits;
 236         reg_write(ohci, OHCI1394_PhyControl,
 237                   OHCI1394_PhyControl_Write(addr, old));
 238
 239         return 0;
 240 }
 241
 242 static int ar_context_add_page(struct ar_context *ctx)
 243 {
 244         struct device *dev = ctx->ohci->card.device;
 245         struct ar_buffer *ab;
 246         dma_addr_t ab_bus;
 247         size_t offset;
 248
 249         ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
 250         if (ab == NULL)
 251                 return -ENOMEM;
 252
 253         ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
 254         if (dma_mapping_error(ab_bus)) {
 255                 free_page((unsigned long) ab);
 256                 return -ENOMEM;
 257         }
 258
 259         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 260         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 261                                                     DESCRIPTOR_STATUS |
 262                                                     DESCRIPTOR_BRANCH_ALWAYS);
 263         offset = offsetof(struct ar_buffer, data);
 264         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 265         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 266         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 267         ab->descriptor.branch_address = 0;
 268
 269         dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 270
 271         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 272         ctx->last_buffer->next = ab;
 273         ctx->last_buffer = ab;
 274
 275         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 276         flush_writes(ctx->ohci);
 277
 278         return 0;
 279 }
 280
 281 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 282 {
 283         struct fw_ohci *ohci = ctx->ohci;
 284         struct fw_packet p;
 285         u32 status, length, tcode;
 286
 287         p.header[0] = le32_to_cpu(buffer[0]);
 288         p.header[1] = le32_to_cpu(buffer[1]);
 289         p.header[2] = le32_to_cpu(buffer[2]);
 290
 291         tcode = (p.header[0] >> 4) & 0x0f;
 292         switch (tcode) {
 293         case TCODE_WRITE_QUADLET_REQUEST:
 294         case TCODE_READ_QUADLET_RESPONSE:
 295                 p.header[3] = (__force __u32) buffer[3];
 296                 p.header_length = 16;
 297                 p.payload_length = 0;
 298                 break;
 299
 300         case TCODE_READ_BLOCK_REQUEST :
 301                 p.header[3] = le32_to_cpu(buffer[3]);
 302                 p.header_length = 16;
 303                 p.payload_length = 0;
 304                 break;
 305
 306         case TCODE_WRITE_BLOCK_REQUEST:
 307         case TCODE_READ_BLOCK_RESPONSE:
 308         case TCODE_LOCK_REQUEST:
 309         case TCODE_LOCK_RESPONSE:
 310                 p.header[3] = le32_to_cpu(buffer[3]);
 311                 p.header_length = 16;
 312                 p.payload_length = p.header[3] >> 16;
 313                 break;
 314
 315         case TCODE_WRITE_RESPONSE:
 316         case TCODE_READ_QUADLET_REQUEST:
 317         case OHCI_TCODE_PHY_PACKET:
 318                 p.header_length = 12;
 319                 p.payload_length = 0;
 320                 break;
 321         }
 322
 323         p.payload = (void *) buffer + p.header_length;
 324
 325         /* FIXME: What to do about evt_* errors? */
 326         length = (p.header_length + p.payload_length + 3) / 4;
 327         status = le32_to_cpu(buffer[length]);
 328
 329         p.ack        = ((status >> 16) & 0x1f) - 16;
 330         p.speed      = (status >> 21) & 0x7;
 331         p.timestamp  = status & 0xffff;
 332         p.generation = ohci->request_generation;
 333
 334         /*
 335          * The OHCI bus reset handler synthesizes a phy packet with
 336          * the new generation number when a bus reset happens (see
 337          * section 8.4.2.3).  This helps us determine when a request
 338          * was received and make sure we send the response in the same
 339          * generation.  We only need this for requests; for responses
 340          * we use the unique tlabel for finding the matching
 341          * request.
 342          */
 343
 344         if (p.ack + 16 == 0x09)
 345                 ohci->request_generation = (buffer[2] >> 16) & 0xff;
 346         else if (ctx == &ohci->ar_request_ctx)
 347                 fw_core_handle_request(&ohci->card, &p);
 348         else
 349                 fw_core_handle_response(&ohci->card, &p);
 350
 351         return buffer + length + 1;
 352 }
 353
 354 static void ar_context_tasklet(unsigned long data)
 355 {
 356         struct ar_context *ctx = (struct ar_context *)data;
 357         struct fw_ohci *ohci = ctx->ohci;
 358         struct ar_buffer *ab;
 359         struct descriptor *d;
 360         void *buffer, *end;
 361
 362         ab = ctx->current_buffer;
 363         d = &ab->descriptor;
 364
 365         if (d->res_count == 0) {
 366                 size_t size, rest, offset;
 367
 368                 /*
 369                  * This descriptor is finished and we may have a
 370                  * packet split across this and the next buffer. We
 371                  * reuse the page for reassembling the split packet.
 372                  */
 373
 374                 offset = offsetof(struct ar_buffer, data);
 375                 dma_unmap_single(ohci->card.device,
 376                                  ab->descriptor.data_address - offset,
 377                                  PAGE_SIZE, DMA_BIDIRECTIONAL);
 378
 379                 buffer = ab;
 380                 ab = ab->next;
 381                 d = &ab->descriptor;
 382                 size = buffer + PAGE_SIZE - ctx->pointer;
 383                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 384                 memmove(buffer, ctx->pointer, size);
 385                 memcpy(buffer + size, ab->data, rest);
 386                 ctx->current_buffer = ab;
 387                 ctx->pointer = (void *) ab->data + rest;
 388                 end = buffer + size + rest;
 389
 390                 while (buffer < end)
 391                         buffer = handle_ar_packet(ctx, buffer);
 392
 393                 free_page((unsigned long)buffer);
 394                 ar_context_add_page(ctx);
 395         } else {
 396                 buffer = ctx->pointer;
 397                 ctx->pointer = end =
 398                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 399
 400                 while (buffer < end)
 401                         buffer = handle_ar_packet(ctx, buffer);
 402         }
 403 }
 404
 405 static int
 406 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 407 {
 408         struct ar_buffer ab;
 409
 410         ctx->regs        = regs;
 411         ctx->ohci        = ohci;
 412         ctx->last_buffer = &ab;
 413         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 414
 415         ar_context_add_page(ctx);
 416         ar_context_add_page(ctx);
 417         ctx->current_buffer = ab.next;
 418         ctx->pointer = ctx->current_buffer->data;
 419
 420         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs),
 421                   le32_to_cpu(ab.descriptor.branch_address));
 422         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 423         flush_writes(ctx->ohci);
 424
 425         return 0;
 426 }
 427
 428 static void context_tasklet(unsigned long data)
 429 {
 430         struct context *ctx = (struct context *) data;
 431         struct fw_ohci *ohci = ctx->ohci;
 432         struct descriptor *d, *last;
 433         u32 address;
 434         int z;
 435
 436         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
 437                                 ctx->buffer_size, DMA_TO_DEVICE);
 438
 439         d    = ctx->tail_descriptor;
 440         last = ctx->tail_descriptor_last;
 441
 442         while (last->branch_address != 0) {
 443                 address = le32_to_cpu(last->branch_address);
 444                 z = address & 0xf;
 445                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
 446                 last = (z == 2) ? d : d + z - 1;
 447
 448                 if (!ctx->callback(ctx, d, last))
 449                         break;
 450
 451                 ctx->tail_descriptor      = d;
 452                 ctx->tail_descriptor_last = last;
 453         }
 454 }
 455
 456 static int
 457 context_init(struct context *ctx, struct fw_ohci *ohci,
 458              size_t buffer_size, u32 regs,
 459              descriptor_callback_t callback)
 460 {
 461         ctx->ohci = ohci;
 462         ctx->regs = regs;
 463         ctx->buffer_size = buffer_size;
 464         ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
 465         if (ctx->buffer == NULL)
 466                 return -ENOMEM;
 467
 468         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 469         ctx->callback = callback;
 470
 471         ctx->buffer_bus =
 472                 dma_map_single(ohci->card.device, ctx->buffer,
 473                                buffer_size, DMA_TO_DEVICE);
 474         if (dma_mapping_error(ctx->buffer_bus)) {
 475                 kfree(ctx->buffer);
 476                 return -ENOMEM;
 477         }
 478
 479         ctx->head_descriptor      = ctx->buffer;
 480         ctx->prev_descriptor      = ctx->buffer;
 481         ctx->tail_descriptor      = ctx->buffer;
 482         ctx->tail_descriptor_last = ctx->buffer;
 483
 484         /*
 485          * We put a dummy descriptor in the buffer that has a NULL
 486          * branch address and looks like it's been sent.  That way we
 487          * have a descriptor to append DMA programs to.  Also, the
 488          * ring buffer invariant is that it always has at least one
 489          * element so that head == tail means buffer full.
 490          */
 491
 492         memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
 493         ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 494         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
 495         ctx->head_descriptor++;
 496
 497         return 0;
 498 }
 499
 500 static void
 501 context_release(struct context *ctx)
 502 {
 503         struct fw_card *card = &ctx->ohci->card;
 504
 505         dma_unmap_single(card->device, ctx->buffer_bus,
 506                          ctx->buffer_size, DMA_TO_DEVICE);
 507         kfree(ctx->buffer);
 508 }
 509
 510 static struct descriptor *
 511 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 512 {
 513         struct descriptor *d, *tail, *end;
 514
 515         d = ctx->head_descriptor;
 516         tail = ctx->tail_descriptor;
 517         end = ctx->buffer + ctx->buffer_size / sizeof(*d);
 518
 519         if (d + z <= tail) {
 520                 goto has_space;
 521         } else if (d > tail && d + z <= end) {
 522                 goto has_space;
 523         } else if (d > tail && ctx->buffer + z <= tail) {
 524                 d = ctx->buffer;
 525                 goto has_space;
 526         }
 527
 528         return NULL;
 529
 530  has_space:
 531         memset(d, 0, z * sizeof(*d));
 532         *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 533
 534         return d;
 535 }
 536
 537 static void context_run(struct context *ctx, u32 extra)
 538 {
 539         struct fw_ohci *ohci = ctx->ohci;
 540
 541         reg_write(ohci, COMMAND_PTR(ctx->regs),
 542                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
 543         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 544         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 545         flush_writes(ohci);
 546 }
 547
 548 static void context_append(struct context *ctx,
 549                            struct descriptor *d, int z, int extra)
 550 {
 551         dma_addr_t d_bus;
 552
 553         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 554
 555         ctx->head_descriptor = d + z + extra;
 556         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
 557         ctx->prev_descriptor = z == 2 ? d : d + z - 1;
 558
 559         dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
 560                                    ctx->buffer_size, DMA_TO_DEVICE);
 561
 562         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 563         flush_writes(ctx->ohci);
 564 }
 565
 566 static void context_stop(struct context *ctx)
 567 {
 568         u32 reg;
 569         int i;
 570
 571         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 572         flush_writes(ctx->ohci);
 573
 574         for (i = 0; i < 10; i++) {
 575                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 576                 if ((reg & CONTEXT_ACTIVE) == 0)
 577                         break;
 578
 579                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 580                 msleep(1);
 581         }
 582 }
 583
 584 struct driver_data {
 585         struct fw_packet *packet;
 586 };
 587
 588 /*
 589  * This function apppends a packet to the DMA queue for transmission.
 590  * Must always be called with the ochi->lock held to ensure proper
 591  * generation handling and locking around packet queue manipulation.
 592  */
 593 static int
 594 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 595 {
 596         struct fw_ohci *ohci = ctx->ohci;
 597         dma_addr_t d_bus, payload_bus;
 598         struct driver_data *driver_data;
 599         struct descriptor *d, *last;
 600         __le32 *header;
 601         int z, tcode;
 602         u32 reg;
 603
 604         d = context_get_descriptors(ctx, 4, &d_bus);
 605         if (d == NULL) {
 606                 packet->ack = RCODE_SEND_ERROR;
 607                 return -1;
 608         }
 609
 610         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 611         d[0].res_count = cpu_to_le16(packet->timestamp);
 612
 613         /*
 614          * The DMA format for asyncronous link packets is different
 615          * from the IEEE1394 layout, so shift the fields around
 616          * accordingly.  If header_length is 8, it's a PHY packet, to
 617          * which we need to prepend an extra quadlet.
 618          */
 619
 620         header = (__le32 *) &d[1];
 621         if (packet->header_length > 8) {
 622                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 623                                         (packet->speed << 16));
 624                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 625                                         (packet->header[0] & 0xffff0000));
 626                 header[2] = cpu_to_le32(packet->header[2]);
 627
 628                 tcode = (packet->header[0] >> 4) & 0x0f;
 629                 if (TCODE_IS_BLOCK_PACKET(tcode))
 630                         header[3] = cpu_to_le32(packet->header[3]);
 631                 else
 632                         header[3] = (__force __le32) packet->header[3];
 633
 634                 d[0].req_count = cpu_to_le16(packet->header_length);
 635         } else {
 636                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 637                                         (packet->speed << 16));
 638                 header[1] = cpu_to_le32(packet->header[0]);
 639                 header[2] = cpu_to_le32(packet->header[1]);
 640                 d[0].req_count = cpu_to_le16(12);
 641         }
 642
 643         driver_data = (struct driver_data *) &d[3];
 644         driver_data->packet = packet;
 645         packet->driver_data = driver_data;
 646
 647         if (packet->payload_length > 0) {
 648                 payload_bus =
 649                         dma_map_single(ohci->card.device, packet->payload,
 650                                        packet->payload_length, DMA_TO_DEVICE);
 651                 if (dma_mapping_error(payload_bus)) {
 652                         packet->ack = RCODE_SEND_ERROR;
 653                         return -1;
 654                 }
 655
 656                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 657                 d[2].data_address = cpu_to_le32(payload_bus);
 658                 last = &d[2];
 659                 z = 3;
 660         } else {
 661                 last = &d[0];
 662                 z = 2;
 663         }
 664
 665         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 666                                      DESCRIPTOR_IRQ_ALWAYS |
 667                                      DESCRIPTOR_BRANCH_ALWAYS);
 668
 669         /* FIXME: Document how the locking works. */
 670         if (ohci->generation != packet->generation) {
 671                 packet->ack = RCODE_GENERATION;
 672                 return -1;
 673         }
 674
 675         context_append(ctx, d, z, 4 - z);
 676
 677         /* If the context isn't already running, start it up. */
 678         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 679         if ((reg & CONTEXT_RUN) == 0)
 680                 context_run(ctx, 0);
 681
 682         return 0;
 683 }
 684
 685 static int handle_at_packet(struct context *context,
 686                             struct descriptor *d,
 687                             struct descriptor *last)
 688 {
 689         struct driver_data *driver_data;
 690         struct fw_packet *packet;
 691         struct fw_ohci *ohci = context->ohci;
 692         dma_addr_t payload_bus;
 693         int evt;
 694
 695         if (last->transfer_status == 0)
 696                 /* This descriptor isn't done yet, stop iteration. */
 697                 return 0;
 698
 699         driver_data = (struct driver_data *) &d[3];
 700         packet = driver_data->packet;
 701         if (packet == NULL)
 702                 /* This packet was cancelled, just continue. */
 703                 return 1;
 704
 705         payload_bus = le32_to_cpu(last->data_address);
 706         if (payload_bus != 0)
 707                 dma_unmap_single(ohci->card.device, payload_bus,
 708                                  packet->payload_length, DMA_TO_DEVICE);
 709
 710         evt = le16_to_cpu(last->transfer_status) & 0x1f;
 711         packet->timestamp = le16_to_cpu(last->res_count);
 712
 713         switch (evt) {
 714         case OHCI1394_evt_timeout:
 715                 /* Async response transmit timed out. */
 716                 packet->ack = RCODE_CANCELLED;
 717                 break;
 718
 719         case OHCI1394_evt_flushed:
 720                 /*
 721                  * The packet was flushed should give same error as
 722                  * when we try to use a stale generation count.
 723                  */
 724                 packet->ack = RCODE_GENERATION;
 725                 break;
 726
 727         case OHCI1394_evt_missing_ack:
 728                 /*
 729                  * Using a valid (current) generation count, but the
 730                  * node is not on the bus or not sending acks.
 731                  */
 732                 packet->ack = RCODE_NO_ACK;
 733                 break;
 734
 735         case ACK_COMPLETE + 0x10:
 736         case ACK_PENDING + 0x10:
 737         case ACK_BUSY_X + 0x10:
 738         case ACK_BUSY_A + 0x10:
 739         case ACK_BUSY_B + 0x10:
 740         case ACK_DATA_ERROR + 0x10:
 741         case ACK_TYPE_ERROR + 0x10:
 742                 packet->ack = evt - 0x10;
 743                 break;
 744
 745         default:
 746                 packet->ack = RCODE_SEND_ERROR;
 747                 break;
 748         }
 749
 750         packet->callback(packet, &ohci->card, packet->ack);
 751
 752         return 1;
 753 }
 754
 755 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
 756 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
 757 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
 758 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
 759 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
 760
 761 static void
 762 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 763 {
 764         struct fw_packet response;
 765         int tcode, length, i;
 766
 767         tcode = HEADER_GET_TCODE(packet->header[0]);
 768         if (TCODE_IS_BLOCK_PACKET(tcode))
 769                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 770         else
 771                 length = 4;
 772
 773         i = csr - CSR_CONFIG_ROM;
 774         if (i + length > CONFIG_ROM_SIZE) {
 775                 fw_fill_response(&response, packet->header,
 776                                  RCODE_ADDRESS_ERROR, NULL, 0);
 777         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
 778                 fw_fill_response(&response, packet->header,
 779                                  RCODE_TYPE_ERROR, NULL, 0);
 780         } else {
 781                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
 782                                  (void *) ohci->config_rom + i, length);
 783         }
 784
 785         fw_core_handle_response(&ohci->card, &response);
 786 }
 787
 788 static void
 789 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 790 {
 791         struct fw_packet response;
 792         int tcode, length, ext_tcode, sel;
 793         __be32 *payload, lock_old;
 794         u32 lock_arg, lock_data;
 795
 796         tcode = HEADER_GET_TCODE(packet->header[0]);
 797         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 798         payload = packet->payload;
 799         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
 800
 801         if (tcode == TCODE_LOCK_REQUEST &&
 802             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
 803                 lock_arg = be32_to_cpu(payload[0]);
 804                 lock_data = be32_to_cpu(payload[1]);
 805         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
 806                 lock_arg = 0;
 807                 lock_data = 0;
 808         } else {
 809                 fw_fill_response(&response, packet->header,
 810                                  RCODE_TYPE_ERROR, NULL, 0);
 811                 goto out;
 812         }
 813
 814         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 815         reg_write(ohci, OHCI1394_CSRData, lock_data);
 816         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 817         reg_write(ohci, OHCI1394_CSRControl, sel);
 818
 819         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
 820                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
 821         else
 822                 fw_notify("swap not done yet\n");
 823
 824         fw_fill_response(&response, packet->header,
 825                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
 826  out:
 827         fw_core_handle_response(&ohci->card, &response);
 828 }
 829
 830 static void
 831 handle_local_request(struct context *ctx, struct fw_packet *packet)
 832 {
 833         u64 offset;
 834         u32 csr;
 835
 836         if (ctx == &ctx->ohci->at_request_ctx) {
 837                 packet->ack = ACK_PENDING;
 838                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 839         }
 840
 841         offset =
 842                 ((unsigned long long)
 843                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
 844                 packet->header[2];
 845         csr = offset - CSR_REGISTER_BASE;
 846
 847         /* Handle config rom reads. */
 848         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
 849                 handle_local_rom(ctx->ohci, packet, csr);
 850         else switch (csr) {
 851         case CSR_BUS_MANAGER_ID:
 852         case CSR_BANDWIDTH_AVAILABLE:
 853         case CSR_CHANNELS_AVAILABLE_HI:
 854         case CSR_CHANNELS_AVAILABLE_LO:
 855                 handle_local_lock(ctx->ohci, packet, csr);
 856                 break;
 857         default:
 858                 if (ctx == &ctx->ohci->at_request_ctx)
 859                         fw_core_handle_request(&ctx->ohci->card, packet);
 860                 else
 861                         fw_core_handle_response(&ctx->ohci->card, packet);
 862                 break;
 863         }
 864
 865         if (ctx == &ctx->ohci->at_response_ctx) {
 866                 packet->ack = ACK_COMPLETE;
 867                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 868         }
 869 }
 870
 871 static void
 872 at_context_transmit(struct context *ctx, struct fw_packet *packet)
 873 {
 874         unsigned long flags;
 875         int retval;
 876
 877         spin_lock_irqsave(&ctx->ohci->lock, flags);
 878
 879         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
 880             ctx->ohci->generation == packet->generation) {
 881                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 882                 handle_local_request(ctx, packet);
 883                 return;
 884         }
 885
 886         retval = at_context_queue_packet(ctx, packet);
 887         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 888
 889         if (retval < 0)
 890                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 891
 892 }
 893
 894 static void bus_reset_tasklet(unsigned long data)
 895 {
 896         struct fw_ohci *ohci = (struct fw_ohci *)data;
 897         int self_id_count, i, j, reg;
 898         int generation, new_generation;
 899         unsigned long flags;
 900
 901         reg = reg_read(ohci, OHCI1394_NodeID);
 902         if (!(reg & OHCI1394_NodeID_idValid)) {
 903                 fw_error("node ID not valid, new bus reset in progress\n");
 904                 return;
 905         }
 906         ohci->node_id = reg & 0xffff;
 907
 908         /*
 909          * The count in the SelfIDCount register is the number of
 910          * bytes in the self ID receive buffer.  Since we also receive
 911          * the inverted quadlets and a header quadlet, we shift one
 912          * bit extra to get the actual number of self IDs.
 913          */
 914
 915         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
 916         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 917
 918         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 919                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
 920                         fw_error("inconsistent self IDs\n");
 921                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
 922         }
 923
 924         /*
 925          * Check the consistency of the self IDs we just read.  The
 926          * problem we face is that a new bus reset can start while we
 927          * read out the self IDs from the DMA buffer. If this happens,
 928          * the DMA buffer will be overwritten with new self IDs and we
 929          * will read out inconsistent data.  The OHCI specification
 930          * (section 11.2) recommends a technique similar to
 931          * linux/seqlock.h, where we remember the generation of the
 932          * self IDs in the buffer before reading them out and compare
 933          * it to the current generation after reading them out.  If
 934          * the two generations match we know we have a consistent set
 935          * of self IDs.
 936          */
 937
 938         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 939         if (new_generation != generation) {
 940                 fw_notify("recursive bus reset detected, "
 941                           "discarding self ids\n");
 942                 return;
 943         }
 944
 945         /* FIXME: Document how the locking works. */
 946         spin_lock_irqsave(&ohci->lock, flags);
 947
 948         ohci->generation = generation;
 949         context_stop(&ohci->at_request_ctx);
 950         context_stop(&ohci->at_response_ctx);
 951         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 952
 953         /*
 954          * This next bit is unrelated to the AT context stuff but we
 955          * have to do it under the spinlock also.  If a new config rom
 956          * was set up before this reset, the old one is now no longer
 957          * in use and we can free it. Update the config rom pointers
 958          * to point to the current config rom and clear the
 959          * next_config_rom pointer so a new udpate can take place.
 960          */
 961
 962         if (ohci->next_config_rom != NULL) {
 963                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 964                                   ohci->config_rom, ohci->config_rom_bus);
 965                 ohci->config_rom      = ohci->next_config_rom;
 966                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
 967                 ohci->next_config_rom = NULL;
 968
 969                 /*
 970                  * Restore config_rom image and manually update
 971                  * config_rom registers.  Writing the header quadlet
 972                  * will indicate that the config rom is ready, so we
 973                  * do that last.
 974                  */
 975                 reg_write(ohci, OHCI1394_BusOptions,
 976                           be32_to_cpu(ohci->config_rom[2]));
 977                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
 978                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
 979         }
 980
 981         spin_unlock_irqrestore(&ohci->lock, flags);
 982
 983         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
 984                                  self_id_count, ohci->self_id_buffer);
 985 }
 986
 987 static irqreturn_t irq_handler(int irq, void *data)
 988 {
 989         struct fw_ohci *ohci = data;
 990         u32 event, iso_event, cycle_time;
 991         int i;
 992
 993         event = reg_read(ohci, OHCI1394_IntEventClear);
 994
 995         if (!event)
 996                 return IRQ_NONE;
 997
 998         reg_write(ohci, OHCI1394_IntEventClear, event);
 999
1000         if (event & OHCI1394_selfIDComplete)
1001                 tasklet_schedule(&ohci->bus_reset_tasklet);
1002
1003         if (event & OHCI1394_RQPkt)
1004                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1005
1006         if (event & OHCI1394_RSPkt)
1007                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1008
1009         if (event & OHCI1394_reqTxComplete)
1010                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1011
1012         if (event & OHCI1394_respTxComplete)
1013                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1014
1015         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1016         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1017
1018         while (iso_event) {
1019                 i = ffs(iso_event) - 1;
1020                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1021                 iso_event &= ~(1 << i);
1022         }
1023
1024         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1025         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1026
1027         while (iso_event) {
1028                 i = ffs(iso_event) - 1;
1029                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1030                 iso_event &= ~(1 << i);
1031         }
1032
1033         if (event & OHCI1394_cycle64Seconds) {
1034                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1035                 if ((cycle_time & 0x80000000) == 0)
1036                         ohci->bus_seconds++;
1037         }
1038
1039         return IRQ_HANDLED;
1040 }
1041
1042 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1043 {
1044         struct fw_ohci *ohci = fw_ohci(card);
1045         struct pci_dev *dev = to_pci_dev(card->device);
1046
1047         /*
1048          * When the link is not yet enabled, the atomic config rom
1049          * update mechanism described below in ohci_set_config_rom()
1050          * is not active.  We have to update ConfigRomHeader and
1051          * BusOptions manually, and the write to ConfigROMmap takes
1052          * effect immediately.  We tie this to the enabling of the
1053          * link, so we have a valid config rom before enabling - the
1054          * OHCI requires that ConfigROMhdr and BusOptions have valid
1055          * values before enabling.
1056          *
1057          * However, when the ConfigROMmap is written, some controllers
1058          * always read back quadlets 0 and 2 from the config rom to
1059          * the ConfigRomHeader and BusOptions registers on bus reset.
1060          * They shouldn't do that in this initial case where the link
1061          * isn't enabled.  This means we have to use the same
1062          * workaround here, setting the bus header to 0 and then write
1063          * the right values in the bus reset tasklet.
1064          */
1065
1066         ohci->next_config_rom =
1067                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1068                                    &ohci->next_config_rom_bus, GFP_KERNEL);
1069         if (ohci->next_config_rom == NULL)
1070                 return -ENOMEM;
1071
1072         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1073         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1074
1075         ohci->next_header = config_rom[0];
1076         ohci->next_config_rom[0] = 0;
1077         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1078         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1079         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1080
1081         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1082
1083         if (request_irq(dev->irq, irq_handler,
1084                         IRQF_SHARED, ohci_driver_name, ohci)) {
1085                 fw_error("Failed to allocate shared interrupt %d.\n",
1086                          dev->irq);
1087                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1088                                   ohci->config_rom, ohci->config_rom_bus);
1089                 return -EIO;
1090         }
1091
1092         reg_write(ohci, OHCI1394_HCControlSet,
1093                   OHCI1394_HCControl_linkEnable |
1094                   OHCI1394_HCControl_BIBimageValid);
1095         flush_writes(ohci);
1096
1097         /*
1098          * We are ready to go, initiate bus reset to finish the
1099          * initialization.
1100          */
1101
1102         fw_core_initiate_bus_reset(&ohci->card, 1);
1103
1104         return 0;
1105 }
1106
1107 static int
1108 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1109 {
1110         struct fw_ohci *ohci;
1111         unsigned long flags;
1112         int retval = 0;
1113         __be32 *next_config_rom;
1114         dma_addr_t next_config_rom_bus;
1115
1116         ohci = fw_ohci(card);
1117
1118         /*
1119          * When the OHCI controller is enabled, the config rom update
1120          * mechanism is a bit tricky, but easy enough to use.  See
1121          * section 5.5.6 in the OHCI specification.
1122          *
1123          * The OHCI controller caches the new config rom address in a
1124          * shadow register (ConfigROMmapNext) and needs a bus reset
1125          * for the changes to take place.  When the bus reset is
1126          * detected, the controller loads the new values for the
1127          * ConfigRomHeader and BusOptions registers from the specified
1128          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1129          * shadow register. All automatically and atomically.
1130          *
1131          * Now, there's a twist to this story.  The automatic load of
1132          * ConfigRomHeader and BusOptions doesn't honor the
1133          * noByteSwapData bit, so with a be32 config rom, the
1134          * controller will load be32 values in to these registers
1135          * during the atomic update, even on litte endian
1136          * architectures.  The workaround we use is to put a 0 in the
1137          * header quadlet; 0 is endian agnostic and means that the
1138          * config rom isn't ready yet.  In the bus reset tasklet we
1139          * then set up the real values for the two registers.
1140          *
1141          * We use ohci->lock to avoid racing with the code that sets
1142          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1143          */
1144
1145         next_config_rom =
1146                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1147                                    &next_config_rom_bus, GFP_KERNEL);
1148         if (next_config_rom == NULL)
1149                 return -ENOMEM;
1150
1151         spin_lock_irqsave(&ohci->lock, flags);
1152
1153         if (ohci->next_config_rom == NULL) {
1154                 ohci->next_config_rom = next_config_rom;
1155                 ohci->next_config_rom_bus = next_config_rom_bus;
1156
1157                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1158                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1159                                   length * 4);
1160
1161                 ohci->next_header = config_rom[0];
1162                 ohci->next_config_rom[0] = 0;
1163
1164                 reg_write(ohci, OHCI1394_ConfigROMmap,
1165                           ohci->next_config_rom_bus);
1166         } else {
1167                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1168                                   next_config_rom, next_config_rom_bus);
1169                 retval = -EBUSY;
1170         }
1171
1172         spin_unlock_irqrestore(&ohci->lock, flags);
1173
1174         /*
1175          * Now initiate a bus reset to have the changes take
1176          * effect. We clean up the old config rom memory and DMA
1177          * mappings in the bus reset tasklet, since the OHCI
1178          * controller could need to access it before the bus reset
1179          * takes effect.
1180          */
1181         if (retval == 0)
1182                 fw_core_initiate_bus_reset(&ohci->card, 1);
1183
1184         return retval;
1185 }
1186
1187 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1188 {
1189         struct fw_ohci *ohci = fw_ohci(card);
1190
1191         at_context_transmit(&ohci->at_request_ctx, packet);
1192 }
1193
1194 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1195 {
1196         struct fw_ohci *ohci = fw_ohci(card);
1197
1198         at_context_transmit(&ohci->at_response_ctx, packet);
1199 }
1200
1201 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1202 {
1203         struct fw_ohci *ohci = fw_ohci(card);
1204         struct context *ctx = &ohci->at_request_ctx;
1205         struct driver_data *driver_data = packet->driver_data;
1206         int retval = -ENOENT;
1207
1208         tasklet_disable(&ctx->tasklet);
1209
1210         if (packet->ack != 0)
1211                 goto out;
1212
1213         driver_data->packet = NULL;
1214         packet->ack = RCODE_CANCELLED;
1215         packet->callback(packet, &ohci->card, packet->ack);
1216         retval = 0;
1217
1218  out:
1219         tasklet_enable(&ctx->tasklet);
1220
1221         return retval;
1222 }
1223
1224 static int
1225 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1226 {
1227         struct fw_ohci *ohci = fw_ohci(card);
1228         unsigned long flags;
1229         int n, retval = 0;
1230
1231         /*
1232          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1233          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1234          */
1235
1236         spin_lock_irqsave(&ohci->lock, flags);
1237
1238         if (ohci->generation != generation) {
1239                 retval = -ESTALE;
1240                 goto out;
1241         }
1242
1243         /*
1244          * Note, if the node ID contains a non-local bus ID, physical DMA is
1245          * enabled for _all_ nodes on remote buses.
1246          */
1247
1248         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1249         if (n < 32)
1250                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1251         else
1252                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1253
1254         flush_writes(ohci);
1255  out:
1256         spin_unlock_irqrestore(&ohci->lock, flags);
1257         return retval;
1258 }
1259
1260 static u64
1261 ohci_get_bus_time(struct fw_card *card)
1262 {
1263         struct fw_ohci *ohci = fw_ohci(card);
1264         u32 cycle_time;
1265         u64 bus_time;
1266
1267         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1268         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1269
1270         return bus_time;
1271 }
1272
1273 static int handle_ir_dualbuffer_packet(struct context *context,
1274                                        struct descriptor *d,
1275                                        struct descriptor *last)
1276 {
1277         struct iso_context *ctx =
1278                 container_of(context, struct iso_context, context);
1279         struct db_descriptor *db = (struct db_descriptor *) d;
1280         __le32 *ir_header;
1281         size_t header_length;
1282         void *p, *end;
1283         int i;
1284
1285         if (db->first_res_count > 0 && db->second_res_count > 0)
1286                 /* This descriptor isn't done yet, stop iteration. */
1287                 return 0;
1288
1289         header_length = le16_to_cpu(db->first_req_count) -
1290                 le16_to_cpu(db->first_res_count);
1291
1292         i = ctx->header_length;
1293         p = db + 1;
1294         end = p + header_length;
1295         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1296                 /*
1297                  * The iso header is byteswapped to little endian by
1298                  * the controller, but the remaining header quadlets
1299                  * are big endian.  We want to present all the headers
1300                  * as big endian, so we have to swap the first
1301                  * quadlet.
1302                  */
1303                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1304                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1305                 i += ctx->base.header_size;
1306                 p += ctx->base.header_size + 4;
1307         }
1308
1309         ctx->header_length = i;
1310
1311         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1312                 ir_header = (__le32 *) (db + 1);
1313                 ctx->base.callback(&ctx->base,
1314                                    le32_to_cpu(ir_header[0]) & 0xffff,
1315                                    ctx->header_length, ctx->header,
1316                                    ctx->base.callback_data);
1317                 ctx->header_length = 0;
1318         }
1319
1320         return 1;
1321 }
1322
1323 static int handle_it_packet(struct context *context,
1324                             struct descriptor *d,
1325                             struct descriptor *last)
1326 {
1327         struct iso_context *ctx =
1328                 container_of(context, struct iso_context, context);
1329
1330         if (last->transfer_status == 0)
1331                 /* This descriptor isn't done yet, stop iteration. */
1332                 return 0;
1333
1334         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1335                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1336                                    0, NULL, ctx->base.callback_data);
1337
1338         return 1;
1339 }
1340
1341 static struct fw_iso_context *
1342 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1343 {
1344         struct fw_ohci *ohci = fw_ohci(card);
1345         struct iso_context *ctx, *list;
1346         descriptor_callback_t callback;
1347         u32 *mask, regs;
1348         unsigned long flags;
1349         int index, retval = -ENOMEM;
1350
1351         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1352                 mask = &ohci->it_context_mask;
1353                 list = ohci->it_context_list;
1354                 callback = handle_it_packet;
1355         } else {
1356                 mask = &ohci->ir_context_mask;
1357                 list = ohci->ir_context_list;
1358                 callback = handle_ir_dualbuffer_packet;
1359         }
1360
1361         /* FIXME: We need a fallback for pre 1.1 OHCI. */
1362         if (callback == handle_ir_dualbuffer_packet &&
1363             ohci->version < OHCI_VERSION_1_1)
1364                 return ERR_PTR(-EINVAL);
1365
1366         spin_lock_irqsave(&ohci->lock, flags);
1367         index = ffs(*mask) - 1;
1368         if (index >= 0)
1369                 *mask &= ~(1 << index);
1370         spin_unlock_irqrestore(&ohci->lock, flags);
1371
1372         if (index < 0)
1373                 return ERR_PTR(-EBUSY);
1374
1375         if (type == FW_ISO_CONTEXT_TRANSMIT)
1376                 regs = OHCI1394_IsoXmitContextBase(index);
1377         else
1378                 regs = OHCI1394_IsoRcvContextBase(index);
1379
1380         ctx = &list[index];
1381         memset(ctx, 0, sizeof(*ctx));
1382         ctx->header_length = 0;
1383         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1384         if (ctx->header == NULL)
1385                 goto out;
1386
1387         retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
1388                               regs, callback);
1389         if (retval < 0)
1390                 goto out_with_header;
1391
1392         return &ctx->base;
1393
1394  out_with_header:
1395         free_page((unsigned long)ctx->header);
1396  out:
1397         spin_lock_irqsave(&ohci->lock, flags);
1398         *mask |= 1 << index;
1399         spin_unlock_irqrestore(&ohci->lock, flags);
1400
1401         return ERR_PTR(retval);
1402 }
1403
1404 static int ohci_start_iso(struct fw_iso_context *base,
1405                           s32 cycle, u32 sync, u32 tags)
1406 {
1407         struct iso_context *ctx = container_of(base, struct iso_context, base);
1408         struct fw_ohci *ohci = ctx->context.ohci;
1409         u32 control, match;
1410         int index;
1411
1412         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1413                 index = ctx - ohci->it_context_list;
1414                 match = 0;
1415                 if (cycle >= 0)
1416                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1417                                 (cycle & 0x7fff) << 16;
1418
1419                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1420                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1421                 context_run(&ctx->context, match);
1422         } else {
1423                 index = ctx - ohci->ir_context_list;
1424                 control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
1425                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1426                 if (cycle >= 0) {
1427                         match |= (cycle & 0x07fff) << 12;
1428                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1429                 }
1430
1431                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1432                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1433                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1434                 context_run(&ctx->context, control);
1435         }
1436
1437         return 0;
1438 }
1439
1440 static int ohci_stop_iso(struct fw_iso_context *base)
1441 {
1442         struct fw_ohci *ohci = fw_ohci(base->card);
1443         struct iso_context *ctx = container_of(base, struct iso_context, base);
1444         int index;
1445
1446         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1447                 index = ctx - ohci->it_context_list;
1448                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1449         } else {
1450                 index = ctx - ohci->ir_context_list;
1451                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1452         }
1453         flush_writes(ohci);
1454         context_stop(&ctx->context);
1455
1456         return 0;
1457 }
1458
1459 static void ohci_free_iso_context(struct fw_iso_context *base)
1460 {
1461         struct fw_ohci *ohci = fw_ohci(base->card);
1462         struct iso_context *ctx = container_of(base, struct iso_context, base);
1463         unsigned long flags;
1464         int index;
1465
1466         ohci_stop_iso(base);
1467         context_release(&ctx->context);
1468         free_page((unsigned long)ctx->header);
1469
1470         spin_lock_irqsave(&ohci->lock, flags);
1471
1472         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1473                 index = ctx - ohci->it_context_list;
1474                 ohci->it_context_mask |= 1 << index;
1475         } else {
1476                 index = ctx - ohci->ir_context_list;
1477                 ohci->ir_context_mask |= 1 << index;
1478         }
1479
1480         spin_unlock_irqrestore(&ohci->lock, flags);
1481 }
1482
1483 static int
1484 ohci_queue_iso_transmit(struct fw_iso_context *base,
1485                         struct fw_iso_packet *packet,
1486                         struct fw_iso_buffer *buffer,
1487                         unsigned long payload)
1488 {
1489         struct iso_context *ctx = container_of(base, struct iso_context, base);
1490         struct descriptor *d, *last, *pd;
1491         struct fw_iso_packet *p;
1492         __le32 *header;
1493         dma_addr_t d_bus, page_bus;
1494         u32 z, header_z, payload_z, irq;
1495         u32 payload_index, payload_end_index, next_page_index;
1496         int page, end_page, i, length, offset;
1497
1498         /*
1499          * FIXME: Cycle lost behavior should be configurable: lose
1500          * packet, retransmit or terminate..
1501          */
1502
1503         p = packet;
1504         payload_index = payload;
1505
1506         if (p->skip)
1507                 z = 1;
1508         else
1509                 z = 2;
1510         if (p->header_length > 0)
1511                 z++;
1512
1513         /* Determine the first page the payload isn't contained in. */
1514         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1515         if (p->payload_length > 0)
1516                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1517         else
1518                 payload_z = 0;
1519
1520         z += payload_z;
1521
1522         /* Get header size in number of descriptors. */
1523         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1524
1525         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1526         if (d == NULL)
1527                 return -ENOMEM;
1528
1529         if (!p->skip) {
1530                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1531                 d[0].req_count = cpu_to_le16(8);
1532
1533                 header = (__le32 *) &d[1];
1534                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1535                                         IT_HEADER_TAG(p->tag) |
1536                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1537                                         IT_HEADER_CHANNEL(ctx->base.channel) |
1538                                         IT_HEADER_SPEED(ctx->base.speed));
1539                 header[1] =
1540                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
1541                                                           p->payload_length));
1542         }
1543
1544         if (p->header_length > 0) {
1545                 d[2].req_count    = cpu_to_le16(p->header_length);
1546                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
1547                 memcpy(&d[z], p->header, p->header_length);
1548         }
1549
1550         pd = d + z - payload_z;
1551         payload_end_index = payload_index + p->payload_length;
1552         for (i = 0; i < payload_z; i++) {
1553                 page               = payload_index >> PAGE_SHIFT;
1554                 offset             = payload_index & ~PAGE_MASK;
1555                 next_page_index    = (page + 1) << PAGE_SHIFT;
1556                 length             =
1557                         min(next_page_index, payload_end_index) - payload_index;
1558                 pd[i].req_count    = cpu_to_le16(length);
1559
1560                 page_bus = page_private(buffer->pages[page]);
1561                 pd[i].data_address = cpu_to_le32(page_bus + offset);
1562
1563                 payload_index += length;
1564         }
1565
1566         if (p->interrupt)
1567                 irq = DESCRIPTOR_IRQ_ALWAYS;
1568         else
1569                 irq = DESCRIPTOR_NO_IRQ;
1570
1571         last = z == 2 ? d : d + z - 1;
1572         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1573                                      DESCRIPTOR_STATUS |
1574                                      DESCRIPTOR_BRANCH_ALWAYS |
1575                                      irq);
1576
1577         context_append(&ctx->context, d, z, header_z);
1578
1579         return 0;
1580 }
1581
1582 static int
1583 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1584                                   struct fw_iso_packet *packet,
1585                                   struct fw_iso_buffer *buffer,
1586                                   unsigned long payload)
1587 {
1588         struct iso_context *ctx = container_of(base, struct iso_context, base);
1589         struct db_descriptor *db = NULL;
1590         struct descriptor *d;
1591         struct fw_iso_packet *p;
1592         dma_addr_t d_bus, page_bus;
1593         u32 z, header_z, length, rest;
1594         int page, offset, packet_count, header_size;
1595
1596         /*
1597          * FIXME: Cycle lost behavior should be configurable: lose
1598          * packet, retransmit or terminate..
1599          */
1600
1601         if (packet->skip) {
1602                 d = context_get_descriptors(&ctx->context, 2, &d_bus);
1603                 if (d == NULL)
1604                         return -ENOMEM;
1605
1606                 db = (struct db_descriptor *) d;
1607                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1608                                           DESCRIPTOR_BRANCH_ALWAYS |
1609                                           DESCRIPTOR_WAIT);
1610                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1611                 context_append(&ctx->context, d, 2, 0);
1612         }
1613
1614         p = packet;
1615         z = 2;
1616
1617         /*
1618          * The OHCI controller puts the status word in the header
1619          * buffer too, so we need 4 extra bytes per packet.
1620          */
1621         packet_count = p->header_length / ctx->base.header_size;
1622         header_size = packet_count * (ctx->base.header_size + 4);
1623
1624         /* Get header size in number of descriptors. */
1625         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1626         page     = payload >> PAGE_SHIFT;
1627         offset   = payload & ~PAGE_MASK;
1628         rest     = p->payload_length;
1629
1630         /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1631         /* FIXME: make packet-per-buffer/dual-buffer a context option */
1632         while (rest > 0) {
1633                 d = context_get_descriptors(&ctx->context,
1634                                             z + header_z, &d_bus);
1635                 if (d == NULL)
1636                         return -ENOMEM;
1637
1638                 db = (struct db_descriptor *) d;
1639                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1640                                           DESCRIPTOR_BRANCH_ALWAYS);
1641                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1642                 db->first_req_count = cpu_to_le16(header_size);
1643                 db->first_res_count = db->first_req_count;
1644                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
1645
1646                 if (offset + rest < PAGE_SIZE)
1647                         length = rest;
1648                 else
1649                         length = PAGE_SIZE - offset;
1650
1651                 db->second_req_count = cpu_to_le16(length);
1652                 db->second_res_count = db->second_req_count;
1653                 page_bus = page_private(buffer->pages[page]);
1654                 db->second_buffer = cpu_to_le32(page_bus + offset);
1655
1656                 if (p->interrupt && length == rest)
1657                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1658
1659                 context_append(&ctx->context, d, z, header_z);
1660                 offset = (offset + length) & ~PAGE_MASK;
1661                 rest -= length;
1662                 page++;
1663         }
1664
1665         return 0;
1666 }
1667
1668 static int
1669 ohci_queue_iso(struct fw_iso_context *base,
1670                struct fw_iso_packet *packet,
1671                struct fw_iso_buffer *buffer,
1672                unsigned long payload)
1673 {
1674         struct iso_context *ctx = container_of(base, struct iso_context, base);
1675
1676         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1677                 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1678         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
1679                 return ohci_queue_iso_receive_dualbuffer(base, packet,
1680                                                          buffer, payload);
1681         else
1682                 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1683                 return -EINVAL;
1684 }
1685
1686 static const struct fw_card_driver ohci_driver = {
1687         .name                   = ohci_driver_name,
1688         .enable                 = ohci_enable,
1689         .update_phy_reg         = ohci_update_phy_reg,
1690         .set_config_rom         = ohci_set_config_rom,
1691         .send_request           = ohci_send_request,
1692         .send_response          = ohci_send_response,
1693         .cancel_packet          = ohci_cancel_packet,
1694         .enable_phys_dma        = ohci_enable_phys_dma,
1695         .get_bus_time           = ohci_get_bus_time,
1696
1697         .allocate_iso_context   = ohci_allocate_iso_context,
1698         .free_iso_context       = ohci_free_iso_context,
1699         .queue_iso              = ohci_queue_iso,
1700         .start_iso              = ohci_start_iso,
1701         .stop_iso               = ohci_stop_iso,
1702 };
1703
1704 static int software_reset(struct fw_ohci *ohci)
1705 {
1706         int i;
1707
1708         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1709
1710         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1711                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1712                      OHCI1394_HCControl_softReset) == 0)
1713                         return 0;
1714                 msleep(1);
1715         }
1716
1717         return -EBUSY;
1718 }
1719
1720 static int __devinit
1721 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1722 {
1723         struct fw_ohci *ohci;
1724         u32 bus_options, max_receive, link_speed;
1725         u64 guid;
1726         int err;
1727         size_t size;
1728
1729         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
1730         if (ohci == NULL) {
1731                 fw_error("Could not malloc fw_ohci data.\n");
1732                 return -ENOMEM;
1733         }
1734
1735         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1736
1737         err = pci_enable_device(dev);
1738         if (err) {
1739                 fw_error("Failed to enable OHCI hardware.\n");
1740                 goto fail_put_card;
1741         }
1742
1743         pci_set_master(dev);
1744         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1745         pci_set_drvdata(dev, ohci);
1746
1747         spin_lock_init(&ohci->lock);
1748
1749         tasklet_init(&ohci->bus_reset_tasklet,
1750                      bus_reset_tasklet, (unsigned long)ohci);
1751
1752         err = pci_request_region(dev, 0, ohci_driver_name);
1753         if (err) {
1754                 fw_error("MMIO resource unavailable\n");
1755                 goto fail_disable;
1756         }
1757
1758         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1759         if (ohci->registers == NULL) {
1760                 fw_error("Failed to remap registers\n");
1761                 err = -ENXIO;
1762                 goto fail_iomem;
1763         }
1764
1765         if (software_reset(ohci)) {
1766                 fw_error("Failed to reset ohci card.\n");
1767                 err = -EBUSY;
1768                 goto fail_registers;
1769         }
1770
1771         /*
1772          * Now enable LPS, which we need in order to start accessing
1773          * most of the registers.  In fact, on some cards (ALI M5251),
1774          * accessing registers in the SClk domain without LPS enabled
1775          * will lock up the machine.  Wait 50msec to make sure we have
1776          * full link enabled.
1777          */
1778         reg_write(ohci, OHCI1394_HCControlSet,
1779                   OHCI1394_HCControl_LPS |
1780                   OHCI1394_HCControl_postedWriteEnable);
1781         flush_writes(ohci);
1782         msleep(50);
1783
1784         reg_write(ohci, OHCI1394_HCControlClear,
1785                   OHCI1394_HCControl_noByteSwapData);
1786
1787         reg_write(ohci, OHCI1394_LinkControlSet,
1788                   OHCI1394_LinkControl_rcvSelfID |
1789                   OHCI1394_LinkControl_cycleTimerEnable |
1790                   OHCI1394_LinkControl_cycleMaster);
1791
1792         ar_context_init(&ohci->ar_request_ctx, ohci,
1793                         OHCI1394_AsReqRcvContextControlSet);
1794
1795         ar_context_init(&ohci->ar_response_ctx, ohci,
1796                         OHCI1394_AsRspRcvContextControlSet);
1797
1798         context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
1799                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
1800
1801         context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
1802                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
1803
1804         reg_write(ohci, OHCI1394_ATRetries,
1805                   OHCI1394_MAX_AT_REQ_RETRIES |
1806                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1807                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1808
1809         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1810         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1811         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1812         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1813         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1814
1815         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1816         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1817         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1818         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1819         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1820
1821         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1822                 fw_error("Out of memory for it/ir contexts.\n");
1823                 err = -ENOMEM;
1824                 goto fail_registers;
1825         }
1826
1827         /* self-id dma buffer allocation */
1828         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1829                                                SELF_ID_BUF_SIZE,
1830                                                &ohci->self_id_bus,
1831                                                GFP_KERNEL);
1832         if (ohci->self_id_cpu == NULL) {
1833                 fw_error("Out of memory for self ID buffer.\n");
1834                 err = -ENOMEM;
1835                 goto fail_registers;
1836         }
1837
1838         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1839         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1840         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1841         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1842         reg_write(ohci, OHCI1394_IntMaskSet,
1843                   OHCI1394_selfIDComplete |
1844                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1845                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1846                   OHCI1394_isochRx | OHCI1394_isochTx |
1847                   OHCI1394_masterIntEnable |
1848                   OHCI1394_cycle64Seconds);
1849
1850         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1851         max_receive = (bus_options >> 12) & 0xf;
1852         link_speed = bus_options & 0x7;
1853         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1854                 reg_read(ohci, OHCI1394_GUIDLo);
1855
1856         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1857         if (err < 0)
1858                 goto fail_self_id;
1859
1860         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1861         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1862                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
1863
1864         return 0;
1865
1866  fail_self_id:
1867         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1868                           ohci->self_id_cpu, ohci->self_id_bus);
1869  fail_registers:
1870         kfree(ohci->it_context_list);
1871         kfree(ohci->ir_context_list);
1872         pci_iounmap(dev, ohci->registers);
1873  fail_iomem:
1874         pci_release_region(dev, 0);
1875  fail_disable:
1876         pci_disable_device(dev);
1877  fail_put_card:
1878         fw_card_put(&ohci->card);
1879
1880         return err;
1881 }
1882
1883 static void pci_remove(struct pci_dev *dev)
1884 {
1885         struct fw_ohci *ohci;
1886
1887         ohci = pci_get_drvdata(dev);
1888         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1889         flush_writes(ohci);
1890         fw_core_remove_card(&ohci->card);
1891
1892         /*
1893          * FIXME: Fail all pending packets here, now that the upper
1894          * layers can't queue any more.
1895          */
1896
1897         software_reset(ohci);
1898         free_irq(dev->irq, ohci);
1899         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1900                           ohci->self_id_cpu, ohci->self_id_bus);
1901         kfree(ohci->it_context_list);
1902         kfree(ohci->ir_context_list);
1903         pci_iounmap(dev, ohci->registers);
1904         pci_release_region(dev, 0);
1905         pci_disable_device(dev);
1906         fw_card_put(&ohci->card);
1907
1908         fw_notify("Removed fw-ohci device.\n");
1909 }
1910
1911 static struct pci_device_id pci_table[] = {
1912         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1913         { }
1914 };
1915
1916 MODULE_DEVICE_TABLE(pci, pci_table);
1917
1918 static struct pci_driver fw_ohci_pci_driver = {
1919         .name           = ohci_driver_name,
1920         .id_table       = pci_table,
1921         .probe          = pci_probe,
1922         .remove         = pci_remove,
1923 };
1924
1925 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1926 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1927 MODULE_LICENSE("GPL");
1928
1929 /* Provide a module alias so root-on-sbp2 initrds don't break. */
1930 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
1931 MODULE_ALIAS("ohci1394");
1932 #endif
1933
1934 static int __init fw_ohci_init(void)
1935 {
1936         return pci_register_driver(&fw_ohci_pci_driver);
1937 }
1938
1939 static void __exit fw_ohci_cleanup(void)
1940 {
1941         pci_unregister_driver(&fw_ohci_pci_driver);
1942 }
1943
1944 module_init(fw_ohci_init);
1945 module_exit(fw_ohci_cleanup);