drivers/firewire/fw-ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/pci.h>
  26 #include <linux/delay.h>
  27 #include <linux/poll.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/mm.h>
  30
  31 #include <asm/uaccess.h>
  32 #include <asm/semaphore.h>
  33
  34 #include "fw-transaction.h"
  35 #include "fw-ohci.h"
  36
  37 #define DESCRIPTOR_OUTPUT_MORE          0
  38 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  39 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  40 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  41 #define DESCRIPTOR_STATUS               (1 << 11)
  42 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  43 #define DESCRIPTOR_PING                 (1 << 7)
  44 #define DESCRIPTOR_YY                   (1 << 6)
  45 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  46 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  47 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  48 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  49 #define DESCRIPTOR_WAIT                 (3 << 0)
  50
  51 struct descriptor {
  52         __le16 req_count;
  53         __le16 control;
  54         __le32 data_address;
  55         __le32 branch_address;
  56         __le16 res_count;
  57         __le16 transfer_status;
  58 } __attribute__((aligned(16)));
  59
  60 struct db_descriptor {
  61         __le16 first_size;
  62         __le16 control;
  63         __le16 second_req_count;
  64         __le16 first_req_count;
  65         __le32 branch_address;
  66         __le16 second_res_count;
  67         __le16 first_res_count;
  68         __le32 reserved0;
  69         __le32 first_buffer;
  70         __le32 second_buffer;
  71         __le32 reserved1;
  72 } __attribute__((aligned(16)));
  73
  74 #define CONTROL_SET(regs)       (regs)
  75 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  76 #define COMMAND_PTR(regs)       ((regs) + 12)
  77 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  78
  79 struct ar_buffer {
  80         struct descriptor descriptor;
  81         struct ar_buffer *next;
  82         __le32 data[0];
  83 };
  84
  85 struct ar_context {
  86         struct fw_ohci *ohci;
  87         struct ar_buffer *current_buffer;
  88         struct ar_buffer *last_buffer;
  89         void *pointer;
  90         u32 regs;
  91         struct tasklet_struct tasklet;
  92 };
  93
  94 struct context;
  95
  96 typedef int (*descriptor_callback_t)(struct context *ctx,
  97                                      struct descriptor *d,
  98                                      struct descriptor *last);
  99 struct context {
 100         struct fw_ohci *ohci;
 101         u32 regs;
 102
 103         struct descriptor *buffer;
 104         dma_addr_t buffer_bus;
 105         size_t buffer_size;
 106         struct descriptor *head_descriptor;
 107         struct descriptor *tail_descriptor;
 108         struct descriptor *tail_descriptor_last;
 109         struct descriptor *prev_descriptor;
 110
 111         descriptor_callback_t callback;
 112
 113         struct tasklet_struct tasklet;
 114 };
 115
 116 #define IT_HEADER_SY(v)          ((v) <<  0)
 117 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 118 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 119 #define IT_HEADER_TAG(v)         ((v) << 14)
 120 #define IT_HEADER_SPEED(v)       ((v) << 16)
 121 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 122
 123 struct iso_context {
 124         struct fw_iso_context base;
 125         struct context context;
 126         void *header;
 127         size_t header_length;
 128 };
 129
 130 #define CONFIG_ROM_SIZE 1024
 131
 132 struct fw_ohci {
 133         struct fw_card card;
 134
 135         u32 version;
 136         __iomem char *registers;
 137         dma_addr_t self_id_bus;
 138         __le32 *self_id_cpu;
 139         struct tasklet_struct bus_reset_tasklet;
 140         int node_id;
 141         int generation;
 142         int request_generation;
 143         u32 bus_seconds;
 144
 145         /*
 146          * Spinlock for accessing fw_ohci data.  Never call out of
 147          * this driver with this lock held.
 148          */
 149         spinlock_t lock;
 150         u32 self_id_buffer[512];
 151
 152         /* Config rom buffers */
 153         __be32 *config_rom;
 154         dma_addr_t config_rom_bus;
 155         __be32 *next_config_rom;
 156         dma_addr_t next_config_rom_bus;
 157         u32 next_header;
 158
 159         struct ar_context ar_request_ctx;
 160         struct ar_context ar_response_ctx;
 161         struct context at_request_ctx;
 162         struct context at_response_ctx;
 163
 164         u32 it_context_mask;
 165         struct iso_context *it_context_list;
 166         u32 ir_context_mask;
 167         struct iso_context *ir_context_list;
 168 };
 169
 170 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 171 {
 172         return container_of(card, struct fw_ohci, card);
 173 }
 174
 175 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 176 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 177 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 178 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 179 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 180 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 181
 182 #define CONTEXT_RUN     0x8000
 183 #define CONTEXT_WAKE    0x1000
 184 #define CONTEXT_DEAD    0x0800
 185 #define CONTEXT_ACTIVE  0x0400
 186
 187 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 188 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 189 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 190
 191 #define FW_OHCI_MAJOR                   240
 192 #define OHCI1394_REGISTER_SIZE          0x800
 193 #define OHCI_LOOP_COUNT                 500
 194 #define OHCI1394_PCI_HCI_Control        0x40
 195 #define SELF_ID_BUF_SIZE                0x800
 196 #define OHCI_TCODE_PHY_PACKET           0x0e
 197 #define OHCI_VERSION_1_1                0x010010
 198 #define ISO_BUFFER_SIZE                 (64 * 1024)
 199 #define AT_BUFFER_SIZE                  4096
 200
 201 static char ohci_driver_name[] = KBUILD_MODNAME;
 202
 203 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 204 {
 205         writel(data, ohci->registers + offset);
 206 }
 207
 208 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 209 {
 210         return readl(ohci->registers + offset);
 211 }
 212
 213 static inline void flush_writes(const struct fw_ohci *ohci)
 214 {
 215         /* Do a dummy read to flush writes. */
 216         reg_read(ohci, OHCI1394_Version);
 217 }
 218
 219 static int
 220 ohci_update_phy_reg(struct fw_card *card, int addr,
 221                     int clear_bits, int set_bits)
 222 {
 223         struct fw_ohci *ohci = fw_ohci(card);
 224         u32 val, old;
 225
 226         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 227         msleep(2);
 228         val = reg_read(ohci, OHCI1394_PhyControl);
 229         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 230                 fw_error("failed to set phy reg bits.\n");
 231                 return -EBUSY;
 232         }
 233
 234         old = OHCI1394_PhyControl_ReadData(val);
 235         old = (old & ~clear_bits) | set_bits;
 236         reg_write(ohci, OHCI1394_PhyControl,
 237                   OHCI1394_PhyControl_Write(addr, old));
 238
 239         return 0;
 240 }
 241
 242 static int ar_context_add_page(struct ar_context *ctx)
 243 {
 244         struct device *dev = ctx->ohci->card.device;
 245         struct ar_buffer *ab;
 246         dma_addr_t ab_bus;
 247         size_t offset;
 248
 249         ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
 250         if (ab == NULL)
 251                 return -ENOMEM;
 252
 253         ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
 254         if (dma_mapping_error(ab_bus)) {
 255                 free_page((unsigned long) ab);
 256                 return -ENOMEM;
 257         }
 258
 259         memset(&ab->descriptor, 0, sizeof(ab->descriptor));
 260         ab->descriptor.control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
 261                                                     DESCRIPTOR_STATUS |
 262                                                     DESCRIPTOR_BRANCH_ALWAYS);
 263         offset = offsetof(struct ar_buffer, data);
 264         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 265         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 266         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 267         ab->descriptor.branch_address = 0;
 268
 269         dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 270
 271         ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
 272         ctx->last_buffer->next = ab;
 273         ctx->last_buffer = ab;
 274
 275         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 276         flush_writes(ctx->ohci);
 277
 278         return 0;
 279 }
 280
 281 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 282 {
 283         struct fw_ohci *ohci = ctx->ohci;
 284         struct fw_packet p;
 285         u32 status, length, tcode;
 286
 287         p.header[0] = le32_to_cpu(buffer[0]);
 288         p.header[1] = le32_to_cpu(buffer[1]);
 289         p.header[2] = le32_to_cpu(buffer[2]);
 290
 291         tcode = (p.header[0] >> 4) & 0x0f;
 292         switch (tcode) {
 293         case TCODE_WRITE_QUADLET_REQUEST:
 294         case TCODE_READ_QUADLET_RESPONSE:
 295                 p.header[3] = (__force __u32) buffer[3];
 296                 p.header_length = 16;
 297                 p.payload_length = 0;
 298                 break;
 299
 300         case TCODE_READ_BLOCK_REQUEST :
 301                 p.header[3] = le32_to_cpu(buffer[3]);
 302                 p.header_length = 16;
 303                 p.payload_length = 0;
 304                 break;
 305
 306         case TCODE_WRITE_BLOCK_REQUEST:
 307         case TCODE_READ_BLOCK_RESPONSE:
 308         case TCODE_LOCK_REQUEST:
 309         case TCODE_LOCK_RESPONSE:
 310                 p.header[3] = le32_to_cpu(buffer[3]);
 311                 p.header_length = 16;
 312                 p.payload_length = p.header[3] >> 16;
 313                 break;
 314
 315         case TCODE_WRITE_RESPONSE:
 316         case TCODE_READ_QUADLET_REQUEST:
 317         case OHCI_TCODE_PHY_PACKET:
 318                 p.header_length = 12;
 319                 p.payload_length = 0;
 320                 break;
 321         }
 322
 323         p.payload = (void *) buffer + p.header_length;
 324
 325         /* FIXME: What to do about evt_* errors? */
 326         length = (p.header_length + p.payload_length + 3) / 4;
 327         status = le32_to_cpu(buffer[length]);
 328
 329         p.ack        = ((status >> 16) & 0x1f) - 16;
 330         p.speed      = (status >> 21) & 0x7;
 331         p.timestamp  = status & 0xffff;
 332         p.generation = ohci->request_generation;
 333
 334         /*
 335          * The OHCI bus reset handler synthesizes a phy packet with
 336          * the new generation number when a bus reset happens (see
 337          * section 8.4.2.3).  This helps us determine when a request
 338          * was received and make sure we send the response in the same
 339          * generation.  We only need this for requests; for responses
 340          * we use the unique tlabel for finding the matching
 341          * request.
 342          */
 343
 344         if (p.ack + 16 == 0x09)
 345                 ohci->request_generation = (buffer[2] >> 16) & 0xff;
 346         else if (ctx == &ohci->ar_request_ctx)
 347                 fw_core_handle_request(&ohci->card, &p);
 348         else
 349                 fw_core_handle_response(&ohci->card, &p);
 350
 351         return buffer + length + 1;
 352 }
 353
 354 static void ar_context_tasklet(unsigned long data)
 355 {
 356         struct ar_context *ctx = (struct ar_context *)data;
 357         struct fw_ohci *ohci = ctx->ohci;
 358         struct ar_buffer *ab;
 359         struct descriptor *d;
 360         void *buffer, *end;
 361
 362         ab = ctx->current_buffer;
 363         d = &ab->descriptor;
 364
 365         if (d->res_count == 0) {
 366                 size_t size, rest, offset;
 367
 368                 /*
 369                  * This descriptor is finished and we may have a
 370                  * packet split across this and the next buffer. We
 371                  * reuse the page for reassembling the split packet.
 372                  */
 373
 374                 offset = offsetof(struct ar_buffer, data);
 375                 dma_unmap_single(ohci->card.device,
 376                                  ab->descriptor.data_address - offset,
 377                                  PAGE_SIZE, DMA_BIDIRECTIONAL);
 378
 379                 buffer = ab;
 380                 ab = ab->next;
 381                 d = &ab->descriptor;
 382                 size = buffer + PAGE_SIZE - ctx->pointer;
 383                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 384                 memmove(buffer, ctx->pointer, size);
 385                 memcpy(buffer + size, ab->data, rest);
 386                 ctx->current_buffer = ab;
 387                 ctx->pointer = (void *) ab->data + rest;
 388                 end = buffer + size + rest;
 389
 390                 while (buffer < end)
 391                         buffer = handle_ar_packet(ctx, buffer);
 392
 393                 free_page((unsigned long)buffer);
 394                 ar_context_add_page(ctx);
 395         } else {
 396                 buffer = ctx->pointer;
 397                 ctx->pointer = end =
 398                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 399
 400                 while (buffer < end)
 401                         buffer = handle_ar_packet(ctx, buffer);
 402         }
 403 }
 404
 405 static int
 406 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 407 {
 408         struct ar_buffer ab;
 409
 410         ctx->regs        = regs;
 411         ctx->ohci        = ohci;
 412         ctx->last_buffer = &ab;
 413         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 414
 415         ar_context_add_page(ctx);
 416         ar_context_add_page(ctx);
 417         ctx->current_buffer = ab.next;
 418         ctx->pointer = ctx->current_buffer->data;
 419
 420         return 0;
 421 }
 422
 423 static void ar_context_run(struct ar_context *ctx)
 424 {
 425         struct ar_buffer *ab = ctx->current_buffer;
 426         dma_addr_t ab_bus;
 427         size_t offset;
 428
 429         offset = offsetof(struct ar_buffer, data);
 430         ab_bus = ab->descriptor.data_address - offset;
 431
 432         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
 433         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
 434         flush_writes(ctx->ohci);
 435 }
 436
 437 static void context_tasklet(unsigned long data)
 438 {
 439         struct context *ctx = (struct context *) data;
 440         struct fw_ohci *ohci = ctx->ohci;
 441         struct descriptor *d, *last;
 442         u32 address;
 443         int z;
 444
 445         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
 446                                 ctx->buffer_size, DMA_TO_DEVICE);
 447
 448         d    = ctx->tail_descriptor;
 449         last = ctx->tail_descriptor_last;
 450
 451         while (last->branch_address != 0) {
 452                 address = le32_to_cpu(last->branch_address);
 453                 z = address & 0xf;
 454                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
 455                 last = (z == 2) ? d : d + z - 1;
 456
 457                 if (!ctx->callback(ctx, d, last))
 458                         break;
 459
 460                 ctx->tail_descriptor      = d;
 461                 ctx->tail_descriptor_last = last;
 462         }
 463 }
 464
 465 static int
 466 context_init(struct context *ctx, struct fw_ohci *ohci,
 467              size_t buffer_size, u32 regs,
 468              descriptor_callback_t callback)
 469 {
 470         ctx->ohci = ohci;
 471         ctx->regs = regs;
 472         ctx->buffer_size = buffer_size;
 473         ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
 474         if (ctx->buffer == NULL)
 475                 return -ENOMEM;
 476
 477         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 478         ctx->callback = callback;
 479
 480         ctx->buffer_bus =
 481                 dma_map_single(ohci->card.device, ctx->buffer,
 482                                buffer_size, DMA_TO_DEVICE);
 483         if (dma_mapping_error(ctx->buffer_bus)) {
 484                 kfree(ctx->buffer);
 485                 return -ENOMEM;
 486         }
 487
 488         ctx->head_descriptor      = ctx->buffer;
 489         ctx->prev_descriptor      = ctx->buffer;
 490         ctx->tail_descriptor      = ctx->buffer;
 491         ctx->tail_descriptor_last = ctx->buffer;
 492
 493         /*
 494          * We put a dummy descriptor in the buffer that has a NULL
 495          * branch address and looks like it's been sent.  That way we
 496          * have a descriptor to append DMA programs to.  Also, the
 497          * ring buffer invariant is that it always has at least one
 498          * element so that head == tail means buffer full.
 499          */
 500
 501         memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
 502         ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
 503         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
 504         ctx->head_descriptor++;
 505
 506         return 0;
 507 }
 508
 509 static void
 510 context_release(struct context *ctx)
 511 {
 512         struct fw_card *card = &ctx->ohci->card;
 513
 514         dma_unmap_single(card->device, ctx->buffer_bus,
 515                          ctx->buffer_size, DMA_TO_DEVICE);
 516         kfree(ctx->buffer);
 517 }
 518
 519 static struct descriptor *
 520 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 521 {
 522         struct descriptor *d, *tail, *end;
 523
 524         d = ctx->head_descriptor;
 525         tail = ctx->tail_descriptor;
 526         end = ctx->buffer + ctx->buffer_size / sizeof(*d);
 527
 528         if (d + z <= tail) {
 529                 goto has_space;
 530         } else if (d > tail && d + z <= end) {
 531                 goto has_space;
 532         } else if (d > tail && ctx->buffer + z <= tail) {
 533                 d = ctx->buffer;
 534                 goto has_space;
 535         }
 536
 537         return NULL;
 538
 539  has_space:
 540         memset(d, 0, z * sizeof(*d));
 541         *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 542
 543         return d;
 544 }
 545
 546 static void context_run(struct context *ctx, u32 extra)
 547 {
 548         struct fw_ohci *ohci = ctx->ohci;
 549
 550         reg_write(ohci, COMMAND_PTR(ctx->regs),
 551                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
 552         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
 553         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
 554         flush_writes(ohci);
 555 }
 556
 557 static void context_append(struct context *ctx,
 558                            struct descriptor *d, int z, int extra)
 559 {
 560         dma_addr_t d_bus;
 561
 562         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
 563
 564         ctx->head_descriptor = d + z + extra;
 565         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
 566         ctx->prev_descriptor = z == 2 ? d : d + z - 1;
 567
 568         dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
 569                                    ctx->buffer_size, DMA_TO_DEVICE);
 570
 571         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 572         flush_writes(ctx->ohci);
 573 }
 574
 575 static void context_stop(struct context *ctx)
 576 {
 577         u32 reg;
 578         int i;
 579
 580         reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 581         flush_writes(ctx->ohci);
 582
 583         for (i = 0; i < 10; i++) {
 584                 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 585                 if ((reg & CONTEXT_ACTIVE) == 0)
 586                         break;
 587
 588                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 589                 msleep(1);
 590         }
 591 }
 592
 593 struct driver_data {
 594         struct fw_packet *packet;
 595 };
 596
 597 /*
 598  * This function apppends a packet to the DMA queue for transmission.
 599  * Must always be called with the ochi->lock held to ensure proper
 600  * generation handling and locking around packet queue manipulation.
 601  */
 602 static int
 603 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 604 {
 605         struct fw_ohci *ohci = ctx->ohci;
 606         dma_addr_t d_bus, payload_bus;
 607         struct driver_data *driver_data;
 608         struct descriptor *d, *last;
 609         __le32 *header;
 610         int z, tcode;
 611         u32 reg;
 612
 613         d = context_get_descriptors(ctx, 4, &d_bus);
 614         if (d == NULL) {
 615                 packet->ack = RCODE_SEND_ERROR;
 616                 return -1;
 617         }
 618
 619         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
 620         d[0].res_count = cpu_to_le16(packet->timestamp);
 621
 622         /*
 623          * The DMA format for asyncronous link packets is different
 624          * from the IEEE1394 layout, so shift the fields around
 625          * accordingly.  If header_length is 8, it's a PHY packet, to
 626          * which we need to prepend an extra quadlet.
 627          */
 628
 629         header = (__le32 *) &d[1];
 630         if (packet->header_length > 8) {
 631                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 632                                         (packet->speed << 16));
 633                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 634                                         (packet->header[0] & 0xffff0000));
 635                 header[2] = cpu_to_le32(packet->header[2]);
 636
 637                 tcode = (packet->header[0] >> 4) & 0x0f;
 638                 if (TCODE_IS_BLOCK_PACKET(tcode))
 639                         header[3] = cpu_to_le32(packet->header[3]);
 640                 else
 641                         header[3] = (__force __le32) packet->header[3];
 642
 643                 d[0].req_count = cpu_to_le16(packet->header_length);
 644         } else {
 645                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 646                                         (packet->speed << 16));
 647                 header[1] = cpu_to_le32(packet->header[0]);
 648                 header[2] = cpu_to_le32(packet->header[1]);
 649                 d[0].req_count = cpu_to_le16(12);
 650         }
 651
 652         driver_data = (struct driver_data *) &d[3];
 653         driver_data->packet = packet;
 654         packet->driver_data = driver_data;
 655
 656         if (packet->payload_length > 0) {
 657                 payload_bus =
 658                         dma_map_single(ohci->card.device, packet->payload,
 659                                        packet->payload_length, DMA_TO_DEVICE);
 660                 if (dma_mapping_error(payload_bus)) {
 661                         packet->ack = RCODE_SEND_ERROR;
 662                         return -1;
 663                 }
 664
 665                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 666                 d[2].data_address = cpu_to_le32(payload_bus);
 667                 last = &d[2];
 668                 z = 3;
 669         } else {
 670                 last = &d[0];
 671                 z = 2;
 672         }
 673
 674         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
 675                                      DESCRIPTOR_IRQ_ALWAYS |
 676                                      DESCRIPTOR_BRANCH_ALWAYS);
 677
 678         /* FIXME: Document how the locking works. */
 679         if (ohci->generation != packet->generation) {
 680                 packet->ack = RCODE_GENERATION;
 681                 return -1;
 682         }
 683
 684         context_append(ctx, d, z, 4 - z);
 685
 686         /* If the context isn't already running, start it up. */
 687         reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
 688         if ((reg & CONTEXT_RUN) == 0)
 689                 context_run(ctx, 0);
 690
 691         return 0;
 692 }
 693
 694 static int handle_at_packet(struct context *context,
 695                             struct descriptor *d,
 696                             struct descriptor *last)
 697 {
 698         struct driver_data *driver_data;
 699         struct fw_packet *packet;
 700         struct fw_ohci *ohci = context->ohci;
 701         dma_addr_t payload_bus;
 702         int evt;
 703
 704         if (last->transfer_status == 0)
 705                 /* This descriptor isn't done yet, stop iteration. */
 706                 return 0;
 707
 708         driver_data = (struct driver_data *) &d[3];
 709         packet = driver_data->packet;
 710         if (packet == NULL)
 711                 /* This packet was cancelled, just continue. */
 712                 return 1;
 713
 714         payload_bus = le32_to_cpu(last->data_address);
 715         if (payload_bus != 0)
 716                 dma_unmap_single(ohci->card.device, payload_bus,
 717                                  packet->payload_length, DMA_TO_DEVICE);
 718
 719         evt = le16_to_cpu(last->transfer_status) & 0x1f;
 720         packet->timestamp = le16_to_cpu(last->res_count);
 721
 722         switch (evt) {
 723         case OHCI1394_evt_timeout:
 724                 /* Async response transmit timed out. */
 725                 packet->ack = RCODE_CANCELLED;
 726                 break;
 727
 728         case OHCI1394_evt_flushed:
 729                 /*
 730                  * The packet was flushed should give same error as
 731                  * when we try to use a stale generation count.
 732                  */
 733                 packet->ack = RCODE_GENERATION;
 734                 break;
 735
 736         case OHCI1394_evt_missing_ack:
 737                 /*
 738                  * Using a valid (current) generation count, but the
 739                  * node is not on the bus or not sending acks.
 740                  */
 741                 packet->ack = RCODE_NO_ACK;
 742                 break;
 743
 744         case ACK_COMPLETE + 0x10:
 745         case ACK_PENDING + 0x10:
 746         case ACK_BUSY_X + 0x10:
 747         case ACK_BUSY_A + 0x10:
 748         case ACK_BUSY_B + 0x10:
 749         case ACK_DATA_ERROR + 0x10:
 750         case ACK_TYPE_ERROR + 0x10:
 751                 packet->ack = evt - 0x10;
 752                 break;
 753
 754         default:
 755                 packet->ack = RCODE_SEND_ERROR;
 756                 break;
 757         }
 758
 759         packet->callback(packet, &ohci->card, packet->ack);
 760
 761         return 1;
 762 }
 763
 764 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
 765 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
 766 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
 767 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
 768 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
 769
 770 static void
 771 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 772 {
 773         struct fw_packet response;
 774         int tcode, length, i;
 775
 776         tcode = HEADER_GET_TCODE(packet->header[0]);
 777         if (TCODE_IS_BLOCK_PACKET(tcode))
 778                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 779         else
 780                 length = 4;
 781
 782         i = csr - CSR_CONFIG_ROM;
 783         if (i + length > CONFIG_ROM_SIZE) {
 784                 fw_fill_response(&response, packet->header,
 785                                  RCODE_ADDRESS_ERROR, NULL, 0);
 786         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
 787                 fw_fill_response(&response, packet->header,
 788                                  RCODE_TYPE_ERROR, NULL, 0);
 789         } else {
 790                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
 791                                  (void *) ohci->config_rom + i, length);
 792         }
 793
 794         fw_core_handle_response(&ohci->card, &response);
 795 }
 796
 797 static void
 798 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 799 {
 800         struct fw_packet response;
 801         int tcode, length, ext_tcode, sel;
 802         __be32 *payload, lock_old;
 803         u32 lock_arg, lock_data;
 804
 805         tcode = HEADER_GET_TCODE(packet->header[0]);
 806         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
 807         payload = packet->payload;
 808         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
 809
 810         if (tcode == TCODE_LOCK_REQUEST &&
 811             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
 812                 lock_arg = be32_to_cpu(payload[0]);
 813                 lock_data = be32_to_cpu(payload[1]);
 814         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
 815                 lock_arg = 0;
 816                 lock_data = 0;
 817         } else {
 818                 fw_fill_response(&response, packet->header,
 819                                  RCODE_TYPE_ERROR, NULL, 0);
 820                 goto out;
 821         }
 822
 823         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 824         reg_write(ohci, OHCI1394_CSRData, lock_data);
 825         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 826         reg_write(ohci, OHCI1394_CSRControl, sel);
 827
 828         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
 829                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
 830         else
 831                 fw_notify("swap not done yet\n");
 832
 833         fw_fill_response(&response, packet->header,
 834                          RCODE_COMPLETE, &lock_old, sizeof(lock_old));
 835  out:
 836         fw_core_handle_response(&ohci->card, &response);
 837 }
 838
 839 static void
 840 handle_local_request(struct context *ctx, struct fw_packet *packet)
 841 {
 842         u64 offset;
 843         u32 csr;
 844
 845         if (ctx == &ctx->ohci->at_request_ctx) {
 846                 packet->ack = ACK_PENDING;
 847                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 848         }
 849
 850         offset =
 851                 ((unsigned long long)
 852                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
 853                 packet->header[2];
 854         csr = offset - CSR_REGISTER_BASE;
 855
 856         /* Handle config rom reads. */
 857         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
 858                 handle_local_rom(ctx->ohci, packet, csr);
 859         else switch (csr) {
 860         case CSR_BUS_MANAGER_ID:
 861         case CSR_BANDWIDTH_AVAILABLE:
 862         case CSR_CHANNELS_AVAILABLE_HI:
 863         case CSR_CHANNELS_AVAILABLE_LO:
 864                 handle_local_lock(ctx->ohci, packet, csr);
 865                 break;
 866         default:
 867                 if (ctx == &ctx->ohci->at_request_ctx)
 868                         fw_core_handle_request(&ctx->ohci->card, packet);
 869                 else
 870                         fw_core_handle_response(&ctx->ohci->card, packet);
 871                 break;
 872         }
 873
 874         if (ctx == &ctx->ohci->at_response_ctx) {
 875                 packet->ack = ACK_COMPLETE;
 876                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 877         }
 878 }
 879
 880 static void
 881 at_context_transmit(struct context *ctx, struct fw_packet *packet)
 882 {
 883         unsigned long flags;
 884         int retval;
 885
 886         spin_lock_irqsave(&ctx->ohci->lock, flags);
 887
 888         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
 889             ctx->ohci->generation == packet->generation) {
 890                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 891                 handle_local_request(ctx, packet);
 892                 return;
 893         }
 894
 895         retval = at_context_queue_packet(ctx, packet);
 896         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 897
 898         if (retval < 0)
 899                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 900
 901 }
 902
 903 static void bus_reset_tasklet(unsigned long data)
 904 {
 905         struct fw_ohci *ohci = (struct fw_ohci *)data;
 906         int self_id_count, i, j, reg;
 907         int generation, new_generation;
 908         unsigned long flags;
 909
 910         reg = reg_read(ohci, OHCI1394_NodeID);
 911         if (!(reg & OHCI1394_NodeID_idValid)) {
 912                 fw_error("node ID not valid, new bus reset in progress\n");
 913                 return;
 914         }
 915         ohci->node_id = reg & 0xffff;
 916
 917         /*
 918          * The count in the SelfIDCount register is the number of
 919          * bytes in the self ID receive buffer.  Since we also receive
 920          * the inverted quadlets and a header quadlet, we shift one
 921          * bit extra to get the actual number of self IDs.
 922          */
 923
 924         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
 925         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 926
 927         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 928                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
 929                         fw_error("inconsistent self IDs\n");
 930                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
 931         }
 932
 933         /*
 934          * Check the consistency of the self IDs we just read.  The
 935          * problem we face is that a new bus reset can start while we
 936          * read out the self IDs from the DMA buffer. If this happens,
 937          * the DMA buffer will be overwritten with new self IDs and we
 938          * will read out inconsistent data.  The OHCI specification
 939          * (section 11.2) recommends a technique similar to
 940          * linux/seqlock.h, where we remember the generation of the
 941          * self IDs in the buffer before reading them out and compare
 942          * it to the current generation after reading them out.  If
 943          * the two generations match we know we have a consistent set
 944          * of self IDs.
 945          */
 946
 947         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 948         if (new_generation != generation) {
 949                 fw_notify("recursive bus reset detected, "
 950                           "discarding self ids\n");
 951                 return;
 952         }
 953
 954         /* FIXME: Document how the locking works. */
 955         spin_lock_irqsave(&ohci->lock, flags);
 956
 957         ohci->generation = generation;
 958         context_stop(&ohci->at_request_ctx);
 959         context_stop(&ohci->at_response_ctx);
 960         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 961
 962         /*
 963          * This next bit is unrelated to the AT context stuff but we
 964          * have to do it under the spinlock also.  If a new config rom
 965          * was set up before this reset, the old one is now no longer
 966          * in use and we can free it. Update the config rom pointers
 967          * to point to the current config rom and clear the
 968          * next_config_rom pointer so a new udpate can take place.
 969          */
 970
 971         if (ohci->next_config_rom != NULL) {
 972                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 973                                   ohci->config_rom, ohci->config_rom_bus);
 974                 ohci->config_rom      = ohci->next_config_rom;
 975                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
 976                 ohci->next_config_rom = NULL;
 977
 978                 /*
 979                  * Restore config_rom image and manually update
 980                  * config_rom registers.  Writing the header quadlet
 981                  * will indicate that the config rom is ready, so we
 982                  * do that last.
 983                  */
 984                 reg_write(ohci, OHCI1394_BusOptions,
 985                           be32_to_cpu(ohci->config_rom[2]));
 986                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
 987                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
 988         }
 989
 990         spin_unlock_irqrestore(&ohci->lock, flags);
 991
 992         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
 993                                  self_id_count, ohci->self_id_buffer);
 994 }
 995
 996 static irqreturn_t irq_handler(int irq, void *data)
 997 {
 998         struct fw_ohci *ohci = data;
 999         u32 event, iso_event, cycle_time;
1000         int i;
1001
1002         event = reg_read(ohci, OHCI1394_IntEventClear);
1003
1004         if (!event)
1005                 return IRQ_NONE;
1006
1007         reg_write(ohci, OHCI1394_IntEventClear, event);
1008
1009         if (event & OHCI1394_selfIDComplete)
1010                 tasklet_schedule(&ohci->bus_reset_tasklet);
1011
1012         if (event & OHCI1394_RQPkt)
1013                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1014
1015         if (event & OHCI1394_RSPkt)
1016                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1017
1018         if (event & OHCI1394_reqTxComplete)
1019                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1020
1021         if (event & OHCI1394_respTxComplete)
1022                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1023
1024         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1025         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1026
1027         while (iso_event) {
1028                 i = ffs(iso_event) - 1;
1029                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1030                 iso_event &= ~(1 << i);
1031         }
1032
1033         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1034         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1035
1036         while (iso_event) {
1037                 i = ffs(iso_event) - 1;
1038                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1039                 iso_event &= ~(1 << i);
1040         }
1041
1042         if (event & OHCI1394_cycle64Seconds) {
1043                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1044                 if ((cycle_time & 0x80000000) == 0)
1045                         ohci->bus_seconds++;
1046         }
1047
1048         return IRQ_HANDLED;
1049 }
1050
1051 static int software_reset(struct fw_ohci *ohci)
1052 {
1053         int i;
1054
1055         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1056
1057         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1058                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1059                      OHCI1394_HCControl_softReset) == 0)
1060                         return 0;
1061                 msleep(1);
1062         }
1063
1064         return -EBUSY;
1065 }
1066
1067 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1068 {
1069         struct fw_ohci *ohci = fw_ohci(card);
1070         struct pci_dev *dev = to_pci_dev(card->device);
1071
1072         if (software_reset(ohci)) {
1073                 fw_error("Failed to reset ohci card.\n");
1074                 return -EBUSY;
1075         }
1076
1077         /*
1078          * Now enable LPS, which we need in order to start accessing
1079          * most of the registers.  In fact, on some cards (ALI M5251),
1080          * accessing registers in the SClk domain without LPS enabled
1081          * will lock up the machine.  Wait 50msec to make sure we have
1082          * full link enabled.
1083          */
1084         reg_write(ohci, OHCI1394_HCControlSet,
1085                   OHCI1394_HCControl_LPS |
1086                   OHCI1394_HCControl_postedWriteEnable);
1087         flush_writes(ohci);
1088         msleep(50);
1089
1090         reg_write(ohci, OHCI1394_HCControlClear,
1091                   OHCI1394_HCControl_noByteSwapData);
1092
1093         reg_write(ohci, OHCI1394_LinkControlSet,
1094                   OHCI1394_LinkControl_rcvSelfID |
1095                   OHCI1394_LinkControl_cycleTimerEnable |
1096                   OHCI1394_LinkControl_cycleMaster);
1097
1098         reg_write(ohci, OHCI1394_ATRetries,
1099                   OHCI1394_MAX_AT_REQ_RETRIES |
1100                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1101                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1102
1103         ar_context_run(&ohci->ar_request_ctx);
1104         ar_context_run(&ohci->ar_response_ctx);
1105
1106         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1107         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1108         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1109         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1110         reg_write(ohci, OHCI1394_IntMaskSet,
1111                   OHCI1394_selfIDComplete |
1112                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1113                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1114                   OHCI1394_isochRx | OHCI1394_isochTx |
1115                   OHCI1394_masterIntEnable |
1116                   OHCI1394_cycle64Seconds);
1117
1118         /* Activate link_on bit and contender bit in our self ID packets.*/
1119         if (ohci_update_phy_reg(card, 4, 0,
1120                                 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1121                 return -EIO;
1122
1123         /*
1124          * When the link is not yet enabled, the atomic config rom
1125          * update mechanism described below in ohci_set_config_rom()
1126          * is not active.  We have to update ConfigRomHeader and
1127          * BusOptions manually, and the write to ConfigROMmap takes
1128          * effect immediately.  We tie this to the enabling of the
1129          * link, so we have a valid config rom before enabling - the
1130          * OHCI requires that ConfigROMhdr and BusOptions have valid
1131          * values before enabling.
1132          *
1133          * However, when the ConfigROMmap is written, some controllers
1134          * always read back quadlets 0 and 2 from the config rom to
1135          * the ConfigRomHeader and BusOptions registers on bus reset.
1136          * They shouldn't do that in this initial case where the link
1137          * isn't enabled.  This means we have to use the same
1138          * workaround here, setting the bus header to 0 and then write
1139          * the right values in the bus reset tasklet.
1140          */
1141
1142         ohci->next_config_rom =
1143                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1144                                    &ohci->next_config_rom_bus, GFP_KERNEL);
1145         if (ohci->next_config_rom == NULL)
1146                 return -ENOMEM;
1147
1148         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1149         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1150
1151         ohci->next_header = config_rom[0];
1152         ohci->next_config_rom[0] = 0;
1153         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1154         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1155         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1156
1157         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1158
1159         if (request_irq(dev->irq, irq_handler,
1160                         IRQF_SHARED, ohci_driver_name, ohci)) {
1161                 fw_error("Failed to allocate shared interrupt %d.\n",
1162                          dev->irq);
1163                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1164                                   ohci->config_rom, ohci->config_rom_bus);
1165                 return -EIO;
1166         }
1167
1168         reg_write(ohci, OHCI1394_HCControlSet,
1169                   OHCI1394_HCControl_linkEnable |
1170                   OHCI1394_HCControl_BIBimageValid);
1171         flush_writes(ohci);
1172
1173         /*
1174          * We are ready to go, initiate bus reset to finish the
1175          * initialization.
1176          */
1177
1178         fw_core_initiate_bus_reset(&ohci->card, 1);
1179
1180         return 0;
1181 }
1182
1183 static int
1184 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1185 {
1186         struct fw_ohci *ohci;
1187         unsigned long flags;
1188         int retval = 0;
1189         __be32 *next_config_rom;
1190         dma_addr_t next_config_rom_bus;
1191
1192         ohci = fw_ohci(card);
1193
1194         /*
1195          * When the OHCI controller is enabled, the config rom update
1196          * mechanism is a bit tricky, but easy enough to use.  See
1197          * section 5.5.6 in the OHCI specification.
1198          *
1199          * The OHCI controller caches the new config rom address in a
1200          * shadow register (ConfigROMmapNext) and needs a bus reset
1201          * for the changes to take place.  When the bus reset is
1202          * detected, the controller loads the new values for the
1203          * ConfigRomHeader and BusOptions registers from the specified
1204          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1205          * shadow register. All automatically and atomically.
1206          *
1207          * Now, there's a twist to this story.  The automatic load of
1208          * ConfigRomHeader and BusOptions doesn't honor the
1209          * noByteSwapData bit, so with a be32 config rom, the
1210          * controller will load be32 values in to these registers
1211          * during the atomic update, even on litte endian
1212          * architectures.  The workaround we use is to put a 0 in the
1213          * header quadlet; 0 is endian agnostic and means that the
1214          * config rom isn't ready yet.  In the bus reset tasklet we
1215          * then set up the real values for the two registers.
1216          *
1217          * We use ohci->lock to avoid racing with the code that sets
1218          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1219          */
1220
1221         next_config_rom =
1222                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1223                                    &next_config_rom_bus, GFP_KERNEL);
1224         if (next_config_rom == NULL)
1225                 return -ENOMEM;
1226
1227         spin_lock_irqsave(&ohci->lock, flags);
1228
1229         if (ohci->next_config_rom == NULL) {
1230                 ohci->next_config_rom = next_config_rom;
1231                 ohci->next_config_rom_bus = next_config_rom_bus;
1232
1233                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1234                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1235                                   length * 4);
1236
1237                 ohci->next_header = config_rom[0];
1238                 ohci->next_config_rom[0] = 0;
1239
1240                 reg_write(ohci, OHCI1394_ConfigROMmap,
1241                           ohci->next_config_rom_bus);
1242         } else {
1243                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1244                                   next_config_rom, next_config_rom_bus);
1245                 retval = -EBUSY;
1246         }
1247
1248         spin_unlock_irqrestore(&ohci->lock, flags);
1249
1250         /*
1251          * Now initiate a bus reset to have the changes take
1252          * effect. We clean up the old config rom memory and DMA
1253          * mappings in the bus reset tasklet, since the OHCI
1254          * controller could need to access it before the bus reset
1255          * takes effect.
1256          */
1257         if (retval == 0)
1258                 fw_core_initiate_bus_reset(&ohci->card, 1);
1259
1260         return retval;
1261 }
1262
1263 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1264 {
1265         struct fw_ohci *ohci = fw_ohci(card);
1266
1267         at_context_transmit(&ohci->at_request_ctx, packet);
1268 }
1269
1270 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1271 {
1272         struct fw_ohci *ohci = fw_ohci(card);
1273
1274         at_context_transmit(&ohci->at_response_ctx, packet);
1275 }
1276
1277 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1278 {
1279         struct fw_ohci *ohci = fw_ohci(card);
1280         struct context *ctx = &ohci->at_request_ctx;
1281         struct driver_data *driver_data = packet->driver_data;
1282         int retval = -ENOENT;
1283
1284         tasklet_disable(&ctx->tasklet);
1285
1286         if (packet->ack != 0)
1287                 goto out;
1288
1289         driver_data->packet = NULL;
1290         packet->ack = RCODE_CANCELLED;
1291         packet->callback(packet, &ohci->card, packet->ack);
1292         retval = 0;
1293
1294  out:
1295         tasklet_enable(&ctx->tasklet);
1296
1297         return retval;
1298 }
1299
1300 static int
1301 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1302 {
1303         struct fw_ohci *ohci = fw_ohci(card);
1304         unsigned long flags;
1305         int n, retval = 0;
1306
1307         /*
1308          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
1309          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
1310          */
1311
1312         spin_lock_irqsave(&ohci->lock, flags);
1313
1314         if (ohci->generation != generation) {
1315                 retval = -ESTALE;
1316                 goto out;
1317         }
1318
1319         /*
1320          * Note, if the node ID contains a non-local bus ID, physical DMA is
1321          * enabled for _all_ nodes on remote buses.
1322          */
1323
1324         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1325         if (n < 32)
1326                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1327         else
1328                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1329
1330         flush_writes(ohci);
1331  out:
1332         spin_unlock_irqrestore(&ohci->lock, flags);
1333         return retval;
1334 }
1335
1336 static u64
1337 ohci_get_bus_time(struct fw_card *card)
1338 {
1339         struct fw_ohci *ohci = fw_ohci(card);
1340         u32 cycle_time;
1341         u64 bus_time;
1342
1343         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1344         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1345
1346         return bus_time;
1347 }
1348
1349 static int handle_ir_dualbuffer_packet(struct context *context,
1350                                        struct descriptor *d,
1351                                        struct descriptor *last)
1352 {
1353         struct iso_context *ctx =
1354                 container_of(context, struct iso_context, context);
1355         struct db_descriptor *db = (struct db_descriptor *) d;
1356         __le32 *ir_header;
1357         size_t header_length;
1358         void *p, *end;
1359         int i;
1360
1361         if (db->first_res_count > 0 && db->second_res_count > 0)
1362                 /* This descriptor isn't done yet, stop iteration. */
1363                 return 0;
1364
1365         header_length = le16_to_cpu(db->first_req_count) -
1366                 le16_to_cpu(db->first_res_count);
1367
1368         i = ctx->header_length;
1369         p = db + 1;
1370         end = p + header_length;
1371         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1372                 /*
1373                  * The iso header is byteswapped to little endian by
1374                  * the controller, but the remaining header quadlets
1375                  * are big endian.  We want to present all the headers
1376                  * as big endian, so we have to swap the first
1377                  * quadlet.
1378                  */
1379                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1380                 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1381                 i += ctx->base.header_size;
1382                 p += ctx->base.header_size + 4;
1383         }
1384
1385         ctx->header_length = i;
1386
1387         if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1388                 ir_header = (__le32 *) (db + 1);
1389                 ctx->base.callback(&ctx->base,
1390                                    le32_to_cpu(ir_header[0]) & 0xffff,
1391                                    ctx->header_length, ctx->header,
1392                                    ctx->base.callback_data);
1393                 ctx->header_length = 0;
1394         }
1395
1396         return 1;
1397 }
1398
1399 static int handle_it_packet(struct context *context,
1400                             struct descriptor *d,
1401                             struct descriptor *last)
1402 {
1403         struct iso_context *ctx =
1404                 container_of(context, struct iso_context, context);
1405
1406         if (last->transfer_status == 0)
1407                 /* This descriptor isn't done yet, stop iteration. */
1408                 return 0;
1409
1410         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1411                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1412                                    0, NULL, ctx->base.callback_data);
1413
1414         return 1;
1415 }
1416
1417 static struct fw_iso_context *
1418 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1419 {
1420         struct fw_ohci *ohci = fw_ohci(card);
1421         struct iso_context *ctx, *list;
1422         descriptor_callback_t callback;
1423         u32 *mask, regs;
1424         unsigned long flags;
1425         int index, retval = -ENOMEM;
1426
1427         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1428                 mask = &ohci->it_context_mask;
1429                 list = ohci->it_context_list;
1430                 callback = handle_it_packet;
1431         } else {
1432                 mask = &ohci->ir_context_mask;
1433                 list = ohci->ir_context_list;
1434                 callback = handle_ir_dualbuffer_packet;
1435         }
1436
1437         /* FIXME: We need a fallback for pre 1.1 OHCI. */
1438         if (callback == handle_ir_dualbuffer_packet &&
1439             ohci->version < OHCI_VERSION_1_1)
1440                 return ERR_PTR(-EINVAL);
1441
1442         spin_lock_irqsave(&ohci->lock, flags);
1443         index = ffs(*mask) - 1;
1444         if (index >= 0)
1445                 *mask &= ~(1 << index);
1446         spin_unlock_irqrestore(&ohci->lock, flags);
1447
1448         if (index < 0)
1449                 return ERR_PTR(-EBUSY);
1450
1451         if (type == FW_ISO_CONTEXT_TRANSMIT)
1452                 regs = OHCI1394_IsoXmitContextBase(index);
1453         else
1454                 regs = OHCI1394_IsoRcvContextBase(index);
1455
1456         ctx = &list[index];
1457         memset(ctx, 0, sizeof(*ctx));
1458         ctx->header_length = 0;
1459         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1460         if (ctx->header == NULL)
1461                 goto out;
1462
1463         retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
1464                               regs, callback);
1465         if (retval < 0)
1466                 goto out_with_header;
1467
1468         return &ctx->base;
1469
1470  out_with_header:
1471         free_page((unsigned long)ctx->header);
1472  out:
1473         spin_lock_irqsave(&ohci->lock, flags);
1474         *mask |= 1 << index;
1475         spin_unlock_irqrestore(&ohci->lock, flags);
1476
1477         return ERR_PTR(retval);
1478 }
1479
1480 static int ohci_start_iso(struct fw_iso_context *base,
1481                           s32 cycle, u32 sync, u32 tags)
1482 {
1483         struct iso_context *ctx = container_of(base, struct iso_context, base);
1484         struct fw_ohci *ohci = ctx->context.ohci;
1485         u32 control, match;
1486         int index;
1487
1488         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1489                 index = ctx - ohci->it_context_list;
1490                 match = 0;
1491                 if (cycle >= 0)
1492                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1493                                 (cycle & 0x7fff) << 16;
1494
1495                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1496                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1497                 context_run(&ctx->context, match);
1498         } else {
1499                 index = ctx - ohci->ir_context_list;
1500                 control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
1501                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1502                 if (cycle >= 0) {
1503                         match |= (cycle & 0x07fff) << 12;
1504                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1505                 }
1506
1507                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1508                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1509                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1510                 context_run(&ctx->context, control);
1511         }
1512
1513         return 0;
1514 }
1515
1516 static int ohci_stop_iso(struct fw_iso_context *base)
1517 {
1518         struct fw_ohci *ohci = fw_ohci(base->card);
1519         struct iso_context *ctx = container_of(base, struct iso_context, base);
1520         int index;
1521
1522         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1523                 index = ctx - ohci->it_context_list;
1524                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1525         } else {
1526                 index = ctx - ohci->ir_context_list;
1527                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1528         }
1529         flush_writes(ohci);
1530         context_stop(&ctx->context);
1531
1532         return 0;
1533 }
1534
1535 static void ohci_free_iso_context(struct fw_iso_context *base)
1536 {
1537         struct fw_ohci *ohci = fw_ohci(base->card);
1538         struct iso_context *ctx = container_of(base, struct iso_context, base);
1539         unsigned long flags;
1540         int index;
1541
1542         ohci_stop_iso(base);
1543         context_release(&ctx->context);
1544         free_page((unsigned long)ctx->header);
1545
1546         spin_lock_irqsave(&ohci->lock, flags);
1547
1548         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1549                 index = ctx - ohci->it_context_list;
1550                 ohci->it_context_mask |= 1 << index;
1551         } else {
1552                 index = ctx - ohci->ir_context_list;
1553                 ohci->ir_context_mask |= 1 << index;
1554         }
1555
1556         spin_unlock_irqrestore(&ohci->lock, flags);
1557 }
1558
1559 static int
1560 ohci_queue_iso_transmit(struct fw_iso_context *base,
1561                         struct fw_iso_packet *packet,
1562                         struct fw_iso_buffer *buffer,
1563                         unsigned long payload)
1564 {
1565         struct iso_context *ctx = container_of(base, struct iso_context, base);
1566         struct descriptor *d, *last, *pd;
1567         struct fw_iso_packet *p;
1568         __le32 *header;
1569         dma_addr_t d_bus, page_bus;
1570         u32 z, header_z, payload_z, irq;
1571         u32 payload_index, payload_end_index, next_page_index;
1572         int page, end_page, i, length, offset;
1573
1574         /*
1575          * FIXME: Cycle lost behavior should be configurable: lose
1576          * packet, retransmit or terminate..
1577          */
1578
1579         p = packet;
1580         payload_index = payload;
1581
1582         if (p->skip)
1583                 z = 1;
1584         else
1585                 z = 2;
1586         if (p->header_length > 0)
1587                 z++;
1588
1589         /* Determine the first page the payload isn't contained in. */
1590         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1591         if (p->payload_length > 0)
1592                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1593         else
1594                 payload_z = 0;
1595
1596         z += payload_z;
1597
1598         /* Get header size in number of descriptors. */
1599         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
1600
1601         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1602         if (d == NULL)
1603                 return -ENOMEM;
1604
1605         if (!p->skip) {
1606                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1607                 d[0].req_count = cpu_to_le16(8);
1608
1609                 header = (__le32 *) &d[1];
1610                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
1611                                         IT_HEADER_TAG(p->tag) |
1612                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
1613                                         IT_HEADER_CHANNEL(ctx->base.channel) |
1614                                         IT_HEADER_SPEED(ctx->base.speed));
1615                 header[1] =
1616                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
1617                                                           p->payload_length));
1618         }
1619
1620         if (p->header_length > 0) {
1621                 d[2].req_count    = cpu_to_le16(p->header_length);
1622                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
1623                 memcpy(&d[z], p->header, p->header_length);
1624         }
1625
1626         pd = d + z - payload_z;
1627         payload_end_index = payload_index + p->payload_length;
1628         for (i = 0; i < payload_z; i++) {
1629                 page               = payload_index >> PAGE_SHIFT;
1630                 offset             = payload_index & ~PAGE_MASK;
1631                 next_page_index    = (page + 1) << PAGE_SHIFT;
1632                 length             =
1633                         min(next_page_index, payload_end_index) - payload_index;
1634                 pd[i].req_count    = cpu_to_le16(length);
1635
1636                 page_bus = page_private(buffer->pages[page]);
1637                 pd[i].data_address = cpu_to_le32(page_bus + offset);
1638
1639                 payload_index += length;
1640         }
1641
1642         if (p->interrupt)
1643                 irq = DESCRIPTOR_IRQ_ALWAYS;
1644         else
1645                 irq = DESCRIPTOR_NO_IRQ;
1646
1647         last = z == 2 ? d : d + z - 1;
1648         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1649                                      DESCRIPTOR_STATUS |
1650                                      DESCRIPTOR_BRANCH_ALWAYS |
1651                                      irq);
1652
1653         context_append(&ctx->context, d, z, header_z);
1654
1655         return 0;
1656 }
1657
1658 static int
1659 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1660                                   struct fw_iso_packet *packet,
1661                                   struct fw_iso_buffer *buffer,
1662                                   unsigned long payload)
1663 {
1664         struct iso_context *ctx = container_of(base, struct iso_context, base);
1665         struct db_descriptor *db = NULL;
1666         struct descriptor *d;
1667         struct fw_iso_packet *p;
1668         dma_addr_t d_bus, page_bus;
1669         u32 z, header_z, length, rest;
1670         int page, offset, packet_count, header_size;
1671
1672         /*
1673          * FIXME: Cycle lost behavior should be configurable: lose
1674          * packet, retransmit or terminate..
1675          */
1676
1677         if (packet->skip) {
1678                 d = context_get_descriptors(&ctx->context, 2, &d_bus);
1679                 if (d == NULL)
1680                         return -ENOMEM;
1681
1682                 db = (struct db_descriptor *) d;
1683                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1684                                           DESCRIPTOR_BRANCH_ALWAYS |
1685                                           DESCRIPTOR_WAIT);
1686                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1687                 context_append(&ctx->context, d, 2, 0);
1688         }
1689
1690         p = packet;
1691         z = 2;
1692
1693         /*
1694          * The OHCI controller puts the status word in the header
1695          * buffer too, so we need 4 extra bytes per packet.
1696          */
1697         packet_count = p->header_length / ctx->base.header_size;
1698         header_size = packet_count * (ctx->base.header_size + 4);
1699
1700         /* Get header size in number of descriptors. */
1701         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
1702         page     = payload >> PAGE_SHIFT;
1703         offset   = payload & ~PAGE_MASK;
1704         rest     = p->payload_length;
1705
1706         /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1707         /* FIXME: make packet-per-buffer/dual-buffer a context option */
1708         while (rest > 0) {
1709                 d = context_get_descriptors(&ctx->context,
1710                                             z + header_z, &d_bus);
1711                 if (d == NULL)
1712                         return -ENOMEM;
1713
1714                 db = (struct db_descriptor *) d;
1715                 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
1716                                           DESCRIPTOR_BRANCH_ALWAYS);
1717                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1718                 db->first_req_count = cpu_to_le16(header_size);
1719                 db->first_res_count = db->first_req_count;
1720                 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
1721
1722                 if (offset + rest < PAGE_SIZE)
1723                         length = rest;
1724                 else
1725                         length = PAGE_SIZE - offset;
1726
1727                 db->second_req_count = cpu_to_le16(length);
1728                 db->second_res_count = db->second_req_count;
1729                 page_bus = page_private(buffer->pages[page]);
1730                 db->second_buffer = cpu_to_le32(page_bus + offset);
1731
1732                 if (p->interrupt && length == rest)
1733                         db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
1734
1735                 context_append(&ctx->context, d, z, header_z);
1736                 offset = (offset + length) & ~PAGE_MASK;
1737                 rest -= length;
1738                 page++;
1739         }
1740
1741         return 0;
1742 }
1743
1744 static int
1745 ohci_queue_iso(struct fw_iso_context *base,
1746                struct fw_iso_packet *packet,
1747                struct fw_iso_buffer *buffer,
1748                unsigned long payload)
1749 {
1750         struct iso_context *ctx = container_of(base, struct iso_context, base);
1751
1752         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1753                 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1754         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
1755                 return ohci_queue_iso_receive_dualbuffer(base, packet,
1756                                                          buffer, payload);
1757         else
1758                 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1759                 return -EINVAL;
1760 }
1761
1762 static const struct fw_card_driver ohci_driver = {
1763         .name                   = ohci_driver_name,
1764         .enable                 = ohci_enable,
1765         .update_phy_reg         = ohci_update_phy_reg,
1766         .set_config_rom         = ohci_set_config_rom,
1767         .send_request           = ohci_send_request,
1768         .send_response          = ohci_send_response,
1769         .cancel_packet          = ohci_cancel_packet,
1770         .enable_phys_dma        = ohci_enable_phys_dma,
1771         .get_bus_time           = ohci_get_bus_time,
1772
1773         .allocate_iso_context   = ohci_allocate_iso_context,
1774         .free_iso_context       = ohci_free_iso_context,
1775         .queue_iso              = ohci_queue_iso,
1776         .start_iso              = ohci_start_iso,
1777         .stop_iso               = ohci_stop_iso,
1778 };
1779
1780 static int __devinit
1781 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1782 {
1783         struct fw_ohci *ohci;
1784         u32 bus_options, max_receive, link_speed;
1785         u64 guid;
1786         int err;
1787         size_t size;
1788
1789         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
1790         if (ohci == NULL) {
1791                 fw_error("Could not malloc fw_ohci data.\n");
1792                 return -ENOMEM;
1793         }
1794
1795         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1796
1797         err = pci_enable_device(dev);
1798         if (err) {
1799                 fw_error("Failed to enable OHCI hardware.\n");
1800                 goto fail_put_card;
1801         }
1802
1803         pci_set_master(dev);
1804         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1805         pci_set_drvdata(dev, ohci);
1806
1807         spin_lock_init(&ohci->lock);
1808
1809         tasklet_init(&ohci->bus_reset_tasklet,
1810                      bus_reset_tasklet, (unsigned long)ohci);
1811
1812         err = pci_request_region(dev, 0, ohci_driver_name);
1813         if (err) {
1814                 fw_error("MMIO resource unavailable\n");
1815                 goto fail_disable;
1816         }
1817
1818         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1819         if (ohci->registers == NULL) {
1820                 fw_error("Failed to remap registers\n");
1821                 err = -ENXIO;
1822                 goto fail_iomem;
1823         }
1824
1825         ar_context_init(&ohci->ar_request_ctx, ohci,
1826                         OHCI1394_AsReqRcvContextControlSet);
1827
1828         ar_context_init(&ohci->ar_response_ctx, ohci,
1829                         OHCI1394_AsRspRcvContextControlSet);
1830
1831         context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
1832                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
1833
1834         context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
1835                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
1836
1837         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1838         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1839         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1840         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1841         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1842
1843         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1844         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1845         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1846         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1847         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1848
1849         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1850                 fw_error("Out of memory for it/ir contexts.\n");
1851                 err = -ENOMEM;
1852                 goto fail_registers;
1853         }
1854
1855         /* self-id dma buffer allocation */
1856         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1857                                                SELF_ID_BUF_SIZE,
1858                                                &ohci->self_id_bus,
1859                                                GFP_KERNEL);
1860         if (ohci->self_id_cpu == NULL) {
1861                 fw_error("Out of memory for self ID buffer.\n");
1862                 err = -ENOMEM;
1863                 goto fail_registers;
1864         }
1865
1866         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1867         max_receive = (bus_options >> 12) & 0xf;
1868         link_speed = bus_options & 0x7;
1869         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1870                 reg_read(ohci, OHCI1394_GUIDLo);
1871
1872         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1873         if (err < 0)
1874                 goto fail_self_id;
1875
1876         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1877         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1878                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
1879
1880         return 0;
1881
1882  fail_self_id:
1883         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1884                           ohci->self_id_cpu, ohci->self_id_bus);
1885  fail_registers:
1886         kfree(ohci->it_context_list);
1887         kfree(ohci->ir_context_list);
1888         pci_iounmap(dev, ohci->registers);
1889  fail_iomem:
1890         pci_release_region(dev, 0);
1891  fail_disable:
1892         pci_disable_device(dev);
1893  fail_put_card:
1894         fw_card_put(&ohci->card);
1895
1896         return err;
1897 }
1898
1899 static void pci_remove(struct pci_dev *dev)
1900 {
1901         struct fw_ohci *ohci;
1902
1903         ohci = pci_get_drvdata(dev);
1904         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1905         flush_writes(ohci);
1906         fw_core_remove_card(&ohci->card);
1907
1908         /*
1909          * FIXME: Fail all pending packets here, now that the upper
1910          * layers can't queue any more.
1911          */
1912
1913         software_reset(ohci);
1914         free_irq(dev->irq, ohci);
1915         dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1916                           ohci->self_id_cpu, ohci->self_id_bus);
1917         kfree(ohci->it_context_list);
1918         kfree(ohci->ir_context_list);
1919         pci_iounmap(dev, ohci->registers);
1920         pci_release_region(dev, 0);
1921         pci_disable_device(dev);
1922         fw_card_put(&ohci->card);
1923
1924         fw_notify("Removed fw-ohci device.\n");
1925 }
1926
1927 #ifdef CONFIG_PM
1928 static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
1929 {
1930         struct fw_ohci *ohci = pci_get_drvdata(pdev);
1931         int err;
1932
1933         software_reset(ohci);
1934         free_irq(pdev->irq, ohci);
1935         err = pci_save_state(pdev);
1936         if (err) {
1937                 fw_error("pci_save_state failed with %d", err);
1938                 return err;
1939         }
1940         err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
1941         if (err) {
1942                 fw_error("pci_set_power_state failed with %d", err);
1943                 return err;
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int pci_resume(struct pci_dev *pdev)
1950 {
1951         struct fw_ohci *ohci = pci_get_drvdata(pdev);
1952         int err;
1953
1954         pci_set_power_state(pdev, PCI_D0);
1955         pci_restore_state(pdev);
1956         err = pci_enable_device(pdev);
1957         if (err) {
1958                 fw_error("pci_enable_device failed with %d", err);
1959                 return err;
1960         }
1961
1962         return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE);
1963 }
1964 #endif
1965
1966 static struct pci_device_id pci_table[] = {
1967         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1968         { }
1969 };
1970
1971 MODULE_DEVICE_TABLE(pci, pci_table);
1972
1973 static struct pci_driver fw_ohci_pci_driver = {
1974         .name           = ohci_driver_name,
1975         .id_table       = pci_table,
1976         .probe          = pci_probe,
1977         .remove         = pci_remove,
1978 #ifdef CONFIG_PM
1979         .resume         = pci_resume,
1980         .suspend        = pci_suspend,
1981 #endif
1982 };
1983
1984 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1985 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1986 MODULE_LICENSE("GPL");
1987
1988 /* Provide a module alias so root-on-sbp2 initrds don't break. */
1989 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
1990 MODULE_ALIAS("ohci1394");
1991 #endif
1992
1993 static int __init fw_ohci_init(void)
1994 {
1995         return pci_register_driver(&fw_ohci_pci_driver);
1996 }
1997
1998 static void __exit fw_ohci_cleanup(void)
1999 {
2000         pci_unregister_driver(&fw_ohci_pci_driver);
2001 }
2002
2003 module_init(fw_ohci_init);
2004 module_exit(fw_ohci_cleanup);