drivers/edac/sb_edac.c

   1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
   2  *
   3  * This driver supports the memory controllers found on the Intel
   4  * processor family Sandy Bridge.
   5  *
   6  * This file may be distributed under the terms of the
   7  * GNU General Public License version 2 only.
   8  *
   9  * Copyright (c) 2011 by:
  10  *       Mauro Carvalho Chehab
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/pci.h>
  16 #include <linux/pci_ids.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/edac.h>
  20 #include <linux/mmzone.h>
  21 #include <linux/smp.h>
  22 #include <linux/bitmap.h>
  23 #include <linux/math64.h>
  24 #include <linux/mod_devicetable.h>
  25 #include <asm/cpu_device_id.h>
  26 #include <asm/intel-family.h>
  27 #include <asm/processor.h>
  28 #include <asm/mce.h>
  29
  30 #include "edac_module.h"
  31
  32 /* Static vars */
  33 static LIST_HEAD(sbridge_edac_list);
  34
  35 /*
  36  * Alter this version for the module when modifications are made
  37  */
  38 #define SBRIDGE_REVISION    " Ver: 1.1.2 "
  39 #define EDAC_MOD_STR        "sb_edac"
  40
  41 /*
  42  * Debug macros
  43  */
  44 #define sbridge_printk(level, fmt, arg...)                      \
  45         edac_printk(level, "sbridge", fmt, ##arg)
  46
  47 #define sbridge_mc_printk(mci, level, fmt, arg...)              \
  48         edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
  49
  50 /*
  51  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  52  */
  53 #define GET_BITFIELD(v, lo, hi) \
  54         (((v) & GENMASK_ULL(hi, lo)) >> (lo))
  55
  56 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
  57 static const u32 sbridge_dram_rule[] = {
  58         0x80, 0x88, 0x90, 0x98, 0xa0,
  59         0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
  60 };
  61
  62 static const u32 ibridge_dram_rule[] = {
  63         0x60, 0x68, 0x70, 0x78, 0x80,
  64         0x88, 0x90, 0x98, 0xa0, 0xa8,
  65         0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
  66         0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
  67 };
  68
  69 static const u32 knl_dram_rule[] = {
  70         0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
  71         0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
  72         0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
  73         0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
  74         0x100, 0x108, 0x110, 0x118,   /* 20-23 */
  75 };
  76
  77 #define DRAM_RULE_ENABLE(reg)   GET_BITFIELD(reg, 0,  0)
  78 #define A7MODE(reg)             GET_BITFIELD(reg, 26, 26)
  79
  80 static char *show_dram_attr(u32 attr)
  81 {
  82         switch (attr) {
  83                 case 0:
  84                         return "DRAM";
  85                 case 1:
  86                         return "MMCFG";
  87                 case 2:
  88                         return "NXM";
  89                 default:
  90                         return "unknown";
  91         }
  92 }
  93
  94 static const u32 sbridge_interleave_list[] = {
  95         0x84, 0x8c, 0x94, 0x9c, 0xa4,
  96         0xac, 0xb4, 0xbc, 0xc4, 0xcc,
  97 };
  98
  99 static const u32 ibridge_interleave_list[] = {
 100         0x64, 0x6c, 0x74, 0x7c, 0x84,
 101         0x8c, 0x94, 0x9c, 0xa4, 0xac,
 102         0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
 103         0xdc, 0xe4, 0xec, 0xf4, 0xfc,
 104 };
 105
 106 static const u32 knl_interleave_list[] = {
 107         0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
 108         0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
 109         0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
 110         0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
 111         0x104, 0x10c, 0x114, 0x11c,   /* 20-23 */
 112 };
 113
 114 struct interleave_pkg {
 115         unsigned char start;
 116         unsigned char end;
 117 };
 118
 119 static const struct interleave_pkg sbridge_interleave_pkg[] = {
 120         { 0, 2 },
 121         { 3, 5 },
 122         { 8, 10 },
 123         { 11, 13 },
 124         { 16, 18 },
 125         { 19, 21 },
 126         { 24, 26 },
 127         { 27, 29 },
 128 };
 129
 130 static const struct interleave_pkg ibridge_interleave_pkg[] = {
 131         { 0, 3 },
 132         { 4, 7 },
 133         { 8, 11 },
 134         { 12, 15 },
 135         { 16, 19 },
 136         { 20, 23 },
 137         { 24, 27 },
 138         { 28, 31 },
 139 };
 140
 141 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
 142                           int interleave)
 143 {
 144         return GET_BITFIELD(reg, table[interleave].start,
 145                             table[interleave].end);
 146 }
 147
 148 /* Devices 12 Function 7 */
 149
 150 #define TOLM            0x80
 151 #define TOHM            0x84
 152 #define HASWELL_TOLM    0xd0
 153 #define HASWELL_TOHM_0  0xd4
 154 #define HASWELL_TOHM_1  0xd8
 155 #define KNL_TOLM        0xd0
 156 #define KNL_TOHM_0      0xd4
 157 #define KNL_TOHM_1      0xd8
 158
 159 #define GET_TOLM(reg)           ((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
 160 #define GET_TOHM(reg)           ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
 161
 162 /* Device 13 Function 6 */
 163
 164 #define SAD_TARGET      0xf0
 165
 166 #define SOURCE_ID(reg)          GET_BITFIELD(reg, 9, 11)
 167
 168 #define SOURCE_ID_KNL(reg)      GET_BITFIELD(reg, 12, 14)
 169
 170 #define SAD_CONTROL     0xf4
 171
 172 /* Device 14 function 0 */
 173
 174 static const u32 tad_dram_rule[] = {
 175         0x40, 0x44, 0x48, 0x4c,
 176         0x50, 0x54, 0x58, 0x5c,
 177         0x60, 0x64, 0x68, 0x6c,
 178 };
 179 #define MAX_TAD ARRAY_SIZE(tad_dram_rule)
 180
 181 #define TAD_LIMIT(reg)          ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
 182 #define TAD_SOCK(reg)           GET_BITFIELD(reg, 10, 11)
 183 #define TAD_CH(reg)             GET_BITFIELD(reg,  8,  9)
 184 #define TAD_TGT3(reg)           GET_BITFIELD(reg,  6,  7)
 185 #define TAD_TGT2(reg)           GET_BITFIELD(reg,  4,  5)
 186 #define TAD_TGT1(reg)           GET_BITFIELD(reg,  2,  3)
 187 #define TAD_TGT0(reg)           GET_BITFIELD(reg,  0,  1)
 188
 189 /* Device 15, function 0 */
 190
 191 #define MCMTR                   0x7c
 192 #define KNL_MCMTR               0x624
 193
 194 #define IS_ECC_ENABLED(mcmtr)           GET_BITFIELD(mcmtr, 2, 2)
 195 #define IS_LOCKSTEP_ENABLED(mcmtr)      GET_BITFIELD(mcmtr, 1, 1)
 196 #define IS_CLOSE_PG(mcmtr)              GET_BITFIELD(mcmtr, 0, 0)
 197
 198 /* Device 15, function 1 */
 199
 200 #define RASENABLES              0xac
 201 #define IS_MIRROR_ENABLED(reg)          GET_BITFIELD(reg, 0, 0)
 202
 203 /* Device 15, functions 2-5 */
 204
 205 static const int mtr_regs[] = {
 206         0x80, 0x84, 0x88,
 207 };
 208
 209 static const int knl_mtr_reg = 0xb60;
 210
 211 #define RANK_DISABLE(mtr)               GET_BITFIELD(mtr, 16, 19)
 212 #define IS_DIMM_PRESENT(mtr)            GET_BITFIELD(mtr, 14, 14)
 213 #define RANK_CNT_BITS(mtr)              GET_BITFIELD(mtr, 12, 13)
 214 #define RANK_WIDTH_BITS(mtr)            GET_BITFIELD(mtr, 2, 4)
 215 #define COL_WIDTH_BITS(mtr)             GET_BITFIELD(mtr, 0, 1)
 216
 217 static const u32 tad_ch_nilv_offset[] = {
 218         0x90, 0x94, 0x98, 0x9c,
 219         0xa0, 0xa4, 0xa8, 0xac,
 220         0xb0, 0xb4, 0xb8, 0xbc,
 221 };
 222 #define CHN_IDX_OFFSET(reg)             GET_BITFIELD(reg, 28, 29)
 223 #define TAD_OFFSET(reg)                 (GET_BITFIELD(reg,  6, 25) << 26)
 224
 225 static const u32 rir_way_limit[] = {
 226         0x108, 0x10c, 0x110, 0x114, 0x118,
 227 };
 228 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
 229
 230 #define IS_RIR_VALID(reg)       GET_BITFIELD(reg, 31, 31)
 231 #define RIR_WAY(reg)            GET_BITFIELD(reg, 28, 29)
 232
 233 #define MAX_RIR_WAY     8
 234
 235 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
 236         { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
 237         { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
 238         { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
 239         { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
 240         { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
 241 };
 242
 243 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
 244         GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
 245
 246 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
 247         GET_BITFIELD(reg,  2, 15) : GET_BITFIELD(reg,  2, 14))
 248
 249 /* Device 16, functions 2-7 */
 250
 251 /*
 252  * FIXME: Implement the error count reads directly
 253  */
 254
 255 static const u32 correrrcnt[] = {
 256         0x104, 0x108, 0x10c, 0x110,
 257 };
 258
 259 #define RANK_ODD_OV(reg)                GET_BITFIELD(reg, 31, 31)
 260 #define RANK_ODD_ERR_CNT(reg)           GET_BITFIELD(reg, 16, 30)
 261 #define RANK_EVEN_OV(reg)               GET_BITFIELD(reg, 15, 15)
 262 #define RANK_EVEN_ERR_CNT(reg)          GET_BITFIELD(reg,  0, 14)
 263
 264 static const u32 correrrthrsld[] = {
 265         0x11c, 0x120, 0x124, 0x128,
 266 };
 267
 268 #define RANK_ODD_ERR_THRSLD(reg)        GET_BITFIELD(reg, 16, 30)
 269 #define RANK_EVEN_ERR_THRSLD(reg)       GET_BITFIELD(reg,  0, 14)
 270
 271
 272 /* Device 17, function 0 */
 273
 274 #define SB_RANK_CFG_A           0x0328
 275
 276 #define IB_RANK_CFG_A           0x0320
 277
 278 /*
 279  * sbridge structs
 280  */
 281
 282 #define NUM_CHANNELS            4       /* Max channels per MC */
 283 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 284 #define KNL_MAX_CHAS            38      /* KNL max num. of Cache Home Agents */
 285 #define KNL_MAX_CHANNELS        6       /* KNL max num. of PCI channels */
 286 #define KNL_MAX_EDCS            8       /* Embedded DRAM controllers */
 287 #define CHANNEL_UNSPECIFIED     0xf     /* Intel IA32 SDM 15-14 */
 288
 289 enum type {
 290         SANDY_BRIDGE,
 291         IVY_BRIDGE,
 292         HASWELL,
 293         BROADWELL,
 294         KNIGHTS_LANDING,
 295 };
 296
 297 enum domain {
 298         IMC0 = 0,
 299         IMC1,
 300         SOCK,
 301 };
 302
 303 enum mirroring_mode {
 304         NON_MIRRORING,
 305         ADDR_RANGE_MIRRORING,
 306         FULL_MIRRORING,
 307 };
 308
 309 struct sbridge_pvt;
 310 struct sbridge_info {
 311         enum type       type;
 312         u32             mcmtr;
 313         u32             rankcfgr;
 314         u64             (*get_tolm)(struct sbridge_pvt *pvt);
 315         u64             (*get_tohm)(struct sbridge_pvt *pvt);
 316         u64             (*rir_limit)(u32 reg);
 317         u64             (*sad_limit)(u32 reg);
 318         u32             (*interleave_mode)(u32 reg);
 319         u32             (*dram_attr)(u32 reg);
 320         const u32       *dram_rule;
 321         const u32       *interleave_list;
 322         const struct interleave_pkg *interleave_pkg;
 323         u8              max_sad;
 324         u8              max_interleave;
 325         u8              (*get_node_id)(struct sbridge_pvt *pvt);
 326         enum mem_type   (*get_memory_type)(struct sbridge_pvt *pvt);
 327         enum dev_type   (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
 328         struct pci_dev  *pci_vtd;
 329 };
 330
 331 struct sbridge_channel {
 332         u32             ranks;
 333         u32             dimms;
 334 };
 335
 336 struct pci_id_descr {
 337         int                     dev_id;
 338         int                     optional;
 339         enum domain             dom;
 340 };
 341
 342 struct pci_id_table {
 343         const struct pci_id_descr       *descr;
 344         int                             n_devs_per_imc;
 345         int                             n_devs_per_sock;
 346         int                             n_imcs_per_sock;
 347         enum type                       type;
 348 };
 349
 350 struct sbridge_dev {
 351         struct list_head        list;
 352         u8                      bus, mc;
 353         u8                      node_id, source_id;
 354         struct pci_dev          **pdev;
 355         enum domain             dom;
 356         int                     n_devs;
 357         int                     i_devs;
 358         struct mem_ctl_info     *mci;
 359 };
 360
 361 struct knl_pvt {
 362         struct pci_dev          *pci_cha[KNL_MAX_CHAS];
 363         struct pci_dev          *pci_channel[KNL_MAX_CHANNELS];
 364         struct pci_dev          *pci_mc0;
 365         struct pci_dev          *pci_mc1;
 366         struct pci_dev          *pci_mc0_misc;
 367         struct pci_dev          *pci_mc1_misc;
 368         struct pci_dev          *pci_mc_info; /* tolm, tohm */
 369 };
 370
 371 struct sbridge_pvt {
 372         /* Devices per socket */
 373         struct pci_dev          *pci_ddrio;
 374         struct pci_dev          *pci_sad0, *pci_sad1;
 375         struct pci_dev          *pci_br0, *pci_br1;
 376         /* Devices per memory controller */
 377         struct pci_dev          *pci_ha, *pci_ta, *pci_ras;
 378         struct pci_dev          *pci_tad[NUM_CHANNELS];
 379
 380         struct sbridge_dev      *sbridge_dev;
 381
 382         struct sbridge_info     info;
 383         struct sbridge_channel  channel[NUM_CHANNELS];
 384
 385         /* Memory type detection */
 386         bool                    is_cur_addr_mirrored, is_lockstep, is_close_pg;
 387         bool                    is_chan_hash;
 388         enum mirroring_mode     mirror_mode;
 389
 390         /* Memory description */
 391         u64                     tolm, tohm;
 392         struct knl_pvt knl;
 393 };
 394
 395 #define PCI_DESCR(device_id, opt, domain)       \
 396         .dev_id = (device_id),          \
 397         .optional = opt,        \
 398         .dom = domain
 399
 400 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
 401                 /* Processor Home Agent */
 402         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0,   0, IMC0) },
 403
 404                 /* Memory controller */
 405         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA,    0, IMC0) },
 406         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS,   0, IMC0) },
 407         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0,  0, IMC0) },
 408         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1,  0, IMC0) },
 409         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2,  0, IMC0) },
 410         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3,  0, IMC0) },
 411         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1, SOCK) },
 412
 413                 /* System Address Decoder */
 414         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0,      0, SOCK) },
 415         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1,      0, SOCK) },
 416
 417                 /* Broadcast Registers */
 418         { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR,        0, SOCK) },
 419 };
 420
 421 #define PCI_ID_TABLE_ENTRY(A, N, M, T) {        \
 422         .descr = A,                     \
 423         .n_devs_per_imc = N,    \
 424         .n_devs_per_sock = ARRAY_SIZE(A),       \
 425         .n_imcs_per_sock = M,   \
 426         .type = T                       \
 427 }
 428
 429 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
 430         PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge, ARRAY_SIZE(pci_dev_descr_sbridge), 1, SANDY_BRIDGE),
 431         {0,}                    /* 0 terminated list. */
 432 };
 433
 434 /* This changes depending if 1HA or 2HA:
 435  * 1HA:
 436  *      0x0eb8 (17.0) is DDRIO0
 437  * 2HA:
 438  *      0x0ebc (17.4) is DDRIO0
 439  */
 440 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0      0x0eb8
 441 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0      0x0ebc
 442
 443 /* pci ids */
 444 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0             0x0ea0
 445 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA          0x0ea8
 446 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS         0x0e71
 447 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0        0x0eaa
 448 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1        0x0eab
 449 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2        0x0eac
 450 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3        0x0ead
 451 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD                 0x0ec8
 452 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0                 0x0ec9
 453 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1                 0x0eca
 454 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1             0x0e60
 455 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA          0x0e68
 456 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS         0x0e79
 457 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0        0x0e6a
 458 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1        0x0e6b
 459 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2        0x0e6c
 460 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3        0x0e6d
 461
 462 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
 463                 /* Processor Home Agent */
 464         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0,        0, IMC0) },
 465         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1,        1, IMC1) },
 466
 467                 /* Memory controller */
 468         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA,     0, IMC0) },
 469         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS,    0, IMC0) },
 470         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0,   0, IMC0) },
 471         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1,   0, IMC0) },
 472         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2,   0, IMC0) },
 473         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3,   0, IMC0) },
 474
 475                 /* Optional, mode 2HA */
 476         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA,     1, IMC1) },
 477         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS,    1, IMC1) },
 478         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0,   1, IMC1) },
 479         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1,   1, IMC1) },
 480         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2,   1, IMC1) },
 481         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3,   1, IMC1) },
 482
 483         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1, SOCK) },
 484         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1, SOCK) },
 485
 486                 /* System Address Decoder */
 487         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD,            0, SOCK) },
 488
 489                 /* Broadcast Registers */
 490         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0,            1, SOCK) },
 491         { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1,            0, SOCK) },
 492
 493 };
 494
 495 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
 496         PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge, 12, 2, IVY_BRIDGE),
 497         {0,}                    /* 0 terminated list. */
 498 };
 499
 500 /* Haswell support */
 501 /* EN processor:
 502  *      - 1 IMC
 503  *      - 3 DDR3 channels, 2 DPC per channel
 504  * EP processor:
 505  *      - 1 or 2 IMC
 506  *      - 4 DDR4 channels, 3 DPC per channel
 507  * EP 4S processor:
 508  *      - 2 IMC
 509  *      - 4 DDR4 channels, 3 DPC per channel
 510  * EX processor:
 511  *      - 2 IMC
 512  *      - each IMC interfaces with a SMI 2 channel
 513  *      - each SMI channel interfaces with a scalable memory buffer
 514  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 515  */
 516 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
 517 #define HASWELL_HASYSDEFEATURE2 0x84
 518 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
 519 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0     0x2fa0
 520 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1     0x2f60
 521 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA  0x2fa8
 522 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM  0x2f71
 523 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA  0x2f68
 524 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM  0x2f79
 525 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
 526 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
 527 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
 528 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
 529 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
 530 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
 531 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
 532 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
 533 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
 534 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
 535 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
 536 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
 537 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
 538 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
 539 static const struct pci_id_descr pci_dev_descr_haswell[] = {
 540         /* first item must be the HA */
 541         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0,      0, IMC0) },
 542         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1,      1, IMC1) },
 543
 544         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA,   0, IMC0) },
 545         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM,   0, IMC0) },
 546         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0, IMC0) },
 547         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0, IMC0) },
 548         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1, IMC0) },
 549         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1, IMC0) },
 550
 551         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA,   1, IMC1) },
 552         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM,   1, IMC1) },
 553         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1, IMC1) },
 554         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1, IMC1) },
 555         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1, IMC1) },
 556         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1, IMC1) },
 557
 558         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0, SOCK) },
 559         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0, SOCK) },
 560         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0,   1, SOCK) },
 561         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1,   1, SOCK) },
 562         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2,   1, SOCK) },
 563         { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3,   1, SOCK) },
 564 };
 565
 566 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
 567         PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell, 13, 2, HASWELL),
 568         {0,}                    /* 0 terminated list. */
 569 };
 570
 571 /* Knight's Landing Support */
 572 /*
 573  * KNL's memory channels are swizzled between memory controllers.
 574  * MC0 is mapped to CH3,4,5 and MC1 is mapped to CH0,1,2
 575  */
 576 #define knl_channel_remap(mc, chan) ((mc) ? (chan) : (chan) + 3)
 577
 578 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
 579 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC       0x7840
 580 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
 581 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN     0x7843
 582 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
 583 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA       0x7844
 584 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
 585 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0     0x782a
 586 /* SAD target - 1-29-1 (1 of these) */
 587 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1     0x782b
 588 /* Caching / Home Agent */
 589 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA      0x782c
 590 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
 591 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM    0x7810
 592
 593 /*
 594  * KNL differs from SB, IB, and Haswell in that it has multiple
 595  * instances of the same device with the same device ID, so we handle that
 596  * by creating as many copies in the table as we expect to find.
 597  * (Like device ID must be grouped together.)
 598  */
 599
 600 static const struct pci_id_descr pci_dev_descr_knl[] = {
 601         [0 ... 1]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC,    0, IMC0)},
 602         [2 ... 7]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN,  0, IMC0) },
 603         [8]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA,    0, IMC0) },
 604         [9]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0, IMC0) },
 605         [10]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0,  0, SOCK) },
 606         [11]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1,  0, SOCK) },
 607         [12 ... 49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA,   0, SOCK) },
 608 };
 609
 610 static const struct pci_id_table pci_dev_descr_knl_table[] = {
 611         PCI_ID_TABLE_ENTRY(pci_dev_descr_knl, ARRAY_SIZE(pci_dev_descr_knl), 1, KNIGHTS_LANDING),
 612         {0,}
 613 };
 614
 615 /*
 616  * Broadwell support
 617  *
 618  * DE processor:
 619  *      - 1 IMC
 620  *      - 2 DDR3 channels, 2 DPC per channel
 621  * EP processor:
 622  *      - 1 or 2 IMC
 623  *      - 4 DDR4 channels, 3 DPC per channel
 624  * EP 4S processor:
 625  *      - 2 IMC
 626  *      - 4 DDR4 channels, 3 DPC per channel
 627  * EX processor:
 628  *      - 2 IMC
 629  *      - each IMC interfaces with a SMI 2 channel
 630  *      - each SMI channel interfaces with a scalable memory buffer
 631  *      - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
 632  */
 633 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
 634 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0   0x6fa0
 635 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1   0x6f60
 636 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA        0x6fa8
 637 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM        0x6f71
 638 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA        0x6f68
 639 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM        0x6f79
 640 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
 641 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
 642 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
 643 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
 644 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
 645 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
 646 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
 647 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
 648 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
 649 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
 650 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
 651
 652 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
 653         /* first item must be the HA */
 654         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0,      0, IMC0) },
 655         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1,      1, IMC1) },
 656
 657         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA,   0, IMC0) },
 658         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM,   0, IMC0) },
 659         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0, IMC0) },
 660         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0, IMC0) },
 661         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1, IMC0) },
 662         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1, IMC0) },
 663
 664         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA,   1, IMC1) },
 665         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM,   1, IMC1) },
 666         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1, IMC1) },
 667         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1, IMC1) },
 668         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1, IMC1) },
 669         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1, IMC1) },
 670
 671         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0, SOCK) },
 672         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0, SOCK) },
 673         { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0,   1, SOCK) },
 674 };
 675
 676 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
 677         PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell, 10, 2, BROADWELL),
 678         {0,}                    /* 0 terminated list. */
 679 };
 680
 681
 682 /****************************************************************************
 683                         Ancillary status routines
 684  ****************************************************************************/
 685
 686 static inline int numrank(enum type type, u32 mtr)
 687 {
 688         int ranks = (1 << RANK_CNT_BITS(mtr));
 689         int max = 4;
 690
 691         if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
 692                 max = 8;
 693
 694         if (ranks > max) {
 695                 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
 696                          ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
 697                 return -EINVAL;
 698         }
 699
 700         return ranks;
 701 }
 702
 703 static inline int numrow(u32 mtr)
 704 {
 705         int rows = (RANK_WIDTH_BITS(mtr) + 12);
 706
 707         if (rows < 13 || rows > 18) {
 708                 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
 709                          rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
 710                 return -EINVAL;
 711         }
 712
 713         return 1 << rows;
 714 }
 715
 716 static inline int numcol(u32 mtr)
 717 {
 718         int cols = (COL_WIDTH_BITS(mtr) + 10);
 719
 720         if (cols > 12) {
 721                 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
 722                          cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
 723                 return -EINVAL;
 724         }
 725
 726         return 1 << cols;
 727 }
 728
 729 static struct sbridge_dev *get_sbridge_dev(u8 bus, enum domain dom, int multi_bus,
 730                                            struct sbridge_dev *prev)
 731 {
 732         struct sbridge_dev *sbridge_dev;
 733
 734         /*
 735          * If we have devices scattered across several busses that pertain
 736          * to the same memory controller, we'll lump them all together.
 737          */
 738         if (multi_bus) {
 739                 return list_first_entry_or_null(&sbridge_edac_list,
 740                                 struct sbridge_dev, list);
 741         }
 742
 743         sbridge_dev = list_entry(prev ? prev->list.next
 744                                       : sbridge_edac_list.next, struct sbridge_dev, list);
 745
 746         list_for_each_entry_from(sbridge_dev, &sbridge_edac_list, list) {
 747                 if (sbridge_dev->bus == bus && (dom == SOCK || dom == sbridge_dev->dom))
 748                         return sbridge_dev;
 749         }
 750
 751         return NULL;
 752 }
 753
 754 static struct sbridge_dev *alloc_sbridge_dev(u8 bus, enum domain dom,
 755                                              const struct pci_id_table *table)
 756 {
 757         struct sbridge_dev *sbridge_dev;
 758
 759         sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
 760         if (!sbridge_dev)
 761                 return NULL;
 762
 763         sbridge_dev->pdev = kcalloc(table->n_devs_per_imc,
 764                                     sizeof(*sbridge_dev->pdev),
 765                                     GFP_KERNEL);
 766         if (!sbridge_dev->pdev) {
 767                 kfree(sbridge_dev);
 768                 return NULL;
 769         }
 770
 771         sbridge_dev->bus = bus;
 772         sbridge_dev->dom = dom;
 773         sbridge_dev->n_devs = table->n_devs_per_imc;
 774         list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
 775
 776         return sbridge_dev;
 777 }
 778
 779 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
 780 {
 781         list_del(&sbridge_dev->list);
 782         kfree(sbridge_dev->pdev);
 783         kfree(sbridge_dev);
 784 }
 785
 786 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
 787 {
 788         u32 reg;
 789
 790         /* Address range is 32:28 */
 791         pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
 792         return GET_TOLM(reg);
 793 }
 794
 795 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
 796 {
 797         u32 reg;
 798
 799         pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
 800         return GET_TOHM(reg);
 801 }
 802
 803 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
 804 {
 805         u32 reg;
 806
 807         pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
 808
 809         return GET_TOLM(reg);
 810 }
 811
 812 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
 813 {
 814         u32 reg;
 815
 816         pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
 817
 818         return GET_TOHM(reg);
 819 }
 820
 821 static u64 rir_limit(u32 reg)
 822 {
 823         return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
 824 }
 825
 826 static u64 sad_limit(u32 reg)
 827 {
 828         return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
 829 }
 830
 831 static u32 interleave_mode(u32 reg)
 832 {
 833         return GET_BITFIELD(reg, 1, 1);
 834 }
 835
 836 static u32 dram_attr(u32 reg)
 837 {
 838         return GET_BITFIELD(reg, 2, 3);
 839 }
 840
 841 static u64 knl_sad_limit(u32 reg)
 842 {
 843         return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
 844 }
 845
 846 static u32 knl_interleave_mode(u32 reg)
 847 {
 848         return GET_BITFIELD(reg, 1, 2);
 849 }
 850
 851 static const char * const knl_intlv_mode[] = {
 852         "[8:6]", "[10:8]", "[14:12]", "[32:30]"
 853 };
 854
 855 static const char *get_intlv_mode_str(u32 reg, enum type t)
 856 {
 857         if (t == KNIGHTS_LANDING)
 858                 return knl_intlv_mode[knl_interleave_mode(reg)];
 859         else
 860                 return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]";
 861 }
 862
 863 static u32 dram_attr_knl(u32 reg)
 864 {
 865         return GET_BITFIELD(reg, 3, 4);
 866 }
 867
 868
 869 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
 870 {
 871         u32 reg;
 872         enum mem_type mtype;
 873
 874         if (pvt->pci_ddrio) {
 875                 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
 876                                       &reg);
 877                 if (GET_BITFIELD(reg, 11, 11))
 878                         /* FIXME: Can also be LRDIMM */
 879                         mtype = MEM_RDDR3;
 880                 else
 881                         mtype = MEM_DDR3;
 882         } else
 883                 mtype = MEM_UNKNOWN;
 884
 885         return mtype;
 886 }
 887
 888 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
 889 {
 890         u32 reg;
 891         bool registered = false;
 892         enum mem_type mtype = MEM_UNKNOWN;
 893
 894         if (!pvt->pci_ddrio)
 895                 goto out;
 896
 897         pci_read_config_dword(pvt->pci_ddrio,
 898                               HASWELL_DDRCRCLKCONTROLS, &reg);
 899         /* Is_Rdimm */
 900         if (GET_BITFIELD(reg, 16, 16))
 901                 registered = true;
 902
 903         pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
 904         if (GET_BITFIELD(reg, 14, 14)) {
 905                 if (registered)
 906                         mtype = MEM_RDDR4;
 907                 else
 908                         mtype = MEM_DDR4;
 909         } else {
 910                 if (registered)
 911                         mtype = MEM_RDDR3;
 912                 else
 913                         mtype = MEM_DDR3;
 914         }
 915
 916 out:
 917         return mtype;
 918 }
 919
 920 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
 921 {
 922         /* for KNL value is fixed */
 923         return DEV_X16;
 924 }
 925
 926 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 927 {
 928         /* there's no way to figure out */
 929         return DEV_UNKNOWN;
 930 }
 931
 932 static enum dev_type __ibridge_get_width(u32 mtr)
 933 {
 934         enum dev_type type;
 935
 936         switch (mtr) {
 937         case 3:
 938                 type = DEV_UNKNOWN;
 939                 break;
 940         case 2:
 941                 type = DEV_X16;
 942                 break;
 943         case 1:
 944                 type = DEV_X8;
 945                 break;
 946         case 0:
 947                 type = DEV_X4;
 948                 break;
 949         }
 950
 951         return type;
 952 }
 953
 954 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 955 {
 956         /*
 957          * ddr3_width on the documentation but also valid for DDR4 on
 958          * Haswell
 959          */
 960         return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
 961 }
 962
 963 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
 964 {
 965         /* ddr3_width on the documentation but also valid for DDR4 */
 966         return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
 967 }
 968
 969 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
 970 {
 971         /* DDR4 RDIMMS and LRDIMMS are supported */
 972         return MEM_RDDR4;
 973 }
 974
 975 static u8 get_node_id(struct sbridge_pvt *pvt)
 976 {
 977         u32 reg;
 978         pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
 979         return GET_BITFIELD(reg, 0, 2);
 980 }
 981
 982 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
 983 {
 984         u32 reg;
 985
 986         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 987         return GET_BITFIELD(reg, 0, 3);
 988 }
 989
 990 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
 991 {
 992         u32 reg;
 993
 994         pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
 995         return GET_BITFIELD(reg, 0, 2);
 996 }
 997
 998
 999 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1000 {
1001         u32 reg;
1002
1003         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
1004         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1005 }
1006
1007 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1008 {
1009         u64 rc;
1010         u32 reg;
1011
1012         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1013         rc = GET_BITFIELD(reg, 26, 31);
1014         pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1015         rc = ((reg << 6) | rc) << 26;
1016
1017         return rc | 0x1ffffff;
1018 }
1019
1020 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1021 {
1022         u32 reg;
1023
1024         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1025         return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1026 }
1027
1028 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1029 {
1030         u64 rc;
1031         u32 reg_lo, reg_hi;
1032
1033         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1034         pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1035         rc = ((u64)reg_hi << 32) | reg_lo;
1036         return rc | 0x3ffffff;
1037 }
1038
1039
1040 static u64 haswell_rir_limit(u32 reg)
1041 {
1042         return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
1043 }
1044
1045 static inline u8 sad_pkg_socket(u8 pkg)
1046 {
1047         /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1048         return ((pkg >> 3) << 2) | (pkg & 0x3);
1049 }
1050
1051 static inline u8 sad_pkg_ha(u8 pkg)
1052 {
1053         return (pkg >> 2) & 0x1;
1054 }
1055
1056 static int haswell_chan_hash(int idx, u64 addr)
1057 {
1058         int i;
1059
1060         /*
1061          * XOR even bits from 12:26 to bit0 of idx,
1062          *     odd bits from 13:27 to bit1
1063          */
1064         for (i = 12; i < 28; i += 2)
1065                 idx ^= (addr >> i) & 3;
1066
1067         return idx;
1068 }
1069
1070 /* Low bits of TAD limit, and some metadata. */
1071 static const u32 knl_tad_dram_limit_lo[] = {
1072         0x400, 0x500, 0x600, 0x700,
1073         0x800, 0x900, 0xa00, 0xb00,
1074 };
1075
1076 /* Low bits of TAD offset. */
1077 static const u32 knl_tad_dram_offset_lo[] = {
1078         0x404, 0x504, 0x604, 0x704,
1079         0x804, 0x904, 0xa04, 0xb04,
1080 };
1081
1082 /* High 16 bits of TAD limit and offset. */
1083 static const u32 knl_tad_dram_hi[] = {
1084         0x408, 0x508, 0x608, 0x708,
1085         0x808, 0x908, 0xa08, 0xb08,
1086 };
1087
1088 /* Number of ways a tad entry is interleaved. */
1089 static const u32 knl_tad_ways[] = {
1090         8, 6, 4, 3, 2, 1,
1091 };
1092
1093 /*
1094  * Retrieve the n'th Target Address Decode table entry
1095  * from the memory controller's TAD table.
1096  *
1097  * @pvt:        driver private data
1098  * @entry:      which entry you want to retrieve
1099  * @mc:         which memory controller (0 or 1)
1100  * @offset:     output tad range offset
1101  * @limit:      output address of first byte above tad range
1102  * @ways:       output number of interleave ways
1103  *
1104  * The offset value has curious semantics.  It's a sort of running total
1105  * of the sizes of all the memory regions that aren't mapped in this
1106  * tad table.
1107  */
1108 static int knl_get_tad(const struct sbridge_pvt *pvt,
1109                 const int entry,
1110                 const int mc,
1111                 u64 *offset,
1112                 u64 *limit,
1113                 int *ways)
1114 {
1115         u32 reg_limit_lo, reg_offset_lo, reg_hi;
1116         struct pci_dev *pci_mc;
1117         int way_id;
1118
1119         switch (mc) {
1120         case 0:
1121                 pci_mc = pvt->knl.pci_mc0;
1122                 break;
1123         case 1:
1124                 pci_mc = pvt->knl.pci_mc1;
1125                 break;
1126         default:
1127                 WARN_ON(1);
1128                 return -EINVAL;
1129         }
1130
1131         pci_read_config_dword(pci_mc,
1132                         knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1133         pci_read_config_dword(pci_mc,
1134                         knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1135         pci_read_config_dword(pci_mc,
1136                         knl_tad_dram_hi[entry], &reg_hi);
1137
1138         /* Is this TAD entry enabled? */
1139         if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1140                 return -ENODEV;
1141
1142         way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1143
1144         if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1145                 *ways = knl_tad_ways[way_id];
1146         } else {
1147                 *ways = 0;
1148                 sbridge_printk(KERN_ERR,
1149                                 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1150                                 way_id);
1151                 return -ENODEV;
1152         }
1153
1154         /*
1155          * The least significant 6 bits of base and limit are truncated.
1156          * For limit, we fill the missing bits with 1s.
1157          */
1158         *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1159                                 ((u64) GET_BITFIELD(reg_hi, 0,  15) << 32);
1160         *limit = ((u64) GET_BITFIELD(reg_limit_lo,  6, 31) << 6) | 63 |
1161                                 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1162
1163         return 0;
1164 }
1165
1166 /* Determine which memory controller is responsible for a given channel. */
1167 static int knl_channel_mc(int channel)
1168 {
1169         WARN_ON(channel < 0 || channel >= 6);
1170
1171         return channel < 3 ? 1 : 0;
1172 }
1173
1174 /*
1175  * Get the Nth entry from EDC_ROUTE_TABLE register.
1176  * (This is the per-tile mapping of logical interleave targets to
1177  *  physical EDC modules.)
1178  *
1179  * entry 0: 0:2
1180  *       1: 3:5
1181  *       2: 6:8
1182  *       3: 9:11
1183  *       4: 12:14
1184  *       5: 15:17
1185  *       6: 18:20
1186  *       7: 21:23
1187  * reserved: 24:31
1188  */
1189 static u32 knl_get_edc_route(int entry, u32 reg)
1190 {
1191         WARN_ON(entry >= KNL_MAX_EDCS);
1192         return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1193 }
1194
1195 /*
1196  * Get the Nth entry from MC_ROUTE_TABLE register.
1197  * (This is the per-tile mapping of logical interleave targets to
1198  *  physical DRAM channels modules.)
1199  *
1200  * entry 0: mc 0:2   channel 18:19
1201  *       1: mc 3:5   channel 20:21
1202  *       2: mc 6:8   channel 22:23
1203  *       3: mc 9:11  channel 24:25
1204  *       4: mc 12:14 channel 26:27
1205  *       5: mc 15:17 channel 28:29
1206  * reserved: 30:31
1207  *
1208  * Though we have 3 bits to identify the MC, we should only see
1209  * the values 0 or 1.
1210  */
1211
1212 static u32 knl_get_mc_route(int entry, u32 reg)
1213 {
1214         int mc, chan;
1215
1216         WARN_ON(entry >= KNL_MAX_CHANNELS);
1217
1218         mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1219         chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1220
1221         return knl_channel_remap(mc, chan);
1222 }
1223
1224 /*
1225  * Render the EDC_ROUTE register in human-readable form.
1226  * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1227  */
1228 static void knl_show_edc_route(u32 reg, char *s)
1229 {
1230         int i;
1231
1232         for (i = 0; i < KNL_MAX_EDCS; i++) {
1233                 s[i*2] = knl_get_edc_route(i, reg) + '0';
1234                 s[i*2+1] = '-';
1235         }
1236
1237         s[KNL_MAX_EDCS*2 - 1] = '\0';
1238 }
1239
1240 /*
1241  * Render the MC_ROUTE register in human-readable form.
1242  * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1243  */
1244 static void knl_show_mc_route(u32 reg, char *s)
1245 {
1246         int i;
1247
1248         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1249                 s[i*2] = knl_get_mc_route(i, reg) + '0';
1250                 s[i*2+1] = '-';
1251         }
1252
1253         s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1254 }
1255
1256 #define KNL_EDC_ROUTE 0xb8
1257 #define KNL_MC_ROUTE 0xb4
1258
1259 /* Is this dram rule backed by regular DRAM in flat mode? */
1260 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1261
1262 /* Is this dram rule cached? */
1263 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1264
1265 /* Is this rule backed by edc ? */
1266 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1267
1268 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1269 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1270
1271 /* Is this rule mod3? */
1272 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1273
1274 /*
1275  * Figure out how big our RAM modules are.
1276  *
1277  * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1278  * have to figure this out from the SAD rules, interleave lists, route tables,
1279  * and TAD rules.
1280  *
1281  * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1282  * inspect the TAD rules to figure out how large the SAD regions really are.
1283  *
1284  * When we know the real size of a SAD region and how many ways it's
1285  * interleaved, we know the individual contribution of each channel to
1286  * TAD is size/ways.
1287  *
1288  * Finally, we have to check whether each channel participates in each SAD
1289  * region.
1290  *
1291  * Fortunately, KNL only supports one DIMM per channel, so once we know how
1292  * much memory the channel uses, we know the DIMM is at least that large.
1293  * (The BIOS might possibly choose not to map all available memory, in which
1294  * case we will underreport the size of the DIMM.)
1295  *
1296  * In theory, we could try to determine the EDC sizes as well, but that would
1297  * only work in flat mode, not in cache mode.
1298  *
1299  * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1300  *            elements)
1301  */
1302 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1303 {
1304         u64 sad_base, sad_size, sad_limit = 0;
1305         u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1306         int sad_rule = 0;
1307         int tad_rule = 0;
1308         int intrlv_ways, tad_ways;
1309         u32 first_pkg, pkg;
1310         int i;
1311         u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1312         u32 dram_rule, interleave_reg;
1313         u32 mc_route_reg[KNL_MAX_CHAS];
1314         u32 edc_route_reg[KNL_MAX_CHAS];
1315         int edram_only;
1316         char edc_route_string[KNL_MAX_EDCS*2];
1317         char mc_route_string[KNL_MAX_CHANNELS*2];
1318         int cur_reg_start;
1319         int mc;
1320         int channel;
1321         int participants[KNL_MAX_CHANNELS];
1322
1323         for (i = 0; i < KNL_MAX_CHANNELS; i++)
1324                 mc_sizes[i] = 0;
1325
1326         /* Read the EDC route table in each CHA. */
1327         cur_reg_start = 0;
1328         for (i = 0; i < KNL_MAX_CHAS; i++) {
1329                 pci_read_config_dword(pvt->knl.pci_cha[i],
1330                                 KNL_EDC_ROUTE, &edc_route_reg[i]);
1331
1332                 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1333                         knl_show_edc_route(edc_route_reg[i-1],
1334                                         edc_route_string);
1335                         if (cur_reg_start == i-1)
1336                                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1337                                         cur_reg_start, edc_route_string);
1338                         else
1339                                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1340                                         cur_reg_start, i-1, edc_route_string);
1341                         cur_reg_start = i;
1342                 }
1343         }
1344         knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1345         if (cur_reg_start == i-1)
1346                 edac_dbg(0, "edc route table for CHA %d: %s\n",
1347                         cur_reg_start, edc_route_string);
1348         else
1349                 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1350                         cur_reg_start, i-1, edc_route_string);
1351
1352         /* Read the MC route table in each CHA. */
1353         cur_reg_start = 0;
1354         for (i = 0; i < KNL_MAX_CHAS; i++) {
1355                 pci_read_config_dword(pvt->knl.pci_cha[i],
1356                         KNL_MC_ROUTE, &mc_route_reg[i]);
1357
1358                 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1359                         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1360                         if (cur_reg_start == i-1)
1361                                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1362                                         cur_reg_start, mc_route_string);
1363                         else
1364                                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1365                                         cur_reg_start, i-1, mc_route_string);
1366                         cur_reg_start = i;
1367                 }
1368         }
1369         knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1370         if (cur_reg_start == i-1)
1371                 edac_dbg(0, "mc route table for CHA %d: %s\n",
1372                         cur_reg_start, mc_route_string);
1373         else
1374                 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1375                         cur_reg_start, i-1, mc_route_string);
1376
1377         /* Process DRAM rules */
1378         for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1379                 /* previous limit becomes the new base */
1380                 sad_base = sad_limit;
1381
1382                 pci_read_config_dword(pvt->pci_sad0,
1383                         pvt->info.dram_rule[sad_rule], &dram_rule);
1384
1385                 if (!DRAM_RULE_ENABLE(dram_rule))
1386                         break;
1387
1388                 edram_only = KNL_EDRAM_ONLY(dram_rule);
1389
1390                 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1391                 sad_size = sad_limit - sad_base;
1392
1393                 pci_read_config_dword(pvt->pci_sad0,
1394                         pvt->info.interleave_list[sad_rule], &interleave_reg);
1395
1396                 /*
1397                  * Find out how many ways this dram rule is interleaved.
1398                  * We stop when we see the first channel again.
1399                  */
1400                 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1401                                                 interleave_reg, 0);
1402                 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1403                         pkg = sad_pkg(pvt->info.interleave_pkg,
1404                                                 interleave_reg, intrlv_ways);
1405
1406                         if ((pkg & 0x8) == 0) {
1407                                 /*
1408                                  * 0 bit means memory is non-local,
1409                                  * which KNL doesn't support
1410                                  */
1411                                 edac_dbg(0, "Unexpected interleave target %d\n",
1412                                         pkg);
1413                                 return -1;
1414                         }
1415
1416                         if (pkg == first_pkg)
1417                                 break;
1418                 }
1419                 if (KNL_MOD3(dram_rule))
1420                         intrlv_ways *= 3;
1421
1422                 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1423                         sad_rule,
1424                         sad_base,
1425                         sad_limit,
1426                         intrlv_ways,
1427                         edram_only ? ", EDRAM" : "");
1428
1429                 /*
1430                  * Find out how big the SAD region really is by iterating
1431                  * over TAD tables (SAD regions may contain holes).
1432                  * Each memory controller might have a different TAD table, so
1433                  * we have to look at both.
1434                  *
1435                  * Livespace is the memory that's mapped in this TAD table,
1436                  * deadspace is the holes (this could be the MMIO hole, or it
1437                  * could be memory that's mapped by the other TAD table but
1438                  * not this one).
1439                  */
1440                 for (mc = 0; mc < 2; mc++) {
1441                         sad_actual_size[mc] = 0;
1442                         tad_livespace = 0;
1443                         for (tad_rule = 0;
1444                                         tad_rule < ARRAY_SIZE(
1445                                                 knl_tad_dram_limit_lo);
1446                                         tad_rule++) {
1447                                 if (knl_get_tad(pvt,
1448                                                 tad_rule,
1449                                                 mc,
1450                                                 &tad_deadspace,
1451                                                 &tad_limit,
1452                                                 &tad_ways))
1453                                         break;
1454
1455                                 tad_size = (tad_limit+1) -
1456                                         (tad_livespace + tad_deadspace);
1457                                 tad_livespace += tad_size;
1458                                 tad_base = (tad_limit+1) - tad_size;
1459
1460                                 if (tad_base < sad_base) {
1461                                         if (tad_limit > sad_base)
1462                                                 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1463                                 } else if (tad_base < sad_limit) {
1464                                         if (tad_limit+1 > sad_limit) {
1465                                                 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1466                                         } else {
1467                                                 /* TAD region is completely inside SAD region */
1468                                                 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1469                                                         tad_rule, tad_base,
1470                                                         tad_limit, tad_size,
1471                                                         mc);
1472                                                 sad_actual_size[mc] += tad_size;
1473                                         }
1474                                 }
1475                                 tad_base = tad_limit+1;
1476                         }
1477                 }
1478
1479                 for (mc = 0; mc < 2; mc++) {
1480                         edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1481                                 mc, sad_actual_size[mc], sad_actual_size[mc]);
1482                 }
1483
1484                 /* Ignore EDRAM rule */
1485                 if (edram_only)
1486                         continue;
1487
1488                 /* Figure out which channels participate in interleave. */
1489                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1490                         participants[channel] = 0;
1491
1492                 /* For each channel, does at least one CHA have
1493                  * this channel mapped to the given target?
1494                  */
1495                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1496                         int target;
1497                         int cha;
1498
1499                         for (target = 0; target < KNL_MAX_CHANNELS; target++) {
1500                                 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1501                                         if (knl_get_mc_route(target,
1502                                                 mc_route_reg[cha]) == channel
1503                                                 && !participants[channel]) {
1504                                                 participants[channel] = 1;
1505                                                 break;
1506                                         }
1507                                 }
1508                         }
1509                 }
1510
1511                 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1512                         mc = knl_channel_mc(channel);
1513                         if (participants[channel]) {
1514                                 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1515                                         channel,
1516                                         sad_actual_size[mc]/intrlv_ways,
1517                                         sad_rule);
1518                                 mc_sizes[channel] +=
1519                                         sad_actual_size[mc]/intrlv_ways;
1520                         }
1521                 }
1522         }
1523
1524         return 0;
1525 }
1526
1527 static void get_source_id(struct mem_ctl_info *mci)
1528 {
1529         struct sbridge_pvt *pvt = mci->pvt_info;
1530         u32 reg;
1531
1532         if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1533             pvt->info.type == KNIGHTS_LANDING)
1534                 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1535         else
1536                 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1537
1538         if (pvt->info.type == KNIGHTS_LANDING)
1539                 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1540         else
1541                 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1542 }
1543
1544 static int __populate_dimms(struct mem_ctl_info *mci,
1545                             u64 knl_mc_sizes[KNL_MAX_CHANNELS],
1546                             enum edac_type mode)
1547 {
1548         struct sbridge_pvt *pvt = mci->pvt_info;
1549         int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
1550                                                          : NUM_CHANNELS;
1551         unsigned int i, j, banks, ranks, rows, cols, npages;
1552         struct dimm_info *dimm;
1553         enum mem_type mtype;
1554         u64 size;
1555
1556         mtype = pvt->info.get_memory_type(pvt);
1557         if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1558                 edac_dbg(0, "Memory is registered\n");
1559         else if (mtype == MEM_UNKNOWN)
1560                 edac_dbg(0, "Cannot determine memory type\n");
1561         else
1562                 edac_dbg(0, "Memory is unregistered\n");
1563
1564         if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1565                 banks = 16;
1566         else
1567                 banks = 8;
1568
1569         for (i = 0; i < channels; i++) {
1570                 u32 mtr;
1571
1572                 int max_dimms_per_channel;
1573
1574                 if (pvt->info.type == KNIGHTS_LANDING) {
1575                         max_dimms_per_channel = 1;
1576                         if (!pvt->knl.pci_channel[i])
1577                                 continue;
1578                 } else {
1579                         max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1580                         if (!pvt->pci_tad[i])
1581                                 continue;
1582                 }
1583
1584                 for (j = 0; j < max_dimms_per_channel; j++) {
1585                         dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0);
1586                         if (pvt->info.type == KNIGHTS_LANDING) {
1587                                 pci_read_config_dword(pvt->knl.pci_channel[i],
1588                                         knl_mtr_reg, &mtr);
1589                         } else {
1590                                 pci_read_config_dword(pvt->pci_tad[i],
1591                                         mtr_regs[j], &mtr);
1592                         }
1593                         edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
1594                         if (IS_DIMM_PRESENT(mtr)) {
1595                                 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
1596                                         sbridge_printk(KERN_ERR, "CPU SrcID #%d, Ha #%d, Channel #%d has DIMMs, but ECC is disabled\n",
1597                                                        pvt->sbridge_dev->source_id,
1598                                                        pvt->sbridge_dev->dom, i);
1599                                         return -ENODEV;
1600                                 }
1601                                 pvt->channel[i].dimms++;
1602
1603                                 ranks = numrank(pvt->info.type, mtr);
1604
1605                                 if (pvt->info.type == KNIGHTS_LANDING) {
1606                                         /* For DDR4, this is fixed. */
1607                                         cols = 1 << 10;
1608                                         rows = knl_mc_sizes[i] /
1609                                                 ((u64) cols * ranks * banks * 8);
1610                                 } else {
1611                                         rows = numrow(mtr);
1612                                         cols = numcol(mtr);
1613                                 }
1614
1615                                 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1616                                 npages = MiB_TO_PAGES(size);
1617
1618                                 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1619                                          pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
1620                                          size, npages,
1621                                          banks, ranks, rows, cols);
1622
1623                                 dimm->nr_pages = npages;
1624                                 dimm->grain = 32;
1625                                 dimm->dtype = pvt->info.get_width(pvt, mtr);
1626                                 dimm->mtype = mtype;
1627                                 dimm->edac_mode = mode;
1628                                 snprintf(dimm->label, sizeof(dimm->label),
1629                                                  "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1630                                                  pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
1631                         }
1632                 }
1633         }
1634
1635         return 0;
1636 }
1637
1638 static int get_dimm_config(struct mem_ctl_info *mci)
1639 {
1640         struct sbridge_pvt *pvt = mci->pvt_info;
1641         u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1642         enum edac_type mode;
1643         u32 reg;
1644
1645         pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1646         edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1647                  pvt->sbridge_dev->mc,
1648                  pvt->sbridge_dev->node_id,
1649                  pvt->sbridge_dev->source_id);
1650
1651         /* KNL doesn't support mirroring or lockstep,
1652          * and is always closed page
1653          */
1654         if (pvt->info.type == KNIGHTS_LANDING) {
1655                 mode = EDAC_S4ECD4ED;
1656                 pvt->mirror_mode = NON_MIRRORING;
1657                 pvt->is_cur_addr_mirrored = false;
1658
1659                 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1660                         return -1;
1661                 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
1662                         edac_dbg(0, "Failed to read KNL_MCMTR register\n");
1663                         return -ENODEV;
1664                 }
1665         } else {
1666                 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1667                         if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg)) {
1668                                 edac_dbg(0, "Failed to read HASWELL_HASYSDEFEATURE2 register\n");
1669                                 return -ENODEV;
1670                         }
1671                         pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1672                         if (GET_BITFIELD(reg, 28, 28)) {
1673                                 pvt->mirror_mode = ADDR_RANGE_MIRRORING;
1674                                 edac_dbg(0, "Address range partial memory mirroring is enabled\n");
1675                                 goto next;
1676                         }
1677                 }
1678                 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg)) {
1679                         edac_dbg(0, "Failed to read RASENABLES register\n");
1680                         return -ENODEV;
1681                 }
1682                 if (IS_MIRROR_ENABLED(reg)) {
1683                         pvt->mirror_mode = FULL_MIRRORING;
1684                         edac_dbg(0, "Full memory mirroring is enabled\n");
1685                 } else {
1686                         pvt->mirror_mode = NON_MIRRORING;
1687                         edac_dbg(0, "Memory mirroring is disabled\n");
1688                 }
1689
1690 next:
1691                 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
1692                         edac_dbg(0, "Failed to read MCMTR register\n");
1693                         return -ENODEV;
1694                 }
1695                 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1696                         edac_dbg(0, "Lockstep is enabled\n");
1697                         mode = EDAC_S8ECD8ED;
1698                         pvt->is_lockstep = true;
1699                 } else {
1700                         edac_dbg(0, "Lockstep is disabled\n");
1701                         mode = EDAC_S4ECD4ED;
1702                         pvt->is_lockstep = false;
1703                 }
1704                 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1705                         edac_dbg(0, "address map is on closed page mode\n");
1706                         pvt->is_close_pg = true;
1707                 } else {
1708                         edac_dbg(0, "address map is on open page mode\n");
1709                         pvt->is_close_pg = false;
1710                 }
1711         }
1712
1713         return __populate_dimms(mci, knl_mc_sizes, mode);
1714 }
1715
1716 static void get_memory_layout(const struct mem_ctl_info *mci)
1717 {
1718         struct sbridge_pvt *pvt = mci->pvt_info;
1719         int i, j, k, n_sads, n_tads, sad_interl;
1720         u32 reg;
1721         u64 limit, prv = 0;
1722         u64 tmp_mb;
1723         u32 gb, mb;
1724         u32 rir_way;
1725
1726         /*
1727          * Step 1) Get TOLM/TOHM ranges
1728          */
1729
1730         pvt->tolm = pvt->info.get_tolm(pvt);
1731         tmp_mb = (1 + pvt->tolm) >> 20;
1732
1733         gb = div_u64_rem(tmp_mb, 1024, &mb);
1734         edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1735                 gb, (mb*1000)/1024, (u64)pvt->tolm);
1736
1737         /* Address range is already 45:25 */
1738         pvt->tohm = pvt->info.get_tohm(pvt);
1739         tmp_mb = (1 + pvt->tohm) >> 20;
1740
1741         gb = div_u64_rem(tmp_mb, 1024, &mb);
1742         edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1743                 gb, (mb*1000)/1024, (u64)pvt->tohm);
1744
1745         /*
1746          * Step 2) Get SAD range and SAD Interleave list
1747          * TAD registers contain the interleave wayness. However, it
1748          * seems simpler to just discover it indirectly, with the
1749          * algorithm bellow.
1750          */
1751         prv = 0;
1752         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1753                 /* SAD_LIMIT Address range is 45:26 */
1754                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1755                                       &reg);
1756                 limit = pvt->info.sad_limit(reg);
1757
1758                 if (!DRAM_RULE_ENABLE(reg))
1759                         continue;
1760
1761                 if (limit <= prv)
1762                         break;
1763
1764                 tmp_mb = (limit + 1) >> 20;
1765                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1766                 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1767                          n_sads,
1768                          show_dram_attr(pvt->info.dram_attr(reg)),
1769                          gb, (mb*1000)/1024,
1770                          ((u64)tmp_mb) << 20L,
1771                          get_intlv_mode_str(reg, pvt->info.type),
1772                          reg);
1773                 prv = limit;
1774
1775                 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1776                                       &reg);
1777                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1778                 for (j = 0; j < 8; j++) {
1779                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1780                         if (j > 0 && sad_interl == pkg)
1781                                 break;
1782
1783                         edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1784                                  n_sads, j, pkg);
1785                 }
1786         }
1787
1788         if (pvt->info.type == KNIGHTS_LANDING)
1789                 return;
1790
1791         /*
1792          * Step 3) Get TAD range
1793          */
1794         prv = 0;
1795         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1796                 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], &reg);
1797                 limit = TAD_LIMIT(reg);
1798                 if (limit <= prv)
1799                         break;
1800                 tmp_mb = (limit + 1) >> 20;
1801
1802                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1803                 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1804                          n_tads, gb, (mb*1000)/1024,
1805                          ((u64)tmp_mb) << 20L,
1806                          (u32)(1 << TAD_SOCK(reg)),
1807                          (u32)TAD_CH(reg) + 1,
1808                          (u32)TAD_TGT0(reg),
1809                          (u32)TAD_TGT1(reg),
1810                          (u32)TAD_TGT2(reg),
1811                          (u32)TAD_TGT3(reg),
1812                          reg);
1813                 prv = limit;
1814         }
1815
1816         /*
1817          * Step 4) Get TAD offsets, per each channel
1818          */
1819         for (i = 0; i < NUM_CHANNELS; i++) {
1820                 if (!pvt->channel[i].dimms)
1821                         continue;
1822                 for (j = 0; j < n_tads; j++) {
1823                         pci_read_config_dword(pvt->pci_tad[i],
1824                                               tad_ch_nilv_offset[j],
1825                                               &reg);
1826                         tmp_mb = TAD_OFFSET(reg) >> 20;
1827                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1828                         edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1829                                  i, j,
1830                                  gb, (mb*1000)/1024,
1831                                  ((u64)tmp_mb) << 20L,
1832                                  reg);
1833                 }
1834         }
1835
1836         /*
1837          * Step 6) Get RIR Wayness/Limit, per each channel
1838          */
1839         for (i = 0; i < NUM_CHANNELS; i++) {
1840                 if (!pvt->channel[i].dimms)
1841                         continue;
1842                 for (j = 0; j < MAX_RIR_RANGES; j++) {
1843                         pci_read_config_dword(pvt->pci_tad[i],
1844                                               rir_way_limit[j],
1845                                               &reg);
1846
1847                         if (!IS_RIR_VALID(reg))
1848                                 continue;
1849
1850                         tmp_mb = pvt->info.rir_limit(reg) >> 20;
1851                         rir_way = 1 << RIR_WAY(reg);
1852                         gb = div_u64_rem(tmp_mb, 1024, &mb);
1853                         edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1854                                  i, j,
1855                                  gb, (mb*1000)/1024,
1856                                  ((u64)tmp_mb) << 20L,
1857                                  rir_way,
1858                                  reg);
1859
1860                         for (k = 0; k < rir_way; k++) {
1861                                 pci_read_config_dword(pvt->pci_tad[i],
1862                                                       rir_offset[j][k],
1863                                                       &reg);
1864                                 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
1865
1866                                 gb = div_u64_rem(tmp_mb, 1024, &mb);
1867                                 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1868                                          i, j, k,
1869                                          gb, (mb*1000)/1024,
1870                                          ((u64)tmp_mb) << 20L,
1871                                          (u32)RIR_RNK_TGT(pvt->info.type, reg),
1872                                          reg);
1873                         }
1874                 }
1875         }
1876 }
1877
1878 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id, u8 ha)
1879 {
1880         struct sbridge_dev *sbridge_dev;
1881
1882         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1883                 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha)
1884                         return sbridge_dev->mci;
1885         }
1886         return NULL;
1887 }
1888
1889 static int get_memory_error_data(struct mem_ctl_info *mci,
1890                                  u64 addr,
1891                                  u8 *socket, u8 *ha,
1892                                  long *channel_mask,
1893                                  u8 *rank,
1894                                  char **area_type, char *msg)
1895 {
1896         struct mem_ctl_info     *new_mci;
1897         struct sbridge_pvt *pvt = mci->pvt_info;
1898         struct pci_dev          *pci_ha;
1899         int                     n_rir, n_sads, n_tads, sad_way, sck_xch;
1900         int                     sad_interl, idx, base_ch;
1901         int                     interleave_mode, shiftup = 0;
1902         unsigned                sad_interleave[pvt->info.max_interleave];
1903         u32                     reg, dram_rule;
1904         u8                      ch_way, sck_way, pkg, sad_ha = 0;
1905         u32                     tad_offset;
1906         u32                     rir_way;
1907         u32                     mb, gb;
1908         u64                     ch_addr, offset, limit = 0, prv = 0;
1909
1910
1911         /*
1912          * Step 0) Check if the address is at special memory ranges
1913          * The check bellow is probably enough to fill all cases where
1914          * the error is not inside a memory, except for the legacy
1915          * range (e. g. VGA addresses). It is unlikely, however, that the
1916          * memory controller would generate an error on that range.
1917          */
1918         if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1919                 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1920                 return -EINVAL;
1921         }
1922         if (addr >= (u64)pvt->tohm) {
1923                 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1924                 return -EINVAL;
1925         }
1926
1927         /*
1928          * Step 1) Get socket
1929          */
1930         for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1931                 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1932                                       &reg);
1933
1934                 if (!DRAM_RULE_ENABLE(reg))
1935                         continue;
1936
1937                 limit = pvt->info.sad_limit(reg);
1938                 if (limit <= prv) {
1939                         sprintf(msg, "Can't discover the memory socket");
1940                         return -EINVAL;
1941                 }
1942                 if  (addr <= limit)
1943                         break;
1944                 prv = limit;
1945         }
1946         if (n_sads == pvt->info.max_sad) {
1947                 sprintf(msg, "Can't discover the memory socket");
1948                 return -EINVAL;
1949         }
1950         dram_rule = reg;
1951         *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1952         interleave_mode = pvt->info.interleave_mode(dram_rule);
1953
1954         pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1955                               &reg);
1956
1957         if (pvt->info.type == SANDY_BRIDGE) {
1958                 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1959                 for (sad_way = 0; sad_way < 8; sad_way++) {
1960                         u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1961                         if (sad_way > 0 && sad_interl == pkg)
1962                                 break;
1963                         sad_interleave[sad_way] = pkg;
1964                         edac_dbg(0, "SAD interleave #%d: %d\n",
1965                                  sad_way, sad_interleave[sad_way]);
1966                 }
1967                 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
1968                          pvt->sbridge_dev->mc,
1969                          n_sads,
1970                          addr,
1971                          limit,
1972                          sad_way + 7,
1973                          !interleave_mode ? "" : "XOR[18:16]");
1974                 if (interleave_mode)
1975                         idx = ((addr >> 6) ^ (addr >> 16)) & 7;
1976                 else
1977                         idx = (addr >> 6) & 7;
1978                 switch (sad_way) {
1979                 case 1:
1980                         idx = 0;
1981                         break;
1982                 case 2:
1983                         idx = idx & 1;
1984                         break;
1985                 case 4:
1986                         idx = idx & 3;
1987                         break;
1988                 case 8:
1989                         break;
1990                 default:
1991                         sprintf(msg, "Can't discover socket interleave");
1992                         return -EINVAL;
1993                 }
1994                 *socket = sad_interleave[idx];
1995                 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
1996                          idx, sad_way, *socket);
1997         } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1998                 int bits, a7mode = A7MODE(dram_rule);
1999
2000                 if (a7mode) {
2001                         /* A7 mode swaps P9 with P6 */
2002                         bits = GET_BITFIELD(addr, 7, 8) << 1;
2003                         bits |= GET_BITFIELD(addr, 9, 9);
2004                 } else
2005                         bits = GET_BITFIELD(addr, 6, 8);
2006
2007                 if (interleave_mode == 0) {
2008                         /* interleave mode will XOR {8,7,6} with {18,17,16} */
2009                         idx = GET_BITFIELD(addr, 16, 18);
2010                         idx ^= bits;
2011                 } else
2012                         idx = bits;
2013
2014                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2015                 *socket = sad_pkg_socket(pkg);
2016                 sad_ha = sad_pkg_ha(pkg);
2017
2018                 if (a7mode) {
2019                         /* MCChanShiftUpEnable */
2020                         pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg);
2021                         shiftup = GET_BITFIELD(reg, 22, 22);
2022                 }
2023
2024                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2025                          idx, *socket, sad_ha, shiftup);
2026         } else {
2027                 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2028                 idx = (addr >> 6) & 7;
2029                 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2030                 *socket = sad_pkg_socket(pkg);
2031                 sad_ha = sad_pkg_ha(pkg);
2032                 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2033                          idx, *socket, sad_ha);
2034         }
2035
2036         *ha = sad_ha;
2037
2038         /*
2039          * Move to the proper node structure, in order to access the
2040          * right PCI registers
2041          */
2042         new_mci = get_mci_for_node_id(*socket, sad_ha);
2043         if (!new_mci) {
2044                 sprintf(msg, "Struct for socket #%u wasn't initialized",
2045                         *socket);
2046                 return -EINVAL;
2047         }
2048         mci = new_mci;
2049         pvt = mci->pvt_info;
2050
2051         /*
2052          * Step 2) Get memory channel
2053          */
2054         prv = 0;
2055         pci_ha = pvt->pci_ha;
2056         for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2057                 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2058                 limit = TAD_LIMIT(reg);
2059                 if (limit <= prv) {
2060                         sprintf(msg, "Can't discover the memory channel");
2061                         return -EINVAL;
2062                 }
2063                 if  (addr <= limit)
2064                         break;
2065                 prv = limit;
2066         }
2067         if (n_tads == MAX_TAD) {
2068                 sprintf(msg, "Can't discover the memory channel");
2069                 return -EINVAL;
2070         }
2071
2072         ch_way = TAD_CH(reg) + 1;
2073         sck_way = TAD_SOCK(reg);
2074
2075         if (ch_way == 3)
2076                 idx = addr >> 6;
2077         else {
2078                 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2079                 if (pvt->is_chan_hash)
2080                         idx = haswell_chan_hash(idx, addr);
2081         }
2082         idx = idx % ch_way;
2083
2084         /*
2085          * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2086          */
2087         switch (idx) {
2088         case 0:
2089                 base_ch = TAD_TGT0(reg);
2090                 break;
2091         case 1:
2092                 base_ch = TAD_TGT1(reg);
2093                 break;
2094         case 2:
2095                 base_ch = TAD_TGT2(reg);
2096                 break;
2097         case 3:
2098                 base_ch = TAD_TGT3(reg);
2099                 break;
2100         default:
2101                 sprintf(msg, "Can't discover the TAD target");
2102                 return -EINVAL;
2103         }
2104         *channel_mask = 1 << base_ch;
2105
2106         pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
2107
2108         if (pvt->mirror_mode == FULL_MIRRORING ||
2109             (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
2110                 *channel_mask |= 1 << ((base_ch + 2) % 4);
2111                 switch(ch_way) {
2112                 case 2:
2113                 case 4:
2114                         sck_xch = (1 << sck_way) * (ch_way >> 1);
2115                         break;
2116                 default:
2117                         sprintf(msg, "Invalid mirror set. Can't decode addr");
2118                         return -EINVAL;
2119                 }
2120
2121                 pvt->is_cur_addr_mirrored = true;
2122         } else {
2123                 sck_xch = (1 << sck_way) * ch_way;
2124                 pvt->is_cur_addr_mirrored = false;
2125         }
2126
2127         if (pvt->is_lockstep)
2128                 *channel_mask |= 1 << ((base_ch + 1) % 4);
2129
2130         offset = TAD_OFFSET(tad_offset);
2131
2132         edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2133                  n_tads,
2134                  addr,
2135                  limit,
2136                  sck_way,
2137                  ch_way,
2138                  offset,
2139                  idx,
2140                  base_ch,
2141                  *channel_mask);
2142
2143         /* Calculate channel address */
2144         /* Remove the TAD offset */
2145
2146         if (offset > addr) {
2147                 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2148                         offset, addr);
2149                 return -EINVAL;
2150         }
2151
2152         ch_addr = addr - offset;
2153         ch_addr >>= (6 + shiftup);
2154         ch_addr /= sck_xch;
2155         ch_addr <<= (6 + shiftup);
2156         ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2157
2158         /*
2159          * Step 3) Decode rank
2160          */
2161         for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2162                 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], &reg);
2163
2164                 if (!IS_RIR_VALID(reg))
2165                         continue;
2166
2167                 limit = pvt->info.rir_limit(reg);
2168                 gb = div_u64_rem(limit >> 20, 1024, &mb);
2169                 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2170                          n_rir,
2171                          gb, (mb*1000)/1024,
2172                          limit,
2173                          1 << RIR_WAY(reg));
2174                 if  (ch_addr <= limit)
2175                         break;
2176         }
2177         if (n_rir == MAX_RIR_RANGES) {
2178                 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2179                         ch_addr);
2180                 return -EINVAL;
2181         }
2182         rir_way = RIR_WAY(reg);
2183
2184         if (pvt->is_close_pg)
2185                 idx = (ch_addr >> 6);
2186         else
2187                 idx = (ch_addr >> 13);  /* FIXME: Datasheet says to shift by 15 */
2188         idx %= 1 << rir_way;
2189
2190         pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], &reg);
2191         *rank = RIR_RNK_TGT(pvt->info.type, reg);
2192
2193         edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2194                  n_rir,
2195                  ch_addr,
2196                  limit,
2197                  rir_way,
2198                  idx);
2199
2200         return 0;
2201 }
2202
2203 /****************************************************************************
2204         Device initialization routines: put/get, init/exit
2205  ****************************************************************************/
2206
2207 /*
2208  *      sbridge_put_all_devices 'put' all the devices that we have
2209  *                              reserved via 'get'
2210  */
2211 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2212 {
2213         int i;
2214
2215         edac_dbg(0, "\n");
2216         for (i = 0; i < sbridge_dev->n_devs; i++) {
2217                 struct pci_dev *pdev = sbridge_dev->pdev[i];
2218                 if (!pdev)
2219                         continue;
2220                 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2221                          pdev->bus->number,
2222                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2223                 pci_dev_put(pdev);
2224         }
2225 }
2226
2227 static void sbridge_put_all_devices(void)
2228 {
2229         struct sbridge_dev *sbridge_dev, *tmp;
2230
2231         list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2232                 sbridge_put_devices(sbridge_dev);
2233                 free_sbridge_dev(sbridge_dev);
2234         }
2235 }
2236
2237 static int sbridge_get_onedevice(struct pci_dev **prev,
2238                                  u8 *num_mc,
2239                                  const struct pci_id_table *table,
2240                                  const unsigned devno,
2241                                  const int multi_bus)
2242 {
2243         struct sbridge_dev *sbridge_dev = NULL;
2244         const struct pci_id_descr *dev_descr = &table->descr[devno];
2245         struct pci_dev *pdev = NULL;
2246         u8 bus = 0;
2247         int i = 0;
2248
2249         sbridge_printk(KERN_DEBUG,
2250                 "Seeking for: PCI ID %04x:%04x\n",
2251                 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2252
2253         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2254                               dev_descr->dev_id, *prev);
2255
2256         if (!pdev) {
2257                 if (*prev) {
2258                         *prev = pdev;
2259                         return 0;
2260                 }
2261
2262                 if (dev_descr->optional)
2263                         return 0;
2264
2265                 /* if the HA wasn't found */
2266                 if (devno == 0)
2267                         return -ENODEV;
2268
2269                 sbridge_printk(KERN_INFO,
2270                         "Device not found: %04x:%04x\n",
2271                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2272
2273                 /* End of list, leave */
2274                 return -ENODEV;
2275         }
2276         bus = pdev->bus->number;
2277
2278 next_imc:
2279         sbridge_dev = get_sbridge_dev(bus, dev_descr->dom, multi_bus, sbridge_dev);
2280         if (!sbridge_dev) {
2281                 /* If the HA1 wasn't found, don't create EDAC second memory controller */
2282                 if (dev_descr->dom == IMC1 && devno != 1) {
2283                         edac_dbg(0, "Skip IMC1: %04x:%04x (since HA1 was absent)\n",
2284                                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2285                         pci_dev_put(pdev);
2286                         return 0;
2287                 }
2288
2289                 if (dev_descr->dom == SOCK)
2290                         goto out_imc;
2291
2292                 sbridge_dev = alloc_sbridge_dev(bus, dev_descr->dom, table);
2293                 if (!sbridge_dev) {
2294                         pci_dev_put(pdev);
2295                         return -ENOMEM;
2296                 }
2297                 (*num_mc)++;
2298         }
2299
2300         if (sbridge_dev->pdev[sbridge_dev->i_devs]) {
2301                 sbridge_printk(KERN_ERR,
2302                         "Duplicated device for %04x:%04x\n",
2303                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2304                 pci_dev_put(pdev);
2305                 return -ENODEV;
2306         }
2307
2308         sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev;
2309
2310         /* pdev belongs to more than one IMC, do extra gets */
2311         if (++i > 1)
2312                 pci_dev_get(pdev);
2313
2314         if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock)
2315                 goto next_imc;
2316
2317 out_imc:
2318         /* Be sure that the device is enabled */
2319         if (unlikely(pci_enable_device(pdev) < 0)) {
2320                 sbridge_printk(KERN_ERR,
2321                         "Couldn't enable %04x:%04x\n",
2322                         PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2323                 return -ENODEV;
2324         }
2325
2326         edac_dbg(0, "Detected %04x:%04x\n",
2327                  PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2328
2329         /*
2330          * As stated on drivers/pci/search.c, the reference count for
2331          * @from is always decremented if it is not %NULL. So, as we need
2332          * to get all devices up to null, we need to do a get for the device
2333          */
2334         pci_dev_get(pdev);
2335
2336         *prev = pdev;
2337
2338         return 0;
2339 }
2340
2341 /*
2342  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2343  *                           devices we want to reference for this driver.
2344  * @num_mc: pointer to the memory controllers count, to be incremented in case
2345  *          of success.
2346  * @table: model specific table
2347  *
2348  * returns 0 in case of success or error code
2349  */
2350 static int sbridge_get_all_devices(u8 *num_mc,
2351                                         const struct pci_id_table *table)
2352 {
2353         int i, rc;
2354         struct pci_dev *pdev = NULL;
2355         int allow_dups = 0;
2356         int multi_bus = 0;
2357
2358         if (table->type == KNIGHTS_LANDING)
2359                 allow_dups = multi_bus = 1;
2360         while (table && table->descr) {
2361                 for (i = 0; i < table->n_devs_per_sock; i++) {
2362                         if (!allow_dups || i == 0 ||
2363                                         table->descr[i].dev_id !=
2364                                                 table->descr[i-1].dev_id) {
2365                                 pdev = NULL;
2366                         }
2367                         do {
2368                                 rc = sbridge_get_onedevice(&pdev, num_mc,
2369                                                            table, i, multi_bus);
2370                                 if (rc < 0) {
2371                                         if (i == 0) {
2372                                                 i = table->n_devs_per_sock;
2373                                                 break;
2374                                         }
2375                                         sbridge_put_all_devices();
2376                                         return -ENODEV;
2377                                 }
2378                         } while (pdev && !allow_dups);
2379                 }
2380                 table++;
2381         }
2382
2383         return 0;
2384 }
2385
2386 /*
2387  * Device IDs for {SBRIDGE,IBRIDGE,HASWELL,BROADWELL}_IMC_HA0_TAD0 are in
2388  * the format: XXXa. So we can convert from a device to the corresponding
2389  * channel like this
2390  */
2391 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2392
2393 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2394                                  struct sbridge_dev *sbridge_dev)
2395 {
2396         struct sbridge_pvt *pvt = mci->pvt_info;
2397         struct pci_dev *pdev;
2398         u8 saw_chan_mask = 0;
2399         int i;
2400
2401         for (i = 0; i < sbridge_dev->n_devs; i++) {
2402                 pdev = sbridge_dev->pdev[i];
2403                 if (!pdev)
2404                         continue;
2405
2406                 switch (pdev->device) {
2407                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2408                         pvt->pci_sad0 = pdev;
2409                         break;
2410                 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2411                         pvt->pci_sad1 = pdev;
2412                         break;
2413                 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2414                         pvt->pci_br0 = pdev;
2415                         break;
2416                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2417                         pvt->pci_ha = pdev;
2418                         break;
2419                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2420                         pvt->pci_ta = pdev;
2421                         break;
2422                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2423                         pvt->pci_ras = pdev;
2424                         break;
2425                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2426                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2427                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2428                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2429                 {
2430                         int id = TAD_DEV_TO_CHAN(pdev->device);
2431                         pvt->pci_tad[id] = pdev;
2432                         saw_chan_mask |= 1 << id;
2433                 }
2434                         break;
2435                 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2436                         pvt->pci_ddrio = pdev;
2437                         break;
2438                 default:
2439                         goto error;
2440                 }
2441
2442                 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2443                          pdev->vendor, pdev->device,
2444                          sbridge_dev->bus,
2445                          pdev);
2446         }
2447
2448         /* Check if everything were registered */
2449         if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
2450             !pvt->pci_ras || !pvt->pci_ta)
2451                 goto enodev;
2452
2453         if (saw_chan_mask != 0x0f)
2454                 goto enodev;
2455         return 0;
2456
2457 enodev:
2458         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2459         return -ENODEV;
2460
2461 error:
2462         sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2463                        PCI_VENDOR_ID_INTEL, pdev->device);
2464         return -EINVAL;
2465 }
2466
2467 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2468                                  struct sbridge_dev *sbridge_dev)
2469 {
2470         struct sbridge_pvt *pvt = mci->pvt_info;
2471         struct pci_dev *pdev;
2472         u8 saw_chan_mask = 0;
2473         int i;
2474
2475         for (i = 0; i < sbridge_dev->n_devs; i++) {
2476                 pdev = sbridge_dev->pdev[i];
2477                 if (!pdev)
2478                         continue;
2479
2480                 switch (pdev->device) {
2481                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2482                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2483                         pvt->pci_ha = pdev;
2484                         break;
2485                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2486                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA:
2487                         pvt->pci_ta = pdev;
2488                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2489                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS:
2490                         pvt->pci_ras = pdev;
2491                         break;
2492                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2493                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2494                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2495                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2496                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2497                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2498                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2499                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2500                 {
2501                         int id = TAD_DEV_TO_CHAN(pdev->device);
2502                         pvt->pci_tad[id] = pdev;
2503                         saw_chan_mask |= 1 << id;
2504                 }
2505                         break;
2506                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2507                         pvt->pci_ddrio = pdev;
2508                         break;
2509                 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2510                         pvt->pci_ddrio = pdev;
2511                         break;
2512                 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2513                         pvt->pci_sad0 = pdev;
2514                         break;
2515                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2516                         pvt->pci_br0 = pdev;
2517                         break;
2518                 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2519                         pvt->pci_br1 = pdev;
2520                         break;
2521                 default:
2522                         goto error;
2523                 }
2524
2525                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2526                          sbridge_dev->bus,
2527                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2528                          pdev);
2529         }
2530
2531         /* Check if everything were registered */
2532         if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
2533             !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
2534                 goto enodev;
2535
2536         if (saw_chan_mask != 0x0f && /* -EN/-EX */
2537             saw_chan_mask != 0x03)   /* -EP */
2538                 goto enodev;
2539         return 0;
2540
2541 enodev:
2542         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2543         return -ENODEV;
2544
2545 error:
2546         sbridge_printk(KERN_ERR,
2547                        "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2548                         pdev->device);
2549         return -EINVAL;
2550 }
2551
2552 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2553                                  struct sbridge_dev *sbridge_dev)
2554 {
2555         struct sbridge_pvt *pvt = mci->pvt_info;
2556         struct pci_dev *pdev;
2557         u8 saw_chan_mask = 0;
2558         int i;
2559
2560         /* there's only one device per system; not tied to any bus */
2561         if (pvt->info.pci_vtd == NULL)
2562                 /* result will be checked later */
2563                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2564                                                    PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2565                                                    NULL);
2566
2567         for (i = 0; i < sbridge_dev->n_devs; i++) {
2568                 pdev = sbridge_dev->pdev[i];
2569                 if (!pdev)
2570                         continue;
2571
2572                 switch (pdev->device) {
2573                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2574                         pvt->pci_sad0 = pdev;
2575                         break;
2576                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2577                         pvt->pci_sad1 = pdev;
2578                         break;
2579                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2580                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2581                         pvt->pci_ha = pdev;
2582                         break;
2583                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2584                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2585                         pvt->pci_ta = pdev;
2586                         break;
2587                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM:
2588                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM:
2589                         pvt->pci_ras = pdev;
2590                         break;
2591                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2592                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2593                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2594                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2595                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2596                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2597                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2598                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2599                 {
2600                         int id = TAD_DEV_TO_CHAN(pdev->device);
2601                         pvt->pci_tad[id] = pdev;
2602                         saw_chan_mask |= 1 << id;
2603                 }
2604                         break;
2605                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2606                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2607                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2608                 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2609                         if (!pvt->pci_ddrio)
2610                                 pvt->pci_ddrio = pdev;
2611                         break;
2612                 default:
2613                         break;
2614                 }
2615
2616                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2617                          sbridge_dev->bus,
2618                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2619                          pdev);
2620         }
2621
2622         /* Check if everything were registered */
2623         if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2624             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2625                 goto enodev;
2626
2627         if (saw_chan_mask != 0x0f && /* -EN/-EX */
2628             saw_chan_mask != 0x03)   /* -EP */
2629                 goto enodev;
2630         return 0;
2631
2632 enodev:
2633         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2634         return -ENODEV;
2635 }
2636
2637 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2638                                  struct sbridge_dev *sbridge_dev)
2639 {
2640         struct sbridge_pvt *pvt = mci->pvt_info;
2641         struct pci_dev *pdev;
2642         u8 saw_chan_mask = 0;
2643         int i;
2644
2645         /* there's only one device per system; not tied to any bus */
2646         if (pvt->info.pci_vtd == NULL)
2647                 /* result will be checked later */
2648                 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2649                                                    PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2650                                                    NULL);
2651
2652         for (i = 0; i < sbridge_dev->n_devs; i++) {
2653                 pdev = sbridge_dev->pdev[i];
2654                 if (!pdev)
2655                         continue;
2656
2657                 switch (pdev->device) {
2658                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2659                         pvt->pci_sad0 = pdev;
2660                         break;
2661                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2662                         pvt->pci_sad1 = pdev;
2663                         break;
2664                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2665                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2666                         pvt->pci_ha = pdev;
2667                         break;
2668                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2669                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2670                         pvt->pci_ta = pdev;
2671                         break;
2672                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM:
2673                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM:
2674                         pvt->pci_ras = pdev;
2675                         break;
2676                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2677                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2678                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2679                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2680                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2681                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2682                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2683                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2684                 {
2685                         int id = TAD_DEV_TO_CHAN(pdev->device);
2686                         pvt->pci_tad[id] = pdev;
2687                         saw_chan_mask |= 1 << id;
2688                 }
2689                         break;
2690                 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2691                         pvt->pci_ddrio = pdev;
2692                         break;
2693                 default:
2694                         break;
2695                 }
2696
2697                 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2698                          sbridge_dev->bus,
2699                          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2700                          pdev);
2701         }
2702
2703         /* Check if everything were registered */
2704         if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
2705             !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2706                 goto enodev;
2707
2708         if (saw_chan_mask != 0x0f && /* -EN/-EX */
2709             saw_chan_mask != 0x03)   /* -EP */
2710                 goto enodev;
2711         return 0;
2712
2713 enodev:
2714         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2715         return -ENODEV;
2716 }
2717
2718 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2719                         struct sbridge_dev *sbridge_dev)
2720 {
2721         struct sbridge_pvt *pvt = mci->pvt_info;
2722         struct pci_dev *pdev;
2723         int dev, func;
2724
2725         int i;
2726         int devidx;
2727
2728         for (i = 0; i < sbridge_dev->n_devs; i++) {
2729                 pdev = sbridge_dev->pdev[i];
2730                 if (!pdev)
2731                         continue;
2732
2733                 /* Extract PCI device and function. */
2734                 dev = (pdev->devfn >> 3) & 0x1f;
2735                 func = pdev->devfn & 0x7;
2736
2737                 switch (pdev->device) {
2738                 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2739                         if (dev == 8)
2740                                 pvt->knl.pci_mc0 = pdev;
2741                         else if (dev == 9)
2742                                 pvt->knl.pci_mc1 = pdev;
2743                         else {
2744                                 sbridge_printk(KERN_ERR,
2745                                         "Memory controller in unexpected place! (dev %d, fn %d)\n",
2746                                         dev, func);
2747                                 continue;
2748                         }
2749                         break;
2750
2751                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2752                         pvt->pci_sad0 = pdev;
2753                         break;
2754
2755                 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2756                         pvt->pci_sad1 = pdev;
2757                         break;
2758
2759                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2760                         /* There are one of these per tile, and range from
2761                          * 1.14.0 to 1.18.5.
2762                          */
2763                         devidx = ((dev-14)*8)+func;
2764
2765                         if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2766                                 sbridge_printk(KERN_ERR,
2767                                         "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2768                                         dev, func);
2769                                 continue;
2770                         }
2771
2772                         WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2773
2774                         pvt->knl.pci_cha[devidx] = pdev;
2775                         break;
2776
2777                 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN:
2778                         devidx = -1;
2779
2780                         /*
2781                          *  MC0 channels 0-2 are device 9 function 2-4,
2782                          *  MC1 channels 3-5 are device 8 function 2-4.
2783                          */
2784
2785                         if (dev == 9)
2786                                 devidx = func-2;
2787                         else if (dev == 8)
2788                                 devidx = 3 + (func-2);
2789
2790                         if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2791                                 sbridge_printk(KERN_ERR,
2792                                         "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2793                                         dev, func);
2794                                 continue;
2795                         }
2796
2797                         WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2798                         pvt->knl.pci_channel[devidx] = pdev;
2799                         break;
2800
2801                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2802                         pvt->knl.pci_mc_info = pdev;
2803                         break;
2804
2805                 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2806                         pvt->pci_ta = pdev;
2807                         break;
2808
2809                 default:
2810                         sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2811                                 pdev->device);
2812                         break;
2813                 }
2814         }
2815
2816         if (!pvt->knl.pci_mc0  || !pvt->knl.pci_mc1 ||
2817             !pvt->pci_sad0     || !pvt->pci_sad1    ||
2818             !pvt->pci_ta) {
2819                 goto enodev;
2820         }
2821
2822         for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2823                 if (!pvt->knl.pci_channel[i]) {
2824                         sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2825                         goto enodev;
2826                 }
2827         }
2828
2829         for (i = 0; i < KNL_MAX_CHAS; i++) {
2830                 if (!pvt->knl.pci_cha[i]) {
2831                         sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2832                         goto enodev;
2833                 }
2834         }
2835
2836         return 0;
2837
2838 enodev:
2839         sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2840         return -ENODEV;
2841 }
2842
2843 /****************************************************************************
2844                         Error check routines
2845  ****************************************************************************/
2846
2847 /*
2848  * While Sandy Bridge has error count registers, SMI BIOS read values from
2849  * and resets the counters. So, they are not reliable for the OS to read
2850  * from them. So, we have no option but to just trust on whatever MCE is
2851  * telling us about the errors.
2852  */
2853 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2854                                     const struct mce *m)
2855 {
2856         struct mem_ctl_info *new_mci;
2857         struct sbridge_pvt *pvt = mci->pvt_info;
2858         enum hw_event_mc_err_type tp_event;
2859         char *type, *optype, msg[256];
2860         bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2861         bool overflow = GET_BITFIELD(m->status, 62, 62);
2862         bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2863         bool recoverable;
2864         u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2865         u32 mscod = GET_BITFIELD(m->status, 16, 31);
2866         u32 errcode = GET_BITFIELD(m->status, 0, 15);
2867         u32 channel = GET_BITFIELD(m->status, 0, 3);
2868         u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2869         long channel_mask, first_channel;
2870         u8  rank, socket, ha;
2871         int rc, dimm;
2872         char *area_type = NULL;
2873
2874         if (pvt->info.type != SANDY_BRIDGE)
2875                 recoverable = true;
2876         else
2877                 recoverable = GET_BITFIELD(m->status, 56, 56);
2878
2879         if (uncorrected_error) {
2880                 if (ripv) {
2881                         type = "FATAL";
2882                         tp_event = HW_EVENT_ERR_FATAL;
2883                 } else {
2884                         type = "NON_FATAL";
2885                         tp_event = HW_EVENT_ERR_UNCORRECTED;
2886                 }
2887         } else {
2888                 type = "CORRECTED";
2889                 tp_event = HW_EVENT_ERR_CORRECTED;
2890         }
2891
2892         /*
2893          * According with Table 15-9 of the Intel Architecture spec vol 3A,
2894          * memory errors should fit in this mask:
2895          *      000f 0000 1mmm cccc (binary)
2896          * where:
2897          *      f = Correction Report Filtering Bit. If 1, subsequent errors
2898          *          won't be shown
2899          *      mmm = error type
2900          *      cccc = channel
2901          * If the mask doesn't match, report an error to the parsing logic
2902          */
2903         if (! ((errcode & 0xef80) == 0x80)) {
2904                 optype = "Can't parse: it is not a mem";
2905         } else {
2906                 switch (optypenum) {
2907                 case 0:
2908                         optype = "generic undef request error";
2909                         break;
2910                 case 1:
2911                         optype = "memory read error";
2912                         break;
2913                 case 2:
2914                         optype = "memory write error";
2915                         break;
2916                 case 3:
2917                         optype = "addr/cmd error";
2918                         break;
2919                 case 4:
2920                         optype = "memory scrubbing error";
2921                         break;
2922                 default:
2923                         optype = "reserved";
2924                         break;
2925                 }
2926         }
2927
2928         /* Only decode errors with an valid address (ADDRV) */
2929         if (!GET_BITFIELD(m->status, 58, 58))
2930                 return;
2931
2932         if (pvt->info.type == KNIGHTS_LANDING) {
2933                 if (channel == 14) {
2934                         edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
2935                                 overflow ? " OVERFLOW" : "",
2936                                 (uncorrected_error && recoverable)
2937                                 ? " recoverable" : "",
2938                                 mscod, errcode,
2939                                 m->bank);
2940                 } else {
2941                         char A = *("A");
2942
2943                         /*
2944                          * Reported channel is in range 0-2, so we can't map it
2945                          * back to mc. To figure out mc we check machine check
2946                          * bank register that reported this error.
2947                          * bank15 means mc0 and bank16 means mc1.
2948                          */
2949                         channel = knl_channel_remap(m->bank == 16, channel);
2950                         channel_mask = 1 << channel;
2951
2952                         snprintf(msg, sizeof(msg),
2953                                 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
2954                                 overflow ? " OVERFLOW" : "",
2955                                 (uncorrected_error && recoverable)
2956                                 ? " recoverable" : " ",
2957                                 mscod, errcode, channel, A + channel);
2958                         edac_mc_handle_error(tp_event, mci, core_err_cnt,
2959                                 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
2960                                 channel, 0, -1,
2961                                 optype, msg);
2962                 }
2963                 return;
2964         } else {
2965                 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
2966                                 &channel_mask, &rank, &area_type, msg);
2967         }
2968
2969         if (rc < 0)
2970                 goto err_parsing;
2971         new_mci = get_mci_for_node_id(socket, ha);
2972         if (!new_mci) {
2973                 strcpy(msg, "Error: socket got corrupted!");
2974                 goto err_parsing;
2975         }
2976         mci = new_mci;
2977         pvt = mci->pvt_info;
2978
2979         first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
2980
2981         if (rank < 4)
2982                 dimm = 0;
2983         else if (rank < 8)
2984                 dimm = 1;
2985         else
2986                 dimm = 2;
2987
2988
2989         /*
2990          * FIXME: On some memory configurations (mirror, lockstep), the
2991          * Memory Controller can't point the error to a single DIMM. The
2992          * EDAC core should be handling the channel mask, in order to point
2993          * to the group of dimm's where the error may be happening.
2994          */
2995         if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
2996                 channel = first_channel;
2997
2998         snprintf(msg, sizeof(msg),
2999                  "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3000                  overflow ? " OVERFLOW" : "",
3001                  (uncorrected_error && recoverable) ? " recoverable" : "",
3002                  area_type,
3003                  mscod, errcode,
3004                  socket, ha,
3005                  channel_mask,
3006                  rank);
3007
3008         edac_dbg(0, "%s\n", msg);
3009
3010         /* FIXME: need support for channel mask */
3011
3012         if (channel == CHANNEL_UNSPECIFIED)
3013                 channel = -1;
3014
3015         /* Call the helper to output message */
3016         edac_mc_handle_error(tp_event, mci, core_err_cnt,
3017                              m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3018                              channel, dimm, -1,
3019                              optype, msg);
3020         return;
3021 err_parsing:
3022         edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3023                              -1, -1, -1,
3024                              msg, "");
3025
3026 }
3027
3028 /*
3029  * Check that logging is enabled and that this is the right type
3030  * of error for us to handle.
3031  */
3032 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3033                                    void *data)
3034 {
3035         struct mce *mce = (struct mce *)data;
3036         struct mem_ctl_info *mci;
3037         struct sbridge_pvt *pvt;
3038         char *type;
3039
3040         if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3041                 return NOTIFY_DONE;
3042
3043         mci = get_mci_for_node_id(mce->socketid, IMC0);
3044         if (!mci)
3045                 return NOTIFY_DONE;
3046         pvt = mci->pvt_info;
3047
3048         /*
3049          * Just let mcelog handle it if the error is
3050          * outside the memory controller. A memory error
3051          * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3052          * bit 12 has an special meaning.
3053          */
3054         if ((mce->status & 0xefff) >> 7 != 1)
3055                 return NOTIFY_DONE;
3056
3057         if (mce->mcgstatus & MCG_STATUS_MCIP)
3058                 type = "Exception";
3059         else
3060                 type = "Event";
3061
3062         sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3063
3064         sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3065                           "Bank %d: %016Lx\n", mce->extcpu, type,
3066                           mce->mcgstatus, mce->bank, mce->status);
3067         sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3068         sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3069         sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3070
3071         sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3072                           "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3073                           mce->time, mce->socketid, mce->apicid);
3074
3075         sbridge_mce_output_error(mci, mce);
3076
3077         /* Advice mcelog that the error were handled */
3078         return NOTIFY_STOP;
3079 }
3080
3081 static struct notifier_block sbridge_mce_dec = {
3082         .notifier_call  = sbridge_mce_check_error,
3083         .priority       = MCE_PRIO_EDAC,
3084 };
3085
3086 /****************************************************************************
3087                         EDAC register/unregister logic
3088  ****************************************************************************/
3089
3090 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3091 {
3092         struct mem_ctl_info *mci = sbridge_dev->mci;
3093         struct sbridge_pvt *pvt;
3094
3095         if (unlikely(!mci || !mci->pvt_info)) {
3096                 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3097
3098                 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3099                 return;
3100         }
3101
3102         pvt = mci->pvt_info;
3103
3104         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3105                  mci, &sbridge_dev->pdev[0]->dev);
3106
3107         /* Remove MC sysfs nodes */
3108         edac_mc_del_mc(mci->pdev);
3109
3110         edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3111         kfree(mci->ctl_name);
3112         edac_mc_free(mci);
3113         sbridge_dev->mci = NULL;
3114 }
3115
3116 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3117 {
3118         struct mem_ctl_info *mci;
3119         struct edac_mc_layer layers[2];
3120         struct sbridge_pvt *pvt;
3121         struct pci_dev *pdev = sbridge_dev->pdev[0];
3122         int rc;
3123
3124         /* allocate a new MC control structure */
3125         layers[0].type = EDAC_MC_LAYER_CHANNEL;
3126         layers[0].size = type == KNIGHTS_LANDING ?
3127                 KNL_MAX_CHANNELS : NUM_CHANNELS;
3128         layers[0].is_virt_csrow = false;
3129         layers[1].type = EDAC_MC_LAYER_SLOT;
3130         layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3131         layers[1].is_virt_csrow = true;
3132         mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3133                             sizeof(*pvt));
3134
3135         if (unlikely(!mci))
3136                 return -ENOMEM;
3137
3138         edac_dbg(0, "MC: mci = %p, dev = %p\n",
3139                  mci, &pdev->dev);
3140
3141         pvt = mci->pvt_info;
3142         memset(pvt, 0, sizeof(*pvt));
3143
3144         /* Associate sbridge_dev and mci for future usage */
3145         pvt->sbridge_dev = sbridge_dev;
3146         sbridge_dev->mci = mci;
3147
3148         mci->mtype_cap = type == KNIGHTS_LANDING ?
3149                 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3150         mci->edac_ctl_cap = EDAC_FLAG_NONE;
3151         mci->edac_cap = EDAC_FLAG_NONE;
3152         mci->mod_name = EDAC_MOD_STR;
3153         mci->dev_name = pci_name(pdev);
3154         mci->ctl_page_to_phys = NULL;
3155
3156         pvt->info.type = type;
3157         switch (type) {
3158         case IVY_BRIDGE:
3159                 pvt->info.rankcfgr = IB_RANK_CFG_A;
3160                 pvt->info.get_tolm = ibridge_get_tolm;
3161                 pvt->info.get_tohm = ibridge_get_tohm;
3162                 pvt->info.dram_rule = ibridge_dram_rule;
3163                 pvt->info.get_memory_type = get_memory_type;
3164                 pvt->info.get_node_id = get_node_id;
3165                 pvt->info.rir_limit = rir_limit;
3166                 pvt->info.sad_limit = sad_limit;
3167                 pvt->info.interleave_mode = interleave_mode;
3168                 pvt->info.dram_attr = dram_attr;
3169                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3170                 pvt->info.interleave_list = ibridge_interleave_list;
3171                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3172                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3173                 pvt->info.get_width = ibridge_get_width;
3174
3175                 /* Store pci devices at mci for faster access */
3176                 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3177                 if (unlikely(rc < 0))
3178                         goto fail0;
3179                 get_source_id(mci);
3180                 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d",
3181                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3182                 break;
3183         case SANDY_BRIDGE:
3184                 pvt->info.rankcfgr = SB_RANK_CFG_A;
3185                 pvt->info.get_tolm = sbridge_get_tolm;
3186                 pvt->info.get_tohm = sbridge_get_tohm;
3187                 pvt->info.dram_rule = sbridge_dram_rule;
3188                 pvt->info.get_memory_type = get_memory_type;
3189                 pvt->info.get_node_id = get_node_id;
3190                 pvt->info.rir_limit = rir_limit;
3191                 pvt->info.sad_limit = sad_limit;
3192                 pvt->info.interleave_mode = interleave_mode;
3193                 pvt->info.dram_attr = dram_attr;
3194                 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3195                 pvt->info.interleave_list = sbridge_interleave_list;
3196                 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
3197                 pvt->info.interleave_pkg = sbridge_interleave_pkg;
3198                 pvt->info.get_width = sbridge_get_width;
3199
3200                 /* Store pci devices at mci for faster access */
3201                 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3202                 if (unlikely(rc < 0))
3203                         goto fail0;
3204                 get_source_id(mci);
3205                 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d",
3206                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3207                 break;
3208         case HASWELL:
3209                 /* rankcfgr isn't used */
3210                 pvt->info.get_tolm = haswell_get_tolm;
3211                 pvt->info.get_tohm = haswell_get_tohm;
3212                 pvt->info.dram_rule = ibridge_dram_rule;
3213                 pvt->info.get_memory_type = haswell_get_memory_type;
3214                 pvt->info.get_node_id = haswell_get_node_id;
3215                 pvt->info.rir_limit = haswell_rir_limit;
3216                 pvt->info.sad_limit = sad_limit;
3217                 pvt->info.interleave_mode = interleave_mode;
3218                 pvt->info.dram_attr = dram_attr;
3219                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3220                 pvt->info.interleave_list = ibridge_interleave_list;
3221                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3222                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3223                 pvt->info.get_width = ibridge_get_width;
3224
3225                 /* Store pci devices at mci for faster access */
3226                 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3227                 if (unlikely(rc < 0))
3228                         goto fail0;
3229                 get_source_id(mci);
3230                 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d",
3231                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3232                 break;
3233         case BROADWELL:
3234                 /* rankcfgr isn't used */
3235                 pvt->info.get_tolm = haswell_get_tolm;
3236                 pvt->info.get_tohm = haswell_get_tohm;
3237                 pvt->info.dram_rule = ibridge_dram_rule;
3238                 pvt->info.get_memory_type = haswell_get_memory_type;
3239                 pvt->info.get_node_id = haswell_get_node_id;
3240                 pvt->info.rir_limit = haswell_rir_limit;
3241                 pvt->info.sad_limit = sad_limit;
3242                 pvt->info.interleave_mode = interleave_mode;
3243                 pvt->info.dram_attr = dram_attr;
3244                 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3245                 pvt->info.interleave_list = ibridge_interleave_list;
3246                 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3247                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3248                 pvt->info.get_width = broadwell_get_width;
3249
3250                 /* Store pci devices at mci for faster access */
3251                 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3252                 if (unlikely(rc < 0))
3253                         goto fail0;
3254                 get_source_id(mci);
3255                 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d",
3256                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3257                 break;
3258         case KNIGHTS_LANDING:
3259                 /* pvt->info.rankcfgr == ??? */
3260                 pvt->info.get_tolm = knl_get_tolm;
3261                 pvt->info.get_tohm = knl_get_tohm;
3262                 pvt->info.dram_rule = knl_dram_rule;
3263                 pvt->info.get_memory_type = knl_get_memory_type;
3264                 pvt->info.get_node_id = knl_get_node_id;
3265                 pvt->info.rir_limit = NULL;
3266                 pvt->info.sad_limit = knl_sad_limit;
3267                 pvt->info.interleave_mode = knl_interleave_mode;
3268                 pvt->info.dram_attr = dram_attr_knl;
3269                 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3270                 pvt->info.interleave_list = knl_interleave_list;
3271                 pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
3272                 pvt->info.interleave_pkg = ibridge_interleave_pkg;
3273                 pvt->info.get_width = knl_get_width;
3274
3275                 rc = knl_mci_bind_devs(mci, sbridge_dev);
3276                 if (unlikely(rc < 0))
3277                         goto fail0;
3278                 get_source_id(mci);
3279                 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d",
3280                         pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
3281                 break;
3282         }
3283
3284         if (!mci->ctl_name) {
3285                 rc = -ENOMEM;
3286                 goto fail0;
3287         }
3288
3289         /* Get dimm basic config and the memory layout */
3290         rc = get_dimm_config(mci);
3291         if (rc < 0) {
3292                 edac_dbg(0, "MC: failed to get_dimm_config()\n");
3293                 goto fail;
3294         }
3295         get_memory_layout(mci);
3296
3297         /* record ptr to the generic device */
3298         mci->pdev = &pdev->dev;
3299
3300         /* add this new MC control structure to EDAC's list of MCs */
3301         if (unlikely(edac_mc_add_mc(mci))) {
3302                 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3303                 rc = -EINVAL;
3304                 goto fail;
3305         }
3306
3307         return 0;
3308
3309 fail:
3310         kfree(mci->ctl_name);
3311 fail0:
3312         edac_mc_free(mci);
3313         sbridge_dev->mci = NULL;
3314         return rc;
3315 }
3316
3317 #define ICPU(model, table) \
3318         { X86_VENDOR_INTEL, 6, model, 0, (unsigned long)&table }
3319
3320 static const struct x86_cpu_id sbridge_cpuids[] = {
3321         ICPU(INTEL_FAM6_SANDYBRIDGE_X,    pci_dev_descr_sbridge_table),
3322         ICPU(INTEL_FAM6_IVYBRIDGE_X,      pci_dev_descr_ibridge_table),
3323         ICPU(INTEL_FAM6_HASWELL_X,        pci_dev_descr_haswell_table),
3324         ICPU(INTEL_FAM6_BROADWELL_X,      pci_dev_descr_broadwell_table),
3325         ICPU(INTEL_FAM6_BROADWELL_XEON_D, pci_dev_descr_broadwell_table),
3326         ICPU(INTEL_FAM6_XEON_PHI_KNL,     pci_dev_descr_knl_table),
3327         ICPU(INTEL_FAM6_XEON_PHI_KNM,     pci_dev_descr_knl_table),
3328         { }
3329 };
3330 MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3331
3332 /*
3333  *      sbridge_probe   Get all devices and register memory controllers
3334  *                      present.
3335  *      return:
3336  *              0 for FOUND a device
3337  *              < 0 for error code
3338  */
3339
3340 static int sbridge_probe(const struct x86_cpu_id *id)
3341 {
3342         int rc = -ENODEV;
3343         u8 mc, num_mc = 0;
3344         struct sbridge_dev *sbridge_dev;
3345         struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
3346
3347         /* get the pci devices we want to reserve for our use */
3348         rc = sbridge_get_all_devices(&num_mc, ptable);
3349
3350         if (unlikely(rc < 0)) {
3351                 edac_dbg(0, "couldn't get all devices\n");
3352                 goto fail0;
3353         }
3354
3355         mc = 0;
3356
3357         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3358                 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3359                          mc, mc + 1, num_mc);
3360
3361                 sbridge_dev->mc = mc++;
3362                 rc = sbridge_register_mci(sbridge_dev, ptable->type);
3363                 if (unlikely(rc < 0))
3364                         goto fail1;
3365         }
3366
3367         sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3368
3369         return 0;
3370
3371 fail1:
3372         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3373                 sbridge_unregister_mci(sbridge_dev);
3374
3375         sbridge_put_all_devices();
3376 fail0:
3377         return rc;
3378 }
3379
3380 /*
3381  *      sbridge_remove  cleanup
3382  *
3383  */
3384 static void sbridge_remove(void)
3385 {
3386         struct sbridge_dev *sbridge_dev;
3387
3388         edac_dbg(0, "\n");
3389
3390         list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3391                 sbridge_unregister_mci(sbridge_dev);
3392
3393         /* Release PCI resources */
3394         sbridge_put_all_devices();
3395 }
3396
3397 /*
3398  *      sbridge_init            Module entry function
3399  *                      Try to initialize this module for its devices
3400  */
3401 static int __init sbridge_init(void)
3402 {
3403         const struct x86_cpu_id *id;
3404         const char *owner;
3405         int rc;
3406
3407         edac_dbg(2, "\n");
3408
3409         owner = edac_get_owner();
3410         if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
3411                 return -EBUSY;
3412
3413         id = x86_match_cpu(sbridge_cpuids);
3414         if (!id)
3415                 return -ENODEV;
3416
3417         /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3418         opstate_init();
3419
3420         rc = sbridge_probe(id);
3421
3422         if (rc >= 0) {
3423                 mce_register_decode_chain(&sbridge_mce_dec);
3424                 if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
3425                         sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3426                 return 0;
3427         }
3428
3429         sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3430                       rc);
3431
3432         return rc;
3433 }
3434
3435 /*
3436  *      sbridge_exit()  Module exit function
3437  *                      Unregister the driver
3438  */
3439 static void __exit sbridge_exit(void)
3440 {
3441         edac_dbg(2, "\n");
3442         sbridge_remove();
3443         mce_unregister_decode_chain(&sbridge_mce_dec);
3444 }
3445
3446 module_init(sbridge_init);
3447 module_exit(sbridge_exit);
3448
3449 module_param(edac_op_state, int, 0444);
3450 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3451
3452 MODULE_LICENSE("GPL");
3453 MODULE_AUTHOR("Mauro Carvalho Chehab");
3454 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3455 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
3456                    SBRIDGE_REVISION);