drivers/dma/tegra210-adma.c

   1 /*
   2  * ADMA driver for Nvidia's Tegra210 ADMA controller.
   3  *
   4  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_dma.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27
  28 #include "virt-dma.h"
  29
  30 #define ADMA_CH_CMD                                     0x00
  31 #define ADMA_CH_STATUS                                  0x0c
  32 #define ADMA_CH_STATUS_XFER_EN                          BIT(0)
  33 #define ADMA_CH_STATUS_XFER_PAUSED                      BIT(1)
  34
  35 #define ADMA_CH_INT_STATUS                              0x10
  36 #define ADMA_CH_INT_STATUS_XFER_DONE                    BIT(0)
  37
  38 #define ADMA_CH_INT_CLEAR                               0x1c
  39 #define ADMA_CH_CTRL                                    0x24
  40 #define ADMA_CH_CTRL_DIR(val)                           (((val) & 0xf) << 12)
  41 #define ADMA_CH_CTRL_DIR_AHUB2MEM                       2
  42 #define ADMA_CH_CTRL_DIR_MEM2AHUB                       4
  43 #define ADMA_CH_CTRL_MODE_CONTINUOUS                    (2 << 8)
  44 #define ADMA_CH_CTRL_FLOWCTRL_EN                        BIT(1)
  45 #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT                   0
  46
  47 #define ADMA_CH_CONFIG                                  0x28
  48 #define ADMA_CH_CONFIG_SRC_BUF(val)                     (((val) & 0x7) << 28)
  49 #define ADMA_CH_CONFIG_TRG_BUF(val)                     (((val) & 0x7) << 24)
  50 #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT                 20
  51 #define ADMA_CH_CONFIG_MAX_BURST_SIZE                   16
  52 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val)              ((val) & 0xf)
  53 #define ADMA_CH_CONFIG_MAX_BUFS                         8
  54
  55 #define ADMA_CH_FIFO_CTRL                               0x2c
  56 #define ADMA_CH_FIFO_CTRL_OVRFW_THRES(val)              (((val) & 0xf) << 24)
  57 #define ADMA_CH_FIFO_CTRL_STARV_THRES(val)              (((val) & 0xf) << 16)
  58 #define ADMA_CH_FIFO_CTRL_TX_FIFO_SIZE_SHIFT            8
  59 #define ADMA_CH_FIFO_CTRL_RX_FIFO_SIZE_SHIFT            0
  60
  61 #define ADMA_CH_LOWER_SRC_ADDR                          0x34
  62 #define ADMA_CH_LOWER_TRG_ADDR                          0x3c
  63 #define ADMA_CH_TC                                      0x44
  64 #define ADMA_CH_TC_COUNT_MASK                           0x3ffffffc
  65
  66 #define ADMA_CH_XFER_STATUS                             0x54
  67 #define ADMA_CH_XFER_STATUS_COUNT_MASK                  0xffff
  68
  69 #define ADMA_GLOBAL_CMD                                 0x00
  70 #define ADMA_GLOBAL_SOFT_RESET                          0x04
  71
  72 #define TEGRA_ADMA_BURST_COMPLETE_TIME                  20
  73
  74 #define ADMA_CH_FIFO_CTRL_DEFAULT       (ADMA_CH_FIFO_CTRL_OVRFW_THRES(1) | \
  75                                          ADMA_CH_FIFO_CTRL_STARV_THRES(1))
  76
  77 #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
  78
  79 struct tegra_adma;
  80
  81 /*
  82  * struct tegra_adma_chip_data - Tegra chip specific data
  83  * @global_reg_offset: Register offset of DMA global register.
  84  * @global_int_clear: Register offset of DMA global interrupt clear.
  85  * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
  86  * @ch_req_rx_shift: Register offset for AHUB receive channel select.
  87  * @ch_base_offset: Reister offset of DMA channel registers.
  88  * @ch_req_mask: Mask for Tx or Rx channel select.
  89  * @ch_req_max: Maximum number of Tx or Rx channels available.
  90  * @ch_reg_size: Size of DMA channel register space.
  91  * @nr_channels: Number of DMA channels available.
  92  */
  93 struct tegra_adma_chip_data {
  94         unsigned int (*adma_get_burst_config)(unsigned int burst_size);
  95         unsigned int global_reg_offset;
  96         unsigned int global_int_clear;
  97         unsigned int ch_req_tx_shift;
  98         unsigned int ch_req_rx_shift;
  99         unsigned int ch_base_offset;
 100         unsigned int ch_req_mask;
 101         unsigned int ch_req_max;
 102         unsigned int ch_reg_size;
 103         unsigned int nr_channels;
 104 };
 105
 106 /*
 107  * struct tegra_adma_chan_regs - Tegra ADMA channel registers
 108  */
 109 struct tegra_adma_chan_regs {
 110         unsigned int ctrl;
 111         unsigned int config;
 112         unsigned int src_addr;
 113         unsigned int trg_addr;
 114         unsigned int fifo_ctrl;
 115         unsigned int cmd;
 116         unsigned int tc;
 117 };
 118
 119 /*
 120  * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
 121  */
 122 struct tegra_adma_desc {
 123         struct virt_dma_desc            vd;
 124         struct tegra_adma_chan_regs     ch_regs;
 125         size_t                          buf_len;
 126         size_t                          period_len;
 127         size_t                          num_periods;
 128 };
 129
 130 /*
 131  * struct tegra_adma_chan - Tegra ADMA channel information
 132  */
 133 struct tegra_adma_chan {
 134         struct virt_dma_chan            vc;
 135         struct tegra_adma_desc          *desc;
 136         struct tegra_adma               *tdma;
 137         int                             irq;
 138         void __iomem                    *chan_addr;
 139
 140         /* Slave channel configuration info */
 141         struct dma_slave_config         sconfig;
 142         enum dma_transfer_direction     sreq_dir;
 143         unsigned int                    sreq_index;
 144         bool                            sreq_reserved;
 145         struct tegra_adma_chan_regs     ch_regs;
 146
 147         /* Transfer count and position info */
 148         unsigned int                    tx_buf_count;
 149         unsigned int                    tx_buf_pos;
 150 };
 151
 152 /*
 153  * struct tegra_adma - Tegra ADMA controller information
 154  */
 155 struct tegra_adma {
 156         struct dma_device               dma_dev;
 157         struct device                   *dev;
 158         void __iomem                    *base_addr;
 159         struct clk                      *ahub_clk;
 160         unsigned int                    nr_channels;
 161         unsigned long                   rx_requests_reserved;
 162         unsigned long                   tx_requests_reserved;
 163
 164         /* Used to store global command register state when suspending */
 165         unsigned int                    global_cmd;
 166
 167         const struct tegra_adma_chip_data *cdata;
 168
 169         /* Last member of the structure */
 170         struct tegra_adma_chan          channels[0];
 171 };
 172
 173 static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
 174 {
 175         writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
 176 }
 177
 178 static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
 179 {
 180         return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
 181 }
 182
 183 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
 184 {
 185         writel(val, tdc->chan_addr + reg);
 186 }
 187
 188 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
 189 {
 190         return readl(tdc->chan_addr + reg);
 191 }
 192
 193 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
 194 {
 195         return container_of(dc, struct tegra_adma_chan, vc.chan);
 196 }
 197
 198 static inline struct tegra_adma_desc *to_tegra_adma_desc(
 199                 struct dma_async_tx_descriptor *td)
 200 {
 201         return container_of(td, struct tegra_adma_desc, vd.tx);
 202 }
 203
 204 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
 205 {
 206         return tdc->tdma->dev;
 207 }
 208
 209 static void tegra_adma_desc_free(struct virt_dma_desc *vd)
 210 {
 211         kfree(container_of(vd, struct tegra_adma_desc, vd));
 212 }
 213
 214 static int tegra_adma_slave_config(struct dma_chan *dc,
 215                                    struct dma_slave_config *sconfig)
 216 {
 217         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 218
 219         memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
 220
 221         return 0;
 222 }
 223
 224 static int tegra_adma_init(struct tegra_adma *tdma)
 225 {
 226         u32 status;
 227         int ret;
 228
 229         /* Clear any interrupts */
 230         tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
 231
 232         /* Assert soft reset */
 233         tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
 234
 235         /* Wait for reset to clear */
 236         ret = readx_poll_timeout(readl,
 237                                  tdma->base_addr +
 238                                  tdma->cdata->global_reg_offset +
 239                                  ADMA_GLOBAL_SOFT_RESET,
 240                                  status, status == 0, 20, 10000);
 241         if (ret)
 242                 return ret;
 243
 244         /* Enable global ADMA registers */
 245         tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
 246
 247         return 0;
 248 }
 249
 250 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
 251                                     enum dma_transfer_direction direction)
 252 {
 253         struct tegra_adma *tdma = tdc->tdma;
 254         unsigned int sreq_index = tdc->sreq_index;
 255
 256         if (tdc->sreq_reserved)
 257                 return tdc->sreq_dir == direction ? 0 : -EINVAL;
 258
 259         if (sreq_index > tdma->cdata->ch_req_max) {
 260                 dev_err(tdma->dev, "invalid DMA request\n");
 261                 return -EINVAL;
 262         }
 263
 264         switch (direction) {
 265         case DMA_MEM_TO_DEV:
 266                 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
 267                         dev_err(tdma->dev, "DMA request reserved\n");
 268                         return -EINVAL;
 269                 }
 270                 break;
 271
 272         case DMA_DEV_TO_MEM:
 273                 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
 274                         dev_err(tdma->dev, "DMA request reserved\n");
 275                         return -EINVAL;
 276                 }
 277                 break;
 278
 279         default:
 280                 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
 281                          dma_chan_name(&tdc->vc.chan));
 282                 return -EINVAL;
 283         }
 284
 285         tdc->sreq_dir = direction;
 286         tdc->sreq_reserved = true;
 287
 288         return 0;
 289 }
 290
 291 static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
 292 {
 293         struct tegra_adma *tdma = tdc->tdma;
 294
 295         if (!tdc->sreq_reserved)
 296                 return;
 297
 298         switch (tdc->sreq_dir) {
 299         case DMA_MEM_TO_DEV:
 300                 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
 301                 break;
 302
 303         case DMA_DEV_TO_MEM:
 304                 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
 305                 break;
 306
 307         default:
 308                 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
 309                          dma_chan_name(&tdc->vc.chan));
 310                 return;
 311         }
 312
 313         tdc->sreq_reserved = false;
 314 }
 315
 316 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
 317 {
 318         u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
 319
 320         return status & ADMA_CH_INT_STATUS_XFER_DONE;
 321 }
 322
 323 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
 324 {
 325         u32 status = tegra_adma_irq_status(tdc);
 326
 327         if (status)
 328                 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
 329
 330         return status;
 331 }
 332
 333 static void tegra_adma_stop(struct tegra_adma_chan *tdc)
 334 {
 335         unsigned int status;
 336
 337         /* Disable ADMA */
 338         tdma_ch_write(tdc, ADMA_CH_CMD, 0);
 339
 340         /* Clear interrupt status */
 341         tegra_adma_irq_clear(tdc);
 342
 343         if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
 344                         status, !(status & ADMA_CH_STATUS_XFER_EN),
 345                         20, 10000)) {
 346                 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
 347                 return;
 348         }
 349
 350         kfree(tdc->desc);
 351         tdc->desc = NULL;
 352 }
 353
 354 static void tegra_adma_start(struct tegra_adma_chan *tdc)
 355 {
 356         struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
 357         struct tegra_adma_chan_regs *ch_regs;
 358         struct tegra_adma_desc *desc;
 359
 360         if (!vd)
 361                 return;
 362
 363         list_del(&vd->node);
 364
 365         desc = to_tegra_adma_desc(&vd->tx);
 366
 367         if (!desc) {
 368                 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
 369                 return;
 370         }
 371
 372         ch_regs = &desc->ch_regs;
 373
 374         tdc->tx_buf_pos = 0;
 375         tdc->tx_buf_count = 0;
 376         tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
 377         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
 378         tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
 379         tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
 380         tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
 381         tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
 382
 383         /* Start ADMA */
 384         tdma_ch_write(tdc, ADMA_CH_CMD, 1);
 385
 386         tdc->desc = desc;
 387 }
 388
 389 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
 390 {
 391         struct tegra_adma_desc *desc = tdc->desc;
 392         unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
 393         unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
 394         unsigned int periods_remaining;
 395
 396         /*
 397          * Handle wrap around of buffer count register
 398          */
 399         if (pos < tdc->tx_buf_pos)
 400                 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
 401         else
 402                 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
 403
 404         periods_remaining = tdc->tx_buf_count % desc->num_periods;
 405         tdc->tx_buf_pos = pos;
 406
 407         return desc->buf_len - (periods_remaining * desc->period_len);
 408 }
 409
 410 static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
 411 {
 412         struct tegra_adma_chan *tdc = dev_id;
 413         unsigned long status;
 414         unsigned long flags;
 415
 416         spin_lock_irqsave(&tdc->vc.lock, flags);
 417
 418         status = tegra_adma_irq_clear(tdc);
 419         if (status == 0 || !tdc->desc) {
 420                 spin_unlock_irqrestore(&tdc->vc.lock, flags);
 421                 return IRQ_NONE;
 422         }
 423
 424         vchan_cyclic_callback(&tdc->desc->vd);
 425
 426         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 427
 428         return IRQ_HANDLED;
 429 }
 430
 431 static void tegra_adma_issue_pending(struct dma_chan *dc)
 432 {
 433         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 434         unsigned long flags;
 435
 436         spin_lock_irqsave(&tdc->vc.lock, flags);
 437
 438         if (vchan_issue_pending(&tdc->vc)) {
 439                 if (!tdc->desc)
 440                         tegra_adma_start(tdc);
 441         }
 442
 443         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 444 }
 445
 446 static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
 447 {
 448         u32 csts;
 449
 450         csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
 451         csts &= ADMA_CH_STATUS_XFER_PAUSED;
 452
 453         return csts ? true : false;
 454 }
 455
 456 static int tegra_adma_pause(struct dma_chan *dc)
 457 {
 458         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 459         struct tegra_adma_desc *desc = tdc->desc;
 460         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
 461         int dcnt = 10;
 462
 463         ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
 464         ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
 465         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
 466
 467         while (dcnt-- && !tegra_adma_is_paused(tdc))
 468                 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
 469
 470         if (dcnt < 0) {
 471                 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
 472                 return -EBUSY;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static int tegra_adma_resume(struct dma_chan *dc)
 479 {
 480         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 481         struct tegra_adma_desc *desc = tdc->desc;
 482         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
 483
 484         ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
 485         ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
 486         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
 487
 488         return 0;
 489 }
 490
 491 static int tegra_adma_terminate_all(struct dma_chan *dc)
 492 {
 493         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 494         unsigned long flags;
 495         LIST_HEAD(head);
 496
 497         spin_lock_irqsave(&tdc->vc.lock, flags);
 498
 499         if (tdc->desc)
 500                 tegra_adma_stop(tdc);
 501
 502         tegra_adma_request_free(tdc);
 503         vchan_get_all_descriptors(&tdc->vc, &head);
 504         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 505         vchan_dma_desc_free_list(&tdc->vc, &head);
 506
 507         return 0;
 508 }
 509
 510 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
 511                                             dma_cookie_t cookie,
 512                                             struct dma_tx_state *txstate)
 513 {
 514         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 515         struct tegra_adma_desc *desc;
 516         struct virt_dma_desc *vd;
 517         enum dma_status ret;
 518         unsigned long flags;
 519         unsigned int residual;
 520
 521         ret = dma_cookie_status(dc, cookie, txstate);
 522         if (ret == DMA_COMPLETE || !txstate)
 523                 return ret;
 524
 525         spin_lock_irqsave(&tdc->vc.lock, flags);
 526
 527         vd = vchan_find_desc(&tdc->vc, cookie);
 528         if (vd) {
 529                 desc = to_tegra_adma_desc(&vd->tx);
 530                 residual = desc->ch_regs.tc;
 531         } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
 532                 residual = tegra_adma_get_residue(tdc);
 533         } else {
 534                 residual = 0;
 535         }
 536
 537         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 538
 539         dma_set_residue(txstate, residual);
 540
 541         return ret;
 542 }
 543
 544 static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
 545 {
 546         if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
 547                 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
 548
 549         return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
 550 }
 551
 552 static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
 553 {
 554         if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
 555                 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
 556
 557         return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
 558 }
 559
 560 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
 561                                       struct tegra_adma_desc *desc,
 562                                       dma_addr_t buf_addr,
 563                                       enum dma_transfer_direction direction)
 564 {
 565         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
 566         const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
 567         unsigned int burst_size, adma_dir;
 568
 569         if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
 570                 return -EINVAL;
 571
 572         switch (direction) {
 573         case DMA_MEM_TO_DEV:
 574                 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
 575                 burst_size = tdc->sconfig.dst_maxburst;
 576                 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
 577                 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
 578                                                       cdata->ch_req_mask,
 579                                                       cdata->ch_req_tx_shift);
 580                 ch_regs->src_addr = buf_addr;
 581                 break;
 582
 583         case DMA_DEV_TO_MEM:
 584                 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
 585                 burst_size = tdc->sconfig.src_maxburst;
 586                 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
 587                 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
 588                                                       cdata->ch_req_mask,
 589                                                       cdata->ch_req_rx_shift);
 590                 ch_regs->trg_addr = buf_addr;
 591                 break;
 592
 593         default:
 594                 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
 595                 return -EINVAL;
 596         }
 597
 598         ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
 599                          ADMA_CH_CTRL_MODE_CONTINUOUS |
 600                          ADMA_CH_CTRL_FLOWCTRL_EN;
 601         ch_regs->config |= cdata->adma_get_burst_config(burst_size);
 602         ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
 603         ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT;
 604         ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
 605
 606         return tegra_adma_request_alloc(tdc, direction);
 607 }
 608
 609 static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
 610         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
 611         size_t period_len, enum dma_transfer_direction direction,
 612         unsigned long flags)
 613 {
 614         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 615         struct tegra_adma_desc *desc = NULL;
 616
 617         if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
 618                 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
 619                 return NULL;
 620         }
 621
 622         if (buf_len % period_len) {
 623                 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
 624                 return NULL;
 625         }
 626
 627         if (!IS_ALIGNED(buf_addr, 4)) {
 628                 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
 629                 return NULL;
 630         }
 631
 632         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 633         if (!desc)
 634                 return NULL;
 635
 636         desc->buf_len = buf_len;
 637         desc->period_len = period_len;
 638         desc->num_periods = buf_len / period_len;
 639
 640         if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
 641                 kfree(desc);
 642                 return NULL;
 643         }
 644
 645         return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
 646 }
 647
 648 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
 649 {
 650         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 651         int ret;
 652
 653         ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
 654         if (ret) {
 655                 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
 656                         dma_chan_name(dc));
 657                 return ret;
 658         }
 659
 660         ret = pm_runtime_get_sync(tdc2dev(tdc));
 661         if (ret < 0) {
 662                 free_irq(tdc->irq, tdc);
 663                 return ret;
 664         }
 665
 666         dma_cookie_init(&tdc->vc.chan);
 667
 668         return 0;
 669 }
 670
 671 static void tegra_adma_free_chan_resources(struct dma_chan *dc)
 672 {
 673         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 674
 675         tegra_adma_terminate_all(dc);
 676         vchan_free_chan_resources(&tdc->vc);
 677         tasklet_kill(&tdc->vc.task);
 678         free_irq(tdc->irq, tdc);
 679         pm_runtime_put(tdc2dev(tdc));
 680
 681         tdc->sreq_index = 0;
 682         tdc->sreq_dir = DMA_TRANS_NONE;
 683 }
 684
 685 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
 686                                            struct of_dma *ofdma)
 687 {
 688         struct tegra_adma *tdma = ofdma->of_dma_data;
 689         struct tegra_adma_chan *tdc;
 690         struct dma_chan *chan;
 691         unsigned int sreq_index;
 692
 693         if (dma_spec->args_count != 1)
 694                 return NULL;
 695
 696         sreq_index = dma_spec->args[0];
 697
 698         if (sreq_index == 0) {
 699                 dev_err(tdma->dev, "DMA request must not be 0\n");
 700                 return NULL;
 701         }
 702
 703         chan = dma_get_any_slave_channel(&tdma->dma_dev);
 704         if (!chan)
 705                 return NULL;
 706
 707         tdc = to_tegra_adma_chan(chan);
 708         tdc->sreq_index = sreq_index;
 709
 710         return chan;
 711 }
 712
 713 static int tegra_adma_runtime_suspend(struct device *dev)
 714 {
 715         struct tegra_adma *tdma = dev_get_drvdata(dev);
 716         struct tegra_adma_chan_regs *ch_reg;
 717         struct tegra_adma_chan *tdc;
 718         int i;
 719
 720         tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
 721         if (!tdma->global_cmd)
 722                 goto clk_disable;
 723
 724         for (i = 0; i < tdma->nr_channels; i++) {
 725                 tdc = &tdma->channels[i];
 726                 ch_reg = &tdc->ch_regs;
 727                 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
 728                 /* skip if channel is not active */
 729                 if (!ch_reg->cmd)
 730                         continue;
 731                 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
 732                 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
 733                 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
 734                 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
 735                 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
 736                 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
 737         }
 738
 739 clk_disable:
 740         clk_disable_unprepare(tdma->ahub_clk);
 741
 742         return 0;
 743 }
 744
 745 static int tegra_adma_runtime_resume(struct device *dev)
 746 {
 747         struct tegra_adma *tdma = dev_get_drvdata(dev);
 748         struct tegra_adma_chan_regs *ch_reg;
 749         struct tegra_adma_chan *tdc;
 750         int ret, i;
 751
 752         ret = clk_prepare_enable(tdma->ahub_clk);
 753         if (ret) {
 754                 dev_err(dev, "ahub clk_enable failed: %d\n", ret);
 755                 return ret;
 756         }
 757         tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
 758
 759         if (!tdma->global_cmd)
 760                 return 0;
 761
 762         for (i = 0; i < tdma->nr_channels; i++) {
 763                 tdc = &tdma->channels[i];
 764                 ch_reg = &tdc->ch_regs;
 765                 /* skip if channel was not active earlier */
 766                 if (!ch_reg->cmd)
 767                         continue;
 768                 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
 769                 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
 770                 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
 771                 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
 772                 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
 773                 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
 774                 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
 775         }
 776
 777         return 0;
 778 }
 779
 780 static const struct tegra_adma_chip_data tegra210_chip_data = {
 781         .adma_get_burst_config  = tegra210_adma_get_burst_config,
 782         .global_reg_offset      = 0xc00,
 783         .global_int_clear       = 0x20,
 784         .ch_req_tx_shift        = 28,
 785         .ch_req_rx_shift        = 24,
 786         .ch_base_offset         = 0,
 787         .ch_req_mask            = 0xf,
 788         .ch_req_max             = 10,
 789         .ch_reg_size            = 0x80,
 790         .nr_channels            = 22,
 791 };
 792
 793 static const struct tegra_adma_chip_data tegra186_chip_data = {
 794         .adma_get_burst_config  = tegra186_adma_get_burst_config,
 795         .global_reg_offset      = 0,
 796         .global_int_clear       = 0x402c,
 797         .ch_req_tx_shift        = 27,
 798         .ch_req_rx_shift        = 22,
 799         .ch_base_offset         = 0x10000,
 800         .ch_req_mask            = 0x1f,
 801         .ch_req_max             = 20,
 802         .ch_reg_size            = 0x100,
 803         .nr_channels            = 32,
 804 };
 805
 806 static const struct of_device_id tegra_adma_of_match[] = {
 807         { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
 808         { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
 809         { },
 810 };
 811 MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
 812
 813 static int tegra_adma_probe(struct platform_device *pdev)
 814 {
 815         const struct tegra_adma_chip_data *cdata;
 816         struct tegra_adma *tdma;
 817         struct resource *res;
 818         int ret, i;
 819
 820         cdata = of_device_get_match_data(&pdev->dev);
 821         if (!cdata) {
 822                 dev_err(&pdev->dev, "device match data not found\n");
 823                 return -ENODEV;
 824         }
 825
 826         tdma = devm_kzalloc(&pdev->dev,
 827                             struct_size(tdma, channels, cdata->nr_channels),
 828                             GFP_KERNEL);
 829         if (!tdma)
 830                 return -ENOMEM;
 831
 832         tdma->dev = &pdev->dev;
 833         tdma->cdata = cdata;
 834         tdma->nr_channels = cdata->nr_channels;
 835         platform_set_drvdata(pdev, tdma);
 836
 837         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 838         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
 839         if (IS_ERR(tdma->base_addr))
 840                 return PTR_ERR(tdma->base_addr);
 841
 842         tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
 843         if (IS_ERR(tdma->ahub_clk)) {
 844                 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
 845                 return PTR_ERR(tdma->ahub_clk);
 846         }
 847
 848         pm_runtime_enable(&pdev->dev);
 849
 850         ret = pm_runtime_get_sync(&pdev->dev);
 851         if (ret < 0)
 852                 goto rpm_disable;
 853
 854         ret = tegra_adma_init(tdma);
 855         if (ret)
 856                 goto rpm_put;
 857
 858         INIT_LIST_HEAD(&tdma->dma_dev.channels);
 859         for (i = 0; i < tdma->nr_channels; i++) {
 860                 struct tegra_adma_chan *tdc = &tdma->channels[i];
 861
 862                 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
 863                                  + (cdata->ch_reg_size * i);
 864
 865                 tdc->irq = of_irq_get(pdev->dev.of_node, i);
 866                 if (tdc->irq <= 0) {
 867                         ret = tdc->irq ?: -ENXIO;
 868                         goto irq_dispose;
 869                 }
 870
 871                 vchan_init(&tdc->vc, &tdma->dma_dev);
 872                 tdc->vc.desc_free = tegra_adma_desc_free;
 873                 tdc->tdma = tdma;
 874         }
 875
 876         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
 877         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
 878         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
 879
 880         tdma->dma_dev.dev = &pdev->dev;
 881         tdma->dma_dev.device_alloc_chan_resources =
 882                                         tegra_adma_alloc_chan_resources;
 883         tdma->dma_dev.device_free_chan_resources =
 884                                         tegra_adma_free_chan_resources;
 885         tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
 886         tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
 887         tdma->dma_dev.device_config = tegra_adma_slave_config;
 888         tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
 889         tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
 890         tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 891         tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 892         tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 893         tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
 894         tdma->dma_dev.device_pause = tegra_adma_pause;
 895         tdma->dma_dev.device_resume = tegra_adma_resume;
 896
 897         ret = dma_async_device_register(&tdma->dma_dev);
 898         if (ret < 0) {
 899                 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
 900                 goto irq_dispose;
 901         }
 902
 903         ret = of_dma_controller_register(pdev->dev.of_node,
 904                                          tegra_dma_of_xlate, tdma);
 905         if (ret < 0) {
 906                 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
 907                 goto dma_remove;
 908         }
 909
 910         pm_runtime_put(&pdev->dev);
 911
 912         dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
 913                  tdma->nr_channels);
 914
 915         return 0;
 916
 917 dma_remove:
 918         dma_async_device_unregister(&tdma->dma_dev);
 919 irq_dispose:
 920         while (--i >= 0)
 921                 irq_dispose_mapping(tdma->channels[i].irq);
 922 rpm_put:
 923         pm_runtime_put_sync(&pdev->dev);
 924 rpm_disable:
 925         pm_runtime_disable(&pdev->dev);
 926
 927         return ret;
 928 }
 929
 930 static int tegra_adma_remove(struct platform_device *pdev)
 931 {
 932         struct tegra_adma *tdma = platform_get_drvdata(pdev);
 933         int i;
 934
 935         of_dma_controller_free(pdev->dev.of_node);
 936         dma_async_device_unregister(&tdma->dma_dev);
 937
 938         for (i = 0; i < tdma->nr_channels; ++i)
 939                 irq_dispose_mapping(tdma->channels[i].irq);
 940
 941         pm_runtime_put_sync(&pdev->dev);
 942         pm_runtime_disable(&pdev->dev);
 943
 944         return 0;
 945 }
 946
 947 static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
 948         SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
 949                            tegra_adma_runtime_resume, NULL)
 950         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 951                                      pm_runtime_force_resume)
 952 };
 953
 954 static struct platform_driver tegra_admac_driver = {
 955         .driver = {
 956                 .name   = "tegra-adma",
 957                 .pm     = &tegra_adma_dev_pm_ops,
 958                 .of_match_table = tegra_adma_of_match,
 959         },
 960         .probe          = tegra_adma_probe,
 961         .remove         = tegra_adma_remove,
 962 };
 963
 964 module_platform_driver(tegra_admac_driver);
 965
 966 MODULE_ALIAS("platform:tegra210-adma");
 967 MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
 968 MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
 969 MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
 970 MODULE_LICENSE("GPL v2");