drivers/dma/tegra210-adma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADMA driver for Nvidia's Tegra210 ADMA controller.
   4  *
   5  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/of_dma.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/slab.h>
  16
  17 #include "virt-dma.h"
  18
  19 #define ADMA_CH_CMD                                     0x00
  20 #define ADMA_CH_STATUS                                  0x0c
  21 #define ADMA_CH_STATUS_XFER_EN                          BIT(0)
  22 #define ADMA_CH_STATUS_XFER_PAUSED                      BIT(1)
  23
  24 #define ADMA_CH_INT_STATUS                              0x10
  25 #define ADMA_CH_INT_STATUS_XFER_DONE                    BIT(0)
  26
  27 #define ADMA_CH_INT_CLEAR                               0x1c
  28 #define ADMA_CH_CTRL                                    0x24
  29 #define ADMA_CH_CTRL_DIR(val)                           (((val) & 0xf) << 12)
  30 #define ADMA_CH_CTRL_DIR_AHUB2MEM                       2
  31 #define ADMA_CH_CTRL_DIR_MEM2AHUB                       4
  32 #define ADMA_CH_CTRL_MODE_CONTINUOUS                    (2 << 8)
  33 #define ADMA_CH_CTRL_FLOWCTRL_EN                        BIT(1)
  34 #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT                   0
  35
  36 #define ADMA_CH_CONFIG                                  0x28
  37 #define ADMA_CH_CONFIG_SRC_BUF(val)                     (((val) & 0x7) << 28)
  38 #define ADMA_CH_CONFIG_TRG_BUF(val)                     (((val) & 0x7) << 24)
  39 #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT                 20
  40 #define ADMA_CH_CONFIG_MAX_BURST_SIZE                   16
  41 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val)              ((val) & 0xf)
  42 #define ADMA_CH_CONFIG_MAX_BUFS                         8
  43
  44 #define ADMA_CH_FIFO_CTRL                               0x2c
  45 #define ADMA_CH_FIFO_CTRL_OVRFW_THRES(val)              (((val) & 0xf) << 24)
  46 #define ADMA_CH_FIFO_CTRL_STARV_THRES(val)              (((val) & 0xf) << 16)
  47 #define ADMA_CH_FIFO_CTRL_TX_FIFO_SIZE_SHIFT            8
  48 #define ADMA_CH_FIFO_CTRL_RX_FIFO_SIZE_SHIFT            0
  49
  50 #define ADMA_CH_LOWER_SRC_ADDR                          0x34
  51 #define ADMA_CH_LOWER_TRG_ADDR                          0x3c
  52 #define ADMA_CH_TC                                      0x44
  53 #define ADMA_CH_TC_COUNT_MASK                           0x3ffffffc
  54
  55 #define ADMA_CH_XFER_STATUS                             0x54
  56 #define ADMA_CH_XFER_STATUS_COUNT_MASK                  0xffff
  57
  58 #define ADMA_GLOBAL_CMD                                 0x00
  59 #define ADMA_GLOBAL_SOFT_RESET                          0x04
  60
  61 #define TEGRA_ADMA_BURST_COMPLETE_TIME                  20
  62
  63 #define ADMA_CH_FIFO_CTRL_DEFAULT       (ADMA_CH_FIFO_CTRL_OVRFW_THRES(1) | \
  64                                          ADMA_CH_FIFO_CTRL_STARV_THRES(1))
  65
  66 #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
  67
  68 struct tegra_adma;
  69
  70 /*
  71  * struct tegra_adma_chip_data - Tegra chip specific data
  72  * @global_reg_offset: Register offset of DMA global register.
  73  * @global_int_clear: Register offset of DMA global interrupt clear.
  74  * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
  75  * @ch_req_rx_shift: Register offset for AHUB receive channel select.
  76  * @ch_base_offset: Reister offset of DMA channel registers.
  77  * @ch_req_mask: Mask for Tx or Rx channel select.
  78  * @ch_req_max: Maximum number of Tx or Rx channels available.
  79  * @ch_reg_size: Size of DMA channel register space.
  80  * @nr_channels: Number of DMA channels available.
  81  */
  82 struct tegra_adma_chip_data {
  83         unsigned int (*adma_get_burst_config)(unsigned int burst_size);
  84         unsigned int global_reg_offset;
  85         unsigned int global_int_clear;
  86         unsigned int ch_req_tx_shift;
  87         unsigned int ch_req_rx_shift;
  88         unsigned int ch_base_offset;
  89         unsigned int ch_req_mask;
  90         unsigned int ch_req_max;
  91         unsigned int ch_reg_size;
  92         unsigned int nr_channels;
  93 };
  94
  95 /*
  96  * struct tegra_adma_chan_regs - Tegra ADMA channel registers
  97  */
  98 struct tegra_adma_chan_regs {
  99         unsigned int ctrl;
 100         unsigned int config;
 101         unsigned int src_addr;
 102         unsigned int trg_addr;
 103         unsigned int fifo_ctrl;
 104         unsigned int cmd;
 105         unsigned int tc;
 106 };
 107
 108 /*
 109  * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
 110  */
 111 struct tegra_adma_desc {
 112         struct virt_dma_desc            vd;
 113         struct tegra_adma_chan_regs     ch_regs;
 114         size_t                          buf_len;
 115         size_t                          period_len;
 116         size_t                          num_periods;
 117 };
 118
 119 /*
 120  * struct tegra_adma_chan - Tegra ADMA channel information
 121  */
 122 struct tegra_adma_chan {
 123         struct virt_dma_chan            vc;
 124         struct tegra_adma_desc          *desc;
 125         struct tegra_adma               *tdma;
 126         int                             irq;
 127         void __iomem                    *chan_addr;
 128
 129         /* Slave channel configuration info */
 130         struct dma_slave_config         sconfig;
 131         enum dma_transfer_direction     sreq_dir;
 132         unsigned int                    sreq_index;
 133         bool                            sreq_reserved;
 134         struct tegra_adma_chan_regs     ch_regs;
 135
 136         /* Transfer count and position info */
 137         unsigned int                    tx_buf_count;
 138         unsigned int                    tx_buf_pos;
 139 };
 140
 141 /*
 142  * struct tegra_adma - Tegra ADMA controller information
 143  */
 144 struct tegra_adma {
 145         struct dma_device               dma_dev;
 146         struct device                   *dev;
 147         void __iomem                    *base_addr;
 148         struct clk                      *ahub_clk;
 149         unsigned int                    nr_channels;
 150         unsigned long                   rx_requests_reserved;
 151         unsigned long                   tx_requests_reserved;
 152
 153         /* Used to store global command register state when suspending */
 154         unsigned int                    global_cmd;
 155
 156         const struct tegra_adma_chip_data *cdata;
 157
 158         /* Last member of the structure */
 159         struct tegra_adma_chan          channels[0];
 160 };
 161
 162 static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
 163 {
 164         writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
 165 }
 166
 167 static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
 168 {
 169         return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
 170 }
 171
 172 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
 173 {
 174         writel(val, tdc->chan_addr + reg);
 175 }
 176
 177 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg)
 178 {
 179         return readl(tdc->chan_addr + reg);
 180 }
 181
 182 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc)
 183 {
 184         return container_of(dc, struct tegra_adma_chan, vc.chan);
 185 }
 186
 187 static inline struct tegra_adma_desc *to_tegra_adma_desc(
 188                 struct dma_async_tx_descriptor *td)
 189 {
 190         return container_of(td, struct tegra_adma_desc, vd.tx);
 191 }
 192
 193 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc)
 194 {
 195         return tdc->tdma->dev;
 196 }
 197
 198 static void tegra_adma_desc_free(struct virt_dma_desc *vd)
 199 {
 200         kfree(container_of(vd, struct tegra_adma_desc, vd));
 201 }
 202
 203 static int tegra_adma_slave_config(struct dma_chan *dc,
 204                                    struct dma_slave_config *sconfig)
 205 {
 206         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 207
 208         memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig));
 209
 210         return 0;
 211 }
 212
 213 static int tegra_adma_init(struct tegra_adma *tdma)
 214 {
 215         u32 status;
 216         int ret;
 217
 218         /* Clear any interrupts */
 219         tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
 220
 221         /* Assert soft reset */
 222         tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
 223
 224         /* Wait for reset to clear */
 225         ret = readx_poll_timeout(readl,
 226                                  tdma->base_addr +
 227                                  tdma->cdata->global_reg_offset +
 228                                  ADMA_GLOBAL_SOFT_RESET,
 229                                  status, status == 0, 20, 10000);
 230         if (ret)
 231                 return ret;
 232
 233         /* Enable global ADMA registers */
 234         tdma_write(tdma, ADMA_GLOBAL_CMD, 1);
 235
 236         return 0;
 237 }
 238
 239 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc,
 240                                     enum dma_transfer_direction direction)
 241 {
 242         struct tegra_adma *tdma = tdc->tdma;
 243         unsigned int sreq_index = tdc->sreq_index;
 244
 245         if (tdc->sreq_reserved)
 246                 return tdc->sreq_dir == direction ? 0 : -EINVAL;
 247
 248         if (sreq_index > tdma->cdata->ch_req_max) {
 249                 dev_err(tdma->dev, "invalid DMA request\n");
 250                 return -EINVAL;
 251         }
 252
 253         switch (direction) {
 254         case DMA_MEM_TO_DEV:
 255                 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
 256                         dev_err(tdma->dev, "DMA request reserved\n");
 257                         return -EINVAL;
 258                 }
 259                 break;
 260
 261         case DMA_DEV_TO_MEM:
 262                 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
 263                         dev_err(tdma->dev, "DMA request reserved\n");
 264                         return -EINVAL;
 265                 }
 266                 break;
 267
 268         default:
 269                 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
 270                          dma_chan_name(&tdc->vc.chan));
 271                 return -EINVAL;
 272         }
 273
 274         tdc->sreq_dir = direction;
 275         tdc->sreq_reserved = true;
 276
 277         return 0;
 278 }
 279
 280 static void tegra_adma_request_free(struct tegra_adma_chan *tdc)
 281 {
 282         struct tegra_adma *tdma = tdc->tdma;
 283
 284         if (!tdc->sreq_reserved)
 285                 return;
 286
 287         switch (tdc->sreq_dir) {
 288         case DMA_MEM_TO_DEV:
 289                 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved);
 290                 break;
 291
 292         case DMA_DEV_TO_MEM:
 293                 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved);
 294                 break;
 295
 296         default:
 297                 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n",
 298                          dma_chan_name(&tdc->vc.chan));
 299                 return;
 300         }
 301
 302         tdc->sreq_reserved = false;
 303 }
 304
 305 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc)
 306 {
 307         u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS);
 308
 309         return status & ADMA_CH_INT_STATUS_XFER_DONE;
 310 }
 311
 312 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc)
 313 {
 314         u32 status = tegra_adma_irq_status(tdc);
 315
 316         if (status)
 317                 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status);
 318
 319         return status;
 320 }
 321
 322 static void tegra_adma_stop(struct tegra_adma_chan *tdc)
 323 {
 324         unsigned int status;
 325
 326         /* Disable ADMA */
 327         tdma_ch_write(tdc, ADMA_CH_CMD, 0);
 328
 329         /* Clear interrupt status */
 330         tegra_adma_irq_clear(tdc);
 331
 332         if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS,
 333                         status, !(status & ADMA_CH_STATUS_XFER_EN),
 334                         20, 10000)) {
 335                 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n");
 336                 return;
 337         }
 338
 339         kfree(tdc->desc);
 340         tdc->desc = NULL;
 341 }
 342
 343 static void tegra_adma_start(struct tegra_adma_chan *tdc)
 344 {
 345         struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc);
 346         struct tegra_adma_chan_regs *ch_regs;
 347         struct tegra_adma_desc *desc;
 348
 349         if (!vd)
 350                 return;
 351
 352         list_del(&vd->node);
 353
 354         desc = to_tegra_adma_desc(&vd->tx);
 355
 356         if (!desc) {
 357                 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n");
 358                 return;
 359         }
 360
 361         ch_regs = &desc->ch_regs;
 362
 363         tdc->tx_buf_pos = 0;
 364         tdc->tx_buf_count = 0;
 365         tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc);
 366         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
 367         tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr);
 368         tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr);
 369         tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl);
 370         tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config);
 371
 372         /* Start ADMA */
 373         tdma_ch_write(tdc, ADMA_CH_CMD, 1);
 374
 375         tdc->desc = desc;
 376 }
 377
 378 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc)
 379 {
 380         struct tegra_adma_desc *desc = tdc->desc;
 381         unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1;
 382         unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS);
 383         unsigned int periods_remaining;
 384
 385         /*
 386          * Handle wrap around of buffer count register
 387          */
 388         if (pos < tdc->tx_buf_pos)
 389                 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos);
 390         else
 391                 tdc->tx_buf_count += pos - tdc->tx_buf_pos;
 392
 393         periods_remaining = tdc->tx_buf_count % desc->num_periods;
 394         tdc->tx_buf_pos = pos;
 395
 396         return desc->buf_len - (periods_remaining * desc->period_len);
 397 }
 398
 399 static irqreturn_t tegra_adma_isr(int irq, void *dev_id)
 400 {
 401         struct tegra_adma_chan *tdc = dev_id;
 402         unsigned long status;
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&tdc->vc.lock, flags);
 406
 407         status = tegra_adma_irq_clear(tdc);
 408         if (status == 0 || !tdc->desc) {
 409                 spin_unlock_irqrestore(&tdc->vc.lock, flags);
 410                 return IRQ_NONE;
 411         }
 412
 413         vchan_cyclic_callback(&tdc->desc->vd);
 414
 415         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 416
 417         return IRQ_HANDLED;
 418 }
 419
 420 static void tegra_adma_issue_pending(struct dma_chan *dc)
 421 {
 422         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 423         unsigned long flags;
 424
 425         spin_lock_irqsave(&tdc->vc.lock, flags);
 426
 427         if (vchan_issue_pending(&tdc->vc)) {
 428                 if (!tdc->desc)
 429                         tegra_adma_start(tdc);
 430         }
 431
 432         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 433 }
 434
 435 static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
 436 {
 437         u32 csts;
 438
 439         csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
 440         csts &= ADMA_CH_STATUS_XFER_PAUSED;
 441
 442         return csts ? true : false;
 443 }
 444
 445 static int tegra_adma_pause(struct dma_chan *dc)
 446 {
 447         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 448         struct tegra_adma_desc *desc = tdc->desc;
 449         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
 450         int dcnt = 10;
 451
 452         ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
 453         ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
 454         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
 455
 456         while (dcnt-- && !tegra_adma_is_paused(tdc))
 457                 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
 458
 459         if (dcnt < 0) {
 460                 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
 461                 return -EBUSY;
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int tegra_adma_resume(struct dma_chan *dc)
 468 {
 469         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 470         struct tegra_adma_desc *desc = tdc->desc;
 471         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
 472
 473         ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
 474         ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
 475         tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
 476
 477         return 0;
 478 }
 479
 480 static int tegra_adma_terminate_all(struct dma_chan *dc)
 481 {
 482         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 483         unsigned long flags;
 484         LIST_HEAD(head);
 485
 486         spin_lock_irqsave(&tdc->vc.lock, flags);
 487
 488         if (tdc->desc)
 489                 tegra_adma_stop(tdc);
 490
 491         tegra_adma_request_free(tdc);
 492         vchan_get_all_descriptors(&tdc->vc, &head);
 493         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 494         vchan_dma_desc_free_list(&tdc->vc, &head);
 495
 496         return 0;
 497 }
 498
 499 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc,
 500                                             dma_cookie_t cookie,
 501                                             struct dma_tx_state *txstate)
 502 {
 503         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 504         struct tegra_adma_desc *desc;
 505         struct virt_dma_desc *vd;
 506         enum dma_status ret;
 507         unsigned long flags;
 508         unsigned int residual;
 509
 510         ret = dma_cookie_status(dc, cookie, txstate);
 511         if (ret == DMA_COMPLETE || !txstate)
 512                 return ret;
 513
 514         spin_lock_irqsave(&tdc->vc.lock, flags);
 515
 516         vd = vchan_find_desc(&tdc->vc, cookie);
 517         if (vd) {
 518                 desc = to_tegra_adma_desc(&vd->tx);
 519                 residual = desc->ch_regs.tc;
 520         } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) {
 521                 residual = tegra_adma_get_residue(tdc);
 522         } else {
 523                 residual = 0;
 524         }
 525
 526         spin_unlock_irqrestore(&tdc->vc.lock, flags);
 527
 528         dma_set_residue(txstate, residual);
 529
 530         return ret;
 531 }
 532
 533 static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
 534 {
 535         if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
 536                 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
 537
 538         return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
 539 }
 540
 541 static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
 542 {
 543         if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
 544                 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
 545
 546         return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
 547 }
 548
 549 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
 550                                       struct tegra_adma_desc *desc,
 551                                       dma_addr_t buf_addr,
 552                                       enum dma_transfer_direction direction)
 553 {
 554         struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
 555         const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
 556         unsigned int burst_size, adma_dir;
 557
 558         if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
 559                 return -EINVAL;
 560
 561         switch (direction) {
 562         case DMA_MEM_TO_DEV:
 563                 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
 564                 burst_size = tdc->sconfig.dst_maxburst;
 565                 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
 566                 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
 567                                                       cdata->ch_req_mask,
 568                                                       cdata->ch_req_tx_shift);
 569                 ch_regs->src_addr = buf_addr;
 570                 break;
 571
 572         case DMA_DEV_TO_MEM:
 573                 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
 574                 burst_size = tdc->sconfig.src_maxburst;
 575                 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
 576                 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
 577                                                       cdata->ch_req_mask,
 578                                                       cdata->ch_req_rx_shift);
 579                 ch_regs->trg_addr = buf_addr;
 580                 break;
 581
 582         default:
 583                 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
 584                 return -EINVAL;
 585         }
 586
 587         ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) |
 588                          ADMA_CH_CTRL_MODE_CONTINUOUS |
 589                          ADMA_CH_CTRL_FLOWCTRL_EN;
 590         ch_regs->config |= cdata->adma_get_burst_config(burst_size);
 591         ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
 592         ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT;
 593         ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
 594
 595         return tegra_adma_request_alloc(tdc, direction);
 596 }
 597
 598 static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic(
 599         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
 600         size_t period_len, enum dma_transfer_direction direction,
 601         unsigned long flags)
 602 {
 603         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 604         struct tegra_adma_desc *desc = NULL;
 605
 606         if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) {
 607                 dev_err(tdc2dev(tdc), "invalid buffer/period len\n");
 608                 return NULL;
 609         }
 610
 611         if (buf_len % period_len) {
 612                 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n");
 613                 return NULL;
 614         }
 615
 616         if (!IS_ALIGNED(buf_addr, 4)) {
 617                 dev_err(tdc2dev(tdc), "invalid buffer alignment\n");
 618                 return NULL;
 619         }
 620
 621         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 622         if (!desc)
 623                 return NULL;
 624
 625         desc->buf_len = buf_len;
 626         desc->period_len = period_len;
 627         desc->num_periods = buf_len / period_len;
 628
 629         if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) {
 630                 kfree(desc);
 631                 return NULL;
 632         }
 633
 634         return vchan_tx_prep(&tdc->vc, &desc->vd, flags);
 635 }
 636
 637 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc)
 638 {
 639         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 640         int ret;
 641
 642         ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc);
 643         if (ret) {
 644                 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n",
 645                         dma_chan_name(dc));
 646                 return ret;
 647         }
 648
 649         ret = pm_runtime_get_sync(tdc2dev(tdc));
 650         if (ret < 0) {
 651                 free_irq(tdc->irq, tdc);
 652                 return ret;
 653         }
 654
 655         dma_cookie_init(&tdc->vc.chan);
 656
 657         return 0;
 658 }
 659
 660 static void tegra_adma_free_chan_resources(struct dma_chan *dc)
 661 {
 662         struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
 663
 664         tegra_adma_terminate_all(dc);
 665         vchan_free_chan_resources(&tdc->vc);
 666         tasklet_kill(&tdc->vc.task);
 667         free_irq(tdc->irq, tdc);
 668         pm_runtime_put(tdc2dev(tdc));
 669
 670         tdc->sreq_index = 0;
 671         tdc->sreq_dir = DMA_TRANS_NONE;
 672 }
 673
 674 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
 675                                            struct of_dma *ofdma)
 676 {
 677         struct tegra_adma *tdma = ofdma->of_dma_data;
 678         struct tegra_adma_chan *tdc;
 679         struct dma_chan *chan;
 680         unsigned int sreq_index;
 681
 682         if (dma_spec->args_count != 1)
 683                 return NULL;
 684
 685         sreq_index = dma_spec->args[0];
 686
 687         if (sreq_index == 0) {
 688                 dev_err(tdma->dev, "DMA request must not be 0\n");
 689                 return NULL;
 690         }
 691
 692         chan = dma_get_any_slave_channel(&tdma->dma_dev);
 693         if (!chan)
 694                 return NULL;
 695
 696         tdc = to_tegra_adma_chan(chan);
 697         tdc->sreq_index = sreq_index;
 698
 699         return chan;
 700 }
 701
 702 static int tegra_adma_runtime_suspend(struct device *dev)
 703 {
 704         struct tegra_adma *tdma = dev_get_drvdata(dev);
 705         struct tegra_adma_chan_regs *ch_reg;
 706         struct tegra_adma_chan *tdc;
 707         int i;
 708
 709         tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
 710         if (!tdma->global_cmd)
 711                 goto clk_disable;
 712
 713         for (i = 0; i < tdma->nr_channels; i++) {
 714                 tdc = &tdma->channels[i];
 715                 ch_reg = &tdc->ch_regs;
 716                 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
 717                 /* skip if channel is not active */
 718                 if (!ch_reg->cmd)
 719                         continue;
 720                 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
 721                 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
 722                 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
 723                 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
 724                 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
 725                 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
 726         }
 727
 728 clk_disable:
 729         clk_disable_unprepare(tdma->ahub_clk);
 730
 731         return 0;
 732 }
 733
 734 static int tegra_adma_runtime_resume(struct device *dev)
 735 {
 736         struct tegra_adma *tdma = dev_get_drvdata(dev);
 737         struct tegra_adma_chan_regs *ch_reg;
 738         struct tegra_adma_chan *tdc;
 739         int ret, i;
 740
 741         ret = clk_prepare_enable(tdma->ahub_clk);
 742         if (ret) {
 743                 dev_err(dev, "ahub clk_enable failed: %d\n", ret);
 744                 return ret;
 745         }
 746         tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
 747
 748         if (!tdma->global_cmd)
 749                 return 0;
 750
 751         for (i = 0; i < tdma->nr_channels; i++) {
 752                 tdc = &tdma->channels[i];
 753                 ch_reg = &tdc->ch_regs;
 754                 /* skip if channel was not active earlier */
 755                 if (!ch_reg->cmd)
 756                         continue;
 757                 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
 758                 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
 759                 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
 760                 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
 761                 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
 762                 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
 763                 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
 764         }
 765
 766         return 0;
 767 }
 768
 769 static const struct tegra_adma_chip_data tegra210_chip_data = {
 770         .adma_get_burst_config  = tegra210_adma_get_burst_config,
 771         .global_reg_offset      = 0xc00,
 772         .global_int_clear       = 0x20,
 773         .ch_req_tx_shift        = 28,
 774         .ch_req_rx_shift        = 24,
 775         .ch_base_offset         = 0,
 776         .ch_req_mask            = 0xf,
 777         .ch_req_max             = 10,
 778         .ch_reg_size            = 0x80,
 779         .nr_channels            = 22,
 780 };
 781
 782 static const struct tegra_adma_chip_data tegra186_chip_data = {
 783         .adma_get_burst_config  = tegra186_adma_get_burst_config,
 784         .global_reg_offset      = 0,
 785         .global_int_clear       = 0x402c,
 786         .ch_req_tx_shift        = 27,
 787         .ch_req_rx_shift        = 22,
 788         .ch_base_offset         = 0x10000,
 789         .ch_req_mask            = 0x1f,
 790         .ch_req_max             = 20,
 791         .ch_reg_size            = 0x100,
 792         .nr_channels            = 32,
 793 };
 794
 795 static const struct of_device_id tegra_adma_of_match[] = {
 796         { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
 797         { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
 798         { },
 799 };
 800 MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
 801
 802 static int tegra_adma_probe(struct platform_device *pdev)
 803 {
 804         const struct tegra_adma_chip_data *cdata;
 805         struct tegra_adma *tdma;
 806         struct resource *res;
 807         int ret, i;
 808
 809         cdata = of_device_get_match_data(&pdev->dev);
 810         if (!cdata) {
 811                 dev_err(&pdev->dev, "device match data not found\n");
 812                 return -ENODEV;
 813         }
 814
 815         tdma = devm_kzalloc(&pdev->dev,
 816                             struct_size(tdma, channels, cdata->nr_channels),
 817                             GFP_KERNEL);
 818         if (!tdma)
 819                 return -ENOMEM;
 820
 821         tdma->dev = &pdev->dev;
 822         tdma->cdata = cdata;
 823         tdma->nr_channels = cdata->nr_channels;
 824         platform_set_drvdata(pdev, tdma);
 825
 826         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 827         tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
 828         if (IS_ERR(tdma->base_addr))
 829                 return PTR_ERR(tdma->base_addr);
 830
 831         tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
 832         if (IS_ERR(tdma->ahub_clk)) {
 833                 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
 834                 return PTR_ERR(tdma->ahub_clk);
 835         }
 836
 837         pm_runtime_enable(&pdev->dev);
 838
 839         ret = pm_runtime_get_sync(&pdev->dev);
 840         if (ret < 0)
 841                 goto rpm_disable;
 842
 843         ret = tegra_adma_init(tdma);
 844         if (ret)
 845                 goto rpm_put;
 846
 847         INIT_LIST_HEAD(&tdma->dma_dev.channels);
 848         for (i = 0; i < tdma->nr_channels; i++) {
 849                 struct tegra_adma_chan *tdc = &tdma->channels[i];
 850
 851                 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
 852                                  + (cdata->ch_reg_size * i);
 853
 854                 tdc->irq = of_irq_get(pdev->dev.of_node, i);
 855                 if (tdc->irq <= 0) {
 856                         ret = tdc->irq ?: -ENXIO;
 857                         goto irq_dispose;
 858                 }
 859
 860                 vchan_init(&tdc->vc, &tdma->dma_dev);
 861                 tdc->vc.desc_free = tegra_adma_desc_free;
 862                 tdc->tdma = tdma;
 863         }
 864
 865         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
 866         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
 867         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
 868
 869         tdma->dma_dev.dev = &pdev->dev;
 870         tdma->dma_dev.device_alloc_chan_resources =
 871                                         tegra_adma_alloc_chan_resources;
 872         tdma->dma_dev.device_free_chan_resources =
 873                                         tegra_adma_free_chan_resources;
 874         tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending;
 875         tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic;
 876         tdma->dma_dev.device_config = tegra_adma_slave_config;
 877         tdma->dma_dev.device_tx_status = tegra_adma_tx_status;
 878         tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all;
 879         tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 880         tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 881         tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 882         tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
 883         tdma->dma_dev.device_pause = tegra_adma_pause;
 884         tdma->dma_dev.device_resume = tegra_adma_resume;
 885
 886         ret = dma_async_device_register(&tdma->dma_dev);
 887         if (ret < 0) {
 888                 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret);
 889                 goto irq_dispose;
 890         }
 891
 892         ret = of_dma_controller_register(pdev->dev.of_node,
 893                                          tegra_dma_of_xlate, tdma);
 894         if (ret < 0) {
 895                 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret);
 896                 goto dma_remove;
 897         }
 898
 899         pm_runtime_put(&pdev->dev);
 900
 901         dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n",
 902                  tdma->nr_channels);
 903
 904         return 0;
 905
 906 dma_remove:
 907         dma_async_device_unregister(&tdma->dma_dev);
 908 irq_dispose:
 909         while (--i >= 0)
 910                 irq_dispose_mapping(tdma->channels[i].irq);
 911 rpm_put:
 912         pm_runtime_put_sync(&pdev->dev);
 913 rpm_disable:
 914         pm_runtime_disable(&pdev->dev);
 915
 916         return ret;
 917 }
 918
 919 static int tegra_adma_remove(struct platform_device *pdev)
 920 {
 921         struct tegra_adma *tdma = platform_get_drvdata(pdev);
 922         int i;
 923
 924         of_dma_controller_free(pdev->dev.of_node);
 925         dma_async_device_unregister(&tdma->dma_dev);
 926
 927         for (i = 0; i < tdma->nr_channels; ++i)
 928                 irq_dispose_mapping(tdma->channels[i].irq);
 929
 930         pm_runtime_put_sync(&pdev->dev);
 931         pm_runtime_disable(&pdev->dev);
 932
 933         return 0;
 934 }
 935
 936 static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
 937         SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
 938                            tegra_adma_runtime_resume, NULL)
 939         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 940                                      pm_runtime_force_resume)
 941 };
 942
 943 static struct platform_driver tegra_admac_driver = {
 944         .driver = {
 945                 .name   = "tegra-adma",
 946                 .pm     = &tegra_adma_dev_pm_ops,
 947                 .of_match_table = tegra_adma_of_match,
 948         },
 949         .probe          = tegra_adma_probe,
 950         .remove         = tegra_adma_remove,
 951 };
 952
 953 module_platform_driver(tegra_admac_driver);
 954
 955 MODULE_ALIAS("platform:tegra210-adma");
 956 MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver");
 957 MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>");
 958 MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>");
 959 MODULE_LICENSE("GPL v2");