drivers/dma/ipu/ipu_idmac.c

   1 /*
   2  * Copyright (C) 2008
   3  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
   4  *
   5  * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/err.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/delay.h>
  17 #include <linux/list.h>
  18 #include <linux/clk.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/string.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23
  24 #include <mach/ipu.h>
  25
  26 #include "ipu_intern.h"
  27
  28 #define FS_VF_IN_VALID  0x00000002
  29 #define FS_ENC_IN_VALID 0x00000001
  30
  31 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
  32                                bool wait_for_stop);
  33
  34 /*
  35  * There can be only one, we could allocate it dynamically, but then we'd have
  36  * to add an extra parameter to some functions, and use something as ugly as
  37  *      struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
  38  * in the ISR
  39  */
  40 static struct ipu ipu_data;
  41
  42 #define to_ipu(id) container_of(id, struct ipu, idmac)
  43
  44 static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
  45 {
  46         return __raw_readl(ipu->reg_ic + reg);
  47 }
  48
  49 #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
  50
  51 static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
  52 {
  53         __raw_writel(value, ipu->reg_ic + reg);
  54 }
  55
  56 #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
  57
  58 static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
  59 {
  60         return __raw_readl(ipu->reg_ipu + reg);
  61 }
  62
  63 static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
  64 {
  65         __raw_writel(value, ipu->reg_ipu + reg);
  66 }
  67
  68 /*****************************************************************************
  69  * IPU / IC common functions
  70  */
  71 static void dump_idmac_reg(struct ipu *ipu)
  72 {
  73         dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
  74                 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
  75                 idmac_read_icreg(ipu, IDMAC_CONF),
  76                 idmac_read_icreg(ipu, IC_CONF),
  77                 idmac_read_icreg(ipu, IDMAC_CHA_EN),
  78                 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
  79                 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
  80         dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
  81                 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
  82                 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
  83                 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
  84                 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
  85                 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
  86                 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
  87 }
  88
  89 static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
  90 {
  91         switch (fmt) {
  92         case IPU_PIX_FMT_GENERIC:       /* generic data */
  93         case IPU_PIX_FMT_RGB332:
  94         case IPU_PIX_FMT_YUV420P:
  95         case IPU_PIX_FMT_YUV422P:
  96         default:
  97                 return 1;
  98         case IPU_PIX_FMT_RGB565:
  99         case IPU_PIX_FMT_YUYV:
 100         case IPU_PIX_FMT_UYVY:
 101                 return 2;
 102         case IPU_PIX_FMT_BGR24:
 103         case IPU_PIX_FMT_RGB24:
 104                 return 3;
 105         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
 106         case IPU_PIX_FMT_BGR32:
 107         case IPU_PIX_FMT_RGB32:
 108         case IPU_PIX_FMT_ABGR32:
 109                 return 4;
 110         }
 111 }
 112
 113 /* Enable direct write to memory by the Camera Sensor Interface */
 114 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
 115 {
 116         uint32_t ic_conf, mask;
 117
 118         switch (channel) {
 119         case IDMAC_IC_0:
 120                 mask = IC_CONF_PRPENC_EN;
 121                 break;
 122         case IDMAC_IC_7:
 123                 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
 124                 break;
 125         default:
 126                 return;
 127         }
 128         ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
 129         idmac_write_icreg(ipu, ic_conf, IC_CONF);
 130 }
 131
 132 /* Called under spin_lock_irqsave(&ipu_data.lock) */
 133 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
 134 {
 135         uint32_t ic_conf, mask;
 136
 137         switch (channel) {
 138         case IDMAC_IC_0:
 139                 mask = IC_CONF_PRPENC_EN;
 140                 break;
 141         case IDMAC_IC_7:
 142                 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
 143                 break;
 144         default:
 145                 return;
 146         }
 147         ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
 148         idmac_write_icreg(ipu, ic_conf, IC_CONF);
 149 }
 150
 151 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
 152 {
 153         uint32_t stat = TASK_STAT_IDLE;
 154         uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
 155
 156         switch (channel) {
 157         case IDMAC_IC_7:
 158                 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
 159                         TSTAT_CSI2MEM_OFFSET;
 160                 break;
 161         case IDMAC_IC_0:
 162         case IDMAC_SDC_0:
 163         case IDMAC_SDC_1:
 164         default:
 165                 break;
 166         }
 167         return stat;
 168 }
 169
 170 struct chan_param_mem_planar {
 171         /* Word 0 */
 172         u32     xv:10;
 173         u32     yv:10;
 174         u32     xb:12;
 175
 176         u32     yb:12;
 177         u32     res1:2;
 178         u32     nsb:1;
 179         u32     lnpb:6;
 180         u32     ubo_l:11;
 181
 182         u32     ubo_h:15;
 183         u32     vbo_l:17;
 184
 185         u32     vbo_h:9;
 186         u32     res2:3;
 187         u32     fw:12;
 188         u32     fh_l:8;
 189
 190         u32     fh_h:4;
 191         u32     res3:28;
 192
 193         /* Word 1 */
 194         u32     eba0;
 195
 196         u32     eba1;
 197
 198         u32     bpp:3;
 199         u32     sl:14;
 200         u32     pfs:3;
 201         u32     bam:3;
 202         u32     res4:2;
 203         u32     npb:6;
 204         u32     res5:1;
 205
 206         u32     sat:2;
 207         u32     res6:30;
 208 } __attribute__ ((packed));
 209
 210 struct chan_param_mem_interleaved {
 211         /* Word 0 */
 212         u32     xv:10;
 213         u32     yv:10;
 214         u32     xb:12;
 215
 216         u32     yb:12;
 217         u32     sce:1;
 218         u32     res1:1;
 219         u32     nsb:1;
 220         u32     lnpb:6;
 221         u32     sx:10;
 222         u32     sy_l:1;
 223
 224         u32     sy_h:9;
 225         u32     ns:10;
 226         u32     sm:10;
 227         u32     sdx_l:3;
 228
 229         u32     sdx_h:2;
 230         u32     sdy:5;
 231         u32     sdrx:1;
 232         u32     sdry:1;
 233         u32     sdr1:1;
 234         u32     res2:2;
 235         u32     fw:12;
 236         u32     fh_l:8;
 237
 238         u32     fh_h:4;
 239         u32     res3:28;
 240
 241         /* Word 1 */
 242         u32     eba0;
 243
 244         u32     eba1;
 245
 246         u32     bpp:3;
 247         u32     sl:14;
 248         u32     pfs:3;
 249         u32     bam:3;
 250         u32     res4:2;
 251         u32     npb:6;
 252         u32     res5:1;
 253
 254         u32     sat:2;
 255         u32     scc:1;
 256         u32     ofs0:5;
 257         u32     ofs1:5;
 258         u32     ofs2:5;
 259         u32     ofs3:5;
 260         u32     wid0:3;
 261         u32     wid1:3;
 262         u32     wid2:3;
 263
 264         u32     wid3:3;
 265         u32     dec_sel:1;
 266         u32     res6:28;
 267 } __attribute__ ((packed));
 268
 269 union chan_param_mem {
 270         struct chan_param_mem_planar            pp;
 271         struct chan_param_mem_interleaved       ip;
 272 };
 273
 274 static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
 275                                           u32 u_offset, u32 v_offset)
 276 {
 277         params->pp.ubo_l = u_offset & 0x7ff;
 278         params->pp.ubo_h = u_offset >> 11;
 279         params->pp.vbo_l = v_offset & 0x1ffff;
 280         params->pp.vbo_h = v_offset >> 17;
 281 }
 282
 283 static void ipu_ch_param_set_size(union chan_param_mem *params,
 284                                   uint32_t pixel_fmt, uint16_t width,
 285                                   uint16_t height, uint16_t stride)
 286 {
 287         u32 u_offset;
 288         u32 v_offset;
 289
 290         params->pp.fw           = width - 1;
 291         params->pp.fh_l         = height - 1;
 292         params->pp.fh_h         = (height - 1) >> 8;
 293         params->pp.sl           = stride - 1;
 294
 295         switch (pixel_fmt) {
 296         case IPU_PIX_FMT_GENERIC:
 297                 /*Represents 8-bit Generic data */
 298                 params->pp.bpp  = 3;
 299                 params->pp.pfs  = 7;
 300                 params->pp.npb  = 31;
 301                 params->pp.sat  = 2;            /* SAT = use 32-bit access */
 302                 break;
 303         case IPU_PIX_FMT_GENERIC_32:
 304                 /*Represents 32-bit Generic data */
 305                 params->pp.bpp  = 0;
 306                 params->pp.pfs  = 7;
 307                 params->pp.npb  = 7;
 308                 params->pp.sat  = 2;            /* SAT = use 32-bit access */
 309                 break;
 310         case IPU_PIX_FMT_RGB565:
 311                 params->ip.bpp  = 2;
 312                 params->ip.pfs  = 4;
 313                 params->ip.npb  = 7;
 314                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 315                 params->ip.ofs0 = 0;            /* Red bit offset */
 316                 params->ip.ofs1 = 5;            /* Green bit offset */
 317                 params->ip.ofs2 = 11;           /* Blue bit offset */
 318                 params->ip.ofs3 = 16;           /* Alpha bit offset */
 319                 params->ip.wid0 = 4;            /* Red bit width - 1 */
 320                 params->ip.wid1 = 5;            /* Green bit width - 1 */
 321                 params->ip.wid2 = 4;            /* Blue bit width - 1 */
 322                 break;
 323         case IPU_PIX_FMT_BGR24:
 324                 params->ip.bpp  = 1;            /* 24 BPP & RGB PFS */
 325                 params->ip.pfs  = 4;
 326                 params->ip.npb  = 7;
 327                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 328                 params->ip.ofs0 = 0;            /* Red bit offset */
 329                 params->ip.ofs1 = 8;            /* Green bit offset */
 330                 params->ip.ofs2 = 16;           /* Blue bit offset */
 331                 params->ip.ofs3 = 24;           /* Alpha bit offset */
 332                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 333                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 334                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 335                 break;
 336         case IPU_PIX_FMT_RGB24:
 337                 params->ip.bpp  = 1;            /* 24 BPP & RGB PFS */
 338                 params->ip.pfs  = 4;
 339                 params->ip.npb  = 7;
 340                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 341                 params->ip.ofs0 = 16;           /* Red bit offset */
 342                 params->ip.ofs1 = 8;            /* Green bit offset */
 343                 params->ip.ofs2 = 0;            /* Blue bit offset */
 344                 params->ip.ofs3 = 24;           /* Alpha bit offset */
 345                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 346                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 347                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 348                 break;
 349         case IPU_PIX_FMT_BGRA32:
 350         case IPU_PIX_FMT_BGR32:
 351         case IPU_PIX_FMT_ABGR32:
 352                 params->ip.bpp  = 0;
 353                 params->ip.pfs  = 4;
 354                 params->ip.npb  = 7;
 355                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 356                 params->ip.ofs0 = 8;            /* Red bit offset */
 357                 params->ip.ofs1 = 16;           /* Green bit offset */
 358                 params->ip.ofs2 = 24;           /* Blue bit offset */
 359                 params->ip.ofs3 = 0;            /* Alpha bit offset */
 360                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 361                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 362                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 363                 params->ip.wid3 = 7;            /* Alpha bit width - 1 */
 364                 break;
 365         case IPU_PIX_FMT_RGBA32:
 366         case IPU_PIX_FMT_RGB32:
 367                 params->ip.bpp  = 0;
 368                 params->ip.pfs  = 4;
 369                 params->ip.npb  = 7;
 370                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 371                 params->ip.ofs0 = 24;           /* Red bit offset */
 372                 params->ip.ofs1 = 16;           /* Green bit offset */
 373                 params->ip.ofs2 = 8;            /* Blue bit offset */
 374                 params->ip.ofs3 = 0;            /* Alpha bit offset */
 375                 params->ip.wid0 = 7;            /* Red bit width - 1 */
 376                 params->ip.wid1 = 7;            /* Green bit width - 1 */
 377                 params->ip.wid2 = 7;            /* Blue bit width - 1 */
 378                 params->ip.wid3 = 7;            /* Alpha bit width - 1 */
 379                 break;
 380         case IPU_PIX_FMT_UYVY:
 381                 params->ip.bpp  = 2;
 382                 params->ip.pfs  = 6;
 383                 params->ip.npb  = 7;
 384                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 385                 break;
 386         case IPU_PIX_FMT_YUV420P2:
 387         case IPU_PIX_FMT_YUV420P:
 388                 params->ip.bpp  = 3;
 389                 params->ip.pfs  = 3;
 390                 params->ip.npb  = 7;
 391                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 392                 u_offset = stride * height;
 393                 v_offset = u_offset + u_offset / 4;
 394                 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
 395                 break;
 396         case IPU_PIX_FMT_YVU422P:
 397                 params->ip.bpp  = 3;
 398                 params->ip.pfs  = 2;
 399                 params->ip.npb  = 7;
 400                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 401                 v_offset = stride * height;
 402                 u_offset = v_offset + v_offset / 2;
 403                 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
 404                 break;
 405         case IPU_PIX_FMT_YUV422P:
 406                 params->ip.bpp  = 3;
 407                 params->ip.pfs  = 2;
 408                 params->ip.npb  = 7;
 409                 params->ip.sat  = 2;            /* SAT = 32-bit access */
 410                 u_offset = stride * height;
 411                 v_offset = u_offset + u_offset / 2;
 412                 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
 413                 break;
 414         default:
 415                 dev_err(ipu_data.dev,
 416                         "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
 417                 break;
 418         }
 419
 420         params->pp.nsb = 1;
 421 }
 422
 423 static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
 424                                         uint16_t burst_pixels)
 425 {
 426         params->pp.npb = burst_pixels - 1;
 427 }
 428
 429 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
 430                                     dma_addr_t buf0, dma_addr_t buf1)
 431 {
 432         params->pp.eba0 = buf0;
 433         params->pp.eba1 = buf1;
 434 }
 435
 436 static void ipu_ch_param_set_rotation(union chan_param_mem *params,
 437                                       enum ipu_rotate_mode rotate)
 438 {
 439         params->pp.bam = rotate;
 440 }
 441
 442 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 443                                 uint32_t num_words)
 444 {
 445         for (; num_words > 0; num_words--) {
 446                 dev_dbg(ipu_data.dev,
 447                         "write param mem - addr = 0x%08X, data = 0x%08X\n",
 448                         addr, *data);
 449                 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
 450                 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
 451                 addr++;
 452                 if ((addr & 0x7) == 5) {
 453                         addr &= ~0x7;   /* set to word 0 */
 454                         addr += 8;      /* increment to next row */
 455                 }
 456         }
 457 }
 458
 459 static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
 460                               uint32_t *resize_coeff,
 461                               uint32_t *downsize_coeff)
 462 {
 463         uint32_t temp_size;
 464         uint32_t temp_downsize;
 465
 466         *resize_coeff   = 1 << 13;
 467         *downsize_coeff = 1 << 13;
 468
 469         /* Cannot downsize more than 8:1 */
 470         if (out_size << 3 < in_size)
 471                 return -EINVAL;
 472
 473         /* compute downsizing coefficient */
 474         temp_downsize = 0;
 475         temp_size = in_size;
 476         while (temp_size >= out_size * 2 && temp_downsize < 2) {
 477                 temp_size >>= 1;
 478                 temp_downsize++;
 479         }
 480         *downsize_coeff = temp_downsize;
 481
 482         /*
 483          * compute resizing coefficient using the following formula:
 484          * resize_coeff = M*(SI -1)/(SO - 1)
 485          * where M = 2^13, SI - input size, SO - output size
 486          */
 487         *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
 488         if (*resize_coeff >= 16384L) {
 489                 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
 490                 *resize_coeff = 0x3FFF;
 491         }
 492
 493         dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
 494                 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
 495                 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
 496                 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
 497
 498         return 0;
 499 }
 500
 501 static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
 502 {
 503         switch (fmt) {
 504         case IPU_PIX_FMT_RGB565:
 505         case IPU_PIX_FMT_BGR24:
 506         case IPU_PIX_FMT_RGB24:
 507         case IPU_PIX_FMT_BGR32:
 508         case IPU_PIX_FMT_RGB32:
 509                 return IPU_COLORSPACE_RGB;
 510         default:
 511                 return IPU_COLORSPACE_YCBCR;
 512         }
 513 }
 514
 515 static int ipu_ic_init_prpenc(struct ipu *ipu,
 516                               union ipu_channel_param *params, bool src_is_csi)
 517 {
 518         uint32_t reg, ic_conf;
 519         uint32_t downsize_coeff, resize_coeff;
 520         enum ipu_color_space in_fmt, out_fmt;
 521
 522         /* Setup vertical resizing */
 523         calc_resize_coeffs(params->video.in_height,
 524                             params->video.out_height,
 525                             &resize_coeff, &downsize_coeff);
 526         reg = (downsize_coeff << 30) | (resize_coeff << 16);
 527
 528         /* Setup horizontal resizing */
 529         calc_resize_coeffs(params->video.in_width,
 530                             params->video.out_width,
 531                             &resize_coeff, &downsize_coeff);
 532         reg |= (downsize_coeff << 14) | resize_coeff;
 533
 534         /* Setup color space conversion */
 535         in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
 536         out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
 537
 538         /*
 539          * Colourspace conversion unsupported yet - see _init_csc() in
 540          * Freescale sources
 541          */
 542         if (in_fmt != out_fmt) {
 543                 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
 544                 return -EOPNOTSUPP;
 545         }
 546
 547         idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
 548
 549         ic_conf = idmac_read_icreg(ipu, IC_CONF);
 550
 551         if (src_is_csi)
 552                 ic_conf &= ~IC_CONF_RWS_EN;
 553         else
 554                 ic_conf |= IC_CONF_RWS_EN;
 555
 556         idmac_write_icreg(ipu, ic_conf, IC_CONF);
 557
 558         return 0;
 559 }
 560
 561 static uint32_t dma_param_addr(uint32_t dma_ch)
 562 {
 563         /* Channel Parameter Memory */
 564         return 0x10000 | (dma_ch << 4);
 565 }
 566
 567 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
 568                                      bool prio)
 569 {
 570         u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
 571
 572         if (prio)
 573                 reg |= 1UL << channel;
 574         else
 575                 reg &= ~(1UL << channel);
 576
 577         idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
 578
 579         dump_idmac_reg(ipu);
 580 }
 581
 582 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
 583 {
 584         uint32_t mask;
 585
 586         switch (channel) {
 587         case IDMAC_IC_0:
 588         case IDMAC_IC_7:
 589                 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
 590                 break;
 591         case IDMAC_SDC_0:
 592         case IDMAC_SDC_1:
 593                 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
 594                 break;
 595         default:
 596                 mask = 0;
 597                 break;
 598         }
 599
 600         return mask;
 601 }
 602
 603 /**
 604  * ipu_enable_channel() - enable an IPU channel.
 605  * @idmac:      IPU DMAC context.
 606  * @ichan:      IDMAC channel.
 607  * @return:     0 on success or negative error code on failure.
 608  */
 609 static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
 610 {
 611         struct ipu *ipu = to_ipu(idmac);
 612         enum ipu_channel channel = ichan->dma_chan.chan_id;
 613         uint32_t reg;
 614         unsigned long flags;
 615
 616         spin_lock_irqsave(&ipu->lock, flags);
 617
 618         /* Reset to buffer 0 */
 619         idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
 620         ichan->active_buffer = 0;
 621         ichan->status = IPU_CHANNEL_ENABLED;
 622
 623         switch (channel) {
 624         case IDMAC_SDC_0:
 625         case IDMAC_SDC_1:
 626         case IDMAC_IC_7:
 627                 ipu_channel_set_priority(ipu, channel, true);
 628         default:
 629                 break;
 630         }
 631
 632         reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
 633
 634         idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
 635
 636         ipu_ic_enable_task(ipu, channel);
 637
 638         spin_unlock_irqrestore(&ipu->lock, flags);
 639         return 0;
 640 }
 641
 642 /**
 643  * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
 644  * @ichan:      IDMAC channel.
 645  * @pixel_fmt:  pixel format of buffer. Pixel format is a FOURCC ASCII code.
 646  * @width:      width of buffer in pixels.
 647  * @height:     height of buffer in pixels.
 648  * @stride:     stride length of buffer in pixels.
 649  * @rot_mode:   rotation mode of buffer. A rotation setting other than
 650  *              IPU_ROTATE_VERT_FLIP should only be used for input buffers of
 651  *              rotation channels.
 652  * @phyaddr_0:  buffer 0 physical address.
 653  * @phyaddr_1:  buffer 1 physical address. Setting this to a value other than
 654  *              NULL enables double buffering mode.
 655  * @return:     0 on success or negative error code on failure.
 656  */
 657 static int ipu_init_channel_buffer(struct idmac_channel *ichan,
 658                                    enum pixel_fmt pixel_fmt,
 659                                    uint16_t width, uint16_t height,
 660                                    uint32_t stride,
 661                                    enum ipu_rotate_mode rot_mode,
 662                                    dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
 663 {
 664         enum ipu_channel channel = ichan->dma_chan.chan_id;
 665         struct idmac *idmac = to_idmac(ichan->dma_chan.device);
 666         struct ipu *ipu = to_ipu(idmac);
 667         union chan_param_mem params = {};
 668         unsigned long flags;
 669         uint32_t reg;
 670         uint32_t stride_bytes;
 671
 672         stride_bytes = stride * bytes_per_pixel(pixel_fmt);
 673
 674         if (stride_bytes % 4) {
 675                 dev_err(ipu->dev,
 676                         "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
 677                         stride, stride_bytes);
 678                 return -EINVAL;
 679         }
 680
 681         /* IC channel's stride must be a multiple of 8 pixels */
 682         if ((channel <= IDMAC_IC_13) && (stride % 8)) {
 683                 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
 684                 return -EINVAL;
 685         }
 686
 687         /* Build parameter memory data for DMA channel */
 688         ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
 689         ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
 690         ipu_ch_param_set_rotation(&params, rot_mode);
 691         /* Some channels (rotation) have restriction on burst length */
 692         switch (channel) {
 693         case IDMAC_IC_7:        /* Hangs with burst 8, 16, other values
 694                                    invalid - Table 44-30 */
 695 /*
 696                 ipu_ch_param_set_burst_size(&params, 8);
 697  */
 698                 break;
 699         case IDMAC_SDC_0:
 700         case IDMAC_SDC_1:
 701                 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
 702                 ipu_ch_param_set_burst_size(&params, 16);
 703                 break;
 704         case IDMAC_IC_0:
 705         default:
 706                 break;
 707         }
 708
 709         spin_lock_irqsave(&ipu->lock, flags);
 710
 711         ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
 712
 713         reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
 714
 715         if (phyaddr_1)
 716                 reg |= 1UL << channel;
 717         else
 718                 reg &= ~(1UL << channel);
 719
 720         idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
 721
 722         ichan->status = IPU_CHANNEL_READY;
 723
 724         spin_unlock_irqrestore(&ipu->lock, flags);
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * ipu_select_buffer() - mark a channel's buffer as ready.
 731  * @channel:    channel ID.
 732  * @buffer_n:   buffer number to mark ready.
 733  */
 734 static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
 735 {
 736         /* No locking - this is a write-one-to-set register, cleared by IPU */
 737         if (buffer_n == 0)
 738                 /* Mark buffer 0 as ready. */
 739                 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
 740         else
 741                 /* Mark buffer 1 as ready. */
 742                 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
 743 }
 744
 745 /**
 746  * ipu_update_channel_buffer() - update physical address of a channel buffer.
 747  * @ichan:      IDMAC channel.
 748  * @buffer_n:   buffer number to update.
 749  *              0 or 1 are the only valid values.
 750  * @phyaddr:    buffer physical address.
 751  */
 752 /* Called under spin_lock(_irqsave)(&ichan->lock) */
 753 static void ipu_update_channel_buffer(struct idmac_channel *ichan,
 754                                       int buffer_n, dma_addr_t phyaddr)
 755 {
 756         enum ipu_channel channel = ichan->dma_chan.chan_id;
 757         uint32_t reg;
 758         unsigned long flags;
 759
 760         spin_lock_irqsave(&ipu_data.lock, flags);
 761
 762         if (buffer_n == 0) {
 763                 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
 764                 if (reg & (1UL << channel)) {
 765                         ipu_ic_disable_task(&ipu_data, channel);
 766                         ichan->status = IPU_CHANNEL_READY;
 767                 }
 768
 769                 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
 770                 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
 771                                    0x0008UL, IPU_IMA_ADDR);
 772                 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
 773         } else {
 774                 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
 775                 if (reg & (1UL << channel)) {
 776                         ipu_ic_disable_task(&ipu_data, channel);
 777                         ichan->status = IPU_CHANNEL_READY;
 778                 }
 779
 780                 /* Check if double-buffering is already enabled */
 781                 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
 782
 783                 if (!(reg & (1UL << channel)))
 784                         idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
 785                                            IPU_CHA_DB_MODE_SEL);
 786
 787                 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
 788                 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
 789                                    0x0009UL, IPU_IMA_ADDR);
 790                 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
 791         }
 792
 793         spin_unlock_irqrestore(&ipu_data.lock, flags);
 794 }
 795
 796 /* Called under spin_lock_irqsave(&ichan->lock) */
 797 static int ipu_submit_buffer(struct idmac_channel *ichan,
 798         struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
 799 {
 800         unsigned int chan_id = ichan->dma_chan.chan_id;
 801         struct device *dev = &ichan->dma_chan.dev->device;
 802
 803         if (async_tx_test_ack(&desc->txd))
 804                 return -EINTR;
 805
 806         /*
 807          * On first invocation this shouldn't be necessary, the call to
 808          * ipu_init_channel_buffer() above will set addresses for us, so we
 809          * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
 810          * doing it again shouldn't hurt either.
 811          */
 812         ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
 813
 814         ipu_select_buffer(chan_id, buf_idx);
 815         dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
 816                 sg, chan_id, buf_idx);
 817
 818         return 0;
 819 }
 820
 821 /* Called under spin_lock_irqsave(&ichan->lock) */
 822 static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
 823                                       struct idmac_tx_desc *desc)
 824 {
 825         struct scatterlist *sg;
 826         int i, ret = 0;
 827
 828         for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
 829                 if (!ichan->sg[i]) {
 830                         ichan->sg[i] = sg;
 831
 832                         ret = ipu_submit_buffer(ichan, desc, sg, i);
 833                         if (ret < 0)
 834                                 return ret;
 835
 836                         sg = sg_next(sg);
 837                 }
 838         }
 839
 840         return ret;
 841 }
 842
 843 static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
 844 {
 845         struct idmac_tx_desc *desc = to_tx_desc(tx);
 846         struct idmac_channel *ichan = to_idmac_chan(tx->chan);
 847         struct idmac *idmac = to_idmac(tx->chan->device);
 848         struct ipu *ipu = to_ipu(idmac);
 849         struct device *dev = &ichan->dma_chan.dev->device;
 850         dma_cookie_t cookie;
 851         unsigned long flags;
 852         int ret;
 853
 854         /* Sanity check */
 855         if (!list_empty(&desc->list)) {
 856                 /* The descriptor doesn't belong to client */
 857                 dev_err(dev, "Descriptor %p not prepared!\n", tx);
 858                 return -EBUSY;
 859         }
 860
 861         mutex_lock(&ichan->chan_mutex);
 862
 863         async_tx_clear_ack(tx);
 864
 865         if (ichan->status < IPU_CHANNEL_READY) {
 866                 struct idmac_video_param *video = &ichan->params.video;
 867                 /*
 868                  * Initial buffer assignment - the first two sg-entries from
 869                  * the descriptor will end up in the IDMAC buffers
 870                  */
 871                 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
 872                         sg_dma_address(&desc->sg[1]);
 873
 874                 WARN_ON(ichan->sg[0] || ichan->sg[1]);
 875
 876                 cookie = ipu_init_channel_buffer(ichan,
 877                                                  video->out_pixel_fmt,
 878                                                  video->out_width,
 879                                                  video->out_height,
 880                                                  video->out_stride,
 881                                                  IPU_ROTATE_NONE,
 882                                                  sg_dma_address(&desc->sg[0]),
 883                                                  dma_1);
 884                 if (cookie < 0)
 885                         goto out;
 886         }
 887
 888         dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
 889
 890         cookie = ichan->dma_chan.cookie;
 891
 892         if (++cookie < 0)
 893                 cookie = 1;
 894
 895         /* from dmaengine.h: "last cookie value returned to client" */
 896         ichan->dma_chan.cookie = cookie;
 897         tx->cookie = cookie;
 898
 899         /* ipu->lock can be taken under ichan->lock, but not v.v. */
 900         spin_lock_irqsave(&ichan->lock, flags);
 901
 902         list_add_tail(&desc->list, &ichan->queue);
 903         /* submit_buffers() atomically verifies and fills empty sg slots */
 904         ret = ipu_submit_channel_buffers(ichan, desc);
 905
 906         spin_unlock_irqrestore(&ichan->lock, flags);
 907
 908         if (ret < 0) {
 909                 cookie = ret;
 910                 goto dequeue;
 911         }
 912
 913         if (ichan->status < IPU_CHANNEL_ENABLED) {
 914                 ret = ipu_enable_channel(idmac, ichan);
 915                 if (ret < 0) {
 916                         cookie = ret;
 917                         goto dequeue;
 918                 }
 919         }
 920
 921         dump_idmac_reg(ipu);
 922
 923 dequeue:
 924         if (cookie < 0) {
 925                 spin_lock_irqsave(&ichan->lock, flags);
 926                 list_del_init(&desc->list);
 927                 spin_unlock_irqrestore(&ichan->lock, flags);
 928                 tx->cookie = cookie;
 929                 ichan->dma_chan.cookie = cookie;
 930         }
 931
 932 out:
 933         mutex_unlock(&ichan->chan_mutex);
 934
 935         return cookie;
 936 }
 937
 938 /* Called with ichan->chan_mutex held */
 939 static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
 940 {
 941         struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
 942         struct idmac *idmac = to_idmac(ichan->dma_chan.device);
 943
 944         if (!desc)
 945                 return -ENOMEM;
 946
 947         /* No interrupts, just disable the tasklet for a moment */
 948         tasklet_disable(&to_ipu(idmac)->tasklet);
 949
 950         ichan->n_tx_desc = n;
 951         ichan->desc = desc;
 952         INIT_LIST_HEAD(&ichan->queue);
 953         INIT_LIST_HEAD(&ichan->free_list);
 954
 955         while (n--) {
 956                 struct dma_async_tx_descriptor *txd = &desc->txd;
 957
 958                 memset(txd, 0, sizeof(*txd));
 959                 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
 960                 txd->tx_submit          = idmac_tx_submit;
 961
 962                 list_add(&desc->list, &ichan->free_list);
 963
 964                 desc++;
 965         }
 966
 967         tasklet_enable(&to_ipu(idmac)->tasklet);
 968
 969         return 0;
 970 }
 971
 972 /**
 973  * ipu_init_channel() - initialize an IPU channel.
 974  * @idmac:      IPU DMAC context.
 975  * @ichan:      pointer to the channel object.
 976  * @return      0 on success or negative error code on failure.
 977  */
 978 static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
 979 {
 980         union ipu_channel_param *params = &ichan->params;
 981         uint32_t ipu_conf;
 982         enum ipu_channel channel = ichan->dma_chan.chan_id;
 983         unsigned long flags;
 984         uint32_t reg;
 985         struct ipu *ipu = to_ipu(idmac);
 986         int ret = 0, n_desc = 0;
 987
 988         dev_dbg(ipu->dev, "init channel = %d\n", channel);
 989
 990         if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
 991             channel != IDMAC_IC_7)
 992                 return -EINVAL;
 993
 994         spin_lock_irqsave(&ipu->lock, flags);
 995
 996         switch (channel) {
 997         case IDMAC_IC_7:
 998                 n_desc = 16;
 999                 reg = idmac_read_icreg(ipu, IC_CONF);
1000                 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
1001                 break;
1002         case IDMAC_IC_0:
1003                 n_desc = 16;
1004                 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
1005                 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
1006                 ret = ipu_ic_init_prpenc(ipu, params, true);
1007                 break;
1008         case IDMAC_SDC_0:
1009         case IDMAC_SDC_1:
1010                 n_desc = 4;
1011         default:
1012                 break;
1013         }
1014
1015         ipu->channel_init_mask |= 1L << channel;
1016
1017         /* Enable IPU sub module */
1018         ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
1019                 ipu_channel_conf_mask(channel);
1020         idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1021
1022         spin_unlock_irqrestore(&ipu->lock, flags);
1023
1024         if (n_desc && !ichan->desc)
1025                 ret = idmac_desc_alloc(ichan, n_desc);
1026
1027         dump_idmac_reg(ipu);
1028
1029         return ret;
1030 }
1031
1032 /**
1033  * ipu_uninit_channel() - uninitialize an IPU channel.
1034  * @idmac:      IPU DMAC context.
1035  * @ichan:      pointer to the channel object.
1036  */
1037 static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1038 {
1039         enum ipu_channel channel = ichan->dma_chan.chan_id;
1040         unsigned long flags;
1041         uint32_t reg;
1042         unsigned long chan_mask = 1UL << channel;
1043         uint32_t ipu_conf;
1044         struct ipu *ipu = to_ipu(idmac);
1045
1046         spin_lock_irqsave(&ipu->lock, flags);
1047
1048         if (!(ipu->channel_init_mask & chan_mask)) {
1049                 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1050                         channel);
1051                 spin_unlock_irqrestore(&ipu->lock, flags);
1052                 return;
1053         }
1054
1055         /* Reset the double buffer */
1056         reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1057         idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1058
1059         ichan->sec_chan_en = false;
1060
1061         switch (channel) {
1062         case IDMAC_IC_7:
1063                 reg = idmac_read_icreg(ipu, IC_CONF);
1064                 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1065                              IC_CONF);
1066                 break;
1067         case IDMAC_IC_0:
1068                 reg = idmac_read_icreg(ipu, IC_CONF);
1069                 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1070                                   IC_CONF);
1071                 break;
1072         case IDMAC_SDC_0:
1073         case IDMAC_SDC_1:
1074         default:
1075                 break;
1076         }
1077
1078         ipu->channel_init_mask &= ~(1L << channel);
1079
1080         ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1081                 ~ipu_channel_conf_mask(channel);
1082         idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1083
1084         spin_unlock_irqrestore(&ipu->lock, flags);
1085
1086         ichan->n_tx_desc = 0;
1087         vfree(ichan->desc);
1088         ichan->desc = NULL;
1089 }
1090
1091 /**
1092  * ipu_disable_channel() - disable an IPU channel.
1093  * @idmac:              IPU DMAC context.
1094  * @ichan:              channel object pointer.
1095  * @wait_for_stop:      flag to set whether to wait for channel end of frame or
1096  *                      return immediately.
1097  * @return:             0 on success or negative error code on failure.
1098  */
1099 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1100                                bool wait_for_stop)
1101 {
1102         enum ipu_channel channel = ichan->dma_chan.chan_id;
1103         struct ipu *ipu = to_ipu(idmac);
1104         uint32_t reg;
1105         unsigned long flags;
1106         unsigned long chan_mask = 1UL << channel;
1107         unsigned int timeout;
1108
1109         if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1110                 timeout = 40;
1111                 /* This waiting always fails. Related to spurious irq problem */
1112                 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1113                        (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1114                         timeout--;
1115                         msleep(10);
1116
1117                         if (!timeout) {
1118                                 dev_dbg(ipu->dev,
1119                                         "Warning: timeout waiting for channel %u to "
1120                                         "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1121                                         "busy = 0x%08X, tstat = 0x%08X\n", channel,
1122                                         idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1123                                         idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1124                                         idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1125                                         idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1126                                 break;
1127                         }
1128                 }
1129                 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1130         }
1131         /* SDC BG and FG must be disabled before DMA is disabled */
1132         if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1133                               channel == IDMAC_SDC_1)) {
1134                 for (timeout = 5;
1135                      timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1136                         msleep(5);
1137         }
1138
1139         spin_lock_irqsave(&ipu->lock, flags);
1140
1141         /* Disable IC task */
1142         ipu_ic_disable_task(ipu, channel);
1143
1144         /* Disable DMA channel(s) */
1145         reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1146         idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1147
1148         /*
1149          * Problem (observed with channel DMAIC_7): after enabling the channel
1150          * and initialising buffers, there comes an interrupt with current still
1151          * pointing at buffer 0, whereas it should use buffer 0 first and only
1152          * generate an interrupt when it is done, then current should already
1153          * point to buffer 1. This spurious interrupt also comes on channel
1154          * DMASDC_0. With DMAIC_7 normally, is we just leave the ISR after the
1155          * first interrupt, there comes the second with current correctly
1156          * pointing to buffer 1 this time. But sometimes this second interrupt
1157          * doesn't come and the channel hangs. Clearing BUFx_RDY when disabling
1158          * the channel seems to prevent the channel from hanging, but it doesn't
1159          * prevent the spurious interrupt. This might also be unsafe. Think
1160          * about the IDMAC controller trying to switch to a buffer, when we
1161          * clear the ready bit, and re-enable it a moment later.
1162          */
1163         reg = idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY);
1164         idmac_write_ipureg(ipu, 0, IPU_CHA_BUF0_RDY);
1165         idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF0_RDY);
1166
1167         reg = idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY);
1168         idmac_write_ipureg(ipu, 0, IPU_CHA_BUF1_RDY);
1169         idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF1_RDY);
1170
1171         spin_unlock_irqrestore(&ipu->lock, flags);
1172
1173         return 0;
1174 }
1175
1176 static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1177         struct idmac_tx_desc **desc, struct scatterlist *sg)
1178 {
1179         struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1180
1181         if (sgnew)
1182                 /* next sg-element in this list */
1183                 return sgnew;
1184
1185         if ((*desc)->list.next == &ichan->queue)
1186                 /* No more descriptors on the queue */
1187                 return NULL;
1188
1189         /* Fetch next descriptor */
1190         *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1191         return (*desc)->sg;
1192 }
1193
1194 /*
1195  * We have several possibilities here:
1196  * current BUF          next BUF
1197  *
1198  * not last sg          next not last sg
1199  * not last sg          next last sg
1200  * last sg              first sg from next descriptor
1201  * last sg              NULL
1202  *
1203  * Besides, the descriptor queue might be empty or not. We process all these
1204  * cases carefully.
1205  */
1206 static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1207 {
1208         struct idmac_channel *ichan = dev_id;
1209         struct device *dev = &ichan->dma_chan.dev->device;
1210         unsigned int chan_id = ichan->dma_chan.chan_id;
1211         struct scatterlist **sg, *sgnext, *sgnew = NULL;
1212         /* Next transfer descriptor */
1213         struct idmac_tx_desc *desc, *descnew;
1214         dma_async_tx_callback callback;
1215         void *callback_param;
1216         bool done = false;
1217         u32 ready0, ready1, curbuf, err;
1218         unsigned long flags;
1219
1220         /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1221
1222         dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1223
1224         spin_lock_irqsave(&ipu_data.lock, flags);
1225
1226         ready0  = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1227         ready1  = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1228         curbuf  = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1229         err     = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1230
1231         if (err & (1 << chan_id)) {
1232                 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1233                 spin_unlock_irqrestore(&ipu_data.lock, flags);
1234                 /*
1235                  * Doing this
1236                  * ichan->sg[0] = ichan->sg[1] = NULL;
1237                  * you can force channel re-enable on the next tx_submit(), but
1238                  * this is dirty - think about descriptors with multiple
1239                  * sg elements.
1240                  */
1241                 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1242                          chan_id, ready0, ready1, curbuf);
1243                 return IRQ_HANDLED;
1244         }
1245         spin_unlock_irqrestore(&ipu_data.lock, flags);
1246
1247         /* Other interrupts do not interfere with this channel */
1248         spin_lock(&ichan->lock);
1249         if (unlikely(chan_id != IDMAC_SDC_0 && chan_id != IDMAC_SDC_1 &&
1250                      ((curbuf >> chan_id) & 1) == ichan->active_buffer &&
1251                      !list_is_last(ichan->queue.next, &ichan->queue))) {
1252                 int i = 100;
1253
1254                 /* This doesn't help. See comment in ipu_disable_channel() */
1255                 while (--i) {
1256                         curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1257                         if (((curbuf >> chan_id) & 1) != ichan->active_buffer)
1258                                 break;
1259                         cpu_relax();
1260                 }
1261
1262                 if (!i) {
1263                         spin_unlock(&ichan->lock);
1264                         dev_dbg(dev,
1265                                 "IRQ on active buffer on channel %x, active "
1266                                 "%d, ready %x, %x, current %x!\n", chan_id,
1267                                 ichan->active_buffer, ready0, ready1, curbuf);
1268                         return IRQ_NONE;
1269                 } else
1270                         dev_dbg(dev,
1271                                 "Buffer deactivated on channel %x, active "
1272                                 "%d, ready %x, %x, current %x, rest %d!\n", chan_id,
1273                                 ichan->active_buffer, ready0, ready1, curbuf, i);
1274         }
1275
1276         if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1277                      (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1278                      )) {
1279                 spin_unlock(&ichan->lock);
1280                 dev_dbg(dev,
1281                         "IRQ with active buffer still ready on channel %x, "
1282                         "active %d, ready %x, %x!\n", chan_id,
1283                         ichan->active_buffer, ready0, ready1);
1284                 return IRQ_NONE;
1285         }
1286
1287         if (unlikely(list_empty(&ichan->queue))) {
1288                 ichan->sg[ichan->active_buffer] = NULL;
1289                 spin_unlock(&ichan->lock);
1290                 dev_err(dev,
1291                         "IRQ without queued buffers on channel %x, active %d, "
1292                         "ready %x, %x!\n", chan_id,
1293                         ichan->active_buffer, ready0, ready1);
1294                 return IRQ_NONE;
1295         }
1296
1297         /*
1298          * active_buffer is a software flag, it shows which buffer we are
1299          * currently expecting back from the hardware, IDMAC should be
1300          * processing the other buffer already
1301          */
1302         sg = &ichan->sg[ichan->active_buffer];
1303         sgnext = ichan->sg[!ichan->active_buffer];
1304
1305         if (!*sg) {
1306                 spin_unlock(&ichan->lock);
1307                 return IRQ_HANDLED;
1308         }
1309
1310         desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1311         descnew = desc;
1312
1313         dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1314                 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1315
1316         /* Find the descriptor of sgnext */
1317         sgnew = idmac_sg_next(ichan, &descnew, *sg);
1318         if (sgnext != sgnew)
1319                 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1320
1321         /*
1322          * if sgnext == NULL sg must be the last element in a scatterlist and
1323          * queue must be empty
1324          */
1325         if (unlikely(!sgnext)) {
1326                 if (!WARN_ON(sg_next(*sg)))
1327                         dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1328                 ichan->sg[!ichan->active_buffer] = sgnew;
1329
1330                 if (unlikely(sgnew)) {
1331                         ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
1332                 } else {
1333                         spin_lock_irqsave(&ipu_data.lock, flags);
1334                         ipu_ic_disable_task(&ipu_data, chan_id);
1335                         spin_unlock_irqrestore(&ipu_data.lock, flags);
1336                         ichan->status = IPU_CHANNEL_READY;
1337                         /* Continue to check for complete descriptor */
1338                 }
1339         }
1340
1341         /* Calculate and submit the next sg element */
1342         sgnew = idmac_sg_next(ichan, &descnew, sgnew);
1343
1344         if (unlikely(!sg_next(*sg)) || !sgnext) {
1345                 /*
1346                  * Last element in scatterlist done, remove from the queue,
1347                  * _init for debugging
1348                  */
1349                 list_del_init(&desc->list);
1350                 done = true;
1351         }
1352
1353         *sg = sgnew;
1354
1355         if (likely(sgnew) &&
1356             ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
1357                 callback = descnew->txd.callback;
1358                 callback_param = descnew->txd.callback_param;
1359                 spin_unlock(&ichan->lock);
1360                 if (callback)
1361                         callback(callback_param);
1362                 spin_lock(&ichan->lock);
1363         }
1364
1365         /* Flip the active buffer - even if update above failed */
1366         ichan->active_buffer = !ichan->active_buffer;
1367         if (done)
1368                 ichan->completed = desc->txd.cookie;
1369
1370         callback = desc->txd.callback;
1371         callback_param = desc->txd.callback_param;
1372
1373         spin_unlock(&ichan->lock);
1374
1375         if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1376                 callback(callback_param);
1377
1378         return IRQ_HANDLED;
1379 }
1380
1381 static void ipu_gc_tasklet(unsigned long arg)
1382 {
1383         struct ipu *ipu = (struct ipu *)arg;
1384         int i;
1385
1386         for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1387                 struct idmac_channel *ichan = ipu->channel + i;
1388                 struct idmac_tx_desc *desc;
1389                 unsigned long flags;
1390                 struct scatterlist *sg;
1391                 int j, k;
1392
1393                 for (j = 0; j < ichan->n_tx_desc; j++) {
1394                         desc = ichan->desc + j;
1395                         spin_lock_irqsave(&ichan->lock, flags);
1396                         if (async_tx_test_ack(&desc->txd)) {
1397                                 list_move(&desc->list, &ichan->free_list);
1398                                 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1399                                         if (ichan->sg[0] == sg)
1400                                                 ichan->sg[0] = NULL;
1401                                         else if (ichan->sg[1] == sg)
1402                                                 ichan->sg[1] = NULL;
1403                                 }
1404                                 async_tx_clear_ack(&desc->txd);
1405                         }
1406                         spin_unlock_irqrestore(&ichan->lock, flags);
1407                 }
1408         }
1409 }
1410
1411 /* Allocate and initialise a transfer descriptor. */
1412 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1413                 struct scatterlist *sgl, unsigned int sg_len,
1414                 enum dma_data_direction direction, unsigned long tx_flags)
1415 {
1416         struct idmac_channel *ichan = to_idmac_chan(chan);
1417         struct idmac_tx_desc *desc = NULL;
1418         struct dma_async_tx_descriptor *txd = NULL;
1419         unsigned long flags;
1420
1421         /* We only can handle these three channels so far */
1422         if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1423             chan->chan_id != IDMAC_IC_7)
1424                 return NULL;
1425
1426         if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
1427                 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1428                 return NULL;
1429         }
1430
1431         mutex_lock(&ichan->chan_mutex);
1432
1433         spin_lock_irqsave(&ichan->lock, flags);
1434         if (!list_empty(&ichan->free_list)) {
1435                 desc = list_entry(ichan->free_list.next,
1436                                   struct idmac_tx_desc, list);
1437
1438                 list_del_init(&desc->list);
1439
1440                 desc->sg_len    = sg_len;
1441                 desc->sg        = sgl;
1442                 txd             = &desc->txd;
1443                 txd->flags      = tx_flags;
1444         }
1445         spin_unlock_irqrestore(&ichan->lock, flags);
1446
1447         mutex_unlock(&ichan->chan_mutex);
1448
1449         tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1450
1451         return txd;
1452 }
1453
1454 /* Re-select the current buffer and re-activate the channel */
1455 static void idmac_issue_pending(struct dma_chan *chan)
1456 {
1457         struct idmac_channel *ichan = to_idmac_chan(chan);
1458         struct idmac *idmac = to_idmac(chan->device);
1459         struct ipu *ipu = to_ipu(idmac);
1460         unsigned long flags;
1461
1462         /* This is not always needed, but doesn't hurt either */
1463         spin_lock_irqsave(&ipu->lock, flags);
1464         ipu_select_buffer(chan->chan_id, ichan->active_buffer);
1465         spin_unlock_irqrestore(&ipu->lock, flags);
1466
1467         /*
1468          * Might need to perform some parts of initialisation from
1469          * ipu_enable_channel(), but not all, we do not want to reset to buffer
1470          * 0, don't need to set priority again either, but re-enabling the task
1471          * and the channel might be a good idea.
1472          */
1473 }
1474
1475 static int __idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1476                            unsigned long arg)
1477 {
1478         struct idmac_channel *ichan = to_idmac_chan(chan);
1479         struct idmac *idmac = to_idmac(chan->device);
1480         unsigned long flags;
1481         int i;
1482
1483         /* Only supports DMA_TERMINATE_ALL */
1484         if (cmd != DMA_TERMINATE_ALL)
1485                 return -ENXIO;
1486
1487         ipu_disable_channel(idmac, ichan,
1488                             ichan->status >= IPU_CHANNEL_ENABLED);
1489
1490         tasklet_disable(&to_ipu(idmac)->tasklet);
1491
1492         /* ichan->queue is modified in ISR, have to spinlock */
1493         spin_lock_irqsave(&ichan->lock, flags);
1494         list_splice_init(&ichan->queue, &ichan->free_list);
1495
1496         if (ichan->desc)
1497                 for (i = 0; i < ichan->n_tx_desc; i++) {
1498                         struct idmac_tx_desc *desc = ichan->desc + i;
1499                         if (list_empty(&desc->list))
1500                                 /* Descriptor was prepared, but not submitted */
1501                                 list_add(&desc->list, &ichan->free_list);
1502
1503                         async_tx_clear_ack(&desc->txd);
1504                 }
1505
1506         ichan->sg[0] = NULL;
1507         ichan->sg[1] = NULL;
1508         spin_unlock_irqrestore(&ichan->lock, flags);
1509
1510         tasklet_enable(&to_ipu(idmac)->tasklet);
1511
1512         ichan->status = IPU_CHANNEL_INITIALIZED;
1513
1514         return 0;
1515 }
1516
1517 static int idmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1518                          unsigned long arg)
1519 {
1520         struct idmac_channel *ichan = to_idmac_chan(chan);
1521         int ret;
1522
1523         mutex_lock(&ichan->chan_mutex);
1524
1525         ret = __idmac_control(chan, cmd, arg);
1526
1527         mutex_unlock(&ichan->chan_mutex);
1528
1529         return ret;
1530 }
1531
1532 #ifdef DEBUG
1533 static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1534 {
1535         struct idmac_channel *ichan = dev_id;
1536         printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1537                irq, ichan->dma_chan.chan_id);
1538         disable_irq_nosync(irq);
1539         return IRQ_HANDLED;
1540 }
1541
1542 static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1543 {
1544         struct idmac_channel *ichan = dev_id;
1545         printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1546                irq, ichan->dma_chan.chan_id);
1547         disable_irq_nosync(irq);
1548         return IRQ_HANDLED;
1549 }
1550
1551 static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1552 #endif
1553
1554 static int idmac_alloc_chan_resources(struct dma_chan *chan)
1555 {
1556         struct idmac_channel *ichan = to_idmac_chan(chan);
1557         struct idmac *idmac = to_idmac(chan->device);
1558         int ret;
1559
1560         /* dmaengine.c now guarantees to only offer free channels */
1561         BUG_ON(chan->client_count > 1);
1562         WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1563
1564         chan->cookie            = 1;
1565         ichan->completed        = -ENXIO;
1566
1567         ret = ipu_irq_map(chan->chan_id);
1568         if (ret < 0)
1569                 goto eimap;
1570
1571         ichan->eof_irq = ret;
1572
1573         /*
1574          * Important to first disable the channel, because maybe someone
1575          * used it before us, e.g., the bootloader
1576          */
1577         ipu_disable_channel(idmac, ichan, true);
1578
1579         ret = ipu_init_channel(idmac, ichan);
1580         if (ret < 0)
1581                 goto eichan;
1582
1583         ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1584                           ichan->eof_name, ichan);
1585         if (ret < 0)
1586                 goto erirq;
1587
1588 #ifdef DEBUG
1589         if (chan->chan_id == IDMAC_IC_7) {
1590                 ic_sof = ipu_irq_map(69);
1591                 if (ic_sof > 0)
1592                         request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1593                 ic_eof = ipu_irq_map(70);
1594                 if (ic_eof > 0)
1595                         request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1596         }
1597 #endif
1598
1599         ichan->status = IPU_CHANNEL_INITIALIZED;
1600
1601         dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1602                 chan->chan_id, ichan->eof_irq);
1603
1604         return ret;
1605
1606 erirq:
1607         ipu_uninit_channel(idmac, ichan);
1608 eichan:
1609         ipu_irq_unmap(chan->chan_id);
1610 eimap:
1611         return ret;
1612 }
1613
1614 static void idmac_free_chan_resources(struct dma_chan *chan)
1615 {
1616         struct idmac_channel *ichan = to_idmac_chan(chan);
1617         struct idmac *idmac = to_idmac(chan->device);
1618
1619         mutex_lock(&ichan->chan_mutex);
1620
1621         __idmac_control(chan, DMA_TERMINATE_ALL, 0);
1622
1623         if (ichan->status > IPU_CHANNEL_FREE) {
1624 #ifdef DEBUG
1625                 if (chan->chan_id == IDMAC_IC_7) {
1626                         if (ic_sof > 0) {
1627                                 free_irq(ic_sof, ichan);
1628                                 ipu_irq_unmap(69);
1629                                 ic_sof = -EINVAL;
1630                         }
1631                         if (ic_eof > 0) {
1632                                 free_irq(ic_eof, ichan);
1633                                 ipu_irq_unmap(70);
1634                                 ic_eof = -EINVAL;
1635                         }
1636                 }
1637 #endif
1638                 free_irq(ichan->eof_irq, ichan);
1639                 ipu_irq_unmap(chan->chan_id);
1640         }
1641
1642         ichan->status = IPU_CHANNEL_FREE;
1643
1644         ipu_uninit_channel(idmac, ichan);
1645
1646         mutex_unlock(&ichan->chan_mutex);
1647
1648         tasklet_schedule(&to_ipu(idmac)->tasklet);
1649 }
1650
1651 static enum dma_status idmac_tx_status(struct dma_chan *chan,
1652                        dma_cookie_t cookie, struct dma_tx_state *txstate)
1653 {
1654         struct idmac_channel *ichan = to_idmac_chan(chan);
1655
1656         dma_set_tx_state(txstate, ichan->completed, chan->cookie, 0);
1657         if (cookie != chan->cookie)
1658                 return DMA_ERROR;
1659         return DMA_SUCCESS;
1660 }
1661
1662 static int __init ipu_idmac_init(struct ipu *ipu)
1663 {
1664         struct idmac *idmac = &ipu->idmac;
1665         struct dma_device *dma = &idmac->dma;
1666         int i;
1667
1668         dma_cap_set(DMA_SLAVE, dma->cap_mask);
1669         dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1670
1671         /* Compulsory common fields */
1672         dma->dev                                = ipu->dev;
1673         dma->device_alloc_chan_resources        = idmac_alloc_chan_resources;
1674         dma->device_free_chan_resources         = idmac_free_chan_resources;
1675         dma->device_tx_status                   = idmac_tx_status;
1676         dma->device_issue_pending               = idmac_issue_pending;
1677
1678         /* Compulsory for DMA_SLAVE fields */
1679         dma->device_prep_slave_sg               = idmac_prep_slave_sg;
1680         dma->device_control                     = idmac_control;
1681
1682         INIT_LIST_HEAD(&dma->channels);
1683         for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1684                 struct idmac_channel *ichan = ipu->channel + i;
1685                 struct dma_chan *dma_chan = &ichan->dma_chan;
1686
1687                 spin_lock_init(&ichan->lock);
1688                 mutex_init(&ichan->chan_mutex);
1689
1690                 ichan->status           = IPU_CHANNEL_FREE;
1691                 ichan->sec_chan_en      = false;
1692                 ichan->completed        = -ENXIO;
1693                 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1694
1695                 dma_chan->device        = &idmac->dma;
1696                 dma_chan->cookie        = 1;
1697                 dma_chan->chan_id       = i;
1698                 list_add_tail(&dma_chan->device_node, &dma->channels);
1699         }
1700
1701         idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1702
1703         return dma_async_device_register(&idmac->dma);
1704 }
1705
1706 static void __exit ipu_idmac_exit(struct ipu *ipu)
1707 {
1708         int i;
1709         struct idmac *idmac = &ipu->idmac;
1710
1711         for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1712                 struct idmac_channel *ichan = ipu->channel + i;
1713
1714                 idmac_control(&ichan->dma_chan, DMA_TERMINATE_ALL, 0);
1715                 idmac_prep_slave_sg(&ichan->dma_chan, NULL, 0, DMA_NONE, 0);
1716         }
1717
1718         dma_async_device_unregister(&idmac->dma);
1719 }
1720
1721 /*****************************************************************************
1722  * IPU common probe / remove
1723  */
1724
1725 static int __init ipu_probe(struct platform_device *pdev)
1726 {
1727         struct ipu_platform_data *pdata = pdev->dev.platform_data;
1728         struct resource *mem_ipu, *mem_ic;
1729         int ret;
1730
1731         spin_lock_init(&ipu_data.lock);
1732
1733         mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1734         mem_ic  = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1735         if (!pdata || !mem_ipu || !mem_ic)
1736                 return -EINVAL;
1737
1738         ipu_data.dev = &pdev->dev;
1739
1740         platform_set_drvdata(pdev, &ipu_data);
1741
1742         ret = platform_get_irq(pdev, 0);
1743         if (ret < 0)
1744                 goto err_noirq;
1745
1746         ipu_data.irq_fn = ret;
1747         ret = platform_get_irq(pdev, 1);
1748         if (ret < 0)
1749                 goto err_noirq;
1750
1751         ipu_data.irq_err = ret;
1752         ipu_data.irq_base = pdata->irq_base;
1753
1754         dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1755                 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1756
1757         /* Remap IPU common registers */
1758         ipu_data.reg_ipu = ioremap(mem_ipu->start,
1759                                    mem_ipu->end - mem_ipu->start + 1);
1760         if (!ipu_data.reg_ipu) {
1761                 ret = -ENOMEM;
1762                 goto err_ioremap_ipu;
1763         }
1764
1765         /* Remap Image Converter and Image DMA Controller registers */
1766         ipu_data.reg_ic = ioremap(mem_ic->start,
1767                                   mem_ic->end - mem_ic->start + 1);
1768         if (!ipu_data.reg_ic) {
1769                 ret = -ENOMEM;
1770                 goto err_ioremap_ic;
1771         }
1772
1773         /* Get IPU clock */
1774         ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1775         if (IS_ERR(ipu_data.ipu_clk)) {
1776                 ret = PTR_ERR(ipu_data.ipu_clk);
1777                 goto err_clk_get;
1778         }
1779
1780         /* Make sure IPU HSP clock is running */
1781         clk_enable(ipu_data.ipu_clk);
1782
1783         /* Disable all interrupts */
1784         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1785         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1786         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1787         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1788         idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1789
1790         dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1791                 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1792
1793         ret = ipu_irq_attach_irq(&ipu_data, pdev);
1794         if (ret < 0)
1795                 goto err_attach_irq;
1796
1797         /* Initialize DMA engine */
1798         ret = ipu_idmac_init(&ipu_data);
1799         if (ret < 0)
1800                 goto err_idmac_init;
1801
1802         tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1803
1804         ipu_data.dev = &pdev->dev;
1805
1806         dev_dbg(ipu_data.dev, "IPU initialized\n");
1807
1808         return 0;
1809
1810 err_idmac_init:
1811 err_attach_irq:
1812         ipu_irq_detach_irq(&ipu_data, pdev);
1813         clk_disable(ipu_data.ipu_clk);
1814         clk_put(ipu_data.ipu_clk);
1815 err_clk_get:
1816         iounmap(ipu_data.reg_ic);
1817 err_ioremap_ic:
1818         iounmap(ipu_data.reg_ipu);
1819 err_ioremap_ipu:
1820 err_noirq:
1821         dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1822         return ret;
1823 }
1824
1825 static int __exit ipu_remove(struct platform_device *pdev)
1826 {
1827         struct ipu *ipu = platform_get_drvdata(pdev);
1828
1829         ipu_idmac_exit(ipu);
1830         ipu_irq_detach_irq(ipu, pdev);
1831         clk_disable(ipu->ipu_clk);
1832         clk_put(ipu->ipu_clk);
1833         iounmap(ipu->reg_ic);
1834         iounmap(ipu->reg_ipu);
1835         tasklet_kill(&ipu->tasklet);
1836         platform_set_drvdata(pdev, NULL);
1837
1838         return 0;
1839 }
1840
1841 /*
1842  * We need two MEM resources - with IPU-common and Image Converter registers,
1843  * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1844  */
1845 static struct platform_driver ipu_platform_driver = {
1846         .driver = {
1847                 .name   = "ipu-core",
1848                 .owner  = THIS_MODULE,
1849         },
1850         .remove         = __exit_p(ipu_remove),
1851 };
1852
1853 static int __init ipu_init(void)
1854 {
1855         return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1856 }
1857 subsys_initcall(ipu_init);
1858
1859 MODULE_DESCRIPTION("IPU core driver");
1860 MODULE_LICENSE("GPL v2");
1861 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1862 MODULE_ALIAS("platform:ipu-core");