drivers/dma/ioat/dma_v2.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine (versions >= 2), which
  25  * does asynchronous data movement and checksumming operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/dmaengine.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/i7300_idle.h>
  37 #include "dma.h"
  38 #include "dma_v2.h"
  39 #include "registers.h"
  40 #include "hw.h"
  41
  42 int ioat_ring_alloc_order = 8;
  43 module_param(ioat_ring_alloc_order, int, 0644);
  44 MODULE_PARM_DESC(ioat_ring_alloc_order,
  45                  "ioat2+: allocate 2^n descriptors per channel"
  46                  " (default: 8 max: 16)");
  47 static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
  48 module_param(ioat_ring_max_alloc_order, int, 0644);
  49 MODULE_PARM_DESC(ioat_ring_max_alloc_order,
  50                  "ioat2+: upper limit for ring size (default: 16)");
  51
  52 void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
  53 {
  54         void * __iomem reg_base = ioat->base.reg_base;
  55
  56         ioat->pending = 0;
  57         ioat->dmacount += ioat2_ring_pending(ioat);
  58         ioat->issued = ioat->head;
  59         /* make descriptor updates globally visible before notifying channel */
  60         wmb();
  61         writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
  62         dev_dbg(to_dev(&ioat->base),
  63                 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
  64                 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
  65 }
  66
  67 void ioat2_issue_pending(struct dma_chan *chan)
  68 {
  69         struct ioat2_dma_chan *ioat = to_ioat2_chan(chan);
  70
  71         spin_lock_bh(&ioat->ring_lock);
  72         if (ioat->pending == 1)
  73                 __ioat2_issue_pending(ioat);
  74         spin_unlock_bh(&ioat->ring_lock);
  75 }
  76
  77 /**
  78  * ioat2_update_pending - log pending descriptors
  79  * @ioat: ioat2+ channel
  80  *
  81  * set pending to '1' unless pending is already set to '2', pending == 2
  82  * indicates that submission is temporarily blocked due to an in-flight
  83  * reset.  If we are already above the ioat_pending_level threshold then
  84  * just issue pending.
  85  *
  86  * called with ring_lock held
  87  */
  88 static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
  89 {
  90         if (unlikely(ioat->pending == 2))
  91                 return;
  92         else if (ioat2_ring_pending(ioat) > ioat_pending_level)
  93                 __ioat2_issue_pending(ioat);
  94         else
  95                 ioat->pending = 1;
  96 }
  97
  98 static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
  99 {
 100         struct ioat_ring_ent *desc;
 101         struct ioat_dma_descriptor *hw;
 102         int idx;
 103
 104         if (ioat2_ring_space(ioat) < 1) {
 105                 dev_err(to_dev(&ioat->base),
 106                         "Unable to start null desc - ring full\n");
 107                 return;
 108         }
 109
 110         dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
 111                 __func__, ioat->head, ioat->tail, ioat->issued);
 112         idx = ioat2_desc_alloc(ioat, 1);
 113         desc = ioat2_get_ring_ent(ioat, idx);
 114
 115         hw = desc->hw;
 116         hw->ctl = 0;
 117         hw->ctl_f.null = 1;
 118         hw->ctl_f.int_en = 1;
 119         hw->ctl_f.compl_write = 1;
 120         /* set size to non-zero value (channel returns error when size is 0) */
 121         hw->size = NULL_DESC_BUFFER_SIZE;
 122         hw->src_addr = 0;
 123         hw->dst_addr = 0;
 124         async_tx_ack(&desc->txd);
 125         ioat2_set_chainaddr(ioat, desc->txd.phys);
 126         dump_desc_dbg(ioat, desc);
 127         __ioat2_issue_pending(ioat);
 128 }
 129
 130 static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
 131 {
 132         spin_lock_bh(&ioat->ring_lock);
 133         __ioat2_start_null_desc(ioat);
 134         spin_unlock_bh(&ioat->ring_lock);
 135 }
 136
 137 static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 138 {
 139         struct ioat_chan_common *chan = &ioat->base;
 140         struct dma_async_tx_descriptor *tx;
 141         struct ioat_ring_ent *desc;
 142         bool seen_current = false;
 143         u16 active;
 144         int i;
 145
 146         dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
 147                 __func__, ioat->head, ioat->tail, ioat->issued);
 148
 149         active = ioat2_ring_active(ioat);
 150         for (i = 0; i < active && !seen_current; i++) {
 151                 prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
 152                 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
 153                 tx = &desc->txd;
 154                 dump_desc_dbg(ioat, desc);
 155                 if (tx->cookie) {
 156                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 157                         chan->completed_cookie = tx->cookie;
 158                         tx->cookie = 0;
 159                         if (tx->callback) {
 160                                 tx->callback(tx->callback_param);
 161                                 tx->callback = NULL;
 162                         }
 163                 }
 164
 165                 if (tx->phys == phys_complete)
 166                         seen_current = true;
 167         }
 168         ioat->tail += i;
 169         BUG_ON(!seen_current); /* no active descs have written a completion? */
 170
 171         chan->last_completion = phys_complete;
 172         if (ioat->head == ioat->tail) {
 173                 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
 174                         __func__);
 175                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
 176                 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
 177         }
 178 }
 179
 180 /**
 181  * ioat2_cleanup - clean finished descriptors (advance tail pointer)
 182  * @chan: ioat channel to be cleaned up
 183  */
 184 static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
 185 {
 186         struct ioat_chan_common *chan = &ioat->base;
 187         unsigned long phys_complete;
 188
 189         prefetch(chan->completion);
 190
 191         if (!spin_trylock_bh(&chan->cleanup_lock))
 192                 return;
 193
 194         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
 195                 spin_unlock_bh(&chan->cleanup_lock);
 196                 return;
 197         }
 198
 199         if (!spin_trylock_bh(&ioat->ring_lock)) {
 200                 spin_unlock_bh(&chan->cleanup_lock);
 201                 return;
 202         }
 203
 204         __cleanup(ioat, phys_complete);
 205
 206         spin_unlock_bh(&ioat->ring_lock);
 207         spin_unlock_bh(&chan->cleanup_lock);
 208 }
 209
 210 void ioat2_cleanup_tasklet(unsigned long data)
 211 {
 212         struct ioat2_dma_chan *ioat = (void *) data;
 213
 214         ioat2_cleanup(ioat);
 215         writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
 216 }
 217
 218 void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
 219 {
 220         struct ioat_chan_common *chan = &ioat->base;
 221
 222         /* set the tail to be re-issued */
 223         ioat->issued = ioat->tail;
 224         ioat->dmacount = 0;
 225         set_bit(IOAT_COMPLETION_PENDING, &chan->state);
 226         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 227
 228         dev_dbg(to_dev(chan),
 229                 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
 230                 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
 231
 232         if (ioat2_ring_pending(ioat)) {
 233                 struct ioat_ring_ent *desc;
 234
 235                 desc = ioat2_get_ring_ent(ioat, ioat->tail);
 236                 ioat2_set_chainaddr(ioat, desc->txd.phys);
 237                 __ioat2_issue_pending(ioat);
 238         } else
 239                 __ioat2_start_null_desc(ioat);
 240 }
 241
 242 int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo)
 243 {
 244         unsigned long end = jiffies + tmo;
 245         int err = 0;
 246         u32 status;
 247
 248         status = ioat_chansts(chan);
 249         if (is_ioat_active(status) || is_ioat_idle(status))
 250                 ioat_suspend(chan);
 251         while (is_ioat_active(status) || is_ioat_idle(status)) {
 252                 if (end && time_after(jiffies, end)) {
 253                         err = -ETIMEDOUT;
 254                         break;
 255                 }
 256                 status = ioat_chansts(chan);
 257                 cpu_relax();
 258         }
 259
 260         return err;
 261 }
 262
 263 int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
 264 {
 265         unsigned long end = jiffies + tmo;
 266         int err = 0;
 267
 268         ioat_reset(chan);
 269         while (ioat_reset_pending(chan)) {
 270                 if (end && time_after(jiffies, end)) {
 271                         err = -ETIMEDOUT;
 272                         break;
 273                 }
 274                 cpu_relax();
 275         }
 276
 277         return err;
 278 }
 279
 280 static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
 281 {
 282         struct ioat_chan_common *chan = &ioat->base;
 283         unsigned long phys_complete;
 284
 285         ioat2_quiesce(chan, 0);
 286         if (ioat_cleanup_preamble(chan, &phys_complete))
 287                 __cleanup(ioat, phys_complete);
 288
 289         __ioat2_restart_chan(ioat);
 290 }
 291
 292 void ioat2_timer_event(unsigned long data)
 293 {
 294         struct ioat2_dma_chan *ioat = (void *) data;
 295         struct ioat_chan_common *chan = &ioat->base;
 296
 297         spin_lock_bh(&chan->cleanup_lock);
 298         if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
 299                 unsigned long phys_complete;
 300                 u64 status;
 301
 302                 spin_lock_bh(&ioat->ring_lock);
 303                 status = ioat_chansts(chan);
 304
 305                 /* when halted due to errors check for channel
 306                  * programming errors before advancing the completion state
 307                  */
 308                 if (is_ioat_halted(status)) {
 309                         u32 chanerr;
 310
 311                         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 312                         dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
 313                                 __func__, chanerr);
 314                         BUG_ON(is_ioat_bug(chanerr));
 315                 }
 316
 317                 /* if we haven't made progress and we have already
 318                  * acknowledged a pending completion once, then be more
 319                  * forceful with a restart
 320                  */
 321                 if (ioat_cleanup_preamble(chan, &phys_complete))
 322                         __cleanup(ioat, phys_complete);
 323                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
 324                         ioat2_restart_channel(ioat);
 325                 else {
 326                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
 327                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 328                 }
 329                 spin_unlock_bh(&ioat->ring_lock);
 330         } else {
 331                 u16 active;
 332
 333                 /* if the ring is idle, empty, and oversized try to step
 334                  * down the size
 335                  */
 336                 spin_lock_bh(&ioat->ring_lock);
 337                 active = ioat2_ring_active(ioat);
 338                 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
 339                         reshape_ring(ioat, ioat->alloc_order-1);
 340                 spin_unlock_bh(&ioat->ring_lock);
 341
 342                 /* keep shrinking until we get back to our minimum
 343                  * default size
 344                  */
 345                 if (ioat->alloc_order > ioat_get_alloc_order())
 346                         mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
 347         }
 348         spin_unlock_bh(&chan->cleanup_lock);
 349 }
 350
 351 static int ioat2_reset_hw(struct ioat_chan_common *chan)
 352 {
 353         /* throw away whatever the channel was doing and get it initialized */
 354         u32 chanerr;
 355
 356         ioat2_quiesce(chan, msecs_to_jiffies(100));
 357
 358         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 359         writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 360
 361         return ioat2_reset_sync(chan, msecs_to_jiffies(200));
 362 }
 363
 364 /**
 365  * ioat2_enumerate_channels - find and initialize the device's channels
 366  * @device: the device to be enumerated
 367  */
 368 int ioat2_enumerate_channels(struct ioatdma_device *device)
 369 {
 370         struct ioat2_dma_chan *ioat;
 371         struct device *dev = &device->pdev->dev;
 372         struct dma_device *dma = &device->common;
 373         u8 xfercap_log;
 374         int i;
 375
 376         INIT_LIST_HEAD(&dma->channels);
 377         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 378         dma->chancnt &= 0x1f; /* bits [4:0] valid */
 379         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
 380                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
 381                          dma->chancnt, ARRAY_SIZE(device->idx));
 382                 dma->chancnt = ARRAY_SIZE(device->idx);
 383         }
 384         xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 385         xfercap_log &= 0x1f; /* bits [4:0] valid */
 386         if (xfercap_log == 0)
 387                 return 0;
 388         dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
 389
 390         /* FIXME which i/oat version is i7300? */
 391 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
 392         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 393                 dma->chancnt--;
 394 #endif
 395         for (i = 0; i < dma->chancnt; i++) {
 396                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 397                 if (!ioat)
 398                         break;
 399
 400                 ioat_init_channel(device, &ioat->base, i,
 401                                   device->timer_fn,
 402                                   device->cleanup_tasklet,
 403                                   (unsigned long) ioat);
 404                 ioat->xfercap_log = xfercap_log;
 405                 spin_lock_init(&ioat->ring_lock);
 406                 if (device->reset_hw(&ioat->base)) {
 407                         i = 0;
 408                         break;
 409                 }
 410         }
 411         dma->chancnt = i;
 412         return i;
 413 }
 414
 415 static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
 416 {
 417         struct dma_chan *c = tx->chan;
 418         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 419         struct ioat_chan_common *chan = &ioat->base;
 420         dma_cookie_t cookie = c->cookie;
 421
 422         cookie++;
 423         if (cookie < 0)
 424                 cookie = 1;
 425         tx->cookie = cookie;
 426         c->cookie = cookie;
 427         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 428
 429         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
 430                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 431         ioat2_update_pending(ioat);
 432         spin_unlock_bh(&ioat->ring_lock);
 433
 434         return cookie;
 435 }
 436
 437 static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
 438 {
 439         struct ioat_dma_descriptor *hw;
 440         struct ioat_ring_ent *desc;
 441         struct ioatdma_device *dma;
 442         dma_addr_t phys;
 443
 444         dma = to_ioatdma_device(chan->device);
 445         hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
 446         if (!hw)
 447                 return NULL;
 448         memset(hw, 0, sizeof(*hw));
 449
 450         desc = kmem_cache_alloc(ioat2_cache, flags);
 451         if (!desc) {
 452                 pci_pool_free(dma->dma_pool, hw, phys);
 453                 return NULL;
 454         }
 455         memset(desc, 0, sizeof(*desc));
 456
 457         dma_async_tx_descriptor_init(&desc->txd, chan);
 458         desc->txd.tx_submit = ioat2_tx_submit_unlock;
 459         desc->hw = hw;
 460         desc->txd.phys = phys;
 461         return desc;
 462 }
 463
 464 static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
 465 {
 466         struct ioatdma_device *dma;
 467
 468         dma = to_ioatdma_device(chan->device);
 469         pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
 470         kmem_cache_free(ioat2_cache, desc);
 471 }
 472
 473 static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
 474 {
 475         struct ioat_ring_ent **ring;
 476         int descs = 1 << order;
 477         int i;
 478
 479         if (order > ioat_get_max_alloc_order())
 480                 return NULL;
 481
 482         /* allocate the array to hold the software ring */
 483         ring = kcalloc(descs, sizeof(*ring), flags);
 484         if (!ring)
 485                 return NULL;
 486         for (i = 0; i < descs; i++) {
 487                 ring[i] = ioat2_alloc_ring_ent(c, flags);
 488                 if (!ring[i]) {
 489                         while (i--)
 490                                 ioat2_free_ring_ent(ring[i], c);
 491                         kfree(ring);
 492                         return NULL;
 493                 }
 494                 set_desc_id(ring[i], i);
 495         }
 496
 497         /* link descs */
 498         for (i = 0; i < descs-1; i++) {
 499                 struct ioat_ring_ent *next = ring[i+1];
 500                 struct ioat_dma_descriptor *hw = ring[i]->hw;
 501
 502                 hw->next = next->txd.phys;
 503         }
 504         ring[i]->hw->next = ring[0]->txd.phys;
 505
 506         return ring;
 507 }
 508
 509 /* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
 510  * @chan: channel to be initialized
 511  */
 512 int ioat2_alloc_chan_resources(struct dma_chan *c)
 513 {
 514         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 515         struct ioat_chan_common *chan = &ioat->base;
 516         struct ioat_ring_ent **ring;
 517         int order;
 518
 519         /* have we already been set up? */
 520         if (ioat->ring)
 521                 return 1 << ioat->alloc_order;
 522
 523         /* Setup register to interrupt and write completion status on error */
 524         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 525
 526         /* allocate a completion writeback area */
 527         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 528         chan->completion = pci_pool_alloc(chan->device->completion_pool,
 529                                           GFP_KERNEL, &chan->completion_dma);
 530         if (!chan->completion)
 531                 return -ENOMEM;
 532
 533         memset(chan->completion, 0, sizeof(*chan->completion));
 534         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
 535                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 536         writel(((u64) chan->completion_dma) >> 32,
 537                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 538
 539         order = ioat_get_alloc_order();
 540         ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
 541         if (!ring)
 542                 return -ENOMEM;
 543
 544         spin_lock_bh(&ioat->ring_lock);
 545         ioat->ring = ring;
 546         ioat->head = 0;
 547         ioat->issued = 0;
 548         ioat->tail = 0;
 549         ioat->pending = 0;
 550         ioat->alloc_order = order;
 551         spin_unlock_bh(&ioat->ring_lock);
 552
 553         tasklet_enable(&chan->cleanup_task);
 554         ioat2_start_null_desc(ioat);
 555
 556         return 1 << ioat->alloc_order;
 557 }
 558
 559 bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
 560 {
 561         /* reshape differs from normal ring allocation in that we want
 562          * to allocate a new software ring while only
 563          * extending/truncating the hardware ring
 564          */
 565         struct ioat_chan_common *chan = &ioat->base;
 566         struct dma_chan *c = &chan->common;
 567         const u16 curr_size = ioat2_ring_mask(ioat) + 1;
 568         const u16 active = ioat2_ring_active(ioat);
 569         const u16 new_size = 1 << order;
 570         struct ioat_ring_ent **ring;
 571         u16 i;
 572
 573         if (order > ioat_get_max_alloc_order())
 574                 return false;
 575
 576         /* double check that we have at least 1 free descriptor */
 577         if (active == curr_size)
 578                 return false;
 579
 580         /* when shrinking, verify that we can hold the current active
 581          * set in the new ring
 582          */
 583         if (active >= new_size)
 584                 return false;
 585
 586         /* allocate the array to hold the software ring */
 587         ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
 588         if (!ring)
 589                 return false;
 590
 591         /* allocate/trim descriptors as needed */
 592         if (new_size > curr_size) {
 593                 /* copy current descriptors to the new ring */
 594                 for (i = 0; i < curr_size; i++) {
 595                         u16 curr_idx = (ioat->tail+i) & (curr_size-1);
 596                         u16 new_idx = (ioat->tail+i) & (new_size-1);
 597
 598                         ring[new_idx] = ioat->ring[curr_idx];
 599                         set_desc_id(ring[new_idx], new_idx);
 600                 }
 601
 602                 /* add new descriptors to the ring */
 603                 for (i = curr_size; i < new_size; i++) {
 604                         u16 new_idx = (ioat->tail+i) & (new_size-1);
 605
 606                         ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
 607                         if (!ring[new_idx]) {
 608                                 while (i--) {
 609                                         u16 new_idx = (ioat->tail+i) & (new_size-1);
 610
 611                                         ioat2_free_ring_ent(ring[new_idx], c);
 612                                 }
 613                                 kfree(ring);
 614                                 return false;
 615                         }
 616                         set_desc_id(ring[new_idx], new_idx);
 617                 }
 618
 619                 /* hw link new descriptors */
 620                 for (i = curr_size-1; i < new_size; i++) {
 621                         u16 new_idx = (ioat->tail+i) & (new_size-1);
 622                         struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
 623                         struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
 624
 625                         hw->next = next->txd.phys;
 626                 }
 627         } else {
 628                 struct ioat_dma_descriptor *hw;
 629                 struct ioat_ring_ent *next;
 630
 631                 /* copy current descriptors to the new ring, dropping the
 632                  * removed descriptors
 633                  */
 634                 for (i = 0; i < new_size; i++) {
 635                         u16 curr_idx = (ioat->tail+i) & (curr_size-1);
 636                         u16 new_idx = (ioat->tail+i) & (new_size-1);
 637
 638                         ring[new_idx] = ioat->ring[curr_idx];
 639                         set_desc_id(ring[new_idx], new_idx);
 640                 }
 641
 642                 /* free deleted descriptors */
 643                 for (i = new_size; i < curr_size; i++) {
 644                         struct ioat_ring_ent *ent;
 645
 646                         ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
 647                         ioat2_free_ring_ent(ent, c);
 648                 }
 649
 650                 /* fix up hardware ring */
 651                 hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
 652                 next = ring[(ioat->tail+new_size) & (new_size-1)];
 653                 hw->next = next->txd.phys;
 654         }
 655
 656         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
 657                 __func__, new_size);
 658
 659         kfree(ioat->ring);
 660         ioat->ring = ring;
 661         ioat->alloc_order = order;
 662
 663         return true;
 664 }
 665
 666 /**
 667  * ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops
 668  * @idx: gets starting descriptor index on successful allocation
 669  * @ioat: ioat2,3 channel (ring) to operate on
 670  * @num_descs: allocation length
 671  */
 672 int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs)
 673 {
 674         struct ioat_chan_common *chan = &ioat->base;
 675
 676         spin_lock_bh(&ioat->ring_lock);
 677         /* never allow the last descriptor to be consumed, we need at
 678          * least one free at all times to allow for on-the-fly ring
 679          * resizing.
 680          */
 681         while (unlikely(ioat2_ring_space(ioat) <= num_descs)) {
 682                 if (reshape_ring(ioat, ioat->alloc_order + 1) &&
 683                     ioat2_ring_space(ioat) > num_descs)
 684                                 break;
 685
 686                 if (printk_ratelimit())
 687                         dev_dbg(to_dev(chan),
 688                                 "%s: ring full! num_descs: %d (%x:%x:%x)\n",
 689                                 __func__, num_descs, ioat->head, ioat->tail,
 690                                 ioat->issued);
 691                 spin_unlock_bh(&ioat->ring_lock);
 692
 693                 /* progress reclaim in the allocation failure case we
 694                  * may be called under bh_disabled so we need to trigger
 695                  * the timer event directly
 696                  */
 697                 spin_lock_bh(&chan->cleanup_lock);
 698                 if (jiffies > chan->timer.expires &&
 699                     timer_pending(&chan->timer)) {
 700                         struct ioatdma_device *device = chan->device;
 701
 702                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 703                         spin_unlock_bh(&chan->cleanup_lock);
 704                         device->timer_fn((unsigned long) ioat);
 705                 } else
 706                         spin_unlock_bh(&chan->cleanup_lock);
 707                 return -ENOMEM;
 708         }
 709
 710         dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
 711                 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
 712
 713         *idx = ioat2_desc_alloc(ioat, num_descs);
 714         return 0;  /* with ioat->ring_lock held */
 715 }
 716
 717 struct dma_async_tx_descriptor *
 718 ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
 719                            dma_addr_t dma_src, size_t len, unsigned long flags)
 720 {
 721         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 722         struct ioat_dma_descriptor *hw;
 723         struct ioat_ring_ent *desc;
 724         dma_addr_t dst = dma_dest;
 725         dma_addr_t src = dma_src;
 726         size_t total_len = len;
 727         int num_descs;
 728         u16 idx;
 729         int i;
 730
 731         num_descs = ioat2_xferlen_to_descs(ioat, len);
 732         if (likely(num_descs) &&
 733             ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
 734                 /* pass */;
 735         else
 736                 return NULL;
 737         i = 0;
 738         do {
 739                 size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
 740
 741                 desc = ioat2_get_ring_ent(ioat, idx + i);
 742                 hw = desc->hw;
 743
 744                 hw->size = copy;
 745                 hw->ctl = 0;
 746                 hw->src_addr = src;
 747                 hw->dst_addr = dst;
 748
 749                 len -= copy;
 750                 dst += copy;
 751                 src += copy;
 752                 dump_desc_dbg(ioat, desc);
 753         } while (++i < num_descs);
 754
 755         desc->txd.flags = flags;
 756         desc->len = total_len;
 757         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 758         hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
 759         hw->ctl_f.compl_write = 1;
 760         dump_desc_dbg(ioat, desc);
 761         /* we leave the channel locked to ensure in order submission */
 762
 763         return &desc->txd;
 764 }
 765
 766 /**
 767  * ioat2_free_chan_resources - release all the descriptors
 768  * @chan: the channel to be cleaned
 769  */
 770 void ioat2_free_chan_resources(struct dma_chan *c)
 771 {
 772         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 773         struct ioat_chan_common *chan = &ioat->base;
 774         struct ioatdma_device *device = chan->device;
 775         struct ioat_ring_ent *desc;
 776         const u16 total_descs = 1 << ioat->alloc_order;
 777         int descs;
 778         int i;
 779
 780         /* Before freeing channel resources first check
 781          * if they have been previously allocated for this channel.
 782          */
 783         if (!ioat->ring)
 784                 return;
 785
 786         tasklet_disable(&chan->cleanup_task);
 787         del_timer_sync(&chan->timer);
 788         device->cleanup_tasklet((unsigned long) ioat);
 789         device->reset_hw(chan);
 790
 791         spin_lock_bh(&ioat->ring_lock);
 792         descs = ioat2_ring_space(ioat);
 793         dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
 794         for (i = 0; i < descs; i++) {
 795                 desc = ioat2_get_ring_ent(ioat, ioat->head + i);
 796                 ioat2_free_ring_ent(desc, c);
 797         }
 798
 799         if (descs < total_descs)
 800                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 801                         total_descs - descs);
 802
 803         for (i = 0; i < total_descs - descs; i++) {
 804                 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
 805                 dump_desc_dbg(ioat, desc);
 806                 ioat2_free_ring_ent(desc, c);
 807         }
 808
 809         kfree(ioat->ring);
 810         ioat->ring = NULL;
 811         ioat->alloc_order = 0;
 812         pci_pool_free(device->completion_pool, chan->completion,
 813                       chan->completion_dma);
 814         spin_unlock_bh(&ioat->ring_lock);
 815
 816         chan->last_completion = 0;
 817         chan->completion_dma = 0;
 818         ioat->pending = 0;
 819         ioat->dmacount = 0;
 820 }
 821
 822 enum dma_status
 823 ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
 824                      dma_cookie_t *done, dma_cookie_t *used)
 825 {
 826         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 827         struct ioatdma_device *device = ioat->base.device;
 828
 829         if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
 830                 return DMA_SUCCESS;
 831
 832         device->cleanup_tasklet((unsigned long) ioat);
 833
 834         return ioat_is_complete(c, cookie, done, used);
 835 }
 836
 837 static ssize_t ring_size_show(struct dma_chan *c, char *page)
 838 {
 839         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 840
 841         return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
 842 }
 843 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
 844
 845 static ssize_t ring_active_show(struct dma_chan *c, char *page)
 846 {
 847         struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 848
 849         /* ...taken outside the lock, no need to be precise */
 850         return sprintf(page, "%d\n", ioat2_ring_active(ioat));
 851 }
 852 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
 853
 854 static struct attribute *ioat2_attrs[] = {
 855         &ring_size_attr.attr,
 856         &ring_active_attr.attr,
 857         &ioat_cap_attr.attr,
 858         &ioat_version_attr.attr,
 859         NULL,
 860 };
 861
 862 struct kobj_type ioat2_ktype = {
 863         .sysfs_ops = &ioat_sysfs_ops,
 864         .default_attrs = ioat2_attrs,
 865 };
 866
 867 int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
 868 {
 869         struct pci_dev *pdev = device->pdev;
 870         struct dma_device *dma;
 871         struct dma_chan *c;
 872         struct ioat_chan_common *chan;
 873         int err;
 874
 875         device->enumerate_channels = ioat2_enumerate_channels;
 876         device->reset_hw = ioat2_reset_hw;
 877         device->cleanup_tasklet = ioat2_cleanup_tasklet;
 878         device->timer_fn = ioat2_timer_event;
 879         device->self_test = ioat_dma_self_test;
 880         dma = &device->common;
 881         dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
 882         dma->device_issue_pending = ioat2_issue_pending;
 883         dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
 884         dma->device_free_chan_resources = ioat2_free_chan_resources;
 885         dma->device_is_tx_complete = ioat2_is_complete;
 886
 887         err = ioat_probe(device);
 888         if (err)
 889                 return err;
 890         ioat_set_tcp_copy_break(2048);
 891
 892         list_for_each_entry(c, &dma->channels, device_node) {
 893                 chan = to_chan_common(c);
 894                 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
 895                        chan->reg_base + IOAT_DCACTRL_OFFSET);
 896         }
 897
 898         err = ioat_register(device);
 899         if (err)
 900                 return err;
 901
 902         ioat_kobject_add(device, &ioat2_ktype);
 903
 904         if (dca)
 905                 device->dca = ioat2_dca_init(pdev, device->reg_base);
 906
 907         return err;
 908 }