drivers/dma/imx-sdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-sdma.c
   4 //
   5 // This file contains a driver for the Freescale Smart DMA engine
   6 //
   7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8 //
   9 // Based on code from Freescale:
  10 //
  11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  12
  13 #include <linux/init.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mm.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firmware.h>
  28 #include <linux/slab.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_dma.h>
  35 #include <linux/workqueue.h>
  36
  37 #include <asm/irq.h>
  38 #include <linux/platform_data/dma-imx-sdma.h>
  39 #include <linux/platform_data/dma-imx.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  43
  44 #include "dmaengine.h"
  45 #include "virt-dma.h"
  46
  47 /* SDMA registers */
  48 #define SDMA_H_C0PTR            0x000
  49 #define SDMA_H_INTR             0x004
  50 #define SDMA_H_STATSTOP         0x008
  51 #define SDMA_H_START            0x00c
  52 #define SDMA_H_EVTOVR           0x010
  53 #define SDMA_H_DSPOVR           0x014
  54 #define SDMA_H_HOSTOVR          0x018
  55 #define SDMA_H_EVTPEND          0x01c
  56 #define SDMA_H_DSPENBL          0x020
  57 #define SDMA_H_RESET            0x024
  58 #define SDMA_H_EVTERR           0x028
  59 #define SDMA_H_INTRMSK          0x02c
  60 #define SDMA_H_PSW              0x030
  61 #define SDMA_H_EVTERRDBG        0x034
  62 #define SDMA_H_CONFIG           0x038
  63 #define SDMA_ONCE_ENB           0x040
  64 #define SDMA_ONCE_DATA          0x044
  65 #define SDMA_ONCE_INSTR         0x048
  66 #define SDMA_ONCE_STAT          0x04c
  67 #define SDMA_ONCE_CMD           0x050
  68 #define SDMA_EVT_MIRROR         0x054
  69 #define SDMA_ILLINSTADDR        0x058
  70 #define SDMA_CHN0ADDR           0x05c
  71 #define SDMA_ONCE_RTB           0x060
  72 #define SDMA_XTRIG_CONF1        0x070
  73 #define SDMA_XTRIG_CONF2        0x074
  74 #define SDMA_CHNENBL0_IMX35     0x200
  75 #define SDMA_CHNENBL0_IMX31     0x080
  76 #define SDMA_CHNPRI_0           0x100
  77
  78 /*
  79  * Buffer descriptor status values.
  80  */
  81 #define BD_DONE  0x01
  82 #define BD_WRAP  0x02
  83 #define BD_CONT  0x04
  84 #define BD_INTR  0x08
  85 #define BD_RROR  0x10
  86 #define BD_LAST  0x20
  87 #define BD_EXTD  0x80
  88
  89 /*
  90  * Data Node descriptor status values.
  91  */
  92 #define DND_END_OF_FRAME  0x80
  93 #define DND_END_OF_XFER   0x40
  94 #define DND_DONE          0x20
  95 #define DND_UNUSED        0x01
  96
  97 /*
  98  * IPCV2 descriptor status values.
  99  */
 100 #define BD_IPCV2_END_OF_FRAME  0x40
 101
 102 #define IPCV2_MAX_NODES        50
 103 /*
 104  * Error bit set in the CCB status field by the SDMA,
 105  * in setbd routine, in case of a transfer error
 106  */
 107 #define DATA_ERROR  0x10000000
 108
 109 /*
 110  * Buffer descriptor commands.
 111  */
 112 #define C0_ADDR             0x01
 113 #define C0_LOAD             0x02
 114 #define C0_DUMP             0x03
 115 #define C0_SETCTX           0x07
 116 #define C0_GETCTX           0x03
 117 #define C0_SETDM            0x01
 118 #define C0_SETPM            0x04
 119 #define C0_GETDM            0x02
 120 #define C0_GETPM            0x08
 121 /*
 122  * Change endianness indicator in the BD command field
 123  */
 124 #define CHANGE_ENDIANNESS   0x80
 125
 126 /*
 127  *  p_2_p watermark_level description
 128  *      Bits            Name                    Description
 129  *      0-7             Lower WML               Lower watermark level
 130  *      8               PS                      1: Pad Swallowing
 131  *                                              0: No Pad Swallowing
 132  *      9               PA                      1: Pad Adding
 133  *                                              0: No Pad Adding
 134  *      10              SPDIF                   If this bit is set both source
 135  *                                              and destination are on SPBA
 136  *      11              Source Bit(SP)          1: Source on SPBA
 137  *                                              0: Source on AIPS
 138  *      12              Destination Bit(DP)     1: Destination on SPBA
 139  *                                              0: Destination on AIPS
 140  *      13-15           ---------               MUST BE 0
 141  *      16-23           Higher WML              HWML
 142  *      24-27           N                       Total number of samples after
 143  *                                              which Pad adding/Swallowing
 144  *                                              must be done. It must be odd.
 145  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 146  *                                              LWML event mask
 147  *                                              0: LWE in EVENTS register
 148  *                                              1: LWE in EVENTS2 register
 149  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 150  *                                              HWML event mask
 151  *                                              0: HWE in EVENTS register
 152  *                                              1: HWE in EVENTS2 register
 153  *      30              ---------               MUST BE 0
 154  *      31              CONT                    1: Amount of samples to be
 155  *                                              transferred is unknown and
 156  *                                              script will keep on
 157  *                                              transferring samples as long as
 158  *                                              both events are detected and
 159  *                                              script must be manually stopped
 160  *                                              by the application
 161  *                                              0: The amount of samples to be
 162  *                                              transferred is equal to the
 163  *                                              count field of mode word
 164  */
 165 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 166 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 167 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 168 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 169 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 170 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 171 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 172 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 173 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 174 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 175
 176 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 177                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 178                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 179
 180 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 181                                  BIT(DMA_MEM_TO_DEV) | \
 182                                  BIT(DMA_DEV_TO_DEV))
 183
 184 /*
 185  * Mode/Count of data node descriptors - IPCv2
 186  */
 187 struct sdma_mode_count {
 188 #define SDMA_BD_MAX_CNT 0xffff
 189         u32 count   : 16; /* size of the buffer pointed by this BD */
 190         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 191         u32 command :  8; /* command mostly used for channel 0 */
 192 };
 193
 194 /*
 195  * Buffer descriptor
 196  */
 197 struct sdma_buffer_descriptor {
 198         struct sdma_mode_count  mode;
 199         u32 buffer_addr;        /* address of the buffer described */
 200         u32 ext_buffer_addr;    /* extended buffer address */
 201 } __attribute__ ((packed));
 202
 203 /**
 204  * struct sdma_channel_control - Channel control Block
 205  *
 206  * @current_bd_ptr:     current buffer descriptor processed
 207  * @base_bd_ptr:        first element of buffer descriptor array
 208  * @unused:             padding. The SDMA engine expects an array of 128 byte
 209  *                      control blocks
 210  */
 211 struct sdma_channel_control {
 212         u32 current_bd_ptr;
 213         u32 base_bd_ptr;
 214         u32 unused[2];
 215 } __attribute__ ((packed));
 216
 217 /**
 218  * struct sdma_state_registers - SDMA context for a channel
 219  *
 220  * @pc:         program counter
 221  * @unused1:    unused
 222  * @t:          test bit: status of arithmetic & test instruction
 223  * @rpc:        return program counter
 224  * @unused0:    unused
 225  * @sf:         source fault while loading data
 226  * @spc:        loop start program counter
 227  * @unused2:    unused
 228  * @df:         destination fault while storing data
 229  * @epc:        loop end program counter
 230  * @lm:         loop mode
 231  */
 232 struct sdma_state_registers {
 233         u32 pc     :14;
 234         u32 unused1: 1;
 235         u32 t      : 1;
 236         u32 rpc    :14;
 237         u32 unused0: 1;
 238         u32 sf     : 1;
 239         u32 spc    :14;
 240         u32 unused2: 1;
 241         u32 df     : 1;
 242         u32 epc    :14;
 243         u32 lm     : 2;
 244 } __attribute__ ((packed));
 245
 246 /**
 247  * struct sdma_context_data - sdma context specific to a channel
 248  *
 249  * @channel_state:      channel state bits
 250  * @gReg:               general registers
 251  * @mda:                burst dma destination address register
 252  * @msa:                burst dma source address register
 253  * @ms:                 burst dma status register
 254  * @md:                 burst dma data register
 255  * @pda:                peripheral dma destination address register
 256  * @psa:                peripheral dma source address register
 257  * @ps:                 peripheral dma status register
 258  * @pd:                 peripheral dma data register
 259  * @ca:                 CRC polynomial register
 260  * @cs:                 CRC accumulator register
 261  * @dda:                dedicated core destination address register
 262  * @dsa:                dedicated core source address register
 263  * @ds:                 dedicated core status register
 264  * @dd:                 dedicated core data register
 265  * @scratch0:           1st word of dedicated ram for context switch
 266  * @scratch1:           2nd word of dedicated ram for context switch
 267  * @scratch2:           3rd word of dedicated ram for context switch
 268  * @scratch3:           4th word of dedicated ram for context switch
 269  * @scratch4:           5th word of dedicated ram for context switch
 270  * @scratch5:           6th word of dedicated ram for context switch
 271  * @scratch6:           7th word of dedicated ram for context switch
 272  * @scratch7:           8th word of dedicated ram for context switch
 273  */
 274 struct sdma_context_data {
 275         struct sdma_state_registers  channel_state;
 276         u32  gReg[8];
 277         u32  mda;
 278         u32  msa;
 279         u32  ms;
 280         u32  md;
 281         u32  pda;
 282         u32  psa;
 283         u32  ps;
 284         u32  pd;
 285         u32  ca;
 286         u32  cs;
 287         u32  dda;
 288         u32  dsa;
 289         u32  ds;
 290         u32  dd;
 291         u32  scratch0;
 292         u32  scratch1;
 293         u32  scratch2;
 294         u32  scratch3;
 295         u32  scratch4;
 296         u32  scratch5;
 297         u32  scratch6;
 298         u32  scratch7;
 299 } __attribute__ ((packed));
 300
 301
 302 struct sdma_engine;
 303
 304 /**
 305  * struct sdma_desc - descriptor structor for one transfer
 306  * @vd:                 descriptor for virt dma
 307  * @num_bd:             number of descriptors currently handling
 308  * @bd_phys:            physical address of bd
 309  * @buf_tail:           ID of the buffer that was processed
 310  * @buf_ptail:          ID of the previous buffer that was processed
 311  * @period_len:         period length, used in cyclic.
 312  * @chn_real_count:     the real count updated from bd->mode.count
 313  * @chn_count:          the transfer count set
 314  * @sdmac:              sdma_channel pointer
 315  * @bd:                 pointer of allocate bd
 316  */
 317 struct sdma_desc {
 318         struct virt_dma_desc    vd;
 319         unsigned int            num_bd;
 320         dma_addr_t              bd_phys;
 321         unsigned int            buf_tail;
 322         unsigned int            buf_ptail;
 323         unsigned int            period_len;
 324         unsigned int            chn_real_count;
 325         unsigned int            chn_count;
 326         struct sdma_channel     *sdmac;
 327         struct sdma_buffer_descriptor *bd;
 328 };
 329
 330 /**
 331  * struct sdma_channel - housekeeping for a SDMA channel
 332  *
 333  * @vc:                 virt_dma base structure
 334  * @desc:               sdma description including vd and other special member
 335  * @sdma:               pointer to the SDMA engine for this channel
 336  * @channel:            the channel number, matches dmaengine chan_id + 1
 337  * @direction:          transfer type. Needed for setting SDMA script
 338  * @slave_config        Slave configuration
 339  * @peripheral_type:    Peripheral type. Needed for setting SDMA script
 340  * @event_id0:          aka dma request line
 341  * @event_id1:          for channels that use 2 events
 342  * @word_size:          peripheral access size
 343  * @pc_from_device:     script address for those device_2_memory
 344  * @pc_to_device:       script address for those memory_2_device
 345  * @device_to_device:   script address for those device_2_device
 346  * @pc_to_pc:           script address for those memory_2_memory
 347  * @flags:              loop mode or not
 348  * @per_address:        peripheral source or destination address in common case
 349  *                      destination address in p_2_p case
 350  * @per_address2:       peripheral source address in p_2_p case
 351  * @event_mask:         event mask used in p_2_p script
 352  * @watermark_level:    value for gReg[7], some script will extend it from
 353  *                      basic watermark such as p_2_p
 354  * @shp_addr:           value for gReg[6]
 355  * @per_addr:           value for gReg[2]
 356  * @status:             status of dma channel
 357  * @data:               specific sdma interface structure
 358  * @bd_pool:            dma_pool for bd
 359  */
 360 struct sdma_channel {
 361         struct virt_dma_chan            vc;
 362         struct sdma_desc                *desc;
 363         struct sdma_engine              *sdma;
 364         unsigned int                    channel;
 365         enum dma_transfer_direction             direction;
 366         struct dma_slave_config         slave_config;
 367         enum sdma_peripheral_type       peripheral_type;
 368         unsigned int                    event_id0;
 369         unsigned int                    event_id1;
 370         enum dma_slave_buswidth         word_size;
 371         unsigned int                    pc_from_device, pc_to_device;
 372         unsigned int                    device_to_device;
 373         unsigned int                    pc_to_pc;
 374         unsigned long                   flags;
 375         dma_addr_t                      per_address, per_address2;
 376         unsigned long                   event_mask[2];
 377         unsigned long                   watermark_level;
 378         u32                             shp_addr, per_addr;
 379         enum dma_status                 status;
 380         struct imx_dma_data             data;
 381         struct work_struct              terminate_worker;
 382 };
 383
 384 #define IMX_DMA_SG_LOOP         BIT(0)
 385
 386 #define MAX_DMA_CHANNELS 32
 387 #define MXC_SDMA_DEFAULT_PRIORITY 1
 388 #define MXC_SDMA_MIN_PRIORITY 1
 389 #define MXC_SDMA_MAX_PRIORITY 7
 390
 391 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 392
 393 /**
 394  * struct sdma_firmware_header - Layout of the firmware image
 395  *
 396  * @magic:              "SDMA"
 397  * @version_major:      increased whenever layout of struct
 398  *                      sdma_script_start_addrs changes.
 399  * @version_minor:      firmware minor version (for binary compatible changes)
 400  * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
 401  * @num_script_addrs:   Number of script addresses in this image
 402  * @ram_code_start:     offset of SDMA ram image in this firmware image
 403  * @ram_code_size:      size of SDMA ram image
 404  * @script_addrs:       Stores the start address of the SDMA scripts
 405  *                      (in SDMA memory space)
 406  */
 407 struct sdma_firmware_header {
 408         u32     magic;
 409         u32     version_major;
 410         u32     version_minor;
 411         u32     script_addrs_start;
 412         u32     num_script_addrs;
 413         u32     ram_code_start;
 414         u32     ram_code_size;
 415 };
 416
 417 struct sdma_driver_data {
 418         int chnenbl0;
 419         int num_events;
 420         struct sdma_script_start_addrs  *script_addrs;
 421 };
 422
 423 struct sdma_engine {
 424         struct device                   *dev;
 425         struct device_dma_parameters    dma_parms;
 426         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 427         struct sdma_channel_control     *channel_control;
 428         void __iomem                    *regs;
 429         struct sdma_context_data        *context;
 430         dma_addr_t                      context_phys;
 431         struct dma_device               dma_device;
 432         struct clk                      *clk_ipg;
 433         struct clk                      *clk_ahb;
 434         spinlock_t                      channel_0_lock;
 435         u32                             script_number;
 436         struct sdma_script_start_addrs  *script_addrs;
 437         const struct sdma_driver_data   *drvdata;
 438         u32                             spba_start_addr;
 439         u32                             spba_end_addr;
 440         unsigned int                    irq;
 441         dma_addr_t                      bd0_phys;
 442         struct sdma_buffer_descriptor   *bd0;
 443 };
 444
 445 static int sdma_config_write(struct dma_chan *chan,
 446                        struct dma_slave_config *dmaengine_cfg,
 447                        enum dma_transfer_direction direction);
 448
 449 static struct sdma_driver_data sdma_imx31 = {
 450         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 451         .num_events = 32,
 452 };
 453
 454 static struct sdma_script_start_addrs sdma_script_imx25 = {
 455         .ap_2_ap_addr = 729,
 456         .uart_2_mcu_addr = 904,
 457         .per_2_app_addr = 1255,
 458         .mcu_2_app_addr = 834,
 459         .uartsh_2_mcu_addr = 1120,
 460         .per_2_shp_addr = 1329,
 461         .mcu_2_shp_addr = 1048,
 462         .ata_2_mcu_addr = 1560,
 463         .mcu_2_ata_addr = 1479,
 464         .app_2_per_addr = 1189,
 465         .app_2_mcu_addr = 770,
 466         .shp_2_per_addr = 1407,
 467         .shp_2_mcu_addr = 979,
 468 };
 469
 470 static struct sdma_driver_data sdma_imx25 = {
 471         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 472         .num_events = 48,
 473         .script_addrs = &sdma_script_imx25,
 474 };
 475
 476 static struct sdma_driver_data sdma_imx35 = {
 477         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 478         .num_events = 48,
 479 };
 480
 481 static struct sdma_script_start_addrs sdma_script_imx51 = {
 482         .ap_2_ap_addr = 642,
 483         .uart_2_mcu_addr = 817,
 484         .mcu_2_app_addr = 747,
 485         .mcu_2_shp_addr = 961,
 486         .ata_2_mcu_addr = 1473,
 487         .mcu_2_ata_addr = 1392,
 488         .app_2_per_addr = 1033,
 489         .app_2_mcu_addr = 683,
 490         .shp_2_per_addr = 1251,
 491         .shp_2_mcu_addr = 892,
 492 };
 493
 494 static struct sdma_driver_data sdma_imx51 = {
 495         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 496         .num_events = 48,
 497         .script_addrs = &sdma_script_imx51,
 498 };
 499
 500 static struct sdma_script_start_addrs sdma_script_imx53 = {
 501         .ap_2_ap_addr = 642,
 502         .app_2_mcu_addr = 683,
 503         .mcu_2_app_addr = 747,
 504         .uart_2_mcu_addr = 817,
 505         .shp_2_mcu_addr = 891,
 506         .mcu_2_shp_addr = 960,
 507         .uartsh_2_mcu_addr = 1032,
 508         .spdif_2_mcu_addr = 1100,
 509         .mcu_2_spdif_addr = 1134,
 510         .firi_2_mcu_addr = 1193,
 511         .mcu_2_firi_addr = 1290,
 512 };
 513
 514 static struct sdma_driver_data sdma_imx53 = {
 515         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 516         .num_events = 48,
 517         .script_addrs = &sdma_script_imx53,
 518 };
 519
 520 static struct sdma_script_start_addrs sdma_script_imx6q = {
 521         .ap_2_ap_addr = 642,
 522         .uart_2_mcu_addr = 817,
 523         .mcu_2_app_addr = 747,
 524         .per_2_per_addr = 6331,
 525         .uartsh_2_mcu_addr = 1032,
 526         .mcu_2_shp_addr = 960,
 527         .app_2_mcu_addr = 683,
 528         .shp_2_mcu_addr = 891,
 529         .spdif_2_mcu_addr = 1100,
 530         .mcu_2_spdif_addr = 1134,
 531 };
 532
 533 static struct sdma_driver_data sdma_imx6q = {
 534         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 535         .num_events = 48,
 536         .script_addrs = &sdma_script_imx6q,
 537 };
 538
 539 static struct sdma_script_start_addrs sdma_script_imx7d = {
 540         .ap_2_ap_addr = 644,
 541         .uart_2_mcu_addr = 819,
 542         .mcu_2_app_addr = 749,
 543         .uartsh_2_mcu_addr = 1034,
 544         .mcu_2_shp_addr = 962,
 545         .app_2_mcu_addr = 685,
 546         .shp_2_mcu_addr = 893,
 547         .spdif_2_mcu_addr = 1102,
 548         .mcu_2_spdif_addr = 1136,
 549 };
 550
 551 static struct sdma_driver_data sdma_imx7d = {
 552         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 553         .num_events = 48,
 554         .script_addrs = &sdma_script_imx7d,
 555 };
 556
 557 static const struct platform_device_id sdma_devtypes[] = {
 558         {
 559                 .name = "imx25-sdma",
 560                 .driver_data = (unsigned long)&sdma_imx25,
 561         }, {
 562                 .name = "imx31-sdma",
 563                 .driver_data = (unsigned long)&sdma_imx31,
 564         }, {
 565                 .name = "imx35-sdma",
 566                 .driver_data = (unsigned long)&sdma_imx35,
 567         }, {
 568                 .name = "imx51-sdma",
 569                 .driver_data = (unsigned long)&sdma_imx51,
 570         }, {
 571                 .name = "imx53-sdma",
 572                 .driver_data = (unsigned long)&sdma_imx53,
 573         }, {
 574                 .name = "imx6q-sdma",
 575                 .driver_data = (unsigned long)&sdma_imx6q,
 576         }, {
 577                 .name = "imx7d-sdma",
 578                 .driver_data = (unsigned long)&sdma_imx7d,
 579         }, {
 580                 /* sentinel */
 581         }
 582 };
 583 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 584
 585 static const struct of_device_id sdma_dt_ids[] = {
 586         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 587         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 588         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 589         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 590         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 591         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 592         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 593         { /* sentinel */ }
 594 };
 595 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 596
 597 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 598 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 599 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 600 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 601
 602 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 603 {
 604         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 605         return chnenbl0 + event * 4;
 606 }
 607
 608 static int sdma_config_ownership(struct sdma_channel *sdmac,
 609                 bool event_override, bool mcu_override, bool dsp_override)
 610 {
 611         struct sdma_engine *sdma = sdmac->sdma;
 612         int channel = sdmac->channel;
 613         unsigned long evt, mcu, dsp;
 614
 615         if (event_override && mcu_override && dsp_override)
 616                 return -EINVAL;
 617
 618         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 619         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 620         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 621
 622         if (dsp_override)
 623                 __clear_bit(channel, &dsp);
 624         else
 625                 __set_bit(channel, &dsp);
 626
 627         if (event_override)
 628                 __clear_bit(channel, &evt);
 629         else
 630                 __set_bit(channel, &evt);
 631
 632         if (mcu_override)
 633                 __clear_bit(channel, &mcu);
 634         else
 635                 __set_bit(channel, &mcu);
 636
 637         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 638         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 639         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 640
 641         return 0;
 642 }
 643
 644 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 645 {
 646         writel(BIT(channel), sdma->regs + SDMA_H_START);
 647 }
 648
 649 /*
 650  * sdma_run_channel0 - run a channel and wait till it's done
 651  */
 652 static int sdma_run_channel0(struct sdma_engine *sdma)
 653 {
 654         int ret;
 655         u32 reg;
 656
 657         sdma_enable_channel(sdma, 0);
 658
 659         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 660                                                 reg, !(reg & 1), 1, 500);
 661         if (ret)
 662                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 663
 664         /* Set bits of CONFIG register with dynamic context switching */
 665         if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
 666                 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
 667
 668         return ret;
 669 }
 670
 671 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 672                 u32 address)
 673 {
 674         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 675         void *buf_virt;
 676         dma_addr_t buf_phys;
 677         int ret;
 678         unsigned long flags;
 679
 680         buf_virt = dma_alloc_coherent(NULL, size, &buf_phys, GFP_KERNEL);
 681         if (!buf_virt) {
 682                 return -ENOMEM;
 683         }
 684
 685         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 686
 687         bd0->mode.command = C0_SETPM;
 688         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 689         bd0->mode.count = size / 2;
 690         bd0->buffer_addr = buf_phys;
 691         bd0->ext_buffer_addr = address;
 692
 693         memcpy(buf_virt, buf, size);
 694
 695         ret = sdma_run_channel0(sdma);
 696
 697         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 698
 699         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 700
 701         return ret;
 702 }
 703
 704 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 705 {
 706         struct sdma_engine *sdma = sdmac->sdma;
 707         int channel = sdmac->channel;
 708         unsigned long val;
 709         u32 chnenbl = chnenbl_ofs(sdma, event);
 710
 711         val = readl_relaxed(sdma->regs + chnenbl);
 712         __set_bit(channel, &val);
 713         writel_relaxed(val, sdma->regs + chnenbl);
 714 }
 715
 716 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 717 {
 718         struct sdma_engine *sdma = sdmac->sdma;
 719         int channel = sdmac->channel;
 720         u32 chnenbl = chnenbl_ofs(sdma, event);
 721         unsigned long val;
 722
 723         val = readl_relaxed(sdma->regs + chnenbl);
 724         __clear_bit(channel, &val);
 725         writel_relaxed(val, sdma->regs + chnenbl);
 726 }
 727
 728 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
 729 {
 730         return container_of(t, struct sdma_desc, vd.tx);
 731 }
 732
 733 static void sdma_start_desc(struct sdma_channel *sdmac)
 734 {
 735         struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
 736         struct sdma_desc *desc;
 737         struct sdma_engine *sdma = sdmac->sdma;
 738         int channel = sdmac->channel;
 739
 740         if (!vd) {
 741                 sdmac->desc = NULL;
 742                 return;
 743         }
 744         sdmac->desc = desc = to_sdma_desc(&vd->tx);
 745         /*
 746          * Do not delete the node in desc_issued list in cyclic mode, otherwise
 747          * the desc allocated will never be freed in vchan_dma_desc_free_list
 748          */
 749         if (!(sdmac->flags & IMX_DMA_SG_LOOP))
 750                 list_del(&vd->node);
 751
 752         sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
 753         sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
 754         sdma_enable_channel(sdma, sdmac->channel);
 755 }
 756
 757 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 758 {
 759         struct sdma_buffer_descriptor *bd;
 760         int error = 0;
 761         enum dma_status old_status = sdmac->status;
 762
 763         /*
 764          * loop mode. Iterate over descriptors, re-setup them and
 765          * call callback function.
 766          */
 767         while (sdmac->desc) {
 768                 struct sdma_desc *desc = sdmac->desc;
 769
 770                 bd = &desc->bd[desc->buf_tail];
 771
 772                 if (bd->mode.status & BD_DONE)
 773                         break;
 774
 775                 if (bd->mode.status & BD_RROR) {
 776                         bd->mode.status &= ~BD_RROR;
 777                         sdmac->status = DMA_ERROR;
 778                         error = -EIO;
 779                 }
 780
 781                /*
 782                 * We use bd->mode.count to calculate the residue, since contains
 783                 * the number of bytes present in the current buffer descriptor.
 784                 */
 785
 786                 desc->chn_real_count = bd->mode.count;
 787                 bd->mode.status |= BD_DONE;
 788                 bd->mode.count = desc->period_len;
 789                 desc->buf_ptail = desc->buf_tail;
 790                 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
 791
 792                 /*
 793                  * The callback is called from the interrupt context in order
 794                  * to reduce latency and to avoid the risk of altering the
 795                  * SDMA transaction status by the time the client tasklet is
 796                  * executed.
 797                  */
 798                 spin_unlock(&sdmac->vc.lock);
 799                 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
 800                 spin_lock(&sdmac->vc.lock);
 801
 802                 if (error)
 803                         sdmac->status = old_status;
 804         }
 805 }
 806
 807 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
 808 {
 809         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 810         struct sdma_buffer_descriptor *bd;
 811         int i, error = 0;
 812
 813         sdmac->desc->chn_real_count = 0;
 814         /*
 815          * non loop mode. Iterate over all descriptors, collect
 816          * errors and call callback function
 817          */
 818         for (i = 0; i < sdmac->desc->num_bd; i++) {
 819                 bd = &sdmac->desc->bd[i];
 820
 821                  if (bd->mode.status & (BD_DONE | BD_RROR))
 822                         error = -EIO;
 823                  sdmac->desc->chn_real_count += bd->mode.count;
 824         }
 825
 826         if (error)
 827                 sdmac->status = DMA_ERROR;
 828         else
 829                 sdmac->status = DMA_COMPLETE;
 830 }
 831
 832 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 833 {
 834         struct sdma_engine *sdma = dev_id;
 835         unsigned long stat;
 836
 837         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 838         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 839         /* channel 0 is special and not handled here, see run_channel0() */
 840         stat &= ~1;
 841
 842         while (stat) {
 843                 int channel = fls(stat) - 1;
 844                 struct sdma_channel *sdmac = &sdma->channel[channel];
 845                 struct sdma_desc *desc;
 846
 847                 spin_lock(&sdmac->vc.lock);
 848                 desc = sdmac->desc;
 849                 if (desc) {
 850                         if (sdmac->flags & IMX_DMA_SG_LOOP) {
 851                                 sdma_update_channel_loop(sdmac);
 852                         } else {
 853                                 mxc_sdma_handle_channel_normal(sdmac);
 854                                 vchan_cookie_complete(&desc->vd);
 855                                 sdma_start_desc(sdmac);
 856                         }
 857                 }
 858
 859                 spin_unlock(&sdmac->vc.lock);
 860                 __clear_bit(channel, &stat);
 861         }
 862
 863         return IRQ_HANDLED;
 864 }
 865
 866 /*
 867  * sets the pc of SDMA script according to the peripheral type
 868  */
 869 static void sdma_get_pc(struct sdma_channel *sdmac,
 870                 enum sdma_peripheral_type peripheral_type)
 871 {
 872         struct sdma_engine *sdma = sdmac->sdma;
 873         int per_2_emi = 0, emi_2_per = 0;
 874         /*
 875          * These are needed once we start to support transfers between
 876          * two peripherals or memory-to-memory transfers
 877          */
 878         int per_2_per = 0, emi_2_emi = 0;
 879
 880         sdmac->pc_from_device = 0;
 881         sdmac->pc_to_device = 0;
 882         sdmac->device_to_device = 0;
 883         sdmac->pc_to_pc = 0;
 884
 885         switch (peripheral_type) {
 886         case IMX_DMATYPE_MEMORY:
 887                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 888                 break;
 889         case IMX_DMATYPE_DSP:
 890                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 891                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 892                 break;
 893         case IMX_DMATYPE_FIRI:
 894                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 895                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 896                 break;
 897         case IMX_DMATYPE_UART:
 898                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 899                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 900                 break;
 901         case IMX_DMATYPE_UART_SP:
 902                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 903                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 904                 break;
 905         case IMX_DMATYPE_ATA:
 906                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 907                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 908                 break;
 909         case IMX_DMATYPE_CSPI:
 910         case IMX_DMATYPE_EXT:
 911         case IMX_DMATYPE_SSI:
 912         case IMX_DMATYPE_SAI:
 913                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 914                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 915                 break;
 916         case IMX_DMATYPE_SSI_DUAL:
 917                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 918                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 919                 break;
 920         case IMX_DMATYPE_SSI_SP:
 921         case IMX_DMATYPE_MMC:
 922         case IMX_DMATYPE_SDHC:
 923         case IMX_DMATYPE_CSPI_SP:
 924         case IMX_DMATYPE_ESAI:
 925         case IMX_DMATYPE_MSHC_SP:
 926                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 927                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 928                 break;
 929         case IMX_DMATYPE_ASRC:
 930                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 931                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 932                 per_2_per = sdma->script_addrs->per_2_per_addr;
 933                 break;
 934         case IMX_DMATYPE_ASRC_SP:
 935                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 936                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 937                 per_2_per = sdma->script_addrs->per_2_per_addr;
 938                 break;
 939         case IMX_DMATYPE_MSHC:
 940                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 941                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 942                 break;
 943         case IMX_DMATYPE_CCM:
 944                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 945                 break;
 946         case IMX_DMATYPE_SPDIF:
 947                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 948                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 949                 break;
 950         case IMX_DMATYPE_IPU_MEMORY:
 951                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 952                 break;
 953         default:
 954                 break;
 955         }
 956
 957         sdmac->pc_from_device = per_2_emi;
 958         sdmac->pc_to_device = emi_2_per;
 959         sdmac->device_to_device = per_2_per;
 960         sdmac->pc_to_pc = emi_2_emi;
 961 }
 962
 963 static int sdma_load_context(struct sdma_channel *sdmac)
 964 {
 965         struct sdma_engine *sdma = sdmac->sdma;
 966         int channel = sdmac->channel;
 967         int load_address;
 968         struct sdma_context_data *context = sdma->context;
 969         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 970         int ret;
 971         unsigned long flags;
 972
 973         if (sdmac->direction == DMA_DEV_TO_MEM)
 974                 load_address = sdmac->pc_from_device;
 975         else if (sdmac->direction == DMA_DEV_TO_DEV)
 976                 load_address = sdmac->device_to_device;
 977         else if (sdmac->direction == DMA_MEM_TO_MEM)
 978                 load_address = sdmac->pc_to_pc;
 979         else
 980                 load_address = sdmac->pc_to_device;
 981
 982         if (load_address < 0)
 983                 return load_address;
 984
 985         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 986         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 987         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 988         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 989         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 990         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 991
 992         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 993
 994         memset(context, 0, sizeof(*context));
 995         context->channel_state.pc = load_address;
 996
 997         /* Send by context the event mask,base address for peripheral
 998          * and watermark level
 999          */
1000         context->gReg[0] = sdmac->event_mask[1];
1001         context->gReg[1] = sdmac->event_mask[0];
1002         context->gReg[2] = sdmac->per_addr;
1003         context->gReg[6] = sdmac->shp_addr;
1004         context->gReg[7] = sdmac->watermark_level;
1005
1006         bd0->mode.command = C0_SETDM;
1007         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
1008         bd0->mode.count = sizeof(*context) / 4;
1009         bd0->buffer_addr = sdma->context_phys;
1010         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1011         ret = sdma_run_channel0(sdma);
1012
1013         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1014
1015         return ret;
1016 }
1017
1018 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1019 {
1020         return container_of(chan, struct sdma_channel, vc.chan);
1021 }
1022
1023 static int sdma_disable_channel(struct dma_chan *chan)
1024 {
1025         struct sdma_channel *sdmac = to_sdma_chan(chan);
1026         struct sdma_engine *sdma = sdmac->sdma;
1027         int channel = sdmac->channel;
1028
1029         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1030         sdmac->status = DMA_ERROR;
1031
1032         return 0;
1033 }
1034 static void sdma_channel_terminate_work(struct work_struct *work)
1035 {
1036         struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1037                                                   terminate_worker);
1038         unsigned long flags;
1039         LIST_HEAD(head);
1040
1041         /*
1042          * According to NXP R&D team a delay of one BD SDMA cost time
1043          * (maximum is 1ms) should be added after disable of the channel
1044          * bit, to ensure SDMA core has really been stopped after SDMA
1045          * clients call .device_terminate_all.
1046          */
1047         usleep_range(1000, 2000);
1048
1049         spin_lock_irqsave(&sdmac->vc.lock, flags);
1050         vchan_get_all_descriptors(&sdmac->vc, &head);
1051         sdmac->desc = NULL;
1052         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1053         vchan_dma_desc_free_list(&sdmac->vc, &head);
1054 }
1055
1056 static int sdma_disable_channel_async(struct dma_chan *chan)
1057 {
1058         struct sdma_channel *sdmac = to_sdma_chan(chan);
1059
1060         sdma_disable_channel(chan);
1061
1062         if (sdmac->desc)
1063                 schedule_work(&sdmac->terminate_worker);
1064
1065         return 0;
1066 }
1067
1068 static void sdma_channel_synchronize(struct dma_chan *chan)
1069 {
1070         struct sdma_channel *sdmac = to_sdma_chan(chan);
1071
1072         vchan_synchronize(&sdmac->vc);
1073
1074         flush_work(&sdmac->terminate_worker);
1075 }
1076
1077 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1078 {
1079         struct sdma_engine *sdma = sdmac->sdma;
1080
1081         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1082         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1083
1084         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1085         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1086
1087         if (sdmac->event_id0 > 31)
1088                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1089
1090         if (sdmac->event_id1 > 31)
1091                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1092
1093         /*
1094          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1095          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1096          * r0(event_mask[1]) and r1(event_mask[0]).
1097          */
1098         if (lwml > hwml) {
1099                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1100                                                 SDMA_WATERMARK_LEVEL_HWML);
1101                 sdmac->watermark_level |= hwml;
1102                 sdmac->watermark_level |= lwml << 16;
1103                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1104         }
1105
1106         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1107                         sdmac->per_address2 <= sdma->spba_end_addr)
1108                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1109
1110         if (sdmac->per_address >= sdma->spba_start_addr &&
1111                         sdmac->per_address <= sdma->spba_end_addr)
1112                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1113
1114         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1115 }
1116
1117 static int sdma_config_channel(struct dma_chan *chan)
1118 {
1119         struct sdma_channel *sdmac = to_sdma_chan(chan);
1120         int ret;
1121
1122         sdma_disable_channel(chan);
1123
1124         sdmac->event_mask[0] = 0;
1125         sdmac->event_mask[1] = 0;
1126         sdmac->shp_addr = 0;
1127         sdmac->per_addr = 0;
1128
1129         switch (sdmac->peripheral_type) {
1130         case IMX_DMATYPE_DSP:
1131                 sdma_config_ownership(sdmac, false, true, true);
1132                 break;
1133         case IMX_DMATYPE_MEMORY:
1134                 sdma_config_ownership(sdmac, false, true, false);
1135                 break;
1136         default:
1137                 sdma_config_ownership(sdmac, true, true, false);
1138                 break;
1139         }
1140
1141         sdma_get_pc(sdmac, sdmac->peripheral_type);
1142
1143         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1144                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1145                 /* Handle multiple event channels differently */
1146                 if (sdmac->event_id1) {
1147                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1148                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1149                                 sdma_set_watermarklevel_for_p2p(sdmac);
1150                 } else
1151                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1152
1153                 /* Address */
1154                 sdmac->shp_addr = sdmac->per_address;
1155                 sdmac->per_addr = sdmac->per_address2;
1156         } else {
1157                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1158         }
1159
1160         ret = sdma_load_context(sdmac);
1161
1162         return ret;
1163 }
1164
1165 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1166                 unsigned int priority)
1167 {
1168         struct sdma_engine *sdma = sdmac->sdma;
1169         int channel = sdmac->channel;
1170
1171         if (priority < MXC_SDMA_MIN_PRIORITY
1172             || priority > MXC_SDMA_MAX_PRIORITY) {
1173                 return -EINVAL;
1174         }
1175
1176         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1177
1178         return 0;
1179 }
1180
1181 static int sdma_request_channel0(struct sdma_engine *sdma)
1182 {
1183         int ret = -EBUSY;
1184
1185         sdma->bd0 = dma_alloc_coherent(NULL, PAGE_SIZE, &sdma->bd0_phys,
1186                                        GFP_NOWAIT);
1187         if (!sdma->bd0) {
1188                 ret = -ENOMEM;
1189                 goto out;
1190         }
1191
1192         sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1193         sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1194
1195         sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1196         return 0;
1197 out:
1198
1199         return ret;
1200 }
1201
1202
1203 static int sdma_alloc_bd(struct sdma_desc *desc)
1204 {
1205         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1206         int ret = 0;
1207
1208         desc->bd = dma_alloc_coherent(NULL, bd_size, &desc->bd_phys,
1209                                       GFP_NOWAIT);
1210         if (!desc->bd) {
1211                 ret = -ENOMEM;
1212                 goto out;
1213         }
1214 out:
1215         return ret;
1216 }
1217
1218 static void sdma_free_bd(struct sdma_desc *desc)
1219 {
1220         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1221
1222         dma_free_coherent(NULL, bd_size, desc->bd, desc->bd_phys);
1223 }
1224
1225 static void sdma_desc_free(struct virt_dma_desc *vd)
1226 {
1227         struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1228
1229         sdma_free_bd(desc);
1230         kfree(desc);
1231 }
1232
1233 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1234 {
1235         struct sdma_channel *sdmac = to_sdma_chan(chan);
1236         struct imx_dma_data *data = chan->private;
1237         struct imx_dma_data mem_data;
1238         int prio, ret;
1239
1240         /*
1241          * MEMCPY may never setup chan->private by filter function such as
1242          * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1243          * Please note in any other slave case, you have to setup chan->private
1244          * with 'struct imx_dma_data' in your own filter function if you want to
1245          * request dma channel by dma_request_channel() rather than
1246          * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1247          * to warn you to correct your filter function.
1248          */
1249         if (!data) {
1250                 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1251                 mem_data.priority = 2;
1252                 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1253                 mem_data.dma_request = 0;
1254                 mem_data.dma_request2 = 0;
1255                 data = &mem_data;
1256
1257                 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1258         }
1259
1260         switch (data->priority) {
1261         case DMA_PRIO_HIGH:
1262                 prio = 3;
1263                 break;
1264         case DMA_PRIO_MEDIUM:
1265                 prio = 2;
1266                 break;
1267         case DMA_PRIO_LOW:
1268         default:
1269                 prio = 1;
1270                 break;
1271         }
1272
1273         sdmac->peripheral_type = data->peripheral_type;
1274         sdmac->event_id0 = data->dma_request;
1275         sdmac->event_id1 = data->dma_request2;
1276
1277         ret = clk_enable(sdmac->sdma->clk_ipg);
1278         if (ret)
1279                 return ret;
1280         ret = clk_enable(sdmac->sdma->clk_ahb);
1281         if (ret)
1282                 goto disable_clk_ipg;
1283
1284         ret = sdma_set_channel_priority(sdmac, prio);
1285         if (ret)
1286                 goto disable_clk_ahb;
1287
1288         return 0;
1289
1290 disable_clk_ahb:
1291         clk_disable(sdmac->sdma->clk_ahb);
1292 disable_clk_ipg:
1293         clk_disable(sdmac->sdma->clk_ipg);
1294         return ret;
1295 }
1296
1297 static void sdma_free_chan_resources(struct dma_chan *chan)
1298 {
1299         struct sdma_channel *sdmac = to_sdma_chan(chan);
1300         struct sdma_engine *sdma = sdmac->sdma;
1301
1302         sdma_disable_channel_async(chan);
1303
1304         sdma_channel_synchronize(chan);
1305
1306         if (sdmac->event_id0)
1307                 sdma_event_disable(sdmac, sdmac->event_id0);
1308         if (sdmac->event_id1)
1309                 sdma_event_disable(sdmac, sdmac->event_id1);
1310
1311         sdmac->event_id0 = 0;
1312         sdmac->event_id1 = 0;
1313
1314         sdma_set_channel_priority(sdmac, 0);
1315
1316         clk_disable(sdma->clk_ipg);
1317         clk_disable(sdma->clk_ahb);
1318 }
1319
1320 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1321                                 enum dma_transfer_direction direction, u32 bds)
1322 {
1323         struct sdma_desc *desc;
1324
1325         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1326         if (!desc)
1327                 goto err_out;
1328
1329         sdmac->status = DMA_IN_PROGRESS;
1330         sdmac->direction = direction;
1331         sdmac->flags = 0;
1332
1333         desc->chn_count = 0;
1334         desc->chn_real_count = 0;
1335         desc->buf_tail = 0;
1336         desc->buf_ptail = 0;
1337         desc->sdmac = sdmac;
1338         desc->num_bd = bds;
1339
1340         if (sdma_alloc_bd(desc))
1341                 goto err_desc_out;
1342
1343         /* No slave_config called in MEMCPY case, so do here */
1344         if (direction == DMA_MEM_TO_MEM)
1345                 sdma_config_ownership(sdmac, false, true, false);
1346
1347         if (sdma_load_context(sdmac))
1348                 goto err_desc_out;
1349
1350         return desc;
1351
1352 err_desc_out:
1353         kfree(desc);
1354 err_out:
1355         return NULL;
1356 }
1357
1358 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1359                 struct dma_chan *chan, dma_addr_t dma_dst,
1360                 dma_addr_t dma_src, size_t len, unsigned long flags)
1361 {
1362         struct sdma_channel *sdmac = to_sdma_chan(chan);
1363         struct sdma_engine *sdma = sdmac->sdma;
1364         int channel = sdmac->channel;
1365         size_t count;
1366         int i = 0, param;
1367         struct sdma_buffer_descriptor *bd;
1368         struct sdma_desc *desc;
1369
1370         if (!chan || !len)
1371                 return NULL;
1372
1373         dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1374                 &dma_src, &dma_dst, len, channel);
1375
1376         desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1377                                         len / SDMA_BD_MAX_CNT + 1);
1378         if (!desc)
1379                 return NULL;
1380
1381         do {
1382                 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1383                 bd = &desc->bd[i];
1384                 bd->buffer_addr = dma_src;
1385                 bd->ext_buffer_addr = dma_dst;
1386                 bd->mode.count = count;
1387                 desc->chn_count += count;
1388                 bd->mode.command = 0;
1389
1390                 dma_src += count;
1391                 dma_dst += count;
1392                 len -= count;
1393                 i++;
1394
1395                 param = BD_DONE | BD_EXTD | BD_CONT;
1396                 /* last bd */
1397                 if (!len) {
1398                         param |= BD_INTR;
1399                         param |= BD_LAST;
1400                         param &= ~BD_CONT;
1401                 }
1402
1403                 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1404                                 i, count, bd->buffer_addr,
1405                                 param & BD_WRAP ? "wrap" : "",
1406                                 param & BD_INTR ? " intr" : "");
1407
1408                 bd->mode.status = param;
1409         } while (len);
1410
1411         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1412 }
1413
1414 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1415                 struct dma_chan *chan, struct scatterlist *sgl,
1416                 unsigned int sg_len, enum dma_transfer_direction direction,
1417                 unsigned long flags, void *context)
1418 {
1419         struct sdma_channel *sdmac = to_sdma_chan(chan);
1420         struct sdma_engine *sdma = sdmac->sdma;
1421         int i, count;
1422         int channel = sdmac->channel;
1423         struct scatterlist *sg;
1424         struct sdma_desc *desc;
1425
1426         sdma_config_write(chan, &sdmac->slave_config, direction);
1427
1428         desc = sdma_transfer_init(sdmac, direction, sg_len);
1429         if (!desc)
1430                 goto err_out;
1431
1432         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1433                         sg_len, channel);
1434
1435         for_each_sg(sgl, sg, sg_len, i) {
1436                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1437                 int param;
1438
1439                 bd->buffer_addr = sg->dma_address;
1440
1441                 count = sg_dma_len(sg);
1442
1443                 if (count > SDMA_BD_MAX_CNT) {
1444                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1445                                         channel, count, SDMA_BD_MAX_CNT);
1446                         goto err_bd_out;
1447                 }
1448
1449                 bd->mode.count = count;
1450                 desc->chn_count += count;
1451
1452                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1453                         goto err_bd_out;
1454
1455                 switch (sdmac->word_size) {
1456                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1457                         bd->mode.command = 0;
1458                         if (count & 3 || sg->dma_address & 3)
1459                                 goto err_bd_out;
1460                         break;
1461                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1462                         bd->mode.command = 2;
1463                         if (count & 1 || sg->dma_address & 1)
1464                                 goto err_bd_out;
1465                         break;
1466                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1467                         bd->mode.command = 1;
1468                         break;
1469                 default:
1470                         goto err_bd_out;
1471                 }
1472
1473                 param = BD_DONE | BD_EXTD | BD_CONT;
1474
1475                 if (i + 1 == sg_len) {
1476                         param |= BD_INTR;
1477                         param |= BD_LAST;
1478                         param &= ~BD_CONT;
1479                 }
1480
1481                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1482                                 i, count, (u64)sg->dma_address,
1483                                 param & BD_WRAP ? "wrap" : "",
1484                                 param & BD_INTR ? " intr" : "");
1485
1486                 bd->mode.status = param;
1487         }
1488
1489         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1490 err_bd_out:
1491         sdma_free_bd(desc);
1492         kfree(desc);
1493 err_out:
1494         sdmac->status = DMA_ERROR;
1495         return NULL;
1496 }
1497
1498 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1499                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1500                 size_t period_len, enum dma_transfer_direction direction,
1501                 unsigned long flags)
1502 {
1503         struct sdma_channel *sdmac = to_sdma_chan(chan);
1504         struct sdma_engine *sdma = sdmac->sdma;
1505         int num_periods = buf_len / period_len;
1506         int channel = sdmac->channel;
1507         int i = 0, buf = 0;
1508         struct sdma_desc *desc;
1509
1510         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1511
1512         sdma_config_write(chan, &sdmac->slave_config, direction);
1513
1514         desc = sdma_transfer_init(sdmac, direction, num_periods);
1515         if (!desc)
1516                 goto err_out;
1517
1518         desc->period_len = period_len;
1519
1520         sdmac->flags |= IMX_DMA_SG_LOOP;
1521
1522         if (period_len > SDMA_BD_MAX_CNT) {
1523                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1524                                 channel, period_len, SDMA_BD_MAX_CNT);
1525                 goto err_bd_out;
1526         }
1527
1528         while (buf < buf_len) {
1529                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1530                 int param;
1531
1532                 bd->buffer_addr = dma_addr;
1533
1534                 bd->mode.count = period_len;
1535
1536                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1537                         goto err_bd_out;
1538                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1539                         bd->mode.command = 0;
1540                 else
1541                         bd->mode.command = sdmac->word_size;
1542
1543                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1544                 if (i + 1 == num_periods)
1545                         param |= BD_WRAP;
1546
1547                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1548                                 i, period_len, (u64)dma_addr,
1549                                 param & BD_WRAP ? "wrap" : "",
1550                                 param & BD_INTR ? " intr" : "");
1551
1552                 bd->mode.status = param;
1553
1554                 dma_addr += period_len;
1555                 buf += period_len;
1556
1557                 i++;
1558         }
1559
1560         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1561 err_bd_out:
1562         sdma_free_bd(desc);
1563         kfree(desc);
1564 err_out:
1565         sdmac->status = DMA_ERROR;
1566         return NULL;
1567 }
1568
1569 static int sdma_config_write(struct dma_chan *chan,
1570                        struct dma_slave_config *dmaengine_cfg,
1571                        enum dma_transfer_direction direction)
1572 {
1573         struct sdma_channel *sdmac = to_sdma_chan(chan);
1574
1575         if (direction == DMA_DEV_TO_MEM) {
1576                 sdmac->per_address = dmaengine_cfg->src_addr;
1577                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1578                         dmaengine_cfg->src_addr_width;
1579                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1580         } else if (direction == DMA_DEV_TO_DEV) {
1581                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1582                 sdmac->per_address = dmaengine_cfg->dst_addr;
1583                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1584                         SDMA_WATERMARK_LEVEL_LWML;
1585                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1586                         SDMA_WATERMARK_LEVEL_HWML;
1587                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1588         } else {
1589                 sdmac->per_address = dmaengine_cfg->dst_addr;
1590                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1591                         dmaengine_cfg->dst_addr_width;
1592                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1593         }
1594         sdmac->direction = direction;
1595         return sdma_config_channel(chan);
1596 }
1597
1598 static int sdma_config(struct dma_chan *chan,
1599                        struct dma_slave_config *dmaengine_cfg)
1600 {
1601         struct sdma_channel *sdmac = to_sdma_chan(chan);
1602
1603         memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1604
1605         /* Set ENBLn earlier to make sure dma request triggered after that */
1606         if (sdmac->event_id0) {
1607                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1608                         return -EINVAL;
1609                 sdma_event_enable(sdmac, sdmac->event_id0);
1610         }
1611
1612         if (sdmac->event_id1) {
1613                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1614                         return -EINVAL;
1615                 sdma_event_enable(sdmac, sdmac->event_id1);
1616         }
1617
1618         return 0;
1619 }
1620
1621 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1622                                       dma_cookie_t cookie,
1623                                       struct dma_tx_state *txstate)
1624 {
1625         struct sdma_channel *sdmac = to_sdma_chan(chan);
1626         struct sdma_desc *desc;
1627         u32 residue;
1628         struct virt_dma_desc *vd;
1629         enum dma_status ret;
1630         unsigned long flags;
1631
1632         ret = dma_cookie_status(chan, cookie, txstate);
1633         if (ret == DMA_COMPLETE || !txstate)
1634                 return ret;
1635
1636         spin_lock_irqsave(&sdmac->vc.lock, flags);
1637         vd = vchan_find_desc(&sdmac->vc, cookie);
1638         if (vd) {
1639                 desc = to_sdma_desc(&vd->tx);
1640                 if (sdmac->flags & IMX_DMA_SG_LOOP)
1641                         residue = (desc->num_bd - desc->buf_ptail) *
1642                                 desc->period_len - desc->chn_real_count;
1643                 else
1644                         residue = desc->chn_count - desc->chn_real_count;
1645         } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1646                 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1647         } else {
1648                 residue = 0;
1649         }
1650         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1651
1652         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1653                          residue);
1654
1655         return sdmac->status;
1656 }
1657
1658 static void sdma_issue_pending(struct dma_chan *chan)
1659 {
1660         struct sdma_channel *sdmac = to_sdma_chan(chan);
1661         unsigned long flags;
1662
1663         spin_lock_irqsave(&sdmac->vc.lock, flags);
1664         if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1665                 sdma_start_desc(sdmac);
1666         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1667 }
1668
1669 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1670 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1671 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1672 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1673
1674 static void sdma_add_scripts(struct sdma_engine *sdma,
1675                 const struct sdma_script_start_addrs *addr)
1676 {
1677         s32 *addr_arr = (u32 *)addr;
1678         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1679         int i;
1680
1681         /* use the default firmware in ROM if missing external firmware */
1682         if (!sdma->script_number)
1683                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1684
1685         for (i = 0; i < sdma->script_number; i++)
1686                 if (addr_arr[i] > 0)
1687                         saddr_arr[i] = addr_arr[i];
1688 }
1689
1690 static void sdma_load_firmware(const struct firmware *fw, void *context)
1691 {
1692         struct sdma_engine *sdma = context;
1693         const struct sdma_firmware_header *header;
1694         const struct sdma_script_start_addrs *addr;
1695         unsigned short *ram_code;
1696
1697         if (!fw) {
1698                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1699                 /* In this case we just use the ROM firmware. */
1700                 return;
1701         }
1702
1703         if (fw->size < sizeof(*header))
1704                 goto err_firmware;
1705
1706         header = (struct sdma_firmware_header *)fw->data;
1707
1708         if (header->magic != SDMA_FIRMWARE_MAGIC)
1709                 goto err_firmware;
1710         if (header->ram_code_start + header->ram_code_size > fw->size)
1711                 goto err_firmware;
1712         switch (header->version_major) {
1713         case 1:
1714                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1715                 break;
1716         case 2:
1717                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1718                 break;
1719         case 3:
1720                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1721                 break;
1722         case 4:
1723                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1724                 break;
1725         default:
1726                 dev_err(sdma->dev, "unknown firmware version\n");
1727                 goto err_firmware;
1728         }
1729
1730         addr = (void *)header + header->script_addrs_start;
1731         ram_code = (void *)header + header->ram_code_start;
1732
1733         clk_enable(sdma->clk_ipg);
1734         clk_enable(sdma->clk_ahb);
1735         /* download the RAM image for SDMA */
1736         sdma_load_script(sdma, ram_code,
1737                         header->ram_code_size,
1738                         addr->ram_code_start_addr);
1739         clk_disable(sdma->clk_ipg);
1740         clk_disable(sdma->clk_ahb);
1741
1742         sdma_add_scripts(sdma, addr);
1743
1744         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1745                         header->version_major,
1746                         header->version_minor);
1747
1748 err_firmware:
1749         release_firmware(fw);
1750 }
1751
1752 #define EVENT_REMAP_CELLS 3
1753
1754 static int sdma_event_remap(struct sdma_engine *sdma)
1755 {
1756         struct device_node *np = sdma->dev->of_node;
1757         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1758         struct property *event_remap;
1759         struct regmap *gpr;
1760         char propname[] = "fsl,sdma-event-remap";
1761         u32 reg, val, shift, num_map, i;
1762         int ret = 0;
1763
1764         if (IS_ERR(np) || IS_ERR(gpr_np))
1765                 goto out;
1766
1767         event_remap = of_find_property(np, propname, NULL);
1768         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1769         if (!num_map) {
1770                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1771                 goto out;
1772         } else if (num_map % EVENT_REMAP_CELLS) {
1773                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1774                                 propname, EVENT_REMAP_CELLS);
1775                 ret = -EINVAL;
1776                 goto out;
1777         }
1778
1779         gpr = syscon_node_to_regmap(gpr_np);
1780         if (IS_ERR(gpr)) {
1781                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1782                 ret = PTR_ERR(gpr);
1783                 goto out;
1784         }
1785
1786         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1787                 ret = of_property_read_u32_index(np, propname, i, &reg);
1788                 if (ret) {
1789                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1790                                         propname, i);
1791                         goto out;
1792                 }
1793
1794                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1795                 if (ret) {
1796                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1797                                         propname, i + 1);
1798                         goto out;
1799                 }
1800
1801                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1802                 if (ret) {
1803                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1804                                         propname, i + 2);
1805                         goto out;
1806                 }
1807
1808                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1809         }
1810
1811 out:
1812         if (!IS_ERR(gpr_np))
1813                 of_node_put(gpr_np);
1814
1815         return ret;
1816 }
1817
1818 static int sdma_get_firmware(struct sdma_engine *sdma,
1819                 const char *fw_name)
1820 {
1821         int ret;
1822
1823         ret = request_firmware_nowait(THIS_MODULE,
1824                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1825                         GFP_KERNEL, sdma, sdma_load_firmware);
1826
1827         return ret;
1828 }
1829
1830 static int sdma_init(struct sdma_engine *sdma)
1831 {
1832         int i, ret;
1833         dma_addr_t ccb_phys;
1834
1835         ret = clk_enable(sdma->clk_ipg);
1836         if (ret)
1837                 return ret;
1838         ret = clk_enable(sdma->clk_ahb);
1839         if (ret)
1840                 goto disable_clk_ipg;
1841
1842         /* Be sure SDMA has not started yet */
1843         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1844
1845         sdma->channel_control = dma_alloc_coherent(NULL,
1846                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1847                         sizeof(struct sdma_context_data),
1848                         &ccb_phys, GFP_KERNEL);
1849
1850         if (!sdma->channel_control) {
1851                 ret = -ENOMEM;
1852                 goto err_dma_alloc;
1853         }
1854
1855         sdma->context = (void *)sdma->channel_control +
1856                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1857         sdma->context_phys = ccb_phys +
1858                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1859
1860         /* Zero-out the CCB structures array just allocated */
1861         memset(sdma->channel_control, 0,
1862                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1863
1864         /* disable all channels */
1865         for (i = 0; i < sdma->drvdata->num_events; i++)
1866                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1867
1868         /* All channels have priority 0 */
1869         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1870                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1871
1872         ret = sdma_request_channel0(sdma);
1873         if (ret)
1874                 goto err_dma_alloc;
1875
1876         sdma_config_ownership(&sdma->channel[0], false, true, false);
1877
1878         /* Set Command Channel (Channel Zero) */
1879         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1880
1881         /* Set bits of CONFIG register but with static context switching */
1882         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1883         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1884
1885         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1886
1887         /* Initializes channel's priorities */
1888         sdma_set_channel_priority(&sdma->channel[0], 7);
1889
1890         clk_disable(sdma->clk_ipg);
1891         clk_disable(sdma->clk_ahb);
1892
1893         return 0;
1894
1895 err_dma_alloc:
1896         clk_disable(sdma->clk_ahb);
1897 disable_clk_ipg:
1898         clk_disable(sdma->clk_ipg);
1899         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1900         return ret;
1901 }
1902
1903 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1904 {
1905         struct sdma_channel *sdmac = to_sdma_chan(chan);
1906         struct imx_dma_data *data = fn_param;
1907
1908         if (!imx_dma_is_general_purpose(chan))
1909                 return false;
1910
1911         sdmac->data = *data;
1912         chan->private = &sdmac->data;
1913
1914         return true;
1915 }
1916
1917 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1918                                    struct of_dma *ofdma)
1919 {
1920         struct sdma_engine *sdma = ofdma->of_dma_data;
1921         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1922         struct imx_dma_data data;
1923
1924         if (dma_spec->args_count != 3)
1925                 return NULL;
1926
1927         data.dma_request = dma_spec->args[0];
1928         data.peripheral_type = dma_spec->args[1];
1929         data.priority = dma_spec->args[2];
1930         /*
1931          * init dma_request2 to zero, which is not used by the dts.
1932          * For P2P, dma_request2 is init from dma_request_channel(),
1933          * chan->private will point to the imx_dma_data, and in
1934          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1935          * be set to sdmac->event_id1.
1936          */
1937         data.dma_request2 = 0;
1938
1939         return dma_request_channel(mask, sdma_filter_fn, &data);
1940 }
1941
1942 static int sdma_probe(struct platform_device *pdev)
1943 {
1944         const struct of_device_id *of_id =
1945                         of_match_device(sdma_dt_ids, &pdev->dev);
1946         struct device_node *np = pdev->dev.of_node;
1947         struct device_node *spba_bus;
1948         const char *fw_name;
1949         int ret;
1950         int irq;
1951         struct resource *iores;
1952         struct resource spba_res;
1953         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1954         int i;
1955         struct sdma_engine *sdma;
1956         s32 *saddr_arr;
1957         const struct sdma_driver_data *drvdata = NULL;
1958
1959         if (of_id)
1960                 drvdata = of_id->data;
1961         else if (pdev->id_entry)
1962                 drvdata = (void *)pdev->id_entry->driver_data;
1963
1964         if (!drvdata) {
1965                 dev_err(&pdev->dev, "unable to find driver data\n");
1966                 return -EINVAL;
1967         }
1968
1969         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1970         if (ret)
1971                 return ret;
1972
1973         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1974         if (!sdma)
1975                 return -ENOMEM;
1976
1977         spin_lock_init(&sdma->channel_0_lock);
1978
1979         sdma->dev = &pdev->dev;
1980         sdma->drvdata = drvdata;
1981
1982         irq = platform_get_irq(pdev, 0);
1983         if (irq < 0)
1984                 return irq;
1985
1986         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1987         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1988         if (IS_ERR(sdma->regs))
1989                 return PTR_ERR(sdma->regs);
1990
1991         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1992         if (IS_ERR(sdma->clk_ipg))
1993                 return PTR_ERR(sdma->clk_ipg);
1994
1995         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1996         if (IS_ERR(sdma->clk_ahb))
1997                 return PTR_ERR(sdma->clk_ahb);
1998
1999         ret = clk_prepare(sdma->clk_ipg);
2000         if (ret)
2001                 return ret;
2002
2003         ret = clk_prepare(sdma->clk_ahb);
2004         if (ret)
2005                 goto err_clk;
2006
2007         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2008                                sdma);
2009         if (ret)
2010                 goto err_irq;
2011
2012         sdma->irq = irq;
2013
2014         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2015         if (!sdma->script_addrs) {
2016                 ret = -ENOMEM;
2017                 goto err_irq;
2018         }
2019
2020         /* initially no scripts available */
2021         saddr_arr = (s32 *)sdma->script_addrs;
2022         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
2023                 saddr_arr[i] = -EINVAL;
2024
2025         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2026         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2027         dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2028
2029         INIT_LIST_HEAD(&sdma->dma_device.channels);
2030         /* Initialize channel parameters */
2031         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2032                 struct sdma_channel *sdmac = &sdma->channel[i];
2033
2034                 sdmac->sdma = sdma;
2035
2036                 sdmac->channel = i;
2037                 sdmac->vc.desc_free = sdma_desc_free;
2038                 INIT_WORK(&sdmac->terminate_worker,
2039                                 sdma_channel_terminate_work);
2040                 /*
2041                  * Add the channel to the DMAC list. Do not add channel 0 though
2042                  * because we need it internally in the SDMA driver. This also means
2043                  * that channel 0 in dmaengine counting matches sdma channel 1.
2044                  */
2045                 if (i)
2046                         vchan_init(&sdmac->vc, &sdma->dma_device);
2047         }
2048
2049         ret = sdma_init(sdma);
2050         if (ret)
2051                 goto err_init;
2052
2053         ret = sdma_event_remap(sdma);
2054         if (ret)
2055                 goto err_init;
2056
2057         if (sdma->drvdata->script_addrs)
2058                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2059         if (pdata && pdata->script_addrs)
2060                 sdma_add_scripts(sdma, pdata->script_addrs);
2061
2062         if (pdata) {
2063                 ret = sdma_get_firmware(sdma, pdata->fw_name);
2064                 if (ret)
2065                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2066         } else {
2067                 /*
2068                  * Because that device tree does not encode ROM script address,
2069                  * the RAM script in firmware is mandatory for device tree
2070                  * probe, otherwise it fails.
2071                  */
2072                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2073                                               &fw_name);
2074                 if (ret)
2075                         dev_warn(&pdev->dev, "failed to get firmware name\n");
2076                 else {
2077                         ret = sdma_get_firmware(sdma, fw_name);
2078                         if (ret)
2079                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2080                 }
2081         }
2082
2083         sdma->dma_device.dev = &pdev->dev;
2084
2085         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2086         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2087         sdma->dma_device.device_tx_status = sdma_tx_status;
2088         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2089         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2090         sdma->dma_device.device_config = sdma_config;
2091         sdma->dma_device.device_terminate_all = sdma_disable_channel_async;
2092         sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2093         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2094         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2095         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2096         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2097         sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2098         sdma->dma_device.device_issue_pending = sdma_issue_pending;
2099         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
2100         dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2101
2102         platform_set_drvdata(pdev, sdma);
2103
2104         ret = dma_async_device_register(&sdma->dma_device);
2105         if (ret) {
2106                 dev_err(&pdev->dev, "unable to register\n");
2107                 goto err_init;
2108         }
2109
2110         if (np) {
2111                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2112                 if (ret) {
2113                         dev_err(&pdev->dev, "failed to register controller\n");
2114                         goto err_register;
2115                 }
2116
2117                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2118                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2119                 if (!ret) {
2120                         sdma->spba_start_addr = spba_res.start;
2121                         sdma->spba_end_addr = spba_res.end;
2122                 }
2123                 of_node_put(spba_bus);
2124         }
2125
2126         return 0;
2127
2128 err_register:
2129         dma_async_device_unregister(&sdma->dma_device);
2130 err_init:
2131         kfree(sdma->script_addrs);
2132 err_irq:
2133         clk_unprepare(sdma->clk_ahb);
2134 err_clk:
2135         clk_unprepare(sdma->clk_ipg);
2136         return ret;
2137 }
2138
2139 static int sdma_remove(struct platform_device *pdev)
2140 {
2141         struct sdma_engine *sdma = platform_get_drvdata(pdev);
2142         int i;
2143
2144         devm_free_irq(&pdev->dev, sdma->irq, sdma);
2145         dma_async_device_unregister(&sdma->dma_device);
2146         kfree(sdma->script_addrs);
2147         clk_unprepare(sdma->clk_ahb);
2148         clk_unprepare(sdma->clk_ipg);
2149         /* Kill the tasklet */
2150         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2151                 struct sdma_channel *sdmac = &sdma->channel[i];
2152
2153                 tasklet_kill(&sdmac->vc.task);
2154                 sdma_free_chan_resources(&sdmac->vc.chan);
2155         }
2156
2157         platform_set_drvdata(pdev, NULL);
2158         return 0;
2159 }
2160
2161 static struct platform_driver sdma_driver = {
2162         .driver         = {
2163                 .name   = "imx-sdma",
2164                 .of_match_table = sdma_dt_ids,
2165         },
2166         .id_table       = sdma_devtypes,
2167         .remove         = sdma_remove,
2168         .probe          = sdma_probe,
2169 };
2170
2171 module_platform_driver(sdma_driver);
2172
2173 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2174 MODULE_DESCRIPTION("i.MX SDMA driver");
2175 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2176 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2177 #endif
2178 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2179 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2180 #endif
2181 MODULE_LICENSE("GPL");