drivers/dma/dma-jz4740.c

   1 /*
   2  *  Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
   3  *  JZ4740 DMAC support
   4  *
   5  *  This program is free software; you can redistribute it and/or modify it
   6  *  under  the terms of the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the GNU General Public License along
  11  *  with this program; if not, write to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/list.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/irq.h>
  26 #include <linux/clk.h>
  27
  28 #include <asm/mach-jz4740/dma.h>
  29
  30 #include "virt-dma.h"
  31
  32 #define JZ_DMA_NR_CHANS 6
  33
  34 #define JZ_REG_DMA_SRC_ADDR(x)          (0x00 + (x) * 0x20)
  35 #define JZ_REG_DMA_DST_ADDR(x)          (0x04 + (x) * 0x20)
  36 #define JZ_REG_DMA_TRANSFER_COUNT(x)    (0x08 + (x) * 0x20)
  37 #define JZ_REG_DMA_REQ_TYPE(x)          (0x0C + (x) * 0x20)
  38 #define JZ_REG_DMA_STATUS_CTRL(x)       (0x10 + (x) * 0x20)
  39 #define JZ_REG_DMA_CMD(x)               (0x14 + (x) * 0x20)
  40 #define JZ_REG_DMA_DESC_ADDR(x)         (0x18 + (x) * 0x20)
  41
  42 #define JZ_REG_DMA_CTRL                 0x300
  43 #define JZ_REG_DMA_IRQ                  0x304
  44 #define JZ_REG_DMA_DOORBELL             0x308
  45 #define JZ_REG_DMA_DOORBELL_SET         0x30C
  46
  47 #define JZ_DMA_STATUS_CTRL_NO_DESC              BIT(31)
  48 #define JZ_DMA_STATUS_CTRL_DESC_INV             BIT(6)
  49 #define JZ_DMA_STATUS_CTRL_ADDR_ERR             BIT(4)
  50 #define JZ_DMA_STATUS_CTRL_TRANSFER_DONE        BIT(3)
  51 #define JZ_DMA_STATUS_CTRL_HALT                 BIT(2)
  52 #define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE      BIT(1)
  53 #define JZ_DMA_STATUS_CTRL_ENABLE               BIT(0)
  54
  55 #define JZ_DMA_CMD_SRC_INC                      BIT(23)
  56 #define JZ_DMA_CMD_DST_INC                      BIT(22)
  57 #define JZ_DMA_CMD_RDIL_MASK                    (0xf << 16)
  58 #define JZ_DMA_CMD_SRC_WIDTH_MASK               (0x3 << 14)
  59 #define JZ_DMA_CMD_DST_WIDTH_MASK               (0x3 << 12)
  60 #define JZ_DMA_CMD_INTERVAL_LENGTH_MASK         (0x7 << 8)
  61 #define JZ_DMA_CMD_BLOCK_MODE                   BIT(7)
  62 #define JZ_DMA_CMD_DESC_VALID                   BIT(4)
  63 #define JZ_DMA_CMD_DESC_VALID_MODE              BIT(3)
  64 #define JZ_DMA_CMD_VALID_IRQ_ENABLE             BIT(2)
  65 #define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE          BIT(1)
  66 #define JZ_DMA_CMD_LINK_ENABLE                  BIT(0)
  67
  68 #define JZ_DMA_CMD_FLAGS_OFFSET 22
  69 #define JZ_DMA_CMD_RDIL_OFFSET 16
  70 #define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
  71 #define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
  72 #define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
  73 #define JZ_DMA_CMD_MODE_OFFSET 7
  74
  75 #define JZ_DMA_CTRL_PRIORITY_MASK               (0x3 << 8)
  76 #define JZ_DMA_CTRL_HALT                        BIT(3)
  77 #define JZ_DMA_CTRL_ADDRESS_ERROR               BIT(2)
  78 #define JZ_DMA_CTRL_ENABLE                      BIT(0)
  79
  80 enum jz4740_dma_width {
  81         JZ4740_DMA_WIDTH_32BIT  = 0,
  82         JZ4740_DMA_WIDTH_8BIT   = 1,
  83         JZ4740_DMA_WIDTH_16BIT  = 2,
  84 };
  85
  86 enum jz4740_dma_transfer_size {
  87         JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
  88         JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
  89         JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
  90         JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
  91         JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
  92 };
  93
  94 enum jz4740_dma_flags {
  95         JZ4740_DMA_SRC_AUTOINC = 0x2,
  96         JZ4740_DMA_DST_AUTOINC = 0x1,
  97 };
  98
  99 enum jz4740_dma_mode {
 100         JZ4740_DMA_MODE_SINGLE  = 0,
 101         JZ4740_DMA_MODE_BLOCK   = 1,
 102 };
 103
 104 struct jz4740_dma_sg {
 105         dma_addr_t addr;
 106         unsigned int len;
 107 };
 108
 109 struct jz4740_dma_desc {
 110         struct virt_dma_desc vdesc;
 111
 112         enum dma_transfer_direction direction;
 113         bool cyclic;
 114
 115         unsigned int num_sgs;
 116         struct jz4740_dma_sg sg[];
 117 };
 118
 119 struct jz4740_dmaengine_chan {
 120         struct virt_dma_chan vchan;
 121         unsigned int id;
 122
 123         dma_addr_t fifo_addr;
 124         unsigned int transfer_shift;
 125
 126         struct jz4740_dma_desc *desc;
 127         unsigned int next_sg;
 128 };
 129
 130 struct jz4740_dma_dev {
 131         struct dma_device ddev;
 132         void __iomem *base;
 133         struct clk *clk;
 134
 135         struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
 136 };
 137
 138 static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
 139         struct jz4740_dmaengine_chan *chan)
 140 {
 141         return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
 142                 ddev);
 143 }
 144
 145 static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
 146 {
 147         return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
 148 }
 149
 150 static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
 151 {
 152         return container_of(vdesc, struct jz4740_dma_desc, vdesc);
 153 }
 154
 155 static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
 156         unsigned int reg)
 157 {
 158         return readl(dmadev->base + reg);
 159 }
 160
 161 static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
 162         unsigned reg, uint32_t val)
 163 {
 164         writel(val, dmadev->base + reg);
 165 }
 166
 167 static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
 168         unsigned int reg, uint32_t val, uint32_t mask)
 169 {
 170         uint32_t tmp;
 171
 172         tmp = jz4740_dma_read(dmadev, reg);
 173         tmp &= ~mask;
 174         tmp |= val;
 175         jz4740_dma_write(dmadev, reg, tmp);
 176 }
 177
 178 static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
 179 {
 180         return kzalloc(sizeof(struct jz4740_dma_desc) +
 181                 sizeof(struct jz4740_dma_sg) * num_sgs, GFP_ATOMIC);
 182 }
 183
 184 static enum jz4740_dma_width jz4740_dma_width(enum dma_slave_buswidth width)
 185 {
 186         switch (width) {
 187         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 188                 return JZ4740_DMA_WIDTH_8BIT;
 189         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 190                 return JZ4740_DMA_WIDTH_16BIT;
 191         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 192                 return JZ4740_DMA_WIDTH_32BIT;
 193         default:
 194                 return JZ4740_DMA_WIDTH_32BIT;
 195         }
 196 }
 197
 198 static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
 199 {
 200         if (maxburst <= 1)
 201                 return JZ4740_DMA_TRANSFER_SIZE_1BYTE;
 202         else if (maxburst <= 3)
 203                 return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
 204         else if (maxburst <= 15)
 205                 return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
 206         else if (maxburst <= 31)
 207                 return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
 208
 209         return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
 210 }
 211
 212 static int jz4740_dma_slave_config(struct dma_chan *c,
 213                                    struct dma_slave_config *config)
 214 {
 215         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
 216         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
 217         enum jz4740_dma_width src_width;
 218         enum jz4740_dma_width dst_width;
 219         enum jz4740_dma_transfer_size transfer_size;
 220         enum jz4740_dma_flags flags;
 221         uint32_t cmd;
 222
 223         switch (config->direction) {
 224         case DMA_MEM_TO_DEV:
 225                 flags = JZ4740_DMA_SRC_AUTOINC;
 226                 transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
 227                 chan->fifo_addr = config->dst_addr;
 228                 break;
 229         case DMA_DEV_TO_MEM:
 230                 flags = JZ4740_DMA_DST_AUTOINC;
 231                 transfer_size = jz4740_dma_maxburst(config->src_maxburst);
 232                 chan->fifo_addr = config->src_addr;
 233                 break;
 234         default:
 235                 return -EINVAL;
 236         }
 237
 238         src_width = jz4740_dma_width(config->src_addr_width);
 239         dst_width = jz4740_dma_width(config->dst_addr_width);
 240
 241         switch (transfer_size) {
 242         case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
 243                 chan->transfer_shift = 1;
 244                 break;
 245         case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
 246                 chan->transfer_shift = 2;
 247                 break;
 248         case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
 249                 chan->transfer_shift = 4;
 250                 break;
 251         case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
 252                 chan->transfer_shift = 5;
 253                 break;
 254         default:
 255                 chan->transfer_shift = 0;
 256                 break;
 257         }
 258
 259         cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
 260         cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
 261         cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
 262         cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
 263         cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
 264         cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
 265
 266         jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
 267         jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
 268         jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
 269                 config->slave_id);
 270
 271         return 0;
 272 }
 273
 274 static int jz4740_dma_terminate_all(struct dma_chan *c)
 275 {
 276         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
 277         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
 278         unsigned long flags;
 279         LIST_HEAD(head);
 280
 281         spin_lock_irqsave(&chan->vchan.lock, flags);
 282         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
 283                         JZ_DMA_STATUS_CTRL_ENABLE);
 284         chan->desc = NULL;
 285         vchan_get_all_descriptors(&chan->vchan, &head);
 286         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 287
 288         vchan_dma_desc_free_list(&chan->vchan, &head);
 289
 290         return 0;
 291 }
 292
 293 static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
 294 {
 295         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
 296         dma_addr_t src_addr, dst_addr;
 297         struct virt_dma_desc *vdesc;
 298         struct jz4740_dma_sg *sg;
 299
 300         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0,
 301                         JZ_DMA_STATUS_CTRL_ENABLE);
 302
 303         if (!chan->desc) {
 304                 vdesc = vchan_next_desc(&chan->vchan);
 305                 if (!vdesc)
 306                         return 0;
 307                 chan->desc = to_jz4740_dma_desc(vdesc);
 308                 chan->next_sg = 0;
 309         }
 310
 311         if (chan->next_sg == chan->desc->num_sgs)
 312                 chan->next_sg = 0;
 313
 314         sg = &chan->desc->sg[chan->next_sg];
 315
 316         if (chan->desc->direction == DMA_MEM_TO_DEV) {
 317                 src_addr = sg->addr;
 318                 dst_addr = chan->fifo_addr;
 319         } else {
 320                 src_addr = chan->fifo_addr;
 321                 dst_addr = sg->addr;
 322         }
 323         jz4740_dma_write(dmadev, JZ_REG_DMA_SRC_ADDR(chan->id), src_addr);
 324         jz4740_dma_write(dmadev, JZ_REG_DMA_DST_ADDR(chan->id), dst_addr);
 325         jz4740_dma_write(dmadev, JZ_REG_DMA_TRANSFER_COUNT(chan->id),
 326                         sg->len >> chan->transfer_shift);
 327
 328         chan->next_sg++;
 329
 330         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id),
 331                         JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
 332                         JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
 333                         JZ_DMA_STATUS_CTRL_ENABLE);
 334
 335         jz4740_dma_write_mask(dmadev, JZ_REG_DMA_CTRL,
 336                         JZ_DMA_CTRL_ENABLE,
 337                         JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
 338
 339         return 0;
 340 }
 341
 342 static void jz4740_dma_chan_irq(struct jz4740_dmaengine_chan *chan)
 343 {
 344         spin_lock(&chan->vchan.lock);
 345         if (chan->desc) {
 346                 if (chan->desc && chan->desc->cyclic) {
 347                         vchan_cyclic_callback(&chan->desc->vdesc);
 348                 } else {
 349                         if (chan->next_sg == chan->desc->num_sgs) {
 350                                 list_del(&chan->desc->vdesc.node);
 351                                 vchan_cookie_complete(&chan->desc->vdesc);
 352                                 chan->desc = NULL;
 353                         }
 354                 }
 355         }
 356         jz4740_dma_start_transfer(chan);
 357         spin_unlock(&chan->vchan.lock);
 358 }
 359
 360 static irqreturn_t jz4740_dma_irq(int irq, void *devid)
 361 {
 362         struct jz4740_dma_dev *dmadev = devid;
 363         uint32_t irq_status;
 364         unsigned int i;
 365
 366         irq_status = readl(dmadev->base + JZ_REG_DMA_IRQ);
 367
 368         for (i = 0; i < 6; ++i) {
 369                 if (irq_status & (1 << i)) {
 370                         jz4740_dma_write_mask(dmadev,
 371                                 JZ_REG_DMA_STATUS_CTRL(i), 0,
 372                                 JZ_DMA_STATUS_CTRL_ENABLE |
 373                                 JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
 374
 375                         jz4740_dma_chan_irq(&dmadev->chan[i]);
 376                 }
 377         }
 378
 379         return IRQ_HANDLED;
 380 }
 381
 382 static void jz4740_dma_issue_pending(struct dma_chan *c)
 383 {
 384         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
 385         unsigned long flags;
 386
 387         spin_lock_irqsave(&chan->vchan.lock, flags);
 388         if (vchan_issue_pending(&chan->vchan) && !chan->desc)
 389                 jz4740_dma_start_transfer(chan);
 390         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 391 }
 392
 393 static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg(
 394         struct dma_chan *c, struct scatterlist *sgl,
 395         unsigned int sg_len, enum dma_transfer_direction direction,
 396         unsigned long flags, void *context)
 397 {
 398         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
 399         struct jz4740_dma_desc *desc;
 400         struct scatterlist *sg;
 401         unsigned int i;
 402
 403         desc = jz4740_dma_alloc_desc(sg_len);
 404         if (!desc)
 405                 return NULL;
 406
 407         for_each_sg(sgl, sg, sg_len, i) {
 408                 desc->sg[i].addr = sg_dma_address(sg);
 409                 desc->sg[i].len = sg_dma_len(sg);
 410         }
 411
 412         desc->num_sgs = sg_len;
 413         desc->direction = direction;
 414         desc->cyclic = false;
 415
 416         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 417 }
 418
 419 static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
 420         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 421         size_t period_len, enum dma_transfer_direction direction,
 422         unsigned long flags)
 423 {
 424         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
 425         struct jz4740_dma_desc *desc;
 426         unsigned int num_periods, i;
 427
 428         if (buf_len % period_len)
 429                 return NULL;
 430
 431         num_periods = buf_len / period_len;
 432
 433         desc = jz4740_dma_alloc_desc(num_periods);
 434         if (!desc)
 435                 return NULL;
 436
 437         for (i = 0; i < num_periods; i++) {
 438                 desc->sg[i].addr = buf_addr;
 439                 desc->sg[i].len = period_len;
 440                 buf_addr += period_len;
 441         }
 442
 443         desc->num_sgs = num_periods;
 444         desc->direction = direction;
 445         desc->cyclic = true;
 446
 447         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 448 }
 449
 450 static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
 451         struct jz4740_dma_desc *desc, unsigned int next_sg)
 452 {
 453         struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
 454         unsigned int residue, count;
 455         unsigned int i;
 456
 457         residue = 0;
 458
 459         for (i = next_sg; i < desc->num_sgs; i++)
 460                 residue += desc->sg[i].len;
 461
 462         if (next_sg != 0) {
 463                 count = jz4740_dma_read(dmadev,
 464                         JZ_REG_DMA_TRANSFER_COUNT(chan->id));
 465                 residue += count << chan->transfer_shift;
 466         }
 467
 468         return residue;
 469 }
 470
 471 static enum dma_status jz4740_dma_tx_status(struct dma_chan *c,
 472         dma_cookie_t cookie, struct dma_tx_state *state)
 473 {
 474         struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
 475         struct virt_dma_desc *vdesc;
 476         enum dma_status status;
 477         unsigned long flags;
 478
 479         status = dma_cookie_status(c, cookie, state);
 480         if (status == DMA_COMPLETE || !state)
 481                 return status;
 482
 483         spin_lock_irqsave(&chan->vchan.lock, flags);
 484         vdesc = vchan_find_desc(&chan->vchan, cookie);
 485         if (cookie == chan->desc->vdesc.tx.cookie) {
 486                 state->residue = jz4740_dma_desc_residue(chan, chan->desc,
 487                                 chan->next_sg);
 488         } else if (vdesc) {
 489                 state->residue = jz4740_dma_desc_residue(chan,
 490                                 to_jz4740_dma_desc(vdesc), 0);
 491         } else {
 492                 state->residue = 0;
 493         }
 494         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 495
 496         return status;
 497 }
 498
 499 static int jz4740_dma_alloc_chan_resources(struct dma_chan *c)
 500 {
 501         return 0;
 502 }
 503
 504 static void jz4740_dma_free_chan_resources(struct dma_chan *c)
 505 {
 506         vchan_free_chan_resources(to_virt_chan(c));
 507 }
 508
 509 static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
 510 {
 511         kfree(container_of(vdesc, struct jz4740_dma_desc, vdesc));
 512 }
 513
 514 #define JZ4740_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 515         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 516
 517 static int jz4740_dma_probe(struct platform_device *pdev)
 518 {
 519         struct jz4740_dmaengine_chan *chan;
 520         struct jz4740_dma_dev *dmadev;
 521         struct dma_device *dd;
 522         unsigned int i;
 523         struct resource *res;
 524         int ret;
 525         int irq;
 526
 527         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
 528         if (!dmadev)
 529                 return -EINVAL;
 530
 531         dd = &dmadev->ddev;
 532
 533         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 534         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
 535         if (IS_ERR(dmadev->base))
 536                 return PTR_ERR(dmadev->base);
 537
 538         dmadev->clk = clk_get(&pdev->dev, "dma");
 539         if (IS_ERR(dmadev->clk))
 540                 return PTR_ERR(dmadev->clk);
 541
 542         clk_prepare_enable(dmadev->clk);
 543
 544         dma_cap_set(DMA_SLAVE, dd->cap_mask);
 545         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
 546         dd->device_alloc_chan_resources = jz4740_dma_alloc_chan_resources;
 547         dd->device_free_chan_resources = jz4740_dma_free_chan_resources;
 548         dd->device_tx_status = jz4740_dma_tx_status;
 549         dd->device_issue_pending = jz4740_dma_issue_pending;
 550         dd->device_prep_slave_sg = jz4740_dma_prep_slave_sg;
 551         dd->device_prep_dma_cyclic = jz4740_dma_prep_dma_cyclic;
 552         dd->device_config = jz4740_dma_slave_config;
 553         dd->device_terminate_all = jz4740_dma_terminate_all;
 554         dd->src_addr_widths = JZ4740_DMA_BUSWIDTHS;
 555         dd->dst_addr_widths = JZ4740_DMA_BUSWIDTHS;
 556         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 557         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
 558         dd->dev = &pdev->dev;
 559         INIT_LIST_HEAD(&dd->channels);
 560
 561         for (i = 0; i < JZ_DMA_NR_CHANS; i++) {
 562                 chan = &dmadev->chan[i];
 563                 chan->id = i;
 564                 chan->vchan.desc_free = jz4740_dma_desc_free;
 565                 vchan_init(&chan->vchan, dd);
 566         }
 567
 568         ret = dma_async_device_register(dd);
 569         if (ret)
 570                 return ret;
 571
 572         irq = platform_get_irq(pdev, 0);
 573         ret = request_irq(irq, jz4740_dma_irq, 0, dev_name(&pdev->dev), dmadev);
 574         if (ret)
 575                 goto err_unregister;
 576
 577         platform_set_drvdata(pdev, dmadev);
 578
 579         return 0;
 580
 581 err_unregister:
 582         dma_async_device_unregister(dd);
 583         return ret;
 584 }
 585
 586 static int jz4740_dma_remove(struct platform_device *pdev)
 587 {
 588         struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
 589         int irq = platform_get_irq(pdev, 0);
 590
 591         free_irq(irq, dmadev);
 592         dma_async_device_unregister(&dmadev->ddev);
 593         clk_disable_unprepare(dmadev->clk);
 594
 595         return 0;
 596 }
 597
 598 static struct platform_driver jz4740_dma_driver = {
 599         .probe = jz4740_dma_probe,
 600         .remove = jz4740_dma_remove,
 601         .driver = {
 602                 .name = "jz4740-dma",
 603         },
 604 };
 605 module_platform_driver(jz4740_dma_driver);
 606
 607 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 608 MODULE_DESCRIPTION("JZ4740 DMA driver");
 609 MODULE_LICENSE("GPL v2");