drivers/dma/cppi41.c

   1 #include <linux/delay.h>
   2 #include <linux/dmaengine.h>
   3 #include <linux/dma-mapping.h>
   4 #include <linux/platform_device.h>
   5 #include <linux/module.h>
   6 #include <linux/of.h>
   7 #include <linux/slab.h>
   8 #include <linux/of_dma.h>
   9 #include <linux/of_irq.h>
  10 #include <linux/dmapool.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/of_address.h>
  13 #include <linux/pm_runtime.h>
  14 #include "dmaengine.h"
  15
  16 #define DESC_TYPE       27
  17 #define DESC_TYPE_HOST  0x10
  18 #define DESC_TYPE_TEARD 0x13
  19
  20 #define TD_DESC_IS_RX   (1 << 16)
  21 #define TD_DESC_DMA_NUM 10
  22
  23 #define DESC_LENGTH_BITS_NUM    21
  24
  25 #define DESC_TYPE_USB   (5 << 26)
  26 #define DESC_PD_COMPLETE        (1 << 31)
  27
  28 /* DMA engine */
  29 #define DMA_TDFDQ       4
  30 #define DMA_TXGCR(x)    (0x800 + (x) * 0x20)
  31 #define DMA_RXGCR(x)    (0x808 + (x) * 0x20)
  32 #define RXHPCRA0                4
  33
  34 #define GCR_CHAN_ENABLE         (1 << 31)
  35 #define GCR_TEARDOWN            (1 << 30)
  36 #define GCR_STARV_RETRY         (1 << 24)
  37 #define GCR_DESC_TYPE_HOST      (1 << 14)
  38
  39 /* DMA scheduler */
  40 #define DMA_SCHED_CTRL          0
  41 #define DMA_SCHED_CTRL_EN       (1 << 31)
  42 #define DMA_SCHED_WORD(x)       ((x) * 4 + 0x800)
  43
  44 #define SCHED_ENTRY0_CHAN(x)    ((x) << 0)
  45 #define SCHED_ENTRY0_IS_RX      (1 << 7)
  46
  47 #define SCHED_ENTRY1_CHAN(x)    ((x) << 8)
  48 #define SCHED_ENTRY1_IS_RX      (1 << 15)
  49
  50 #define SCHED_ENTRY2_CHAN(x)    ((x) << 16)
  51 #define SCHED_ENTRY2_IS_RX      (1 << 23)
  52
  53 #define SCHED_ENTRY3_CHAN(x)    ((x) << 24)
  54 #define SCHED_ENTRY3_IS_RX      (1 << 31)
  55
  56 /* Queue manager */
  57 /* 4 KiB of memory for descriptors, 2 for each endpoint */
  58 #define ALLOC_DECS_NUM          128
  59 #define DESCS_AREAS             1
  60 #define TOTAL_DESCS_NUM         (ALLOC_DECS_NUM * DESCS_AREAS)
  61 #define QMGR_SCRATCH_SIZE       (TOTAL_DESCS_NUM * 4)
  62
  63 #define QMGR_LRAM0_BASE         0x80
  64 #define QMGR_LRAM_SIZE          0x84
  65 #define QMGR_LRAM1_BASE         0x88
  66 #define QMGR_MEMBASE(x)         (0x1000 + (x) * 0x10)
  67 #define QMGR_MEMCTRL(x)         (0x1004 + (x) * 0x10)
  68 #define QMGR_MEMCTRL_IDX_SH     16
  69 #define QMGR_MEMCTRL_DESC_SH    8
  70
  71 #define QMGR_NUM_PEND   5
  72 #define QMGR_PEND(x)    (0x90 + (x) * 4)
  73
  74 #define QMGR_PENDING_SLOT_Q(x)  (x / 32)
  75 #define QMGR_PENDING_BIT_Q(x)   (x % 32)
  76
  77 #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)
  78 #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)
  79 #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)
  80 #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10)
  81
  82 /* Glue layer specific */
  83 /* USBSS  / USB AM335x */
  84 #define USBSS_IRQ_STATUS        0x28
  85 #define USBSS_IRQ_ENABLER       0x2c
  86 #define USBSS_IRQ_CLEARR        0x30
  87
  88 #define USBSS_IRQ_PD_COMP       (1 <<  2)
  89
  90 /* Packet Descriptor */
  91 #define PD2_ZERO_LENGTH         (1 << 19)
  92
  93 struct cppi41_channel {
  94         struct dma_chan chan;
  95         struct dma_async_tx_descriptor txd;
  96         struct cppi41_dd *cdd;
  97         struct cppi41_desc *desc;
  98         dma_addr_t desc_phys;
  99         void __iomem *gcr_reg;
 100         int is_tx;
 101         u32 residue;
 102
 103         unsigned int q_num;
 104         unsigned int q_comp_num;
 105         unsigned int port_num;
 106
 107         unsigned td_retry;
 108         unsigned td_queued:1;
 109         unsigned td_seen:1;
 110         unsigned td_desc_seen:1;
 111
 112         struct list_head node;          /* Node for pending list */
 113 };
 114
 115 struct cppi41_desc {
 116         u32 pd0;
 117         u32 pd1;
 118         u32 pd2;
 119         u32 pd3;
 120         u32 pd4;
 121         u32 pd5;
 122         u32 pd6;
 123         u32 pd7;
 124 } __aligned(32);
 125
 126 struct chan_queues {
 127         u16 submit;
 128         u16 complete;
 129 };
 130
 131 struct cppi41_dd {
 132         struct dma_device ddev;
 133
 134         void *qmgr_scratch;
 135         dma_addr_t scratch_phys;
 136
 137         struct cppi41_desc *cd;
 138         dma_addr_t descs_phys;
 139         u32 first_td_desc;
 140         struct cppi41_channel *chan_busy[ALLOC_DECS_NUM];
 141
 142         void __iomem *usbss_mem;
 143         void __iomem *ctrl_mem;
 144         void __iomem *sched_mem;
 145         void __iomem *qmgr_mem;
 146         unsigned int irq;
 147         const struct chan_queues *queues_rx;
 148         const struct chan_queues *queues_tx;
 149         struct chan_queues td_queue;
 150
 151         struct list_head pending;       /* Pending queued transfers */
 152         spinlock_t lock;                /* Lock for pending list */
 153
 154         /* context for suspend/resume */
 155         unsigned int dma_tdfdq;
 156 };
 157
 158 #define FIST_COMPLETION_QUEUE   93
 159 static struct chan_queues usb_queues_tx[] = {
 160         /* USB0 ENDP 1 */
 161         [ 0] = { .submit = 32, .complete =  93},
 162         [ 1] = { .submit = 34, .complete =  94},
 163         [ 2] = { .submit = 36, .complete =  95},
 164         [ 3] = { .submit = 38, .complete =  96},
 165         [ 4] = { .submit = 40, .complete =  97},
 166         [ 5] = { .submit = 42, .complete =  98},
 167         [ 6] = { .submit = 44, .complete =  99},
 168         [ 7] = { .submit = 46, .complete = 100},
 169         [ 8] = { .submit = 48, .complete = 101},
 170         [ 9] = { .submit = 50, .complete = 102},
 171         [10] = { .submit = 52, .complete = 103},
 172         [11] = { .submit = 54, .complete = 104},
 173         [12] = { .submit = 56, .complete = 105},
 174         [13] = { .submit = 58, .complete = 106},
 175         [14] = { .submit = 60, .complete = 107},
 176
 177         /* USB1 ENDP1 */
 178         [15] = { .submit = 62, .complete = 125},
 179         [16] = { .submit = 64, .complete = 126},
 180         [17] = { .submit = 66, .complete = 127},
 181         [18] = { .submit = 68, .complete = 128},
 182         [19] = { .submit = 70, .complete = 129},
 183         [20] = { .submit = 72, .complete = 130},
 184         [21] = { .submit = 74, .complete = 131},
 185         [22] = { .submit = 76, .complete = 132},
 186         [23] = { .submit = 78, .complete = 133},
 187         [24] = { .submit = 80, .complete = 134},
 188         [25] = { .submit = 82, .complete = 135},
 189         [26] = { .submit = 84, .complete = 136},
 190         [27] = { .submit = 86, .complete = 137},
 191         [28] = { .submit = 88, .complete = 138},
 192         [29] = { .submit = 90, .complete = 139},
 193 };
 194
 195 static const struct chan_queues usb_queues_rx[] = {
 196         /* USB0 ENDP 1 */
 197         [ 0] = { .submit =  1, .complete = 109},
 198         [ 1] = { .submit =  2, .complete = 110},
 199         [ 2] = { .submit =  3, .complete = 111},
 200         [ 3] = { .submit =  4, .complete = 112},
 201         [ 4] = { .submit =  5, .complete = 113},
 202         [ 5] = { .submit =  6, .complete = 114},
 203         [ 6] = { .submit =  7, .complete = 115},
 204         [ 7] = { .submit =  8, .complete = 116},
 205         [ 8] = { .submit =  9, .complete = 117},
 206         [ 9] = { .submit = 10, .complete = 118},
 207         [10] = { .submit = 11, .complete = 119},
 208         [11] = { .submit = 12, .complete = 120},
 209         [12] = { .submit = 13, .complete = 121},
 210         [13] = { .submit = 14, .complete = 122},
 211         [14] = { .submit = 15, .complete = 123},
 212
 213         /* USB1 ENDP 1 */
 214         [15] = { .submit = 16, .complete = 141},
 215         [16] = { .submit = 17, .complete = 142},
 216         [17] = { .submit = 18, .complete = 143},
 217         [18] = { .submit = 19, .complete = 144},
 218         [19] = { .submit = 20, .complete = 145},
 219         [20] = { .submit = 21, .complete = 146},
 220         [21] = { .submit = 22, .complete = 147},
 221         [22] = { .submit = 23, .complete = 148},
 222         [23] = { .submit = 24, .complete = 149},
 223         [24] = { .submit = 25, .complete = 150},
 224         [25] = { .submit = 26, .complete = 151},
 225         [26] = { .submit = 27, .complete = 152},
 226         [27] = { .submit = 28, .complete = 153},
 227         [28] = { .submit = 29, .complete = 154},
 228         [29] = { .submit = 30, .complete = 155},
 229 };
 230
 231 struct cppi_glue_infos {
 232         irqreturn_t (*isr)(int irq, void *data);
 233         const struct chan_queues *queues_rx;
 234         const struct chan_queues *queues_tx;
 235         struct chan_queues td_queue;
 236 };
 237
 238 static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
 239 {
 240         return container_of(c, struct cppi41_channel, chan);
 241 }
 242
 243 static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
 244 {
 245         struct cppi41_channel *c;
 246         u32 descs_size;
 247         u32 desc_num;
 248
 249         descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM;
 250
 251         if (!((desc >= cdd->descs_phys) &&
 252                         (desc < (cdd->descs_phys + descs_size)))) {
 253                 return NULL;
 254         }
 255
 256         desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
 257         BUG_ON(desc_num >= ALLOC_DECS_NUM);
 258         c = cdd->chan_busy[desc_num];
 259         cdd->chan_busy[desc_num] = NULL;
 260         return c;
 261 }
 262
 263 static void cppi_writel(u32 val, void *__iomem *mem)
 264 {
 265         __raw_writel(val, mem);
 266 }
 267
 268 static u32 cppi_readl(void *__iomem *mem)
 269 {
 270         return __raw_readl(mem);
 271 }
 272
 273 static u32 pd_trans_len(u32 val)
 274 {
 275         return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
 276 }
 277
 278 static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
 279 {
 280         u32 desc;
 281
 282         desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
 283         desc &= ~0x1f;
 284         return desc;
 285 }
 286
 287 static irqreturn_t cppi41_irq(int irq, void *data)
 288 {
 289         struct cppi41_dd *cdd = data;
 290         struct cppi41_channel *c;
 291         u32 status;
 292         int i;
 293
 294         status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
 295         if (!(status & USBSS_IRQ_PD_COMP))
 296                 return IRQ_NONE;
 297         cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
 298
 299         for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
 300                         i++) {
 301                 u32 val;
 302                 u32 q_num;
 303
 304                 val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
 305                 if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) {
 306                         u32 mask;
 307                         /* set corresponding bit for completetion Q 93 */
 308                         mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE);
 309                         /* not set all bits for queues less than Q 93 */
 310                         mask--;
 311                         /* now invert and keep only Q 93+ set */
 312                         val &= ~mask;
 313                 }
 314
 315                 if (val)
 316                         __iormb();
 317
 318                 while (val) {
 319                         u32 desc, len;
 320                         int error;
 321
 322                         error = pm_runtime_get(cdd->ddev.dev);
 323                         if (error < 0)
 324                                 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
 325                                         __func__, error);
 326
 327                         q_num = __fls(val);
 328                         val &= ~(1 << q_num);
 329                         q_num += 32 * i;
 330                         desc = cppi41_pop_desc(cdd, q_num);
 331                         c = desc_to_chan(cdd, desc);
 332                         if (WARN_ON(!c)) {
 333                                 pr_err("%s() q %d desc %08x\n", __func__,
 334                                                 q_num, desc);
 335                                 continue;
 336                         }
 337
 338                         if (c->desc->pd2 & PD2_ZERO_LENGTH)
 339                                 len = 0;
 340                         else
 341                                 len = pd_trans_len(c->desc->pd0);
 342
 343                         c->residue = pd_trans_len(c->desc->pd6) - len;
 344                         dma_cookie_complete(&c->txd);
 345                         dmaengine_desc_get_callback_invoke(&c->txd, NULL);
 346
 347                         pm_runtime_mark_last_busy(cdd->ddev.dev);
 348                         pm_runtime_put_autosuspend(cdd->ddev.dev);
 349                 }
 350         }
 351         return IRQ_HANDLED;
 352 }
 353
 354 static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
 355 {
 356         dma_cookie_t cookie;
 357
 358         cookie = dma_cookie_assign(tx);
 359
 360         return cookie;
 361 }
 362
 363 static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan)
 364 {
 365         struct cppi41_channel *c = to_cpp41_chan(chan);
 366         struct cppi41_dd *cdd = c->cdd;
 367         int error;
 368
 369         error = pm_runtime_get_sync(cdd->ddev.dev);
 370         if (error < 0) {
 371                 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
 372                         __func__, error);
 373                 pm_runtime_put_noidle(cdd->ddev.dev);
 374
 375                 return error;
 376         }
 377
 378         dma_cookie_init(chan);
 379         dma_async_tx_descriptor_init(&c->txd, chan);
 380         c->txd.tx_submit = cppi41_tx_submit;
 381
 382         if (!c->is_tx)
 383                 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
 384
 385         pm_runtime_mark_last_busy(cdd->ddev.dev);
 386         pm_runtime_put_autosuspend(cdd->ddev.dev);
 387
 388         return 0;
 389 }
 390
 391 static void cppi41_dma_free_chan_resources(struct dma_chan *chan)
 392 {
 393         struct cppi41_channel *c = to_cpp41_chan(chan);
 394         struct cppi41_dd *cdd = c->cdd;
 395         int error;
 396
 397         error = pm_runtime_get_sync(cdd->ddev.dev);
 398         if (error < 0) {
 399                 pm_runtime_put_noidle(cdd->ddev.dev);
 400
 401                 return;
 402         }
 403
 404         WARN_ON(!list_empty(&cdd->pending));
 405
 406         pm_runtime_mark_last_busy(cdd->ddev.dev);
 407         pm_runtime_put_autosuspend(cdd->ddev.dev);
 408 }
 409
 410 static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan,
 411         dma_cookie_t cookie, struct dma_tx_state *txstate)
 412 {
 413         struct cppi41_channel *c = to_cpp41_chan(chan);
 414         enum dma_status ret;
 415
 416         /* lock */
 417         ret = dma_cookie_status(chan, cookie, txstate);
 418         if (txstate && ret == DMA_COMPLETE)
 419                 txstate->residue = c->residue;
 420         /* unlock */
 421
 422         return ret;
 423 }
 424
 425 static void push_desc_queue(struct cppi41_channel *c)
 426 {
 427         struct cppi41_dd *cdd = c->cdd;
 428         u32 desc_num;
 429         u32 desc_phys;
 430         u32 reg;
 431
 432         c->residue = 0;
 433
 434         reg = GCR_CHAN_ENABLE;
 435         if (!c->is_tx) {
 436                 reg |= GCR_STARV_RETRY;
 437                 reg |= GCR_DESC_TYPE_HOST;
 438                 reg |= c->q_comp_num;
 439         }
 440
 441         cppi_writel(reg, c->gcr_reg);
 442
 443         /*
 444          * We don't use writel() but __raw_writel() so we have to make sure
 445          * that the DMA descriptor in coherent memory made to the main memory
 446          * before starting the dma engine.
 447          */
 448         __iowmb();
 449
 450         desc_phys = lower_32_bits(c->desc_phys);
 451         desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
 452         WARN_ON(cdd->chan_busy[desc_num]);
 453         cdd->chan_busy[desc_num] = c;
 454
 455         reg = (sizeof(struct cppi41_desc) - 24) / 4;
 456         reg |= desc_phys;
 457         cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
 458 }
 459
 460 static void pending_desc(struct cppi41_channel *c)
 461 {
 462         struct cppi41_dd *cdd = c->cdd;
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&cdd->lock, flags);
 466         list_add_tail(&c->node, &cdd->pending);
 467         spin_unlock_irqrestore(&cdd->lock, flags);
 468 }
 469
 470 static void cppi41_dma_issue_pending(struct dma_chan *chan)
 471 {
 472         struct cppi41_channel *c = to_cpp41_chan(chan);
 473         struct cppi41_dd *cdd = c->cdd;
 474         int error;
 475
 476         error = pm_runtime_get(cdd->ddev.dev);
 477         if ((error != -EINPROGRESS) && error < 0) {
 478                 pm_runtime_put_noidle(cdd->ddev.dev);
 479                 dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
 480                         error);
 481
 482                 return;
 483         }
 484
 485         if (likely(pm_runtime_active(cdd->ddev.dev)))
 486                 push_desc_queue(c);
 487         else
 488                 pending_desc(c);
 489
 490         pm_runtime_mark_last_busy(cdd->ddev.dev);
 491         pm_runtime_put_autosuspend(cdd->ddev.dev);
 492 }
 493
 494 static u32 get_host_pd0(u32 length)
 495 {
 496         u32 reg;
 497
 498         reg = DESC_TYPE_HOST << DESC_TYPE;
 499         reg |= length;
 500
 501         return reg;
 502 }
 503
 504 static u32 get_host_pd1(struct cppi41_channel *c)
 505 {
 506         u32 reg;
 507
 508         reg = 0;
 509
 510         return reg;
 511 }
 512
 513 static u32 get_host_pd2(struct cppi41_channel *c)
 514 {
 515         u32 reg;
 516
 517         reg = DESC_TYPE_USB;
 518         reg |= c->q_comp_num;
 519
 520         return reg;
 521 }
 522
 523 static u32 get_host_pd3(u32 length)
 524 {
 525         u32 reg;
 526
 527         /* PD3 = packet size */
 528         reg = length;
 529
 530         return reg;
 531 }
 532
 533 static u32 get_host_pd6(u32 length)
 534 {
 535         u32 reg;
 536
 537         /* PD6 buffer size */
 538         reg = DESC_PD_COMPLETE;
 539         reg |= length;
 540
 541         return reg;
 542 }
 543
 544 static u32 get_host_pd4_or_7(u32 addr)
 545 {
 546         u32 reg;
 547
 548         reg = addr;
 549
 550         return reg;
 551 }
 552
 553 static u32 get_host_pd5(void)
 554 {
 555         u32 reg;
 556
 557         reg = 0;
 558
 559         return reg;
 560 }
 561
 562 static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg(
 563         struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len,
 564         enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
 565 {
 566         struct cppi41_channel *c = to_cpp41_chan(chan);
 567         struct cppi41_desc *d;
 568         struct scatterlist *sg;
 569         unsigned int i;
 570
 571         d = c->desc;
 572         for_each_sg(sgl, sg, sg_len, i) {
 573                 u32 addr;
 574                 u32 len;
 575
 576                 /* We need to use more than one desc once musb supports sg */
 577                 addr = lower_32_bits(sg_dma_address(sg));
 578                 len = sg_dma_len(sg);
 579
 580                 d->pd0 = get_host_pd0(len);
 581                 d->pd1 = get_host_pd1(c);
 582                 d->pd2 = get_host_pd2(c);
 583                 d->pd3 = get_host_pd3(len);
 584                 d->pd4 = get_host_pd4_or_7(addr);
 585                 d->pd5 = get_host_pd5();
 586                 d->pd6 = get_host_pd6(len);
 587                 d->pd7 = get_host_pd4_or_7(addr);
 588
 589                 d++;
 590         }
 591
 592         return &c->txd;
 593 }
 594
 595 static void cppi41_compute_td_desc(struct cppi41_desc *d)
 596 {
 597         d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
 598 }
 599
 600 static int cppi41_tear_down_chan(struct cppi41_channel *c)
 601 {
 602         struct cppi41_dd *cdd = c->cdd;
 603         struct cppi41_desc *td;
 604         u32 reg;
 605         u32 desc_phys;
 606         u32 td_desc_phys;
 607
 608         td = cdd->cd;
 609         td += cdd->first_td_desc;
 610
 611         td_desc_phys = cdd->descs_phys;
 612         td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
 613
 614         if (!c->td_queued) {
 615                 cppi41_compute_td_desc(td);
 616                 __iowmb();
 617
 618                 reg = (sizeof(struct cppi41_desc) - 24) / 4;
 619                 reg |= td_desc_phys;
 620                 cppi_writel(reg, cdd->qmgr_mem +
 621                                 QMGR_QUEUE_D(cdd->td_queue.submit));
 622
 623                 reg = GCR_CHAN_ENABLE;
 624                 if (!c->is_tx) {
 625                         reg |= GCR_STARV_RETRY;
 626                         reg |= GCR_DESC_TYPE_HOST;
 627                         reg |= c->q_comp_num;
 628                 }
 629                 reg |= GCR_TEARDOWN;
 630                 cppi_writel(reg, c->gcr_reg);
 631                 c->td_queued = 1;
 632                 c->td_retry = 500;
 633         }
 634
 635         if (!c->td_seen || !c->td_desc_seen) {
 636
 637                 desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
 638                 if (!desc_phys)
 639                         desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
 640
 641                 if (desc_phys == c->desc_phys) {
 642                         c->td_desc_seen = 1;
 643
 644                 } else if (desc_phys == td_desc_phys) {
 645                         u32 pd0;
 646
 647                         __iormb();
 648                         pd0 = td->pd0;
 649                         WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
 650                         WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
 651                         WARN_ON((pd0 & 0x1f) != c->port_num);
 652                         c->td_seen = 1;
 653                 } else if (desc_phys) {
 654                         WARN_ON_ONCE(1);
 655                 }
 656         }
 657         c->td_retry--;
 658         /*
 659          * If the TX descriptor / channel is in use, the caller needs to poke
 660          * his TD bit multiple times. After that he hardware releases the
 661          * transfer descriptor followed by TD descriptor. Waiting seems not to
 662          * cause any difference.
 663          * RX seems to be thrown out right away. However once the TearDown
 664          * descriptor gets through we are done. If we have seens the transfer
 665          * descriptor before the TD we fetch it from enqueue, it has to be
 666          * there waiting for us.
 667          */
 668         if (!c->td_seen && c->td_retry) {
 669                 udelay(1);
 670                 return -EAGAIN;
 671         }
 672         WARN_ON(!c->td_retry);
 673
 674         if (!c->td_desc_seen) {
 675                 desc_phys = cppi41_pop_desc(cdd, c->q_num);
 676                 if (!desc_phys)
 677                         desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
 678                 WARN_ON(!desc_phys);
 679         }
 680
 681         c->td_queued = 0;
 682         c->td_seen = 0;
 683         c->td_desc_seen = 0;
 684         cppi_writel(0, c->gcr_reg);
 685         return 0;
 686 }
 687
 688 static int cppi41_stop_chan(struct dma_chan *chan)
 689 {
 690         struct cppi41_channel *c = to_cpp41_chan(chan);
 691         struct cppi41_dd *cdd = c->cdd;
 692         u32 desc_num;
 693         u32 desc_phys;
 694         int ret;
 695
 696         desc_phys = lower_32_bits(c->desc_phys);
 697         desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
 698         if (!cdd->chan_busy[desc_num])
 699                 return 0;
 700
 701         ret = cppi41_tear_down_chan(c);
 702         if (ret)
 703                 return ret;
 704
 705         WARN_ON(!cdd->chan_busy[desc_num]);
 706         cdd->chan_busy[desc_num] = NULL;
 707
 708         return 0;
 709 }
 710
 711 static void cleanup_chans(struct cppi41_dd *cdd)
 712 {
 713         while (!list_empty(&cdd->ddev.channels)) {
 714                 struct cppi41_channel *cchan;
 715
 716                 cchan = list_first_entry(&cdd->ddev.channels,
 717                                 struct cppi41_channel, chan.device_node);
 718                 list_del(&cchan->chan.device_node);
 719                 kfree(cchan);
 720         }
 721 }
 722
 723 static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
 724 {
 725         struct cppi41_channel *cchan;
 726         int i;
 727         int ret;
 728         u32 n_chans;
 729
 730         ret = of_property_read_u32(dev->of_node, "#dma-channels",
 731                         &n_chans);
 732         if (ret)
 733                 return ret;
 734         /*
 735          * The channels can only be used as TX or as RX. So we add twice
 736          * that much dma channels because USB can only do RX or TX.
 737          */
 738         n_chans *= 2;
 739
 740         for (i = 0; i < n_chans; i++) {
 741                 cchan = kzalloc(sizeof(*cchan), GFP_KERNEL);
 742                 if (!cchan)
 743                         goto err;
 744
 745                 cchan->cdd = cdd;
 746                 if (i & 1) {
 747                         cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
 748                         cchan->is_tx = 1;
 749                 } else {
 750                         cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
 751                         cchan->is_tx = 0;
 752                 }
 753                 cchan->port_num = i >> 1;
 754                 cchan->desc = &cdd->cd[i];
 755                 cchan->desc_phys = cdd->descs_phys;
 756                 cchan->desc_phys += i * sizeof(struct cppi41_desc);
 757                 cchan->chan.device = &cdd->ddev;
 758                 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
 759         }
 760         cdd->first_td_desc = n_chans;
 761
 762         return 0;
 763 err:
 764         cleanup_chans(cdd);
 765         return -ENOMEM;
 766 }
 767
 768 static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
 769 {
 770         unsigned int mem_decs;
 771         int i;
 772
 773         mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc);
 774
 775         for (i = 0; i < DESCS_AREAS; i++) {
 776
 777                 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
 778                 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
 779
 780                 dma_free_coherent(dev, mem_decs, cdd->cd,
 781                                 cdd->descs_phys);
 782         }
 783 }
 784
 785 static void disable_sched(struct cppi41_dd *cdd)
 786 {
 787         cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
 788 }
 789
 790 static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
 791 {
 792         disable_sched(cdd);
 793
 794         purge_descs(dev, cdd);
 795
 796         cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
 797         cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
 798         dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
 799                         cdd->scratch_phys);
 800 }
 801
 802 static int init_descs(struct device *dev, struct cppi41_dd *cdd)
 803 {
 804         unsigned int desc_size;
 805         unsigned int mem_decs;
 806         int i;
 807         u32 reg;
 808         u32 idx;
 809
 810         BUILD_BUG_ON(sizeof(struct cppi41_desc) &
 811                         (sizeof(struct cppi41_desc) - 1));
 812         BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32);
 813         BUILD_BUG_ON(ALLOC_DECS_NUM < 32);
 814
 815         desc_size = sizeof(struct cppi41_desc);
 816         mem_decs = ALLOC_DECS_NUM * desc_size;
 817
 818         idx = 0;
 819         for (i = 0; i < DESCS_AREAS; i++) {
 820
 821                 reg = idx << QMGR_MEMCTRL_IDX_SH;
 822                 reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH;
 823                 reg |= ilog2(ALLOC_DECS_NUM) - 5;
 824
 825                 BUILD_BUG_ON(DESCS_AREAS != 1);
 826                 cdd->cd = dma_alloc_coherent(dev, mem_decs,
 827                                 &cdd->descs_phys, GFP_KERNEL);
 828                 if (!cdd->cd)
 829                         return -ENOMEM;
 830
 831                 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
 832                 cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
 833
 834                 idx += ALLOC_DECS_NUM;
 835         }
 836         return 0;
 837 }
 838
 839 static void init_sched(struct cppi41_dd *cdd)
 840 {
 841         unsigned ch;
 842         unsigned word;
 843         u32 reg;
 844
 845         word = 0;
 846         cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
 847         for (ch = 0; ch < 15 * 2; ch += 2) {
 848
 849                 reg = SCHED_ENTRY0_CHAN(ch);
 850                 reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
 851
 852                 reg |= SCHED_ENTRY2_CHAN(ch + 1);
 853                 reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX;
 854                 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
 855                 word++;
 856         }
 857         reg = 15 * 2 * 2 - 1;
 858         reg |= DMA_SCHED_CTRL_EN;
 859         cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
 860 }
 861
 862 static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
 863 {
 864         int ret;
 865
 866         BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
 867         cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
 868                         &cdd->scratch_phys, GFP_KERNEL);
 869         if (!cdd->qmgr_scratch)
 870                 return -ENOMEM;
 871
 872         cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
 873         cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
 874         cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
 875
 876         ret = init_descs(dev, cdd);
 877         if (ret)
 878                 goto err_td;
 879
 880         cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
 881         init_sched(cdd);
 882         return 0;
 883 err_td:
 884         deinit_cppi41(dev, cdd);
 885         return ret;
 886 }
 887
 888 static struct platform_driver cpp41_dma_driver;
 889 /*
 890  * The param format is:
 891  * X Y
 892  * X: Port
 893  * Y: 0 = RX else TX
 894  */
 895 #define INFO_PORT       0
 896 #define INFO_IS_TX      1
 897
 898 static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
 899 {
 900         struct cppi41_channel *cchan;
 901         struct cppi41_dd *cdd;
 902         const struct chan_queues *queues;
 903         u32 *num = param;
 904
 905         if (chan->device->dev->driver != &cpp41_dma_driver.driver)
 906                 return false;
 907
 908         cchan = to_cpp41_chan(chan);
 909
 910         if (cchan->port_num != num[INFO_PORT])
 911                 return false;
 912
 913         if (cchan->is_tx && !num[INFO_IS_TX])
 914                 return false;
 915         cdd = cchan->cdd;
 916         if (cchan->is_tx)
 917                 queues = cdd->queues_tx;
 918         else
 919                 queues = cdd->queues_rx;
 920
 921         BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx));
 922         if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx)))
 923                 return false;
 924
 925         cchan->q_num = queues[cchan->port_num].submit;
 926         cchan->q_comp_num = queues[cchan->port_num].complete;
 927         return true;
 928 }
 929
 930 static struct of_dma_filter_info cpp41_dma_info = {
 931         .filter_fn = cpp41_dma_filter_fn,
 932 };
 933
 934 static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
 935                 struct of_dma *ofdma)
 936 {
 937         int count = dma_spec->args_count;
 938         struct of_dma_filter_info *info = ofdma->of_dma_data;
 939
 940         if (!info || !info->filter_fn)
 941                 return NULL;
 942
 943         if (count != 2)
 944                 return NULL;
 945
 946         return dma_request_channel(info->dma_cap, info->filter_fn,
 947                         &dma_spec->args[0]);
 948 }
 949
 950 static const struct cppi_glue_infos usb_infos = {
 951         .isr = cppi41_irq,
 952         .queues_rx = usb_queues_rx,
 953         .queues_tx = usb_queues_tx,
 954         .td_queue = { .submit = 31, .complete = 0 },
 955 };
 956
 957 static const struct of_device_id cppi41_dma_ids[] = {
 958         { .compatible = "ti,am3359-cppi41", .data = &usb_infos},
 959         {},
 960 };
 961 MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
 962
 963 static const struct cppi_glue_infos *get_glue_info(struct device *dev)
 964 {
 965         const struct of_device_id *of_id;
 966
 967         of_id = of_match_node(cppi41_dma_ids, dev->of_node);
 968         if (!of_id)
 969                 return NULL;
 970         return of_id->data;
 971 }
 972
 973 #define CPPI41_DMA_BUSWIDTHS    (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 974                                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 975                                 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
 976                                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 977
 978 static int cppi41_dma_probe(struct platform_device *pdev)
 979 {
 980         struct cppi41_dd *cdd;
 981         struct device *dev = &pdev->dev;
 982         const struct cppi_glue_infos *glue_info;
 983         int irq;
 984         int ret;
 985
 986         glue_info = get_glue_info(dev);
 987         if (!glue_info)
 988                 return -EINVAL;
 989
 990         cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
 991         if (!cdd)
 992                 return -ENOMEM;
 993
 994         dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
 995         cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
 996         cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
 997         cdd->ddev.device_tx_status = cppi41_dma_tx_status;
 998         cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
 999         cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
1000         cdd->ddev.device_terminate_all = cppi41_stop_chan;
1001         cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1002         cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS;
1003         cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS;
1004         cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1005         cdd->ddev.dev = dev;
1006         INIT_LIST_HEAD(&cdd->ddev.channels);
1007         cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
1008
1009         cdd->usbss_mem = of_iomap(dev->of_node, 0);
1010         cdd->ctrl_mem = of_iomap(dev->of_node, 1);
1011         cdd->sched_mem = of_iomap(dev->of_node, 2);
1012         cdd->qmgr_mem = of_iomap(dev->of_node, 3);
1013         spin_lock_init(&cdd->lock);
1014         INIT_LIST_HEAD(&cdd->pending);
1015
1016         platform_set_drvdata(pdev, cdd);
1017
1018         if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
1019                         !cdd->qmgr_mem)
1020                 return -ENXIO;
1021
1022         pm_runtime_enable(dev);
1023         pm_runtime_set_autosuspend_delay(dev, 100);
1024         pm_runtime_use_autosuspend(dev);
1025         ret = pm_runtime_get_sync(dev);
1026         if (ret < 0)
1027                 goto err_get_sync;
1028
1029         cdd->queues_rx = glue_info->queues_rx;
1030         cdd->queues_tx = glue_info->queues_tx;
1031         cdd->td_queue = glue_info->td_queue;
1032
1033         ret = init_cppi41(dev, cdd);
1034         if (ret)
1035                 goto err_init_cppi;
1036
1037         ret = cppi41_add_chans(dev, cdd);
1038         if (ret)
1039                 goto err_chans;
1040
1041         irq = irq_of_parse_and_map(dev->of_node, 0);
1042         if (!irq) {
1043                 ret = -EINVAL;
1044                 goto err_irq;
1045         }
1046
1047         cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1048
1049         ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED,
1050                         dev_name(dev), cdd);
1051         if (ret)
1052                 goto err_irq;
1053         cdd->irq = irq;
1054
1055         ret = dma_async_device_register(&cdd->ddev);
1056         if (ret)
1057                 goto err_dma_reg;
1058
1059         ret = of_dma_controller_register(dev->of_node,
1060                         cppi41_dma_xlate, &cpp41_dma_info);
1061         if (ret)
1062                 goto err_of;
1063
1064         pm_runtime_mark_last_busy(dev);
1065         pm_runtime_put_autosuspend(dev);
1066
1067         return 0;
1068 err_of:
1069         dma_async_device_unregister(&cdd->ddev);
1070 err_dma_reg:
1071 err_irq:
1072         cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1073         cleanup_chans(cdd);
1074 err_chans:
1075         deinit_cppi41(dev, cdd);
1076 err_init_cppi:
1077         pm_runtime_dont_use_autosuspend(dev);
1078 err_get_sync:
1079         pm_runtime_put_sync(dev);
1080         pm_runtime_disable(dev);
1081         iounmap(cdd->usbss_mem);
1082         iounmap(cdd->ctrl_mem);
1083         iounmap(cdd->sched_mem);
1084         iounmap(cdd->qmgr_mem);
1085         return ret;
1086 }
1087
1088 static int cppi41_dma_remove(struct platform_device *pdev)
1089 {
1090         struct cppi41_dd *cdd = platform_get_drvdata(pdev);
1091         int error;
1092
1093         error = pm_runtime_get_sync(&pdev->dev);
1094         if (error < 0)
1095                 dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n",
1096                         __func__, error);
1097         of_dma_controller_free(pdev->dev.of_node);
1098         dma_async_device_unregister(&cdd->ddev);
1099
1100         cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1101         devm_free_irq(&pdev->dev, cdd->irq, cdd);
1102         cleanup_chans(cdd);
1103         deinit_cppi41(&pdev->dev, cdd);
1104         iounmap(cdd->usbss_mem);
1105         iounmap(cdd->ctrl_mem);
1106         iounmap(cdd->sched_mem);
1107         iounmap(cdd->qmgr_mem);
1108         pm_runtime_dont_use_autosuspend(&pdev->dev);
1109         pm_runtime_put_sync(&pdev->dev);
1110         pm_runtime_disable(&pdev->dev);
1111         return 0;
1112 }
1113
1114 static int __maybe_unused cppi41_suspend(struct device *dev)
1115 {
1116         struct cppi41_dd *cdd = dev_get_drvdata(dev);
1117
1118         cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
1119         cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1120         disable_sched(cdd);
1121
1122         return 0;
1123 }
1124
1125 static int __maybe_unused cppi41_resume(struct device *dev)
1126 {
1127         struct cppi41_dd *cdd = dev_get_drvdata(dev);
1128         struct cppi41_channel *c;
1129         int i;
1130
1131         for (i = 0; i < DESCS_AREAS; i++)
1132                 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
1133
1134         list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
1135                 if (!c->is_tx)
1136                         cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
1137
1138         init_sched(cdd);
1139
1140         cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
1141         cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
1142         cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
1143         cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
1144
1145         cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1146
1147         return 0;
1148 }
1149
1150 static int __maybe_unused cppi41_runtime_suspend(struct device *dev)
1151 {
1152         struct cppi41_dd *cdd = dev_get_drvdata(dev);
1153
1154         WARN_ON(!list_empty(&cdd->pending));
1155
1156         return 0;
1157 }
1158
1159 static int __maybe_unused cppi41_runtime_resume(struct device *dev)
1160 {
1161         struct cppi41_dd *cdd = dev_get_drvdata(dev);
1162         struct cppi41_channel *c, *_c;
1163         unsigned long flags;
1164
1165         spin_lock_irqsave(&cdd->lock, flags);
1166         list_for_each_entry_safe(c, _c, &cdd->pending, node) {
1167                 push_desc_queue(c);
1168                 list_del(&c->node);
1169         }
1170         spin_unlock_irqrestore(&cdd->lock, flags);
1171
1172         return 0;
1173 }
1174
1175 static const struct dev_pm_ops cppi41_pm_ops = {
1176         SET_LATE_SYSTEM_SLEEP_PM_OPS(cppi41_suspend, cppi41_resume)
1177         SET_RUNTIME_PM_OPS(cppi41_runtime_suspend,
1178                            cppi41_runtime_resume,
1179                            NULL)
1180 };
1181
1182 static struct platform_driver cpp41_dma_driver = {
1183         .probe  = cppi41_dma_probe,
1184         .remove = cppi41_dma_remove,
1185         .driver = {
1186                 .name = "cppi41-dma-engine",
1187                 .pm = &cppi41_pm_ops,
1188                 .of_match_table = of_match_ptr(cppi41_dma_ids),
1189         },
1190 };
1191
1192 module_platform_driver(cpp41_dma_driver);
1193 MODULE_LICENSE("GPL");
1194 MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");