drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008-2010 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40 #include <linux/slab.h>
  41
  42 #include <crypto/algapi.h>
  43 #include <crypto/aes.h>
  44 #include <crypto/des.h>
  45 #include <crypto/sha.h>
  46 #include <crypto/md5.h>
  47 #include <crypto/aead.h>
  48 #include <crypto/authenc.h>
  49 #include <crypto/skcipher.h>
  50 #include <crypto/hash.h>
  51 #include <crypto/internal/hash.h>
  52 #include <crypto/scatterwalk.h>
  53
  54 #include "talitos.h"
  55
  56 #define TALITOS_TIMEOUT 100000
  57 #define TALITOS_MAX_DATA_LEN 65535
  58
  59 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  60 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  61 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  62
  63 /* descriptor pointer entry */
  64 struct talitos_ptr {
  65         __be16 len;     /* length */
  66         u8 j_extent;    /* jump to sg link table and/or extent */
  67         u8 eptr;        /* extended address */
  68         __be32 ptr;     /* address */
  69 };
  70
  71 static const struct talitos_ptr zero_entry = {
  72         .len = 0,
  73         .j_extent = 0,
  74         .eptr = 0,
  75         .ptr = 0
  76 };
  77
  78 /* descriptor */
  79 struct talitos_desc {
  80         __be32 hdr;                     /* header high bits */
  81         __be32 hdr_lo;                  /* header low bits */
  82         struct talitos_ptr ptr[7];      /* ptr/len pair array */
  83 };
  84
  85 /**
  86  * talitos_request - descriptor submission request
  87  * @desc: descriptor pointer (kernel virtual)
  88  * @dma_desc: descriptor's physical bus address
  89  * @callback: whom to call when descriptor processing is done
  90  * @context: caller context (optional)
  91  */
  92 struct talitos_request {
  93         struct talitos_desc *desc;
  94         dma_addr_t dma_desc;
  95         void (*callback) (struct device *dev, struct talitos_desc *desc,
  96                           void *context, int error);
  97         void *context;
  98 };
  99
 100 /* per-channel fifo management */
 101 struct talitos_channel {
 102         /* request fifo */
 103         struct talitos_request *fifo;
 104
 105         /* number of requests pending in channel h/w fifo */
 106         atomic_t submit_count ____cacheline_aligned;
 107
 108         /* request submission (head) lock */
 109         spinlock_t head_lock ____cacheline_aligned;
 110         /* index to next free descriptor request */
 111         int head;
 112
 113         /* request release (tail) lock */
 114         spinlock_t tail_lock ____cacheline_aligned;
 115         /* index to next in-progress/done descriptor request */
 116         int tail;
 117 };
 118
 119 struct talitos_private {
 120         struct device *dev;
 121         struct of_device *ofdev;
 122         void __iomem *reg;
 123         int irq;
 124
 125         /* SEC version geometry (from device tree node) */
 126         unsigned int num_channels;
 127         unsigned int chfifo_len;
 128         unsigned int exec_units;
 129         unsigned int desc_types;
 130
 131         /* SEC Compatibility info */
 132         unsigned long features;
 133
 134         /*
 135          * length of the request fifo
 136          * fifo_len is chfifo_len rounded up to next power of 2
 137          * so we can use bitwise ops to wrap
 138          */
 139         unsigned int fifo_len;
 140
 141         struct talitos_channel *chan;
 142
 143         /* next channel to be assigned next incoming descriptor */
 144         atomic_t last_chan ____cacheline_aligned;
 145
 146         /* request callback tasklet */
 147         struct tasklet_struct done_task;
 148
 149         /* list of registered algorithms */
 150         struct list_head alg_list;
 151
 152         /* hwrng device */
 153         struct hwrng rng;
 154 };
 155
 156 /* .features flag */
 157 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
 158 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
 159 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
 160
 161 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
 162 {
 163         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
 164         talitos_ptr->eptr = cpu_to_be32(upper_32_bits(dma_addr));
 165 }
 166
 167 /*
 168  * map virtual single (contiguous) pointer to h/w descriptor pointer
 169  */
 170 static void map_single_talitos_ptr(struct device *dev,
 171                                    struct talitos_ptr *talitos_ptr,
 172                                    unsigned short len, void *data,
 173                                    unsigned char extent,
 174                                    enum dma_data_direction dir)
 175 {
 176         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
 177
 178         talitos_ptr->len = cpu_to_be16(len);
 179         to_talitos_ptr(talitos_ptr, dma_addr);
 180         talitos_ptr->j_extent = extent;
 181 }
 182
 183 /*
 184  * unmap bus single (contiguous) h/w descriptor pointer
 185  */
 186 static void unmap_single_talitos_ptr(struct device *dev,
 187                                      struct talitos_ptr *talitos_ptr,
 188                                      enum dma_data_direction dir)
 189 {
 190         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
 191                          be16_to_cpu(talitos_ptr->len), dir);
 192 }
 193
 194 static int reset_channel(struct device *dev, int ch)
 195 {
 196         struct talitos_private *priv = dev_get_drvdata(dev);
 197         unsigned int timeout = TALITOS_TIMEOUT;
 198
 199         setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
 200
 201         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
 202                && --timeout)
 203                 cpu_relax();
 204
 205         if (timeout == 0) {
 206                 dev_err(dev, "failed to reset channel %d\n", ch);
 207                 return -EIO;
 208         }
 209
 210         /* set 36-bit addressing, done writeback enable and done IRQ enable */
 211         setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
 212                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
 213
 214         /* and ICCR writeback, if available */
 215         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 216                 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
 217                           TALITOS_CCCR_LO_IWSE);
 218
 219         return 0;
 220 }
 221
 222 static int reset_device(struct device *dev)
 223 {
 224         struct talitos_private *priv = dev_get_drvdata(dev);
 225         unsigned int timeout = TALITOS_TIMEOUT;
 226
 227         setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
 228
 229         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 230                && --timeout)
 231                 cpu_relax();
 232
 233         if (timeout == 0) {
 234                 dev_err(dev, "failed to reset device\n");
 235                 return -EIO;
 236         }
 237
 238         return 0;
 239 }
 240
 241 /*
 242  * Reset and initialize the device
 243  */
 244 static int init_device(struct device *dev)
 245 {
 246         struct talitos_private *priv = dev_get_drvdata(dev);
 247         int ch, err;
 248
 249         /*
 250          * Master reset
 251          * errata documentation: warning: certain SEC interrupts
 252          * are not fully cleared by writing the MCR:SWR bit,
 253          * set bit twice to completely reset
 254          */
 255         err = reset_device(dev);
 256         if (err)
 257                 return err;
 258
 259         err = reset_device(dev);
 260         if (err)
 261                 return err;
 262
 263         /* reset channels */
 264         for (ch = 0; ch < priv->num_channels; ch++) {
 265                 err = reset_channel(dev, ch);
 266                 if (err)
 267                         return err;
 268         }
 269
 270         /* enable channel done and error interrupts */
 271         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 272         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 273
 274         /* disable integrity check error interrupts (use writeback instead) */
 275         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 276                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 277                           TALITOS_MDEUICR_LO_ICE);
 278
 279         return 0;
 280 }
 281
 282 /**
 283  * talitos_submit - submits a descriptor to the device for processing
 284  * @dev:        the SEC device to be used
 285  * @desc:       the descriptor to be processed by the device
 286  * @callback:   whom to call when processing is complete
 287  * @context:    a handle for use by caller (optional)
 288  *
 289  * desc must contain valid dma-mapped (bus physical) address pointers.
 290  * callback must check err and feedback in descriptor header
 291  * for device processing status.
 292  */
 293 static int talitos_submit(struct device *dev, struct talitos_desc *desc,
 294                           void (*callback)(struct device *dev,
 295                                            struct talitos_desc *desc,
 296                                            void *context, int error),
 297                           void *context)
 298 {
 299         struct talitos_private *priv = dev_get_drvdata(dev);
 300         struct talitos_request *request;
 301         unsigned long flags, ch;
 302         int head;
 303
 304         /* select done notification */
 305         desc->hdr |= DESC_HDR_DONE_NOTIFY;
 306
 307         /* emulate SEC's round-robin channel fifo polling scheme */
 308         ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
 309
 310         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 311
 312         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
 313                 /* h/w fifo is full */
 314                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 315                 return -EAGAIN;
 316         }
 317
 318         head = priv->chan[ch].head;
 319         request = &priv->chan[ch].fifo[head];
 320
 321         /* map descriptor and save caller data */
 322         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 323                                            DMA_BIDIRECTIONAL);
 324         request->callback = callback;
 325         request->context = context;
 326
 327         /* increment fifo head */
 328         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
 329
 330         smp_wmb();
 331         request->desc = desc;
 332
 333         /* GO! */
 334         wmb();
 335         out_be32(priv->reg + TALITOS_FF(ch),
 336                  cpu_to_be32(upper_32_bits(request->dma_desc)));
 337         out_be32(priv->reg + TALITOS_FF_LO(ch),
 338                  cpu_to_be32(lower_32_bits(request->dma_desc)));
 339
 340         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
 341
 342         return -EINPROGRESS;
 343 }
 344
 345 /*
 346  * process what was done, notify callback of error if not
 347  */
 348 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 349 {
 350         struct talitos_private *priv = dev_get_drvdata(dev);
 351         struct talitos_request *request, saved_req;
 352         unsigned long flags;
 353         int tail, status;
 354
 355         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 356
 357         tail = priv->chan[ch].tail;
 358         while (priv->chan[ch].fifo[tail].desc) {
 359                 request = &priv->chan[ch].fifo[tail];
 360
 361                 /* descriptors with their done bits set don't get the error */
 362                 rmb();
 363                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 364                         status = 0;
 365                 else
 366                         if (!error)
 367                                 break;
 368                         else
 369                                 status = error;
 370
 371                 dma_unmap_single(dev, request->dma_desc,
 372                                  sizeof(struct talitos_desc),
 373                                  DMA_BIDIRECTIONAL);
 374
 375                 /* copy entries so we can call callback outside lock */
 376                 saved_req.desc = request->desc;
 377                 saved_req.callback = request->callback;
 378                 saved_req.context = request->context;
 379
 380                 /* release request entry in fifo */
 381                 smp_wmb();
 382                 request->desc = NULL;
 383
 384                 /* increment fifo tail */
 385                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
 386
 387                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 388
 389                 atomic_dec(&priv->chan[ch].submit_count);
 390
 391                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 392                                    status);
 393                 /* channel may resume processing in single desc error case */
 394                 if (error && !reset_ch && status == error)
 395                         return;
 396                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 397                 tail = priv->chan[ch].tail;
 398         }
 399
 400         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
 401 }
 402
 403 /*
 404  * process completed requests for channels that have done status
 405  */
 406 static void talitos_done(unsigned long data)
 407 {
 408         struct device *dev = (struct device *)data;
 409         struct talitos_private *priv = dev_get_drvdata(dev);
 410         int ch;
 411
 412         for (ch = 0; ch < priv->num_channels; ch++)
 413                 flush_channel(dev, ch, 0, 0);
 414
 415         /* At this point, all completed channels have been processed.
 416          * Unmask done interrupts for channels completed later on.
 417          */
 418         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 419         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 420 }
 421
 422 /*
 423  * locate current (offending) descriptor
 424  */
 425 static struct talitos_desc *current_desc(struct device *dev, int ch)
 426 {
 427         struct talitos_private *priv = dev_get_drvdata(dev);
 428         int tail = priv->chan[ch].tail;
 429         dma_addr_t cur_desc;
 430
 431         cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
 432
 433         while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
 434                 tail = (tail + 1) & (priv->fifo_len - 1);
 435                 if (tail == priv->chan[ch].tail) {
 436                         dev_err(dev, "couldn't locate current descriptor\n");
 437                         return NULL;
 438                 }
 439         }
 440
 441         return priv->chan[ch].fifo[tail].desc;
 442 }
 443
 444 /*
 445  * user diagnostics; report root cause of error based on execution unit status
 446  */
 447 static void report_eu_error(struct device *dev, int ch,
 448                             struct talitos_desc *desc)
 449 {
 450         struct talitos_private *priv = dev_get_drvdata(dev);
 451         int i;
 452
 453         switch (desc->hdr & DESC_HDR_SEL0_MASK) {
 454         case DESC_HDR_SEL0_AFEU:
 455                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 456                         in_be32(priv->reg + TALITOS_AFEUISR),
 457                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 458                 break;
 459         case DESC_HDR_SEL0_DEU:
 460                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 461                         in_be32(priv->reg + TALITOS_DEUISR),
 462                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 463                 break;
 464         case DESC_HDR_SEL0_MDEUA:
 465         case DESC_HDR_SEL0_MDEUB:
 466                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 467                         in_be32(priv->reg + TALITOS_MDEUISR),
 468                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 469                 break;
 470         case DESC_HDR_SEL0_RNG:
 471                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 472                         in_be32(priv->reg + TALITOS_RNGUISR),
 473                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 474                 break;
 475         case DESC_HDR_SEL0_PKEU:
 476                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 477                         in_be32(priv->reg + TALITOS_PKEUISR),
 478                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 479                 break;
 480         case DESC_HDR_SEL0_AESU:
 481                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 482                         in_be32(priv->reg + TALITOS_AESUISR),
 483                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 484                 break;
 485         case DESC_HDR_SEL0_CRCU:
 486                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 487                         in_be32(priv->reg + TALITOS_CRCUISR),
 488                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 489                 break;
 490         case DESC_HDR_SEL0_KEU:
 491                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 492                         in_be32(priv->reg + TALITOS_KEUISR),
 493                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 494                 break;
 495         }
 496
 497         switch (desc->hdr & DESC_HDR_SEL1_MASK) {
 498         case DESC_HDR_SEL1_MDEUA:
 499         case DESC_HDR_SEL1_MDEUB:
 500                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 501                         in_be32(priv->reg + TALITOS_MDEUISR),
 502                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 503                 break;
 504         case DESC_HDR_SEL1_CRCU:
 505                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 506                         in_be32(priv->reg + TALITOS_CRCUISR),
 507                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 508                 break;
 509         }
 510
 511         for (i = 0; i < 8; i++)
 512                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 513                         in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
 514                         in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
 515 }
 516
 517 /*
 518  * recover from error interrupts
 519  */
 520 static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
 521 {
 522         struct device *dev = (struct device *)data;
 523         struct talitos_private *priv = dev_get_drvdata(dev);
 524         unsigned int timeout = TALITOS_TIMEOUT;
 525         int ch, error, reset_dev = 0, reset_ch = 0;
 526         u32 v, v_lo;
 527
 528         for (ch = 0; ch < priv->num_channels; ch++) {
 529                 /* skip channels without errors */
 530                 if (!(isr & (1 << (ch * 2 + 1))))
 531                         continue;
 532
 533                 error = -EINVAL;
 534
 535                 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
 536                 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
 537
 538                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 539                         dev_err(dev, "double fetch fifo overflow error\n");
 540                         error = -EAGAIN;
 541                         reset_ch = 1;
 542                 }
 543                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 544                         /* h/w dropped descriptor */
 545                         dev_err(dev, "single fetch fifo overflow error\n");
 546                         error = -EAGAIN;
 547                 }
 548                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 549                         dev_err(dev, "master data transfer error\n");
 550                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 551                         dev_err(dev, "s/g data length zero error\n");
 552                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 553                         dev_err(dev, "fetch pointer zero error\n");
 554                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 555                         dev_err(dev, "illegal descriptor header error\n");
 556                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 557                         dev_err(dev, "invalid execution unit error\n");
 558                 if (v_lo & TALITOS_CCPSR_LO_EU)
 559                         report_eu_error(dev, ch, current_desc(dev, ch));
 560                 if (v_lo & TALITOS_CCPSR_LO_GB)
 561                         dev_err(dev, "gather boundary error\n");
 562                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 563                         dev_err(dev, "gather return/length error\n");
 564                 if (v_lo & TALITOS_CCPSR_LO_SB)
 565                         dev_err(dev, "scatter boundary error\n");
 566                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 567                         dev_err(dev, "scatter return/length error\n");
 568
 569                 flush_channel(dev, ch, error, reset_ch);
 570
 571                 if (reset_ch) {
 572                         reset_channel(dev, ch);
 573                 } else {
 574                         setbits32(priv->reg + TALITOS_CCCR(ch),
 575                                   TALITOS_CCCR_CONT);
 576                         setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
 577                         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
 578                                TALITOS_CCCR_CONT) && --timeout)
 579                                 cpu_relax();
 580                         if (timeout == 0) {
 581                                 dev_err(dev, "failed to restart channel %d\n",
 582                                         ch);
 583                                 reset_dev = 1;
 584                         }
 585                 }
 586         }
 587         if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
 588                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 589                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 590
 591                 /* purge request queues */
 592                 for (ch = 0; ch < priv->num_channels; ch++)
 593                         flush_channel(dev, ch, -EIO, 1);
 594
 595                 /* reset and reinitialize the device */
 596                 init_device(dev);
 597         }
 598 }
 599
 600 static irqreturn_t talitos_interrupt(int irq, void *data)
 601 {
 602         struct device *dev = data;
 603         struct talitos_private *priv = dev_get_drvdata(dev);
 604         u32 isr, isr_lo;
 605
 606         isr = in_be32(priv->reg + TALITOS_ISR);
 607         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
 608         /* Acknowledge interrupt */
 609         out_be32(priv->reg + TALITOS_ICR, isr);
 610         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
 611
 612         if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
 613                 talitos_error((unsigned long)data, isr, isr_lo);
 614         else
 615                 if (likely(isr & TALITOS_ISR_CHDONE)) {
 616                         /* mask further done interrupts. */
 617                         clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
 618                         /* done_task will unmask done interrupts at exit */
 619                         tasklet_schedule(&priv->done_task);
 620                 }
 621
 622         return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
 623 }
 624
 625 /*
 626  * hwrng
 627  */
 628 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 629 {
 630         struct device *dev = (struct device *)rng->priv;
 631         struct talitos_private *priv = dev_get_drvdata(dev);
 632         u32 ofl;
 633         int i;
 634
 635         for (i = 0; i < 20; i++) {
 636                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 637                       TALITOS_RNGUSR_LO_OFL;
 638                 if (ofl || !wait)
 639                         break;
 640                 udelay(10);
 641         }
 642
 643         return !!ofl;
 644 }
 645
 646 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 647 {
 648         struct device *dev = (struct device *)rng->priv;
 649         struct talitos_private *priv = dev_get_drvdata(dev);
 650
 651         /* rng fifo requires 64-bit accesses */
 652         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 653         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 654
 655         return sizeof(u32);
 656 }
 657
 658 static int talitos_rng_init(struct hwrng *rng)
 659 {
 660         struct device *dev = (struct device *)rng->priv;
 661         struct talitos_private *priv = dev_get_drvdata(dev);
 662         unsigned int timeout = TALITOS_TIMEOUT;
 663
 664         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 665         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 666                && --timeout)
 667                 cpu_relax();
 668         if (timeout == 0) {
 669                 dev_err(dev, "failed to reset rng hw\n");
 670                 return -ENODEV;
 671         }
 672
 673         /* start generating */
 674         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 675
 676         return 0;
 677 }
 678
 679 static int talitos_register_rng(struct device *dev)
 680 {
 681         struct talitos_private *priv = dev_get_drvdata(dev);
 682
 683         priv->rng.name          = dev_driver_string(dev),
 684         priv->rng.init          = talitos_rng_init,
 685         priv->rng.data_present  = talitos_rng_data_present,
 686         priv->rng.data_read     = talitos_rng_data_read,
 687         priv->rng.priv          = (unsigned long)dev;
 688
 689         return hwrng_register(&priv->rng);
 690 }
 691
 692 static void talitos_unregister_rng(struct device *dev)
 693 {
 694         struct talitos_private *priv = dev_get_drvdata(dev);
 695
 696         hwrng_unregister(&priv->rng);
 697 }
 698
 699 /*
 700  * crypto alg
 701  */
 702 #define TALITOS_CRA_PRIORITY            3000
 703 #define TALITOS_MAX_KEY_SIZE            64
 704 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 705
 706 #define MD5_BLOCK_SIZE    64
 707
 708 struct talitos_ctx {
 709         struct device *dev;
 710         __be32 desc_hdr_template;
 711         u8 key[TALITOS_MAX_KEY_SIZE];
 712         u8 iv[TALITOS_MAX_IV_LENGTH];
 713         unsigned int keylen;
 714         unsigned int enckeylen;
 715         unsigned int authkeylen;
 716         unsigned int authsize;
 717 };
 718
 719 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
 720 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 721
 722 struct talitos_ahash_req_ctx {
 723         u64 count;
 724         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
 725         unsigned int hw_context_size;
 726         u8 buf[HASH_MAX_BLOCK_SIZE];
 727         u8 bufnext[HASH_MAX_BLOCK_SIZE];
 728         unsigned int swinit;
 729         unsigned int first;
 730         unsigned int last;
 731         unsigned int to_hash_later;
 732         struct scatterlist bufsl[2];
 733         struct scatterlist *psrc;
 734 };
 735
 736 static int aead_setauthsize(struct crypto_aead *authenc,
 737                             unsigned int authsize)
 738 {
 739         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 740
 741         ctx->authsize = authsize;
 742
 743         return 0;
 744 }
 745
 746 static int aead_setkey(struct crypto_aead *authenc,
 747                        const u8 *key, unsigned int keylen)
 748 {
 749         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 750         struct rtattr *rta = (void *)key;
 751         struct crypto_authenc_key_param *param;
 752         unsigned int authkeylen;
 753         unsigned int enckeylen;
 754
 755         if (!RTA_OK(rta, keylen))
 756                 goto badkey;
 757
 758         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
 759                 goto badkey;
 760
 761         if (RTA_PAYLOAD(rta) < sizeof(*param))
 762                 goto badkey;
 763
 764         param = RTA_DATA(rta);
 765         enckeylen = be32_to_cpu(param->enckeylen);
 766
 767         key += RTA_ALIGN(rta->rta_len);
 768         keylen -= RTA_ALIGN(rta->rta_len);
 769
 770         if (keylen < enckeylen)
 771                 goto badkey;
 772
 773         authkeylen = keylen - enckeylen;
 774
 775         if (keylen > TALITOS_MAX_KEY_SIZE)
 776                 goto badkey;
 777
 778         memcpy(&ctx->key, key, keylen);
 779
 780         ctx->keylen = keylen;
 781         ctx->enckeylen = enckeylen;
 782         ctx->authkeylen = authkeylen;
 783
 784         return 0;
 785
 786 badkey:
 787         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 788         return -EINVAL;
 789 }
 790
 791 /*
 792  * talitos_edesc - s/w-extended descriptor
 793  * @src_nents: number of segments in input scatterlist
 794  * @dst_nents: number of segments in output scatterlist
 795  * @dma_len: length of dma mapped link_tbl space
 796  * @dma_link_tbl: bus physical address of link_tbl
 797  * @desc: h/w descriptor
 798  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 799  *
 800  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 801  * is greater than 1, an integrity check value is concatenated to the end
 802  * of link_tbl data
 803  */
 804 struct talitos_edesc {
 805         int src_nents;
 806         int dst_nents;
 807         int src_is_chained;
 808         int dst_is_chained;
 809         int dma_len;
 810         dma_addr_t dma_link_tbl;
 811         struct talitos_desc desc;
 812         struct talitos_ptr link_tbl[0];
 813 };
 814
 815 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 816                           unsigned int nents, enum dma_data_direction dir,
 817                           int chained)
 818 {
 819         if (unlikely(chained))
 820                 while (sg) {
 821                         dma_map_sg(dev, sg, 1, dir);
 822                         sg = scatterwalk_sg_next(sg);
 823                 }
 824         else
 825                 dma_map_sg(dev, sg, nents, dir);
 826         return nents;
 827 }
 828
 829 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 830                                    enum dma_data_direction dir)
 831 {
 832         while (sg) {
 833                 dma_unmap_sg(dev, sg, 1, dir);
 834                 sg = scatterwalk_sg_next(sg);
 835         }
 836 }
 837
 838 static void talitos_sg_unmap(struct device *dev,
 839                              struct talitos_edesc *edesc,
 840                              struct scatterlist *src,
 841                              struct scatterlist *dst)
 842 {
 843         unsigned int src_nents = edesc->src_nents ? : 1;
 844         unsigned int dst_nents = edesc->dst_nents ? : 1;
 845
 846         if (src != dst) {
 847                 if (edesc->src_is_chained)
 848                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 849                 else
 850                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 851
 852                 if (dst) {
 853                         if (edesc->dst_is_chained)
 854                                 talitos_unmap_sg_chain(dev, dst,
 855                                                        DMA_FROM_DEVICE);
 856                         else
 857                                 dma_unmap_sg(dev, dst, dst_nents,
 858                                              DMA_FROM_DEVICE);
 859                 }
 860         } else
 861                 if (edesc->src_is_chained)
 862                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 863                 else
 864                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 865 }
 866
 867 static void ipsec_esp_unmap(struct device *dev,
 868                             struct talitos_edesc *edesc,
 869                             struct aead_request *areq)
 870 {
 871         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 872         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 873         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 874         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 875
 876         dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
 877
 878         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 879
 880         if (edesc->dma_len)
 881                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 882                                  DMA_BIDIRECTIONAL);
 883 }
 884
 885 /*
 886  * ipsec_esp descriptor callbacks
 887  */
 888 static void ipsec_esp_encrypt_done(struct device *dev,
 889                                    struct talitos_desc *desc, void *context,
 890                                    int err)
 891 {
 892         struct aead_request *areq = context;
 893         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 894         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 895         struct talitos_edesc *edesc;
 896         struct scatterlist *sg;
 897         void *icvdata;
 898
 899         edesc = container_of(desc, struct talitos_edesc, desc);
 900
 901         ipsec_esp_unmap(dev, edesc, areq);
 902
 903         /* copy the generated ICV to dst */
 904         if (edesc->dma_len) {
 905                 icvdata = &edesc->link_tbl[edesc->src_nents +
 906                                            edesc->dst_nents + 2];
 907                 sg = sg_last(areq->dst, edesc->dst_nents);
 908                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 909                        icvdata, ctx->authsize);
 910         }
 911
 912         kfree(edesc);
 913
 914         aead_request_complete(areq, err);
 915 }
 916
 917 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 918                                           struct talitos_desc *desc,
 919                                           void *context, int err)
 920 {
 921         struct aead_request *req = context;
 922         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 923         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 924         struct talitos_edesc *edesc;
 925         struct scatterlist *sg;
 926         void *icvdata;
 927
 928         edesc = container_of(desc, struct talitos_edesc, desc);
 929
 930         ipsec_esp_unmap(dev, edesc, req);
 931
 932         if (!err) {
 933                 /* auth check */
 934                 if (edesc->dma_len)
 935                         icvdata = &edesc->link_tbl[edesc->src_nents +
 936                                                    edesc->dst_nents + 2];
 937                 else
 938                         icvdata = &edesc->link_tbl[0];
 939
 940                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 941                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 942                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 943         }
 944
 945         kfree(edesc);
 946
 947         aead_request_complete(req, err);
 948 }
 949
 950 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 951                                           struct talitos_desc *desc,
 952                                           void *context, int err)
 953 {
 954         struct aead_request *req = context;
 955         struct talitos_edesc *edesc;
 956
 957         edesc = container_of(desc, struct talitos_edesc, desc);
 958
 959         ipsec_esp_unmap(dev, edesc, req);
 960
 961         /* check ICV auth status */
 962         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 963                      DESC_HDR_LO_ICCR1_PASS))
 964                 err = -EBADMSG;
 965
 966         kfree(edesc);
 967
 968         aead_request_complete(req, err);
 969 }
 970
 971 /*
 972  * convert scatterlist to SEC h/w link table format
 973  * stop at cryptlen bytes
 974  */
 975 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 976                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 977 {
 978         int n_sg = sg_count;
 979
 980         while (n_sg--) {
 981                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
 982                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 983                 link_tbl_ptr->j_extent = 0;
 984                 link_tbl_ptr++;
 985                 cryptlen -= sg_dma_len(sg);
 986                 sg = scatterwalk_sg_next(sg);
 987         }
 988
 989         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 990         link_tbl_ptr--;
 991         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 992                 /* Empty this entry, and move to previous one */
 993                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 994                 link_tbl_ptr->len = 0;
 995                 sg_count--;
 996                 link_tbl_ptr--;
 997         }
 998         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
 999                                         + cryptlen);
1000
1001         /* tag end of link table */
1002         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1003
1004         return sg_count;
1005 }
1006
1007 /*
1008  * fill in and submit ipsec_esp descriptor
1009  */
1010 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
1011                      u8 *giv, u64 seq,
1012                      void (*callback) (struct device *dev,
1013                                        struct talitos_desc *desc,
1014                                        void *context, int error))
1015 {
1016         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
1017         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
1018         struct device *dev = ctx->dev;
1019         struct talitos_desc *desc = &edesc->desc;
1020         unsigned int cryptlen = areq->cryptlen;
1021         unsigned int authsize = ctx->authsize;
1022         unsigned int ivsize = crypto_aead_ivsize(aead);
1023         int sg_count, ret;
1024         int sg_link_tbl_len;
1025
1026         /* hmac key */
1027         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
1028                                0, DMA_TO_DEVICE);
1029         /* hmac data */
1030         map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
1031                                sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
1032         /* cipher iv */
1033         map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
1034                                DMA_TO_DEVICE);
1035
1036         /* cipher key */
1037         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1038                                (char *)&ctx->key + ctx->authkeylen, 0,
1039                                DMA_TO_DEVICE);
1040
1041         /*
1042          * cipher in
1043          * map and adjust cipher len to aead request cryptlen.
1044          * extent is bytes of HMAC postpended to ciphertext,
1045          * typically 12 for ipsec
1046          */
1047         desc->ptr[4].len = cpu_to_be16(cryptlen);
1048         desc->ptr[4].j_extent = authsize;
1049
1050         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1051                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1052                                                            : DMA_TO_DEVICE,
1053                                   edesc->src_is_chained);
1054
1055         if (sg_count == 1) {
1056                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1057         } else {
1058                 sg_link_tbl_len = cryptlen;
1059
1060                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1061                         sg_link_tbl_len = cryptlen + authsize;
1062
1063                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1064                                           &edesc->link_tbl[0]);
1065                 if (sg_count > 1) {
1066                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1067                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1068                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1069                                                    edesc->dma_len,
1070                                                    DMA_BIDIRECTIONAL);
1071                 } else {
1072                         /* Only one segment now, so no link tbl needed */
1073                         to_talitos_ptr(&desc->ptr[4],
1074                                        sg_dma_address(areq->src));
1075                 }
1076         }
1077
1078         /* cipher out */
1079         desc->ptr[5].len = cpu_to_be16(cryptlen);
1080         desc->ptr[5].j_extent = authsize;
1081
1082         if (areq->src != areq->dst)
1083                 sg_count = talitos_map_sg(dev, areq->dst,
1084                                           edesc->dst_nents ? : 1,
1085                                           DMA_FROM_DEVICE,
1086                                           edesc->dst_is_chained);
1087
1088         if (sg_count == 1) {
1089                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1090         } else {
1091                 struct talitos_ptr *link_tbl_ptr =
1092                         &edesc->link_tbl[edesc->src_nents + 1];
1093
1094                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1095                                (edesc->src_nents + 1) *
1096                                sizeof(struct talitos_ptr));
1097                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1098                                           link_tbl_ptr);
1099
1100                 /* Add an entry to the link table for ICV data */
1101                 link_tbl_ptr += sg_count - 1;
1102                 link_tbl_ptr->j_extent = 0;
1103                 sg_count++;
1104                 link_tbl_ptr++;
1105                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1106                 link_tbl_ptr->len = cpu_to_be16(authsize);
1107
1108                 /* icv data follows link tables */
1109                 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1110                                (edesc->src_nents + edesc->dst_nents + 2) *
1111                                sizeof(struct talitos_ptr));
1112                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1113                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1114                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1115         }
1116
1117         /* iv out */
1118         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1119                                DMA_FROM_DEVICE);
1120
1121         ret = talitos_submit(dev, desc, callback, areq);
1122         if (ret != -EINPROGRESS) {
1123                 ipsec_esp_unmap(dev, edesc, areq);
1124                 kfree(edesc);
1125         }
1126         return ret;
1127 }
1128
1129 /*
1130  * derive number of elements in scatterlist
1131  */
1132 static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
1133 {
1134         struct scatterlist *sg = sg_list;
1135         int sg_nents = 0;
1136
1137         *chained = 0;
1138         while (nbytes > 0) {
1139                 sg_nents++;
1140                 nbytes -= sg->length;
1141                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1142                         *chained = 1;
1143                 sg = scatterwalk_sg_next(sg);
1144         }
1145
1146         return sg_nents;
1147 }
1148
1149 /**
1150  * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1151  * @sgl:                 The SG list
1152  * @nents:               Number of SG entries
1153  * @buf:                 Where to copy to
1154  * @buflen:              The number of bytes to copy
1155  * @skip:                The number of bytes to skip before copying.
1156  *                       Note: skip + buflen should equal SG total size.
1157  *
1158  * Returns the number of copied bytes.
1159  *
1160  **/
1161 static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1162                                     void *buf, size_t buflen, unsigned int skip)
1163 {
1164         unsigned int offset = 0;
1165         unsigned int boffset = 0;
1166         struct sg_mapping_iter miter;
1167         unsigned long flags;
1168         unsigned int sg_flags = SG_MITER_ATOMIC;
1169         size_t total_buffer = buflen + skip;
1170
1171         sg_flags |= SG_MITER_FROM_SG;
1172
1173         sg_miter_start(&miter, sgl, nents, sg_flags);
1174
1175         local_irq_save(flags);
1176
1177         while (sg_miter_next(&miter) && offset < total_buffer) {
1178                 unsigned int len;
1179                 unsigned int ignore;
1180
1181                 if ((offset + miter.length) > skip) {
1182                         if (offset < skip) {
1183                                 /* Copy part of this segment */
1184                                 ignore = skip - offset;
1185                                 len = miter.length - ignore;
1186                                 memcpy(buf + boffset, miter.addr + ignore, len);
1187                         } else {
1188                                 /* Copy all of this segment */
1189                                 len = miter.length;
1190                                 memcpy(buf + boffset, miter.addr, len);
1191                         }
1192                         boffset += len;
1193                 }
1194                 offset += miter.length;
1195         }
1196
1197         sg_miter_stop(&miter);
1198
1199         local_irq_restore(flags);
1200         return boffset;
1201 }
1202
1203 /*
1204  * allocate and map the extended descriptor
1205  */
1206 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1207                                                  struct scatterlist *src,
1208                                                  struct scatterlist *dst,
1209                                                  int hash_result,
1210                                                  unsigned int cryptlen,
1211                                                  unsigned int authsize,
1212                                                  int icv_stashing,
1213                                                  u32 cryptoflags)
1214 {
1215         struct talitos_edesc *edesc;
1216         int src_nents, dst_nents, alloc_len, dma_len;
1217         int src_chained, dst_chained = 0;
1218         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1219                       GFP_ATOMIC;
1220
1221         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1222                 dev_err(dev, "length exceeds h/w max limit\n");
1223                 return ERR_PTR(-EINVAL);
1224         }
1225
1226         src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1227         src_nents = (src_nents == 1) ? 0 : src_nents;
1228
1229         if (hash_result) {
1230                 dst_nents = 0;
1231         } else {
1232                 if (dst == src) {
1233                         dst_nents = src_nents;
1234                 } else {
1235                         dst_nents = sg_count(dst, cryptlen + authsize,
1236                                              &dst_chained);
1237                         dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1238                 }
1239         }
1240
1241         /*
1242          * allocate space for base edesc plus the link tables,
1243          * allowing for two separate entries for ICV and generated ICV (+ 2),
1244          * and the ICV data itself
1245          */
1246         alloc_len = sizeof(struct talitos_edesc);
1247         if (src_nents || dst_nents) {
1248                 dma_len = (src_nents + dst_nents + 2) *
1249                                  sizeof(struct talitos_ptr) + authsize;
1250                 alloc_len += dma_len;
1251         } else {
1252                 dma_len = 0;
1253                 alloc_len += icv_stashing ? authsize : 0;
1254         }
1255
1256         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1257         if (!edesc) {
1258                 dev_err(dev, "could not allocate edescriptor\n");
1259                 return ERR_PTR(-ENOMEM);
1260         }
1261
1262         edesc->src_nents = src_nents;
1263         edesc->dst_nents = dst_nents;
1264         edesc->src_is_chained = src_chained;
1265         edesc->dst_is_chained = dst_chained;
1266         edesc->dma_len = dma_len;
1267         if (dma_len)
1268                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1269                                                      edesc->dma_len,
1270                                                      DMA_BIDIRECTIONAL);
1271
1272         return edesc;
1273 }
1274
1275 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1276                                               int icv_stashing)
1277 {
1278         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1279         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1280
1281         return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1282                                    areq->cryptlen, ctx->authsize, icv_stashing,
1283                                    areq->base.flags);
1284 }
1285
1286 static int aead_encrypt(struct aead_request *req)
1287 {
1288         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1289         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1290         struct talitos_edesc *edesc;
1291
1292         /* allocate extended descriptor */
1293         edesc = aead_edesc_alloc(req, 0);
1294         if (IS_ERR(edesc))
1295                 return PTR_ERR(edesc);
1296
1297         /* set encrypt */
1298         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1299
1300         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1301 }
1302
1303 static int aead_decrypt(struct aead_request *req)
1304 {
1305         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1306         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1307         unsigned int authsize = ctx->authsize;
1308         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1309         struct talitos_edesc *edesc;
1310         struct scatterlist *sg;
1311         void *icvdata;
1312
1313         req->cryptlen -= authsize;
1314
1315         /* allocate extended descriptor */
1316         edesc = aead_edesc_alloc(req, 1);
1317         if (IS_ERR(edesc))
1318                 return PTR_ERR(edesc);
1319
1320         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1321             ((!edesc->src_nents && !edesc->dst_nents) ||
1322              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1323
1324                 /* decrypt and check the ICV */
1325                 edesc->desc.hdr = ctx->desc_hdr_template |
1326                                   DESC_HDR_DIR_INBOUND |
1327                                   DESC_HDR_MODE1_MDEU_CICV;
1328
1329                 /* reset integrity check result bits */
1330                 edesc->desc.hdr_lo = 0;
1331
1332                 return ipsec_esp(edesc, req, NULL, 0,
1333                                  ipsec_esp_decrypt_hwauth_done);
1334
1335         }
1336
1337         /* Have to check the ICV with software */
1338         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1339
1340         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1341         if (edesc->dma_len)
1342                 icvdata = &edesc->link_tbl[edesc->src_nents +
1343                                            edesc->dst_nents + 2];
1344         else
1345                 icvdata = &edesc->link_tbl[0];
1346
1347         sg = sg_last(req->src, edesc->src_nents ? : 1);
1348
1349         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1350                ctx->authsize);
1351
1352         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
1353 }
1354
1355 static int aead_givencrypt(struct aead_givcrypt_request *req)
1356 {
1357         struct aead_request *areq = &req->areq;
1358         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1359         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1360         struct talitos_edesc *edesc;
1361
1362         /* allocate extended descriptor */
1363         edesc = aead_edesc_alloc(areq, 0);
1364         if (IS_ERR(edesc))
1365                 return PTR_ERR(edesc);
1366
1367         /* set encrypt */
1368         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1369
1370         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1371         /* avoid consecutive packets going out with same IV */
1372         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1373
1374         return ipsec_esp(edesc, areq, req->giv, req->seq,
1375                          ipsec_esp_encrypt_done);
1376 }
1377
1378 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1379                              const u8 *key, unsigned int keylen)
1380 {
1381         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1382         struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1383
1384         if (keylen > TALITOS_MAX_KEY_SIZE)
1385                 goto badkey;
1386
1387         if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1388                 goto badkey;
1389
1390         memcpy(&ctx->key, key, keylen);
1391         ctx->keylen = keylen;
1392
1393         return 0;
1394
1395 badkey:
1396         crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1397         return -EINVAL;
1398 }
1399
1400 static void common_nonsnoop_unmap(struct device *dev,
1401                                   struct talitos_edesc *edesc,
1402                                   struct ablkcipher_request *areq)
1403 {
1404         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1405         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1406         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1407
1408         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1409
1410         if (edesc->dma_len)
1411                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1412                                  DMA_BIDIRECTIONAL);
1413 }
1414
1415 static void ablkcipher_done(struct device *dev,
1416                             struct talitos_desc *desc, void *context,
1417                             int err)
1418 {
1419         struct ablkcipher_request *areq = context;
1420         struct talitos_edesc *edesc;
1421
1422         edesc = container_of(desc, struct talitos_edesc, desc);
1423
1424         common_nonsnoop_unmap(dev, edesc, areq);
1425
1426         kfree(edesc);
1427
1428         areq->base.complete(&areq->base, err);
1429 }
1430
1431 static int common_nonsnoop(struct talitos_edesc *edesc,
1432                            struct ablkcipher_request *areq,
1433                            u8 *giv,
1434                            void (*callback) (struct device *dev,
1435                                              struct talitos_desc *desc,
1436                                              void *context, int error))
1437 {
1438         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1439         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1440         struct device *dev = ctx->dev;
1441         struct talitos_desc *desc = &edesc->desc;
1442         unsigned int cryptlen = areq->nbytes;
1443         unsigned int ivsize;
1444         int sg_count, ret;
1445
1446         /* first DWORD empty */
1447         desc->ptr[0].len = 0;
1448         to_talitos_ptr(&desc->ptr[0], 0);
1449         desc->ptr[0].j_extent = 0;
1450
1451         /* cipher iv */
1452         ivsize = crypto_ablkcipher_ivsize(cipher);
1453         map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1454                                DMA_TO_DEVICE);
1455
1456         /* cipher key */
1457         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1458                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1459
1460         /*
1461          * cipher in
1462          */
1463         desc->ptr[3].len = cpu_to_be16(cryptlen);
1464         desc->ptr[3].j_extent = 0;
1465
1466         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1467                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1468                                                            : DMA_TO_DEVICE,
1469                                   edesc->src_is_chained);
1470
1471         if (sg_count == 1) {
1472                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1473         } else {
1474                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1475                                           &edesc->link_tbl[0]);
1476                 if (sg_count > 1) {
1477                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1478                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1479                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1480                                                    edesc->dma_len,
1481                                                    DMA_BIDIRECTIONAL);
1482                 } else {
1483                         /* Only one segment now, so no link tbl needed */
1484                         to_talitos_ptr(&desc->ptr[3],
1485                                        sg_dma_address(areq->src));
1486                 }
1487         }
1488
1489         /* cipher out */
1490         desc->ptr[4].len = cpu_to_be16(cryptlen);
1491         desc->ptr[4].j_extent = 0;
1492
1493         if (areq->src != areq->dst)
1494                 sg_count = talitos_map_sg(dev, areq->dst,
1495                                           edesc->dst_nents ? : 1,
1496                                           DMA_FROM_DEVICE,
1497                                           edesc->dst_is_chained);
1498
1499         if (sg_count == 1) {
1500                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1501         } else {
1502                 struct talitos_ptr *link_tbl_ptr =
1503                         &edesc->link_tbl[edesc->src_nents + 1];
1504
1505                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1506                                               (edesc->src_nents + 1) *
1507                                               sizeof(struct talitos_ptr));
1508                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1509                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1510                                           link_tbl_ptr);
1511                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1512                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1513         }
1514
1515         /* iv out */
1516         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1517                                DMA_FROM_DEVICE);
1518
1519         /* last DWORD empty */
1520         desc->ptr[6].len = 0;
1521         to_talitos_ptr(&desc->ptr[6], 0);
1522         desc->ptr[6].j_extent = 0;
1523
1524         ret = talitos_submit(dev, desc, callback, areq);
1525         if (ret != -EINPROGRESS) {
1526                 common_nonsnoop_unmap(dev, edesc, areq);
1527                 kfree(edesc);
1528         }
1529         return ret;
1530 }
1531
1532 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1533                                                     areq)
1534 {
1535         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1536         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1537
1538         return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1539                                    areq->nbytes, 0, 0, areq->base.flags);
1540 }
1541
1542 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1543 {
1544         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1545         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1546         struct talitos_edesc *edesc;
1547
1548         /* allocate extended descriptor */
1549         edesc = ablkcipher_edesc_alloc(areq);
1550         if (IS_ERR(edesc))
1551                 return PTR_ERR(edesc);
1552
1553         /* set encrypt */
1554         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1555
1556         return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1557 }
1558
1559 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1560 {
1561         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1562         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1563         struct talitos_edesc *edesc;
1564
1565         /* allocate extended descriptor */
1566         edesc = ablkcipher_edesc_alloc(areq);
1567         if (IS_ERR(edesc))
1568                 return PTR_ERR(edesc);
1569
1570         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1571
1572         return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1573 }
1574
1575 static void common_nonsnoop_hash_unmap(struct device *dev,
1576                                        struct talitos_edesc *edesc,
1577                                        struct ahash_request *areq)
1578 {
1579         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1580
1581         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1582
1583         /* When using hashctx-in, must unmap it. */
1584         if (edesc->desc.ptr[1].len)
1585                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1586                                          DMA_TO_DEVICE);
1587
1588         if (edesc->desc.ptr[2].len)
1589                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1590                                          DMA_TO_DEVICE);
1591
1592         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1593
1594         if (edesc->dma_len)
1595                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1596                                  DMA_BIDIRECTIONAL);
1597
1598 }
1599
1600 static void ahash_done(struct device *dev,
1601                        struct talitos_desc *desc, void *context,
1602                        int err)
1603 {
1604         struct ahash_request *areq = context;
1605         struct talitos_edesc *edesc =
1606                  container_of(desc, struct talitos_edesc, desc);
1607         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1608
1609         if (!req_ctx->last && req_ctx->to_hash_later) {
1610                 /* Position any partial block for next update/final/finup */
1611                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1612         }
1613         common_nonsnoop_hash_unmap(dev, edesc, areq);
1614
1615         kfree(edesc);
1616
1617         areq->base.complete(&areq->base, err);
1618 }
1619
1620 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1621                                 struct ahash_request *areq, unsigned int length,
1622                                 void (*callback) (struct device *dev,
1623                                                   struct talitos_desc *desc,
1624                                                   void *context, int error))
1625 {
1626         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1627         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1628         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1629         struct device *dev = ctx->dev;
1630         struct talitos_desc *desc = &edesc->desc;
1631         int sg_count, ret;
1632
1633         /* first DWORD empty */
1634         desc->ptr[0] = zero_entry;
1635
1636         /* hash context in */
1637         if (!req_ctx->first || req_ctx->swinit) {
1638                 map_single_talitos_ptr(dev, &desc->ptr[1],
1639                                        req_ctx->hw_context_size,
1640                                        (char *)req_ctx->hw_context, 0,
1641                                        DMA_TO_DEVICE);
1642                 req_ctx->swinit = 0;
1643         } else {
1644                 desc->ptr[1] = zero_entry;
1645                 /* Indicate next op is not the first. */
1646                 req_ctx->first = 0;
1647         }
1648
1649         /* HMAC key */
1650         if (ctx->keylen)
1651                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1652                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1653         else
1654                 desc->ptr[2] = zero_entry;
1655
1656         /*
1657          * data in
1658          */
1659         desc->ptr[3].len = cpu_to_be16(length);
1660         desc->ptr[3].j_extent = 0;
1661
1662         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1663                                   edesc->src_nents ? : 1,
1664                                   DMA_TO_DEVICE,
1665                                   edesc->src_is_chained);
1666
1667         if (sg_count == 1) {
1668                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1669         } else {
1670                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1671                                           &edesc->link_tbl[0]);
1672                 if (sg_count > 1) {
1673                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1674                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1675                         dma_sync_single_for_device(ctx->dev,
1676                                                    edesc->dma_link_tbl,
1677                                                    edesc->dma_len,
1678                                                    DMA_BIDIRECTIONAL);
1679                 } else {
1680                         /* Only one segment now, so no link tbl needed */
1681                         to_talitos_ptr(&desc->ptr[3],
1682                                        sg_dma_address(req_ctx->psrc));
1683                 }
1684         }
1685
1686         /* fifth DWORD empty */
1687         desc->ptr[4] = zero_entry;
1688
1689         /* hash/HMAC out -or- hash context out */
1690         if (req_ctx->last)
1691                 map_single_talitos_ptr(dev, &desc->ptr[5],
1692                                        crypto_ahash_digestsize(tfm),
1693                                        areq->result, 0, DMA_FROM_DEVICE);
1694         else
1695                 map_single_talitos_ptr(dev, &desc->ptr[5],
1696                                        req_ctx->hw_context_size,
1697                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1698
1699         /* last DWORD empty */
1700         desc->ptr[6] = zero_entry;
1701
1702         ret = talitos_submit(dev, desc, callback, areq);
1703         if (ret != -EINPROGRESS) {
1704                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1705                 kfree(edesc);
1706         }
1707         return ret;
1708 }
1709
1710 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1711                                                unsigned int nbytes)
1712 {
1713         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1714         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1715         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1716
1717         return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
1718                                    nbytes, 0, 0, areq->base.flags);
1719 }
1720
1721 static int ahash_init(struct ahash_request *areq)
1722 {
1723         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1724         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1725
1726         /* Initialize the context */
1727         req_ctx->count = 0;
1728         req_ctx->first = 1; /* first indicates h/w must init its context */
1729         req_ctx->swinit = 0; /* assume h/w init of context */
1730         req_ctx->hw_context_size =
1731                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1732                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1733                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1734
1735         return 0;
1736 }
1737
1738 /*
1739  * on h/w without explicit sha224 support, we initialize h/w context
1740  * manually with sha224 constants, and tell it to run sha256.
1741  */
1742 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1743 {
1744         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1745
1746         ahash_init(areq);
1747         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1748
1749         req_ctx->hw_context[0] = cpu_to_be32(SHA224_H0);
1750         req_ctx->hw_context[1] = cpu_to_be32(SHA224_H1);
1751         req_ctx->hw_context[2] = cpu_to_be32(SHA224_H2);
1752         req_ctx->hw_context[3] = cpu_to_be32(SHA224_H3);
1753         req_ctx->hw_context[4] = cpu_to_be32(SHA224_H4);
1754         req_ctx->hw_context[5] = cpu_to_be32(SHA224_H5);
1755         req_ctx->hw_context[6] = cpu_to_be32(SHA224_H6);
1756         req_ctx->hw_context[7] = cpu_to_be32(SHA224_H7);
1757
1758         /* init 64-bit count */
1759         req_ctx->hw_context[8] = 0;
1760         req_ctx->hw_context[9] = 0;
1761
1762         return 0;
1763 }
1764
1765 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1766 {
1767         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1768         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1769         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1770         struct talitos_edesc *edesc;
1771         unsigned int blocksize =
1772                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1773         unsigned int nbytes_to_hash;
1774         unsigned int to_hash_later;
1775         unsigned int index;
1776         int chained;
1777
1778         index = req_ctx->count & (blocksize - 1);
1779         req_ctx->count += nbytes;
1780
1781         if (!req_ctx->last && (index + nbytes) < blocksize) {
1782                 /* Buffer the partial block */
1783                 sg_copy_to_buffer(areq->src,
1784                                   sg_count(areq->src, nbytes, &chained),
1785                                   req_ctx->buf + index, nbytes);
1786                 return 0;
1787         }
1788
1789         if (index) {
1790                 /* partial block from previous update; chain it in. */
1791                 sg_init_table(req_ctx->bufsl, (nbytes) ? 2 : 1);
1792                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, index);
1793                 if (nbytes)
1794                         scatterwalk_sg_chain(req_ctx->bufsl, 2,
1795                                              areq->src);
1796                 req_ctx->psrc = req_ctx->bufsl;
1797         } else {
1798                 req_ctx->psrc = areq->src;
1799         }
1800         nbytes_to_hash =  index + nbytes;
1801         if (!req_ctx->last) {
1802                 to_hash_later = (nbytes_to_hash & (blocksize - 1));
1803                 if (to_hash_later) {
1804                         int nents;
1805                         /* Must copy to_hash_later bytes from the end
1806                          * to bufnext (a partial block) for later.
1807                          */
1808                         nents = sg_count(areq->src, nbytes, &chained);
1809                         sg_copy_end_to_buffer(areq->src, nents,
1810                                               req_ctx->bufnext,
1811                                               to_hash_later,
1812                                               nbytes - to_hash_later);
1813
1814                         /* Adjust count for what will be hashed now */
1815                         nbytes_to_hash -= to_hash_later;
1816                 }
1817                 req_ctx->to_hash_later = to_hash_later;
1818         }
1819
1820         /* allocate extended descriptor */
1821         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1822         if (IS_ERR(edesc))
1823                 return PTR_ERR(edesc);
1824
1825         edesc->desc.hdr = ctx->desc_hdr_template;
1826
1827         /* On last one, request SEC to pad; otherwise continue */
1828         if (req_ctx->last)
1829                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1830         else
1831                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1832
1833         /* request SEC to INIT hash. */
1834         if (req_ctx->first && !req_ctx->swinit)
1835                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1836
1837         /* When the tfm context has a keylen, it's an HMAC.
1838          * A first or last (ie. not middle) descriptor must request HMAC.
1839          */
1840         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1841                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1842
1843         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1844                                     ahash_done);
1845 }
1846
1847 static int ahash_update(struct ahash_request *areq)
1848 {
1849         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1850
1851         req_ctx->last = 0;
1852
1853         return ahash_process_req(areq, areq->nbytes);
1854 }
1855
1856 static int ahash_final(struct ahash_request *areq)
1857 {
1858         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1859
1860         req_ctx->last = 1;
1861
1862         return ahash_process_req(areq, 0);
1863 }
1864
1865 static int ahash_finup(struct ahash_request *areq)
1866 {
1867         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1868
1869         req_ctx->last = 1;
1870
1871         return ahash_process_req(areq, areq->nbytes);
1872 }
1873
1874 static int ahash_digest(struct ahash_request *areq)
1875 {
1876         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1877         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1878
1879         ahash->init(areq);
1880         req_ctx->last = 1;
1881
1882         return ahash_process_req(areq, areq->nbytes);
1883 }
1884
1885 struct talitos_alg_template {
1886         u32 type;
1887         union {
1888                 struct crypto_alg crypto;
1889                 struct ahash_alg hash;
1890         } alg;
1891         __be32 desc_hdr_template;
1892 };
1893
1894 static struct talitos_alg_template driver_algs[] = {
1895         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1896         {       .type = CRYPTO_ALG_TYPE_AEAD,
1897                 .alg.crypto = {
1898                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1899                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1900                         .cra_blocksize = AES_BLOCK_SIZE,
1901                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1902                         .cra_type = &crypto_aead_type,
1903                         .cra_aead = {
1904                                 .setkey = aead_setkey,
1905                                 .setauthsize = aead_setauthsize,
1906                                 .encrypt = aead_encrypt,
1907                                 .decrypt = aead_decrypt,
1908                                 .givencrypt = aead_givencrypt,
1909                                 .geniv = "<built-in>",
1910                                 .ivsize = AES_BLOCK_SIZE,
1911                                 .maxauthsize = SHA1_DIGEST_SIZE,
1912                         }
1913                 },
1914                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1915                                      DESC_HDR_SEL0_AESU |
1916                                      DESC_HDR_MODE0_AESU_CBC |
1917                                      DESC_HDR_SEL1_MDEUA |
1918                                      DESC_HDR_MODE1_MDEU_INIT |
1919                                      DESC_HDR_MODE1_MDEU_PAD |
1920                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1921         },
1922         {       .type = CRYPTO_ALG_TYPE_AEAD,
1923                 .alg.crypto = {
1924                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1925                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1926                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1927                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1928                         .cra_type = &crypto_aead_type,
1929                         .cra_aead = {
1930                                 .setkey = aead_setkey,
1931                                 .setauthsize = aead_setauthsize,
1932                                 .encrypt = aead_encrypt,
1933                                 .decrypt = aead_decrypt,
1934                                 .givencrypt = aead_givencrypt,
1935                                 .geniv = "<built-in>",
1936                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1937                                 .maxauthsize = SHA1_DIGEST_SIZE,
1938                         }
1939                 },
1940                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1941                                      DESC_HDR_SEL0_DEU |
1942                                      DESC_HDR_MODE0_DEU_CBC |
1943                                      DESC_HDR_MODE0_DEU_3DES |
1944                                      DESC_HDR_SEL1_MDEUA |
1945                                      DESC_HDR_MODE1_MDEU_INIT |
1946                                      DESC_HDR_MODE1_MDEU_PAD |
1947                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1948         },
1949         {       .type = CRYPTO_ALG_TYPE_AEAD,
1950                 .alg.crypto = {
1951                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1952                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1953                         .cra_blocksize = AES_BLOCK_SIZE,
1954                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1955                         .cra_type = &crypto_aead_type,
1956                         .cra_aead = {
1957                                 .setkey = aead_setkey,
1958                                 .setauthsize = aead_setauthsize,
1959                                 .encrypt = aead_encrypt,
1960                                 .decrypt = aead_decrypt,
1961                                 .givencrypt = aead_givencrypt,
1962                                 .geniv = "<built-in>",
1963                                 .ivsize = AES_BLOCK_SIZE,
1964                                 .maxauthsize = SHA256_DIGEST_SIZE,
1965                         }
1966                 },
1967                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1968                                      DESC_HDR_SEL0_AESU |
1969                                      DESC_HDR_MODE0_AESU_CBC |
1970                                      DESC_HDR_SEL1_MDEUA |
1971                                      DESC_HDR_MODE1_MDEU_INIT |
1972                                      DESC_HDR_MODE1_MDEU_PAD |
1973                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1974         },
1975         {       .type = CRYPTO_ALG_TYPE_AEAD,
1976                 .alg.crypto = {
1977                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1978                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1979                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1980                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1981                         .cra_type = &crypto_aead_type,
1982                         .cra_aead = {
1983                                 .setkey = aead_setkey,
1984                                 .setauthsize = aead_setauthsize,
1985                                 .encrypt = aead_encrypt,
1986                                 .decrypt = aead_decrypt,
1987                                 .givencrypt = aead_givencrypt,
1988                                 .geniv = "<built-in>",
1989                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1990                                 .maxauthsize = SHA256_DIGEST_SIZE,
1991                         }
1992                 },
1993                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1994                                      DESC_HDR_SEL0_DEU |
1995                                      DESC_HDR_MODE0_DEU_CBC |
1996                                      DESC_HDR_MODE0_DEU_3DES |
1997                                      DESC_HDR_SEL1_MDEUA |
1998                                      DESC_HDR_MODE1_MDEU_INIT |
1999                                      DESC_HDR_MODE1_MDEU_PAD |
2000                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2001         },
2002         {       .type = CRYPTO_ALG_TYPE_AEAD,
2003                 .alg.crypto = {
2004                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2005                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2006                         .cra_blocksize = AES_BLOCK_SIZE,
2007                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2008                         .cra_type = &crypto_aead_type,
2009                         .cra_aead = {
2010                                 .setkey = aead_setkey,
2011                                 .setauthsize = aead_setauthsize,
2012                                 .encrypt = aead_encrypt,
2013                                 .decrypt = aead_decrypt,
2014                                 .givencrypt = aead_givencrypt,
2015                                 .geniv = "<built-in>",
2016                                 .ivsize = AES_BLOCK_SIZE,
2017                                 .maxauthsize = MD5_DIGEST_SIZE,
2018                         }
2019                 },
2020                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2021                                      DESC_HDR_SEL0_AESU |
2022                                      DESC_HDR_MODE0_AESU_CBC |
2023                                      DESC_HDR_SEL1_MDEUA |
2024                                      DESC_HDR_MODE1_MDEU_INIT |
2025                                      DESC_HDR_MODE1_MDEU_PAD |
2026                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2027         },
2028         {       .type = CRYPTO_ALG_TYPE_AEAD,
2029                 .alg.crypto = {
2030                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2031                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2032                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2033                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2034                         .cra_type = &crypto_aead_type,
2035                         .cra_aead = {
2036                                 .setkey = aead_setkey,
2037                                 .setauthsize = aead_setauthsize,
2038                                 .encrypt = aead_encrypt,
2039                                 .decrypt = aead_decrypt,
2040                                 .givencrypt = aead_givencrypt,
2041                                 .geniv = "<built-in>",
2042                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2043                                 .maxauthsize = MD5_DIGEST_SIZE,
2044                         }
2045                 },
2046                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2047                                      DESC_HDR_SEL0_DEU |
2048                                      DESC_HDR_MODE0_DEU_CBC |
2049                                      DESC_HDR_MODE0_DEU_3DES |
2050                                      DESC_HDR_SEL1_MDEUA |
2051                                      DESC_HDR_MODE1_MDEU_INIT |
2052                                      DESC_HDR_MODE1_MDEU_PAD |
2053                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2054         },
2055         /* ABLKCIPHER algorithms. */
2056         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2057                 .alg.crypto = {
2058                         .cra_name = "cbc(aes)",
2059                         .cra_driver_name = "cbc-aes-talitos",
2060                         .cra_blocksize = AES_BLOCK_SIZE,
2061                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2062                                      CRYPTO_ALG_ASYNC,
2063                         .cra_type = &crypto_ablkcipher_type,
2064                         .cra_ablkcipher = {
2065                                 .setkey = ablkcipher_setkey,
2066                                 .encrypt = ablkcipher_encrypt,
2067                                 .decrypt = ablkcipher_decrypt,
2068                                 .geniv = "eseqiv",
2069                                 .min_keysize = AES_MIN_KEY_SIZE,
2070                                 .max_keysize = AES_MAX_KEY_SIZE,
2071                                 .ivsize = AES_BLOCK_SIZE,
2072                         }
2073                 },
2074                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2075                                      DESC_HDR_SEL0_AESU |
2076                                      DESC_HDR_MODE0_AESU_CBC,
2077         },
2078         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2079                 .alg.crypto = {
2080                         .cra_name = "cbc(des3_ede)",
2081                         .cra_driver_name = "cbc-3des-talitos",
2082                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2083                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2084                                      CRYPTO_ALG_ASYNC,
2085                         .cra_type = &crypto_ablkcipher_type,
2086                         .cra_ablkcipher = {
2087                                 .setkey = ablkcipher_setkey,
2088                                 .encrypt = ablkcipher_encrypt,
2089                                 .decrypt = ablkcipher_decrypt,
2090                                 .geniv = "eseqiv",
2091                                 .min_keysize = DES3_EDE_KEY_SIZE,
2092                                 .max_keysize = DES3_EDE_KEY_SIZE,
2093                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2094                         }
2095                 },
2096                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2097                                      DESC_HDR_SEL0_DEU |
2098                                      DESC_HDR_MODE0_DEU_CBC |
2099                                      DESC_HDR_MODE0_DEU_3DES,
2100         },
2101         /* AHASH algorithms. */
2102         {       .type = CRYPTO_ALG_TYPE_AHASH,
2103                 .alg.hash = {
2104                         .init = ahash_init,
2105                         .update = ahash_update,
2106                         .final = ahash_final,
2107                         .finup = ahash_finup,
2108                         .digest = ahash_digest,
2109                         .halg.digestsize = MD5_DIGEST_SIZE,
2110                         .halg.base = {
2111                                 .cra_name = "md5",
2112                                 .cra_driver_name = "md5-talitos",
2113                                 .cra_blocksize = MD5_BLOCK_SIZE,
2114                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2115                                              CRYPTO_ALG_ASYNC,
2116                                 .cra_type = &crypto_ahash_type
2117                         }
2118                 },
2119                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2120                                      DESC_HDR_SEL0_MDEUA |
2121                                      DESC_HDR_MODE0_MDEU_MD5,
2122         },
2123         {       .type = CRYPTO_ALG_TYPE_AHASH,
2124                 .alg.hash = {
2125                         .init = ahash_init,
2126                         .update = ahash_update,
2127                         .final = ahash_final,
2128                         .finup = ahash_finup,
2129                         .digest = ahash_digest,
2130                         .halg.digestsize = SHA1_DIGEST_SIZE,
2131                         .halg.base = {
2132                                 .cra_name = "sha1",
2133                                 .cra_driver_name = "sha1-talitos",
2134                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2135                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2136                                              CRYPTO_ALG_ASYNC,
2137                                 .cra_type = &crypto_ahash_type
2138                         }
2139                 },
2140                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2141                                      DESC_HDR_SEL0_MDEUA |
2142                                      DESC_HDR_MODE0_MDEU_SHA1,
2143         },
2144         {       .type = CRYPTO_ALG_TYPE_AHASH,
2145                 .alg.hash = {
2146                         .init = ahash_init,
2147                         .update = ahash_update,
2148                         .final = ahash_final,
2149                         .finup = ahash_finup,
2150                         .digest = ahash_digest,
2151                         .halg.digestsize = SHA224_DIGEST_SIZE,
2152                         .halg.base = {
2153                                 .cra_name = "sha224",
2154                                 .cra_driver_name = "sha224-talitos",
2155                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2156                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2157                                              CRYPTO_ALG_ASYNC,
2158                                 .cra_type = &crypto_ahash_type
2159                         }
2160                 },
2161                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2162                                      DESC_HDR_SEL0_MDEUA |
2163                                      DESC_HDR_MODE0_MDEU_SHA224,
2164         },
2165         {       .type = CRYPTO_ALG_TYPE_AHASH,
2166                 .alg.hash = {
2167                         .init = ahash_init,
2168                         .update = ahash_update,
2169                         .final = ahash_final,
2170                         .finup = ahash_finup,
2171                         .digest = ahash_digest,
2172                         .halg.digestsize = SHA256_DIGEST_SIZE,
2173                         .halg.base = {
2174                                 .cra_name = "sha256",
2175                                 .cra_driver_name = "sha256-talitos",
2176                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2177                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2178                                              CRYPTO_ALG_ASYNC,
2179                                 .cra_type = &crypto_ahash_type
2180                         }
2181                 },
2182                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2183                                      DESC_HDR_SEL0_MDEUA |
2184                                      DESC_HDR_MODE0_MDEU_SHA256,
2185         },
2186         {       .type = CRYPTO_ALG_TYPE_AHASH,
2187                 .alg.hash = {
2188                         .init = ahash_init,
2189                         .update = ahash_update,
2190                         .final = ahash_final,
2191                         .finup = ahash_finup,
2192                         .digest = ahash_digest,
2193                         .halg.digestsize = SHA384_DIGEST_SIZE,
2194                         .halg.base = {
2195                                 .cra_name = "sha384",
2196                                 .cra_driver_name = "sha384-talitos",
2197                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2198                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2199                                              CRYPTO_ALG_ASYNC,
2200                                 .cra_type = &crypto_ahash_type
2201                         }
2202                 },
2203                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2204                                      DESC_HDR_SEL0_MDEUB |
2205                                      DESC_HDR_MODE0_MDEUB_SHA384,
2206         },
2207         {       .type = CRYPTO_ALG_TYPE_AHASH,
2208                 .alg.hash = {
2209                         .init = ahash_init,
2210                         .update = ahash_update,
2211                         .final = ahash_final,
2212                         .finup = ahash_finup,
2213                         .digest = ahash_digest,
2214                         .halg.digestsize = SHA512_DIGEST_SIZE,
2215                         .halg.base = {
2216                                 .cra_name = "sha512",
2217                                 .cra_driver_name = "sha512-talitos",
2218                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2219                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2220                                              CRYPTO_ALG_ASYNC,
2221                                 .cra_type = &crypto_ahash_type
2222                         }
2223                 },
2224                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2225                                      DESC_HDR_SEL0_MDEUB |
2226                                      DESC_HDR_MODE0_MDEUB_SHA512,
2227         },
2228 };
2229
2230 struct talitos_crypto_alg {
2231         struct list_head entry;
2232         struct device *dev;
2233         struct talitos_alg_template algt;
2234 };
2235
2236 static int talitos_cra_init(struct crypto_tfm *tfm)
2237 {
2238         struct crypto_alg *alg = tfm->__crt_alg;
2239         struct talitos_crypto_alg *talitos_alg;
2240         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2241
2242         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2243                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2244                                            struct talitos_crypto_alg,
2245                                            algt.alg.hash);
2246         else
2247                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2248                                            algt.alg.crypto);
2249
2250         /* update context with ptr to dev */
2251         ctx->dev = talitos_alg->dev;
2252
2253         /* copy descriptor header template value */
2254         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2255
2256         return 0;
2257 }
2258
2259 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2260 {
2261         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2262
2263         talitos_cra_init(tfm);
2264
2265         /* random first IV */
2266         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2267
2268         return 0;
2269 }
2270
2271 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2272 {
2273         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2274
2275         talitos_cra_init(tfm);
2276
2277         ctx->keylen = 0;
2278         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2279                                  sizeof(struct talitos_ahash_req_ctx));
2280
2281         return 0;
2282 }
2283
2284 /*
2285  * given the alg's descriptor header template, determine whether descriptor
2286  * type and primary/secondary execution units required match the hw
2287  * capabilities description provided in the device tree node.
2288  */
2289 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2290 {
2291         struct talitos_private *priv = dev_get_drvdata(dev);
2292         int ret;
2293
2294         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2295               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2296
2297         if (SECONDARY_EU(desc_hdr_template))
2298                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2299                               & priv->exec_units);
2300
2301         return ret;
2302 }
2303
2304 static int talitos_remove(struct of_device *ofdev)
2305 {
2306         struct device *dev = &ofdev->dev;
2307         struct talitos_private *priv = dev_get_drvdata(dev);
2308         struct talitos_crypto_alg *t_alg, *n;
2309         int i;
2310
2311         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2312                 switch (t_alg->algt.type) {
2313                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2314                 case CRYPTO_ALG_TYPE_AEAD:
2315                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2316                         break;
2317                 case CRYPTO_ALG_TYPE_AHASH:
2318                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2319                         break;
2320                 }
2321                 list_del(&t_alg->entry);
2322                 kfree(t_alg);
2323         }
2324
2325         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2326                 talitos_unregister_rng(dev);
2327
2328         for (i = 0; i < priv->num_channels; i++)
2329                 if (priv->chan[i].fifo)
2330                         kfree(priv->chan[i].fifo);
2331
2332         kfree(priv->chan);
2333
2334         if (priv->irq != NO_IRQ) {
2335                 free_irq(priv->irq, dev);
2336                 irq_dispose_mapping(priv->irq);
2337         }
2338
2339         tasklet_kill(&priv->done_task);
2340
2341         iounmap(priv->reg);
2342
2343         dev_set_drvdata(dev, NULL);
2344
2345         kfree(priv);
2346
2347         return 0;
2348 }
2349
2350 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2351                                                     struct talitos_alg_template
2352                                                            *template)
2353 {
2354         struct talitos_private *priv = dev_get_drvdata(dev);
2355         struct talitos_crypto_alg *t_alg;
2356         struct crypto_alg *alg;
2357
2358         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2359         if (!t_alg)
2360                 return ERR_PTR(-ENOMEM);
2361
2362         t_alg->algt = *template;
2363
2364         switch (t_alg->algt.type) {
2365         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2366                 alg = &t_alg->algt.alg.crypto;
2367                 alg->cra_init = talitos_cra_init;
2368                 break;
2369         case CRYPTO_ALG_TYPE_AEAD:
2370                 alg = &t_alg->algt.alg.crypto;
2371                 alg->cra_init = talitos_cra_init_aead;
2372                 break;
2373         case CRYPTO_ALG_TYPE_AHASH:
2374                 alg = &t_alg->algt.alg.hash.halg.base;
2375                 alg->cra_init = talitos_cra_init_ahash;
2376                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2377                     !strcmp(alg->cra_name, "sha224")) {
2378                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2379                         t_alg->algt.desc_hdr_template =
2380                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2381                                         DESC_HDR_SEL0_MDEUA |
2382                                         DESC_HDR_MODE0_MDEU_SHA256;
2383                 }
2384                 break;
2385         }
2386
2387         alg->cra_module = THIS_MODULE;
2388         alg->cra_priority = TALITOS_CRA_PRIORITY;
2389         alg->cra_alignmask = 0;
2390         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2391
2392         t_alg->dev = dev;
2393
2394         return t_alg;
2395 }
2396
2397 static int talitos_probe(struct of_device *ofdev,
2398                          const struct of_device_id *match)
2399 {
2400         struct device *dev = &ofdev->dev;
2401         struct device_node *np = ofdev->dev.of_node;
2402         struct talitos_private *priv;
2403         const unsigned int *prop;
2404         int i, err;
2405
2406         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2407         if (!priv)
2408                 return -ENOMEM;
2409
2410         dev_set_drvdata(dev, priv);
2411
2412         priv->ofdev = ofdev;
2413
2414         tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
2415
2416         INIT_LIST_HEAD(&priv->alg_list);
2417
2418         priv->irq = irq_of_parse_and_map(np, 0);
2419
2420         if (priv->irq == NO_IRQ) {
2421                 dev_err(dev, "failed to map irq\n");
2422                 err = -EINVAL;
2423                 goto err_out;
2424         }
2425
2426         /* get the irq line */
2427         err = request_irq(priv->irq, talitos_interrupt, 0,
2428                           dev_driver_string(dev), dev);
2429         if (err) {
2430                 dev_err(dev, "failed to request irq %d\n", priv->irq);
2431                 irq_dispose_mapping(priv->irq);
2432                 priv->irq = NO_IRQ;
2433                 goto err_out;
2434         }
2435
2436         priv->reg = of_iomap(np, 0);
2437         if (!priv->reg) {
2438                 dev_err(dev, "failed to of_iomap\n");
2439                 err = -ENOMEM;
2440                 goto err_out;
2441         }
2442
2443         /* get SEC version capabilities from device tree */
2444         prop = of_get_property(np, "fsl,num-channels", NULL);
2445         if (prop)
2446                 priv->num_channels = *prop;
2447
2448         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2449         if (prop)
2450                 priv->chfifo_len = *prop;
2451
2452         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2453         if (prop)
2454                 priv->exec_units = *prop;
2455
2456         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2457         if (prop)
2458                 priv->desc_types = *prop;
2459
2460         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2461             !priv->exec_units || !priv->desc_types) {
2462                 dev_err(dev, "invalid property data in device tree node\n");
2463                 err = -EINVAL;
2464                 goto err_out;
2465         }
2466
2467         if (of_device_is_compatible(np, "fsl,sec3.0"))
2468                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2469
2470         if (of_device_is_compatible(np, "fsl,sec2.1"))
2471                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2472                                   TALITOS_FTR_SHA224_HWINIT;
2473
2474         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2475                              priv->num_channels, GFP_KERNEL);
2476         if (!priv->chan) {
2477                 dev_err(dev, "failed to allocate channel management space\n");
2478                 err = -ENOMEM;
2479                 goto err_out;
2480         }
2481
2482         for (i = 0; i < priv->num_channels; i++) {
2483                 spin_lock_init(&priv->chan[i].head_lock);
2484                 spin_lock_init(&priv->chan[i].tail_lock);
2485         }
2486
2487         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2488
2489         for (i = 0; i < priv->num_channels; i++) {
2490                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2491                                              priv->fifo_len, GFP_KERNEL);
2492                 if (!priv->chan[i].fifo) {
2493                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2494                         err = -ENOMEM;
2495                         goto err_out;
2496                 }
2497         }
2498
2499         for (i = 0; i < priv->num_channels; i++)
2500                 atomic_set(&priv->chan[i].submit_count,
2501                            -(priv->chfifo_len - 1));
2502
2503         dma_set_mask(dev, DMA_BIT_MASK(36));
2504
2505         /* reset and initialize the h/w */
2506         err = init_device(dev);
2507         if (err) {
2508                 dev_err(dev, "failed to initialize device\n");
2509                 goto err_out;
2510         }
2511
2512         /* register the RNG, if available */
2513         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2514                 err = talitos_register_rng(dev);
2515                 if (err) {
2516                         dev_err(dev, "failed to register hwrng: %d\n", err);
2517                         goto err_out;
2518                 } else
2519                         dev_info(dev, "hwrng\n");
2520         }
2521
2522         /* register crypto algorithms the device supports */
2523         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2524                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2525                         struct talitos_crypto_alg *t_alg;
2526                         char *name = NULL;
2527
2528                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2529                         if (IS_ERR(t_alg)) {
2530                                 err = PTR_ERR(t_alg);
2531                                 goto err_out;
2532                         }
2533
2534                         switch (t_alg->algt.type) {
2535                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2536                         case CRYPTO_ALG_TYPE_AEAD:
2537                                 err = crypto_register_alg(
2538                                                 &t_alg->algt.alg.crypto);
2539                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2540                                 break;
2541                         case CRYPTO_ALG_TYPE_AHASH:
2542                                 err = crypto_register_ahash(
2543                                                 &t_alg->algt.alg.hash);
2544                                 name =
2545                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2546                                 break;
2547                         }
2548                         if (err) {
2549                                 dev_err(dev, "%s alg registration failed\n",
2550                                         name);
2551                                 kfree(t_alg);
2552                         } else {
2553                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2554                                 dev_info(dev, "%s\n", name);
2555                         }
2556                 }
2557         }
2558
2559         return 0;
2560
2561 err_out:
2562         talitos_remove(ofdev);
2563
2564         return err;
2565 }
2566
2567 static const struct of_device_id talitos_match[] = {
2568         {
2569                 .compatible = "fsl,sec2.0",
2570         },
2571         {},
2572 };
2573 MODULE_DEVICE_TABLE(of, talitos_match);
2574
2575 static struct of_platform_driver talitos_driver = {
2576         .driver = {
2577                 .name = "talitos",
2578                 .owner = THIS_MODULE,
2579                 .of_match_table = talitos_match,
2580         },
2581         .probe = talitos_probe,
2582         .remove = talitos_remove,
2583 };
2584
2585 static int __init talitos_init(void)
2586 {
2587         return of_register_platform_driver(&talitos_driver);
2588 }
2589 module_init(talitos_init);
2590
2591 static void __exit talitos_exit(void)
2592 {
2593         of_unregister_platform_driver(&talitos_driver);
2594 }
2595 module_exit(talitos_exit);
2596
2597 MODULE_LICENSE("GPL");
2598 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2599 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");