2 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
4 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
5 * Author: Arnaud Ebalard <arno@natisbad.org>
7 * This work is based on an initial version written by
8 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <crypto/md5.h>
16 #include <crypto/sha.h>
20 struct mv_cesa_ahash_dma_iter {
21 struct mv_cesa_dma_iter base;
22 struct mv_cesa_sg_dma_iter src;
26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
27 struct ahash_request *req)
29 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
30 unsigned int len = req->nbytes + creq->cache_ptr;
33 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
35 mv_cesa_req_dma_iter_init(&iter->base, len);
36 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
37 iter->src.op_offset = creq->cache_ptr;
41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
43 iter->src.op_offset = 0;
45 return mv_cesa_req_dma_iter_next_op(&iter->base);
49 mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags)
51 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
60 mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req)
65 dma_pool_free(cesa_dev->dma->cache_pool, req->cache,
69 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
75 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
83 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
88 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
93 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
95 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
97 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
100 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
102 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
104 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
105 mv_cesa_ahash_dma_free_cache(&creq->req.dma);
106 mv_cesa_dma_cleanup(&creq->base);
109 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
111 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
113 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
114 mv_cesa_ahash_dma_cleanup(req);
117 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
119 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
121 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
122 mv_cesa_ahash_dma_last_cleanup(req);
125 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
127 unsigned int index, padlen;
129 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
130 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
135 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
137 unsigned int index, padlen;
140 /* Pad out to 56 mod 64 */
141 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
142 padlen = mv_cesa_ahash_pad_len(creq);
143 memset(buf + 1, 0, padlen - 1);
146 __le64 bits = cpu_to_le64(creq->len << 3);
147 memcpy(buf + padlen, &bits, sizeof(bits));
149 __be64 bits = cpu_to_be64(creq->len << 3);
150 memcpy(buf + padlen, &bits, sizeof(bits));
156 static void mv_cesa_ahash_std_step(struct ahash_request *req)
158 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
159 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
160 struct mv_cesa_engine *engine = creq->base.engine;
161 struct mv_cesa_op_ctx *op;
162 unsigned int new_cache_ptr = 0;
165 unsigned int digsize;
168 mv_cesa_adjust_op(engine, &creq->op_tmpl);
169 memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
172 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
173 for (i = 0; i < digsize / 4; i++)
174 writel_relaxed(creq->state[i], engine->regs + CESA_IVDIG(i));
178 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
179 creq->cache, creq->cache_ptr);
181 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
182 CESA_SA_SRAM_PAYLOAD_SIZE);
184 if (!creq->last_req) {
185 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
186 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
189 if (len - creq->cache_ptr)
190 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
192 CESA_SA_DATA_SRAM_OFFSET +
194 len - creq->cache_ptr,
199 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
201 if (creq->last_req && sreq->offset == req->nbytes &&
202 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
203 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
204 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
205 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
206 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
209 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
210 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
212 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
213 mv_cesa_set_mac_op_total_len(op, creq->len);
215 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
217 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
218 len &= CESA_HASH_BLOCK_SIZE_MSK;
219 new_cache_ptr = 64 - trailerlen;
220 memcpy_fromio(creq->cache,
222 CESA_SA_DATA_SRAM_OFFSET + len,
225 len += mv_cesa_ahash_pad_req(creq,
227 CESA_SA_DATA_SRAM_OFFSET);
230 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
231 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
233 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
237 mv_cesa_set_mac_op_frag_len(op, len);
238 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
240 /* FIXME: only update enc_len field */
241 memcpy_toio(engine->sram, op, sizeof(*op));
243 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
244 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
245 CESA_SA_DESC_CFG_FRAG_MSK);
247 creq->cache_ptr = new_cache_ptr;
249 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
250 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
251 BUG_ON(readl(engine->regs + CESA_SA_CMD) &
252 CESA_SA_CMD_EN_CESA_SA_ACCL0);
253 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
256 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
258 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
259 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
261 if (sreq->offset < (req->nbytes - creq->cache_ptr))
267 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
269 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
270 struct mv_cesa_req *basereq = &creq->base;
272 mv_cesa_dma_prepare(basereq, basereq->engine);
275 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
277 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
278 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
283 static void mv_cesa_ahash_step(struct crypto_async_request *req)
285 struct ahash_request *ahashreq = ahash_request_cast(req);
286 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
288 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
289 mv_cesa_dma_step(&creq->base);
291 mv_cesa_ahash_std_step(ahashreq);
294 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
296 struct ahash_request *ahashreq = ahash_request_cast(req);
297 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
299 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
300 return mv_cesa_dma_process(&creq->base, status);
302 return mv_cesa_ahash_std_process(ahashreq, status);
305 static void mv_cesa_ahash_complete(struct crypto_async_request *req)
307 struct ahash_request *ahashreq = ahash_request_cast(req);
308 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
309 struct mv_cesa_engine *engine = creq->base.engine;
310 unsigned int digsize;
313 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
314 for (i = 0; i < digsize / 4; i++)
315 creq->state[i] = readl_relaxed(engine->regs + CESA_IVDIG(i));
317 if (creq->last_req) {
319 * Hardware's MD5 digest is in little endian format, but
320 * SHA in big endian format
323 __le32 *result = (void *)ahashreq->result;
325 for (i = 0; i < digsize / 4; i++)
326 result[i] = cpu_to_le32(creq->state[i]);
328 __be32 *result = (void *)ahashreq->result;
330 for (i = 0; i < digsize / 4; i++)
331 result[i] = cpu_to_be32(creq->state[i]);
335 atomic_sub(ahashreq->nbytes, &engine->load);
338 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
339 struct mv_cesa_engine *engine)
341 struct ahash_request *ahashreq = ahash_request_cast(req);
342 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
344 creq->base.engine = engine;
346 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
347 mv_cesa_ahash_dma_prepare(ahashreq);
349 mv_cesa_ahash_std_prepare(ahashreq);
352 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
354 struct ahash_request *ahashreq = ahash_request_cast(req);
355 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
358 mv_cesa_ahash_last_cleanup(ahashreq);
360 mv_cesa_ahash_cleanup(ahashreq);
363 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
366 ahashreq->nbytes - creq->cache_ptr);
369 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
370 .step = mv_cesa_ahash_step,
371 .process = mv_cesa_ahash_process,
372 .cleanup = mv_cesa_ahash_req_cleanup,
373 .complete = mv_cesa_ahash_complete,
376 static void mv_cesa_ahash_init(struct ahash_request *req,
377 struct mv_cesa_op_ctx *tmpl, bool algo_le)
379 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
381 memset(creq, 0, sizeof(*creq));
382 mv_cesa_update_op_cfg(tmpl,
383 CESA_SA_DESC_CFG_OP_MAC_ONLY |
384 CESA_SA_DESC_CFG_FIRST_FRAG,
385 CESA_SA_DESC_CFG_OP_MSK |
386 CESA_SA_DESC_CFG_FRAG_MSK);
387 mv_cesa_set_mac_op_total_len(tmpl, 0);
388 mv_cesa_set_mac_op_frag_len(tmpl, 0);
389 creq->op_tmpl = *tmpl;
391 creq->algo_le = algo_le;
394 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
396 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
398 ctx->base.ops = &mv_cesa_ahash_req_ops;
400 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
401 sizeof(struct mv_cesa_ahash_req));
405 static bool mv_cesa_ahash_cache_req(struct ahash_request *req)
407 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
410 if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && !creq->last_req) {
416 sg_pcopy_to_buffer(req->src, creq->src_nents,
417 creq->cache + creq->cache_ptr,
420 creq->cache_ptr += req->nbytes;
426 static struct mv_cesa_op_ctx *
427 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
428 struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
431 struct mv_cesa_op_ctx *op;
434 op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
438 /* Set the operation block fragment length. */
439 mv_cesa_set_mac_op_frag_len(op, frag_len);
441 /* Append dummy desc to launch operation */
442 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
446 if (mv_cesa_mac_op_is_first_frag(tmpl))
447 mv_cesa_update_op_cfg(tmpl,
448 CESA_SA_DESC_CFG_MID_FRAG,
449 CESA_SA_DESC_CFG_FRAG_MSK);
455 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
456 struct mv_cesa_ahash_req *creq,
459 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
462 if (!creq->cache_ptr)
465 ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags);
469 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr);
471 return mv_cesa_dma_add_data_transfer(chain,
472 CESA_SA_DATA_SRAM_OFFSET,
473 ahashdreq->cache_dma,
475 CESA_TDMA_DST_IN_SRAM,
479 static struct mv_cesa_op_ctx *
480 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
481 struct mv_cesa_ahash_dma_iter *dma_iter,
482 struct mv_cesa_ahash_req *creq,
483 unsigned int frag_len, gfp_t flags)
485 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
486 unsigned int len, trailerlen, padoff = 0;
487 struct mv_cesa_op_ctx *op;
491 * If the transfer is smaller than our maximum length, and we have
492 * some data outstanding, we can ask the engine to finish the hash.
494 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
495 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
500 mv_cesa_set_mac_op_total_len(op, creq->len);
501 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
502 CESA_SA_DESC_CFG_NOT_FRAG :
503 CESA_SA_DESC_CFG_LAST_FRAG,
504 CESA_SA_DESC_CFG_FRAG_MSK);
510 * The request is longer than the engine can handle, or we have
511 * no data outstanding. Manually generate the padding, adding it
512 * as a "mid" fragment.
514 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
518 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
520 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
522 ret = mv_cesa_dma_add_data_transfer(chain,
523 CESA_SA_DATA_SRAM_OFFSET +
525 ahashdreq->padding_dma,
526 len, CESA_TDMA_DST_IN_SRAM,
531 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
536 if (len == trailerlen)
542 ret = mv_cesa_dma_add_data_transfer(chain,
543 CESA_SA_DATA_SRAM_OFFSET,
544 ahashdreq->padding_dma +
547 CESA_TDMA_DST_IN_SRAM,
552 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
556 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
558 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
559 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
560 GFP_KERNEL : GFP_ATOMIC;
561 struct mv_cesa_req *basereq = &creq->base;
562 struct mv_cesa_ahash_dma_iter iter;
563 struct mv_cesa_op_ctx *op = NULL;
564 unsigned int frag_len;
567 basereq->chain.first = NULL;
568 basereq->chain.last = NULL;
570 if (creq->src_nents) {
571 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
579 mv_cesa_tdma_desc_iter_init(&basereq->chain);
580 mv_cesa_ahash_req_iter_init(&iter, req);
583 * Add the cache (left-over data from a previous block) first.
584 * This will never overflow the SRAM size.
586 ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags);
592 * Add all the new data, inserting an operation block and
593 * launch command between each full SRAM block-worth of
594 * data. We intentionally do not add the final op block.
597 ret = mv_cesa_dma_add_op_transfers(&basereq->chain,
603 frag_len = iter.base.op_len;
605 if (!mv_cesa_ahash_req_iter_next_op(&iter))
608 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
616 /* Account for the data that was in the cache. */
617 frag_len = iter.base.op_len;
621 * At this point, frag_len indicates whether we have any data
622 * outstanding which needs an operation. Queue up the final
623 * operation, which depends whether this is the final request.
626 op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq,
629 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
638 /* Add dummy desc to wait for crypto operation end */
639 ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);
645 creq->cache_ptr = req->nbytes + creq->cache_ptr -
650 basereq->chain.last->flags |= (CESA_TDMA_END_OF_REQ |
651 CESA_TDMA_BREAK_CHAIN);
656 mv_cesa_dma_cleanup(basereq);
657 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
660 mv_cesa_ahash_last_cleanup(req);
665 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
667 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
669 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
670 if (creq->src_nents < 0) {
671 dev_err(cesa_dev->dev, "Invalid number of src SG");
672 return creq->src_nents;
675 *cached = mv_cesa_ahash_cache_req(req);
680 if (cesa_dev->caps->has_tdma)
681 return mv_cesa_ahash_dma_req_init(req);
686 static int mv_cesa_ahash_queue_req(struct ahash_request *req)
688 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
689 struct mv_cesa_engine *engine;
693 ret = mv_cesa_ahash_req_init(req, &cached);
700 engine = mv_cesa_select_engine(req->nbytes);
701 mv_cesa_ahash_prepare(&req->base, engine);
703 ret = mv_cesa_queue_req(&req->base, &creq->base);
705 if (mv_cesa_req_needs_cleanup(&req->base, ret))
706 mv_cesa_ahash_cleanup(req);
711 static int mv_cesa_ahash_update(struct ahash_request *req)
713 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
715 creq->len += req->nbytes;
717 return mv_cesa_ahash_queue_req(req);
720 static int mv_cesa_ahash_final(struct ahash_request *req)
722 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
723 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
725 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
726 creq->last_req = true;
729 return mv_cesa_ahash_queue_req(req);
732 static int mv_cesa_ahash_finup(struct ahash_request *req)
734 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
735 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
737 creq->len += req->nbytes;
738 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
739 creq->last_req = true;
741 return mv_cesa_ahash_queue_req(req);
744 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
745 u64 *len, void *cache)
747 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
748 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
749 unsigned int digsize = crypto_ahash_digestsize(ahash);
750 unsigned int blocksize;
752 blocksize = crypto_ahash_blocksize(ahash);
755 memcpy(hash, creq->state, digsize);
756 memset(cache, 0, blocksize);
757 memcpy(cache, creq->cache, creq->cache_ptr);
762 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
763 u64 len, const void *cache)
765 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
766 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
767 unsigned int digsize = crypto_ahash_digestsize(ahash);
768 unsigned int blocksize;
769 unsigned int cache_ptr;
772 ret = crypto_ahash_init(req);
776 blocksize = crypto_ahash_blocksize(ahash);
777 if (len >= blocksize)
778 mv_cesa_update_op_cfg(&creq->op_tmpl,
779 CESA_SA_DESC_CFG_MID_FRAG,
780 CESA_SA_DESC_CFG_FRAG_MSK);
783 memcpy(creq->state, hash, digsize);
786 cache_ptr = do_div(len, blocksize);
790 memcpy(creq->cache, cache, cache_ptr);
791 creq->cache_ptr = cache_ptr;
796 static int mv_cesa_md5_init(struct ahash_request *req)
798 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
799 struct mv_cesa_op_ctx tmpl = { };
801 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
803 mv_cesa_ahash_init(req, &tmpl, true);
805 creq->state[0] = MD5_H0;
806 creq->state[1] = MD5_H1;
807 creq->state[2] = MD5_H2;
808 creq->state[3] = MD5_H3;
813 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
815 struct md5_state *out_state = out;
817 return mv_cesa_ahash_export(req, out_state->hash,
818 &out_state->byte_count, out_state->block);
821 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
823 const struct md5_state *in_state = in;
825 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
829 static int mv_cesa_md5_digest(struct ahash_request *req)
833 ret = mv_cesa_md5_init(req);
837 return mv_cesa_ahash_finup(req);
840 struct ahash_alg mv_md5_alg = {
841 .init = mv_cesa_md5_init,
842 .update = mv_cesa_ahash_update,
843 .final = mv_cesa_ahash_final,
844 .finup = mv_cesa_ahash_finup,
845 .digest = mv_cesa_md5_digest,
846 .export = mv_cesa_md5_export,
847 .import = mv_cesa_md5_import,
849 .digestsize = MD5_DIGEST_SIZE,
850 .statesize = sizeof(struct md5_state),
853 .cra_driver_name = "mv-md5",
855 .cra_flags = CRYPTO_ALG_ASYNC |
856 CRYPTO_ALG_KERN_DRIVER_ONLY,
857 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
858 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
859 .cra_init = mv_cesa_ahash_cra_init,
860 .cra_module = THIS_MODULE,
865 static int mv_cesa_sha1_init(struct ahash_request *req)
867 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
868 struct mv_cesa_op_ctx tmpl = { };
870 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
872 mv_cesa_ahash_init(req, &tmpl, false);
874 creq->state[0] = SHA1_H0;
875 creq->state[1] = SHA1_H1;
876 creq->state[2] = SHA1_H2;
877 creq->state[3] = SHA1_H3;
878 creq->state[4] = SHA1_H4;
883 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
885 struct sha1_state *out_state = out;
887 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
891 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
893 const struct sha1_state *in_state = in;
895 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
899 static int mv_cesa_sha1_digest(struct ahash_request *req)
903 ret = mv_cesa_sha1_init(req);
907 return mv_cesa_ahash_finup(req);
910 struct ahash_alg mv_sha1_alg = {
911 .init = mv_cesa_sha1_init,
912 .update = mv_cesa_ahash_update,
913 .final = mv_cesa_ahash_final,
914 .finup = mv_cesa_ahash_finup,
915 .digest = mv_cesa_sha1_digest,
916 .export = mv_cesa_sha1_export,
917 .import = mv_cesa_sha1_import,
919 .digestsize = SHA1_DIGEST_SIZE,
920 .statesize = sizeof(struct sha1_state),
923 .cra_driver_name = "mv-sha1",
925 .cra_flags = CRYPTO_ALG_ASYNC |
926 CRYPTO_ALG_KERN_DRIVER_ONLY,
927 .cra_blocksize = SHA1_BLOCK_SIZE,
928 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
929 .cra_init = mv_cesa_ahash_cra_init,
930 .cra_module = THIS_MODULE,
935 static int mv_cesa_sha256_init(struct ahash_request *req)
937 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
938 struct mv_cesa_op_ctx tmpl = { };
940 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
942 mv_cesa_ahash_init(req, &tmpl, false);
944 creq->state[0] = SHA256_H0;
945 creq->state[1] = SHA256_H1;
946 creq->state[2] = SHA256_H2;
947 creq->state[3] = SHA256_H3;
948 creq->state[4] = SHA256_H4;
949 creq->state[5] = SHA256_H5;
950 creq->state[6] = SHA256_H6;
951 creq->state[7] = SHA256_H7;
956 static int mv_cesa_sha256_digest(struct ahash_request *req)
960 ret = mv_cesa_sha256_init(req);
964 return mv_cesa_ahash_finup(req);
967 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
969 struct sha256_state *out_state = out;
971 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
975 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
977 const struct sha256_state *in_state = in;
979 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
983 struct ahash_alg mv_sha256_alg = {
984 .init = mv_cesa_sha256_init,
985 .update = mv_cesa_ahash_update,
986 .final = mv_cesa_ahash_final,
987 .finup = mv_cesa_ahash_finup,
988 .digest = mv_cesa_sha256_digest,
989 .export = mv_cesa_sha256_export,
990 .import = mv_cesa_sha256_import,
992 .digestsize = SHA256_DIGEST_SIZE,
993 .statesize = sizeof(struct sha256_state),
995 .cra_name = "sha256",
996 .cra_driver_name = "mv-sha256",
998 .cra_flags = CRYPTO_ALG_ASYNC |
999 CRYPTO_ALG_KERN_DRIVER_ONLY,
1000 .cra_blocksize = SHA256_BLOCK_SIZE,
1001 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1002 .cra_init = mv_cesa_ahash_cra_init,
1003 .cra_module = THIS_MODULE,
1008 struct mv_cesa_ahash_result {
1009 struct completion completion;
1013 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1016 struct mv_cesa_ahash_result *result = req->data;
1018 if (error == -EINPROGRESS)
1021 result->error = error;
1022 complete(&result->completion);
1025 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1026 void *state, unsigned int blocksize)
1028 struct mv_cesa_ahash_result result;
1029 struct scatterlist sg;
1032 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1033 mv_cesa_hmac_ahash_complete, &result);
1034 sg_init_one(&sg, pad, blocksize);
1035 ahash_request_set_crypt(req, &sg, pad, blocksize);
1036 init_completion(&result.completion);
1038 ret = crypto_ahash_init(req);
1042 ret = crypto_ahash_update(req);
1043 if (ret && ret != -EINPROGRESS)
1046 wait_for_completion_interruptible(&result.completion);
1048 return result.error;
1050 ret = crypto_ahash_export(req, state);
1057 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1058 const u8 *key, unsigned int keylen,
1060 unsigned int blocksize)
1062 struct mv_cesa_ahash_result result;
1063 struct scatterlist sg;
1067 if (keylen <= blocksize) {
1068 memcpy(ipad, key, keylen);
1070 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1075 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1076 mv_cesa_hmac_ahash_complete,
1078 sg_init_one(&sg, keydup, keylen);
1079 ahash_request_set_crypt(req, &sg, ipad, keylen);
1080 init_completion(&result.completion);
1082 ret = crypto_ahash_digest(req);
1083 if (ret == -EINPROGRESS) {
1084 wait_for_completion_interruptible(&result.completion);
1088 /* Set the memory region to 0 to avoid any leak. */
1089 memset(keydup, 0, keylen);
1095 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1098 memset(ipad + keylen, 0, blocksize - keylen);
1099 memcpy(opad, ipad, blocksize);
1101 for (i = 0; i < blocksize; i++) {
1109 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1110 const u8 *key, unsigned int keylen,
1111 void *istate, void *ostate)
1113 struct ahash_request *req;
1114 struct crypto_ahash *tfm;
1115 unsigned int blocksize;
1120 tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1121 CRYPTO_ALG_TYPE_AHASH_MASK);
1123 return PTR_ERR(tfm);
1125 req = ahash_request_alloc(tfm, GFP_KERNEL);
1131 crypto_ahash_clear_flags(tfm, ~0);
1133 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1135 ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1141 opad = ipad + blocksize;
1143 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1147 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1151 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1156 ahash_request_free(req);
1158 crypto_free_ahash(tfm);
1163 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1165 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1167 ctx->base.ops = &mv_cesa_ahash_req_ops;
1169 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1170 sizeof(struct mv_cesa_ahash_req));
1174 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1176 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1177 struct mv_cesa_op_ctx tmpl = { };
1179 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1180 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1182 mv_cesa_ahash_init(req, &tmpl, true);
1187 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1188 unsigned int keylen)
1190 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1191 struct md5_state istate, ostate;
1194 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1198 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1199 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1201 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1202 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1207 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1211 ret = mv_cesa_ahmac_md5_init(req);
1215 return mv_cesa_ahash_finup(req);
1218 struct ahash_alg mv_ahmac_md5_alg = {
1219 .init = mv_cesa_ahmac_md5_init,
1220 .update = mv_cesa_ahash_update,
1221 .final = mv_cesa_ahash_final,
1222 .finup = mv_cesa_ahash_finup,
1223 .digest = mv_cesa_ahmac_md5_digest,
1224 .setkey = mv_cesa_ahmac_md5_setkey,
1225 .export = mv_cesa_md5_export,
1226 .import = mv_cesa_md5_import,
1228 .digestsize = MD5_DIGEST_SIZE,
1229 .statesize = sizeof(struct md5_state),
1231 .cra_name = "hmac(md5)",
1232 .cra_driver_name = "mv-hmac-md5",
1233 .cra_priority = 300,
1234 .cra_flags = CRYPTO_ALG_ASYNC |
1235 CRYPTO_ALG_KERN_DRIVER_ONLY,
1236 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1237 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1238 .cra_init = mv_cesa_ahmac_cra_init,
1239 .cra_module = THIS_MODULE,
1244 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1246 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1247 struct mv_cesa_op_ctx tmpl = { };
1249 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1250 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1252 mv_cesa_ahash_init(req, &tmpl, false);
1257 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1258 unsigned int keylen)
1260 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1261 struct sha1_state istate, ostate;
1264 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1268 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1269 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1271 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1272 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1277 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1281 ret = mv_cesa_ahmac_sha1_init(req);
1285 return mv_cesa_ahash_finup(req);
1288 struct ahash_alg mv_ahmac_sha1_alg = {
1289 .init = mv_cesa_ahmac_sha1_init,
1290 .update = mv_cesa_ahash_update,
1291 .final = mv_cesa_ahash_final,
1292 .finup = mv_cesa_ahash_finup,
1293 .digest = mv_cesa_ahmac_sha1_digest,
1294 .setkey = mv_cesa_ahmac_sha1_setkey,
1295 .export = mv_cesa_sha1_export,
1296 .import = mv_cesa_sha1_import,
1298 .digestsize = SHA1_DIGEST_SIZE,
1299 .statesize = sizeof(struct sha1_state),
1301 .cra_name = "hmac(sha1)",
1302 .cra_driver_name = "mv-hmac-sha1",
1303 .cra_priority = 300,
1304 .cra_flags = CRYPTO_ALG_ASYNC |
1305 CRYPTO_ALG_KERN_DRIVER_ONLY,
1306 .cra_blocksize = SHA1_BLOCK_SIZE,
1307 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1308 .cra_init = mv_cesa_ahmac_cra_init,
1309 .cra_module = THIS_MODULE,
1314 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1315 unsigned int keylen)
1317 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1318 struct sha256_state istate, ostate;
1321 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1325 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1326 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1328 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1329 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1334 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1336 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1337 struct mv_cesa_op_ctx tmpl = { };
1339 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1340 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1342 mv_cesa_ahash_init(req, &tmpl, false);
1347 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1351 ret = mv_cesa_ahmac_sha256_init(req);
1355 return mv_cesa_ahash_finup(req);
1358 struct ahash_alg mv_ahmac_sha256_alg = {
1359 .init = mv_cesa_ahmac_sha256_init,
1360 .update = mv_cesa_ahash_update,
1361 .final = mv_cesa_ahash_final,
1362 .finup = mv_cesa_ahash_finup,
1363 .digest = mv_cesa_ahmac_sha256_digest,
1364 .setkey = mv_cesa_ahmac_sha256_setkey,
1365 .export = mv_cesa_sha256_export,
1366 .import = mv_cesa_sha256_import,
1368 .digestsize = SHA256_DIGEST_SIZE,
1369 .statesize = sizeof(struct sha256_state),
1371 .cra_name = "hmac(sha256)",
1372 .cra_driver_name = "mv-hmac-sha256",
1373 .cra_priority = 300,
1374 .cra_flags = CRYPTO_ALG_ASYNC |
1375 CRYPTO_ALG_KERN_DRIVER_ONLY,
1376 .cra_blocksize = SHA256_BLOCK_SIZE,
1377 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1378 .cra_init = mv_cesa_ahmac_cra_init,
1379 .cra_module = THIS_MODULE,