2 * This file is part of the Chelsio T6 Crypto driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #ifndef __CHCR_CORE_H__
37 #define __CHCR_CORE_H__
39 #include <crypto/algapi.h>
43 #include "cxgb4_uld.h"
45 #define DRV_MODULE_NAME "chcr"
46 #define DRV_VERSION "1.0.0.0"
48 #define MAX_PENDING_REQ_TO_HW 20
49 #define CHCR_TEST_RESPONSE_TIMEOUT 1000
51 #define PAD_ERROR_BIT 1
52 #define CHK_PAD_ERR_BIT(x) (((x) >> PAD_ERROR_BIT) & 1)
54 #define MAC_ERROR_BIT 0
55 #define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1)
57 #define WR_MIN_LEN (sizeof(struct chcr_wr) + \
58 sizeof(struct cpl_rx_phys_dsgl) + \
59 sizeof(struct ulptx_sgl))
61 #define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
72 #define KEYCTX_TX_WR_IV_S 55
73 #define KEYCTX_TX_WR_IV_M 0x1ffULL
74 #define KEYCTX_TX_WR_IV_V(x) ((x) << KEYCTX_TX_WR_IV_S)
75 #define KEYCTX_TX_WR_IV_G(x) \
76 (((x) >> KEYCTX_TX_WR_IV_S) & KEYCTX_TX_WR_IV_M)
78 #define KEYCTX_TX_WR_AAD_S 47
79 #define KEYCTX_TX_WR_AAD_M 0xffULL
80 #define KEYCTX_TX_WR_AAD_V(x) ((x) << KEYCTX_TX_WR_AAD_S)
81 #define KEYCTX_TX_WR_AAD_G(x) (((x) >> KEYCTX_TX_WR_AAD_S) & \
84 #define KEYCTX_TX_WR_AADST_S 39
85 #define KEYCTX_TX_WR_AADST_M 0xffULL
86 #define KEYCTX_TX_WR_AADST_V(x) ((x) << KEYCTX_TX_WR_AADST_S)
87 #define KEYCTX_TX_WR_AADST_G(x) \
88 (((x) >> KEYCTX_TX_WR_AADST_S) & KEYCTX_TX_WR_AADST_M)
90 #define KEYCTX_TX_WR_CIPHER_S 30
91 #define KEYCTX_TX_WR_CIPHER_M 0x1ffULL
92 #define KEYCTX_TX_WR_CIPHER_V(x) ((x) << KEYCTX_TX_WR_CIPHER_S)
93 #define KEYCTX_TX_WR_CIPHER_G(x) \
94 (((x) >> KEYCTX_TX_WR_CIPHER_S) & KEYCTX_TX_WR_CIPHER_M)
96 #define KEYCTX_TX_WR_CIPHERST_S 23
97 #define KEYCTX_TX_WR_CIPHERST_M 0x7f
98 #define KEYCTX_TX_WR_CIPHERST_V(x) ((x) << KEYCTX_TX_WR_CIPHERST_S)
99 #define KEYCTX_TX_WR_CIPHERST_G(x) \
100 (((x) >> KEYCTX_TX_WR_CIPHERST_S) & KEYCTX_TX_WR_CIPHERST_M)
102 #define KEYCTX_TX_WR_AUTH_S 14
103 #define KEYCTX_TX_WR_AUTH_M 0x1ff
104 #define KEYCTX_TX_WR_AUTH_V(x) ((x) << KEYCTX_TX_WR_AUTH_S)
105 #define KEYCTX_TX_WR_AUTH_G(x) \
106 (((x) >> KEYCTX_TX_WR_AUTH_S) & KEYCTX_TX_WR_AUTH_M)
108 #define KEYCTX_TX_WR_AUTHST_S 7
109 #define KEYCTX_TX_WR_AUTHST_M 0x7f
110 #define KEYCTX_TX_WR_AUTHST_V(x) ((x) << KEYCTX_TX_WR_AUTHST_S)
111 #define KEYCTX_TX_WR_AUTHST_G(x) \
112 (((x) >> KEYCTX_TX_WR_AUTHST_S) & KEYCTX_TX_WR_AUTHST_M)
114 #define KEYCTX_TX_WR_AUTHIN_S 0
115 #define KEYCTX_TX_WR_AUTHIN_M 0x7f
116 #define KEYCTX_TX_WR_AUTHIN_V(x) ((x) << KEYCTX_TX_WR_AUTHIN_S)
117 #define KEYCTX_TX_WR_AUTHIN_G(x) \
118 (((x) >> KEYCTX_TX_WR_AUTHIN_S) & KEYCTX_TX_WR_AUTHIN_M)
121 struct fw_crypto_lookaside_wr wreq;
122 struct ulp_txpkt ulptx;
123 struct ulptx_idata sc_imm;
124 struct cpl_tx_sec_pdu sec_cpl;
125 struct _key_ctx key_ctx;
129 spinlock_t lock_chcr_dev;
130 struct uld_ctx *u_ctx;
131 unsigned char tx_channel_id;
132 unsigned char rx_channel_id;
136 struct list_head entry;
137 struct cxgb4_lld_info lldi;
138 struct chcr_dev *dev;
141 struct sge_opaque_hdr {
143 dma_addr_t addr[MAX_SKB_FRAGS + 1];
146 struct chcr_ipsec_req {
147 struct ulp_txpkt ulptx;
148 struct ulptx_idata sc_imm;
149 struct cpl_tx_sec_pdu sec_cpl;
150 struct _key_ctx key_ctx;
153 struct chcr_ipsec_wr {
154 struct fw_ulptx_wr wreq;
155 struct chcr_ipsec_req req;
158 struct ipsec_sa_entry {
160 unsigned int enckey_len;
161 unsigned int kctx_len;
162 unsigned int authsize;
165 char key[2 * AES_MAX_KEY_SIZE];
169 * sgl_len - calculates the size of an SGL of the given capacity
170 * @n: the number of SGL entries
171 * Calculates the number of flits needed for a scatter/gather list that
172 * can hold the given number of entries.
174 static inline unsigned int sgl_len(unsigned int n)
177 return (3 * n) / 2 + (n & 1) + 2;
180 struct uld_ctx *assign_chcr_device(void);
181 int chcr_send_wr(struct sk_buff *skb);
182 int start_crypto(void);
183 int stop_crypto(void);
184 int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
185 const struct pkt_gl *pgl);
186 int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev);
187 int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
189 int chcr_ipsec_xmit(struct sk_buff *skb, struct net_device *dev);
190 void chcr_add_xfrmops(const struct cxgb4_lld_info *lld);
191 #endif /* __CHCR_CORE_H__ */