1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/delay.h>
4 #include <linux/firmware.h>
5 #include <linux/list.h>
6 #include <linux/module.h>
7 #include <linux/mutex.h>
9 #include <linux/pci_ids.h>
11 #include "nitrox_dev.h"
12 #include "nitrox_common.h"
13 #include "nitrox_csr.h"
14 #include "nitrox_hal.h"
15 #include "nitrox_isr.h"
16 #include "nitrox_debugfs.h"
18 #define CNN55XX_DEV_ID 0x12
22 #define DRIVER_VERSION "1.1"
23 #define FW_DIR "cavium/"
25 #define SE_FW FW_DIR "cnn55xx_se.fw"
27 static const char nitrox_driver_name[] = "CNN55XX";
29 static LIST_HEAD(ndevlist);
30 static DEFINE_MUTEX(devlist_lock);
31 static unsigned int num_devices;
34 * nitrox_pci_tbl - PCI Device ID Table
36 static const struct pci_device_id nitrox_pci_tbl[] = {
37 {PCI_VDEVICE(CAVIUM, CNN55XX_DEV_ID), 0},
38 /* required last entry */
41 MODULE_DEVICE_TABLE(pci, nitrox_pci_tbl);
43 static unsigned int qlen = DEFAULT_CMD_QLEN;
44 module_param(qlen, uint, 0644);
45 MODULE_PARM_DESC(qlen, "Command queue length - default 2048");
48 int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs);
50 int nitrox_sriov_configure(struct pci_dev *pdev, int num_vfs)
57 * struct ucode - Firmware Header
59 * @version: firmware version
60 * @code_size: code section size
66 char version[VERSION_LEN - 1];
73 * write_to_ucd_unit - Write Firmware to NITROX UCD unit
75 static void write_to_ucd_unit(struct nitrox_device *ndev,
78 u32 code_size = be32_to_cpu(ucode->code_size) * 2;
94 * Total of 8 blocks, each size 32KB
97 /* set the block number */
98 offset = UCD_UCODE_LOAD_BLOCK_NUM;
99 nitrox_write_csr(ndev, offset, 0);
101 code_size = roundup(code_size, 8);
103 data = ucode->code[i];
104 /* write 8 bytes at a time */
105 offset = UCD_UCODE_LOAD_IDX_DATAX(i);
106 nitrox_write_csr(ndev, offset, data);
111 /* put all SE cores in group 0 */
112 offset = POM_GRP_EXECMASKX(SE_GROUP);
113 nitrox_write_csr(ndev, offset, (~0ULL));
115 for (i = 0; i < ndev->hw.se_cores; i++) {
117 * write block number and firware length
118 * bit:<2:0> block number
119 * bit:3 is set SE uses 32KB microcode
120 * bit:3 is clear SE uses 64KB microcode
122 offset = UCD_SE_EID_UCODE_BLOCK_NUMX(i);
123 nitrox_write_csr(ndev, offset, 0x8);
125 usleep_range(300, 400);
128 static int nitrox_load_fw(struct nitrox_device *ndev, const char *fw_name)
130 const struct firmware *fw;
134 dev_info(DEV(ndev), "Loading firmware \"%s\"\n", fw_name);
136 ret = request_firmware(&fw, fw_name, DEV(ndev));
138 dev_err(DEV(ndev), "failed to get firmware %s\n", fw_name);
142 ucode = (struct ucode *)fw->data;
143 /* copy the firmware version */
144 memcpy(ndev->hw.fw_name, ucode->version, (VERSION_LEN - 2));
145 ndev->hw.fw_name[VERSION_LEN - 1] = '\0';
147 write_to_ucd_unit(ndev, ucode);
148 release_firmware(fw);
154 * nitrox_add_to_devlist - add NITROX device to global device list
155 * @ndev: NITROX device
157 static int nitrox_add_to_devlist(struct nitrox_device *ndev)
159 struct nitrox_device *dev;
162 INIT_LIST_HEAD(&ndev->list);
163 refcount_set(&ndev->refcnt, 1);
165 mutex_lock(&devlist_lock);
166 list_for_each_entry(dev, &ndevlist, list) {
172 ndev->idx = num_devices++;
173 list_add_tail(&ndev->list, &ndevlist);
175 mutex_unlock(&devlist_lock);
180 * nitrox_remove_from_devlist - remove NITROX device from
182 * @ndev: NITROX device
184 static void nitrox_remove_from_devlist(struct nitrox_device *ndev)
186 mutex_lock(&devlist_lock);
187 list_del(&ndev->list);
189 mutex_unlock(&devlist_lock);
192 struct nitrox_device *nitrox_get_first_device(void)
194 struct nitrox_device *ndev = NULL;
196 mutex_lock(&devlist_lock);
197 list_for_each_entry(ndev, &ndevlist, list) {
198 if (nitrox_ready(ndev))
201 mutex_unlock(&devlist_lock);
205 refcount_inc(&ndev->refcnt);
206 /* barrier to sync with other cpus */
207 smp_mb__after_atomic();
211 void nitrox_put_device(struct nitrox_device *ndev)
216 refcount_dec(&ndev->refcnt);
217 /* barrier to sync with other cpus */
218 smp_mb__after_atomic();
221 static int nitrox_device_flr(struct pci_dev *pdev)
225 pos = pci_save_state(pdev);
227 dev_err(&pdev->dev, "Failed to save pci state\n");
231 /* check flr support */
232 if (pcie_has_flr(pdev))
235 pci_restore_state(pdev);
240 static int nitrox_pf_sw_init(struct nitrox_device *ndev)
244 err = nitrox_common_sw_init(ndev);
248 err = nitrox_register_interrupts(ndev);
250 nitrox_common_sw_cleanup(ndev);
255 static void nitrox_pf_sw_cleanup(struct nitrox_device *ndev)
257 nitrox_unregister_interrupts(ndev);
258 nitrox_common_sw_cleanup(ndev);
262 * nitrox_bist_check - Check NITORX BIST registers status
263 * @ndev: NITROX device
265 static int nitrox_bist_check(struct nitrox_device *ndev)
270 for (i = 0; i < NR_CLUSTERS; i++) {
271 value += nitrox_read_csr(ndev, EMU_BIST_STATUSX(i));
272 value += nitrox_read_csr(ndev, EFL_CORE_BIST_REGX(i));
274 value += nitrox_read_csr(ndev, UCD_BIST_STATUS);
275 value += nitrox_read_csr(ndev, NPS_CORE_BIST_REG);
276 value += nitrox_read_csr(ndev, NPS_CORE_NPC_BIST_REG);
277 value += nitrox_read_csr(ndev, NPS_PKT_SLC_BIST_REG);
278 value += nitrox_read_csr(ndev, NPS_PKT_IN_BIST_REG);
279 value += nitrox_read_csr(ndev, POM_BIST_REG);
280 value += nitrox_read_csr(ndev, BMI_BIST_REG);
281 value += nitrox_read_csr(ndev, EFL_TOP_BIST_STAT);
282 value += nitrox_read_csr(ndev, BMO_BIST_REG);
283 value += nitrox_read_csr(ndev, LBC_BIST_STATUS);
284 value += nitrox_read_csr(ndev, PEM_BIST_STATUSX(0));
290 static int nitrox_pf_hw_init(struct nitrox_device *ndev)
294 err = nitrox_bist_check(ndev);
296 dev_err(&ndev->pdev->dev, "BIST check failed\n");
299 /* get cores information */
300 nitrox_get_hwinfo(ndev);
302 nitrox_config_nps_unit(ndev);
303 nitrox_config_pom_unit(ndev);
304 nitrox_config_efl_unit(ndev);
305 /* configure IO units */
306 nitrox_config_bmi_unit(ndev);
307 nitrox_config_bmo_unit(ndev);
308 /* configure Local Buffer Cache */
309 nitrox_config_lbc_unit(ndev);
310 nitrox_config_rand_unit(ndev);
312 /* load firmware on SE cores */
313 err = nitrox_load_fw(ndev, SE_FW);
317 nitrox_config_emu_unit(ndev);
323 * nitrox_probe - NITROX Initialization function.
324 * @pdev: PCI device information struct
325 * @id: entry in nitrox_pci_tbl
327 * Return: 0, if the driver is bound to the device, or
328 * a negative error if there is failure.
330 static int nitrox_probe(struct pci_dev *pdev,
331 const struct pci_device_id *id)
333 struct nitrox_device *ndev;
336 dev_info_once(&pdev->dev, "%s driver version %s\n",
337 nitrox_driver_name, DRIVER_VERSION);
339 err = pci_enable_device_mem(pdev);
344 err = nitrox_device_flr(pdev);
346 dev_err(&pdev->dev, "FLR failed\n");
347 pci_disable_device(pdev);
351 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
352 dev_dbg(&pdev->dev, "DMA to 64-BIT address\n");
354 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
356 dev_err(&pdev->dev, "DMA configuration failed\n");
357 pci_disable_device(pdev);
362 err = pci_request_mem_regions(pdev, nitrox_driver_name);
364 pci_disable_device(pdev);
367 pci_set_master(pdev);
369 ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
375 pci_set_drvdata(pdev, ndev);
378 /* add to device list */
379 nitrox_add_to_devlist(ndev);
381 ndev->hw.vendor_id = pdev->vendor;
382 ndev->hw.device_id = pdev->device;
383 ndev->hw.revision_id = pdev->revision;
384 /* command timeout in jiffies */
385 ndev->timeout = msecs_to_jiffies(CMD_TIMEOUT);
386 ndev->node = dev_to_node(&pdev->dev);
387 if (ndev->node == NUMA_NO_NODE)
390 ndev->bar_addr = ioremap(pci_resource_start(pdev, 0),
391 pci_resource_len(pdev, 0));
392 if (!ndev->bar_addr) {
396 /* allocate command queus based on cpus, max queues are 64 */
397 ndev->nr_queues = min_t(u32, MAX_PF_QUEUES, num_online_cpus());
400 err = nitrox_pf_sw_init(ndev);
404 err = nitrox_pf_hw_init(ndev);
408 nitrox_debugfs_init(ndev);
410 /* clear the statistics */
411 atomic64_set(&ndev->stats.posted, 0);
412 atomic64_set(&ndev->stats.completed, 0);
413 atomic64_set(&ndev->stats.dropped, 0);
415 atomic_set(&ndev->state, __NDEV_READY);
416 /* barrier to sync with other cpus */
417 smp_mb__after_atomic();
419 err = nitrox_crypto_register();
426 nitrox_debugfs_exit(ndev);
427 atomic_set(&ndev->state, __NDEV_NOT_READY);
428 /* barrier to sync with other cpus */
429 smp_mb__after_atomic();
431 nitrox_pf_sw_cleanup(ndev);
433 nitrox_remove_from_devlist(ndev);
435 pci_set_drvdata(pdev, NULL);
437 pci_release_mem_regions(pdev);
438 pci_disable_device(pdev);
443 * nitrox_remove - Unbind the driver from the device.
444 * @pdev: PCI device information struct
446 static void nitrox_remove(struct pci_dev *pdev)
448 struct nitrox_device *ndev = pci_get_drvdata(pdev);
453 if (!refcount_dec_and_test(&ndev->refcnt)) {
454 dev_err(DEV(ndev), "Device refcnt not zero (%d)\n",
455 refcount_read(&ndev->refcnt));
459 dev_info(DEV(ndev), "Removing Device %x:%x\n",
460 ndev->hw.vendor_id, ndev->hw.device_id);
462 atomic_set(&ndev->state, __NDEV_NOT_READY);
463 /* barrier to sync with other cpus */
464 smp_mb__after_atomic();
466 nitrox_remove_from_devlist(ndev);
468 #ifdef CONFIG_PCI_IOV
470 nitrox_sriov_configure(pdev, 0);
472 nitrox_crypto_unregister();
473 nitrox_debugfs_exit(ndev);
474 nitrox_pf_sw_cleanup(ndev);
476 iounmap(ndev->bar_addr);
479 pci_set_drvdata(pdev, NULL);
480 pci_release_mem_regions(pdev);
481 pci_disable_device(pdev);
484 static void nitrox_shutdown(struct pci_dev *pdev)
486 pci_set_drvdata(pdev, NULL);
487 pci_release_mem_regions(pdev);
488 pci_disable_device(pdev);
491 static struct pci_driver nitrox_driver = {
492 .name = nitrox_driver_name,
493 .id_table = nitrox_pci_tbl,
494 .probe = nitrox_probe,
495 .remove = nitrox_remove,
496 .shutdown = nitrox_shutdown,
497 #ifdef CONFIG_PCI_IOV
498 .sriov_configure = nitrox_sriov_configure,
502 module_pci_driver(nitrox_driver);
504 MODULE_AUTHOR("Srikanth Jampala <Jampala.Srikanth@cavium.com>");
505 MODULE_DESCRIPTION("Cavium CNN55XX PF Driver" DRIVER_VERSION " ");
506 MODULE_LICENSE("GPL");
507 MODULE_VERSION(DRIVER_VERSION);
508 MODULE_FIRMWARE(SE_FW);